Method of fabricating group iii-v based optoelectronic devices on silicon-on-insulator wafers

Abstract

A method of fabricating a III-V based optoelectronic device on a silicon-on-insulator wafer. The silicon-on-insulator wafer includes a silicon device layer, a substrate, and an insulator layer between the substrate and the silicon device layer. The method includes the steps of providing a device coupon formed of a plurality of III-V based layers, providing the silicon-on-insulator wafer, the wafer including a cavity having a bonding region, transferring the device coupon into the cavity and bonding a layer of the device coupon to the bonding region, leaving a channel around one or more sides of the device coupon, filling the channel with a bridge waveguide material, and performing one or more etching steps on the device coupon, the silicon-on-insulator wafer, and / or the channel to provide a III-V semiconductor based waveguide in the device coupon, one or more bridge waveguides in the channel, and a silicon waveguide in the silicon-on-insulator wafer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method of fabricating a group III-V based optoelectronic device on a silicon-on-insulator wafer. BACKGROUND

[0002] Hybrid optoelectronic devices utilizing group III-V based semiconductors and silicon platforms benefit from the advantages of both technologies. For example, the field of silicon photonics benefits from low manufacturing costs due to the detailed understanding of the properties of silicon fabrication. Similarly, group III-V based semiconductor devices (e.g., lasers, electro-absorption modulators, photodetectors, semiconductor optical amplifiers, and electro-absorption modulated laser) have higher performance than their silicon counterparts.

[0003] However, there remain problems that hinder the widespread adoption of III-V / Si based optoelectronic devices. Among the most significant are the high optical loss of such devices, the lack of methods to mass produce the devices, and reliability issues during the fabrication of the devices. For example, in micro-transfer printing based fabrication processes, high alignment accuracy (typically less than 0.5 μιη) can be required, which can hinder high throughput from large printing arrays. Additionally, a 2-4 μιη T-junction interface can be required for III-V waveguide facets, and a 1 μιη T-junction interface can be required for SOI waveguide facets. In some instances, this can add an additional 2 dB of optical loss to the coupling between the two.

[0004] As an alternative to micro-transfer printing, flip-chip bonding techniques have been proposed. In these techniques, a group III-V based semiconductor device is fabricated on a group III-V based wafer. The wafer is then inverted and aligned to a silicon based platform wafer. The sacrificial layer that bonded the group III-V based semiconductor device to the group III-V based wafer is then removed, and the group III-V based semiconductor is bonded to the silicon platform. However, when the group III-V based semiconductor device includes multiple layers, the layers must be grown in the opposite order as would be required if the device were to be bonded to the silicon platform (as the chip is "inverted").

[0005] It is possible to identify that a III-V / Si hybrid device has been fabricated by flip-chip bonding techniques, for example, by secondary ion mass spectrometry (SIMS), as it is possible to identify that the region or layer of the III-V device closest to the silicon platform is grown last compared to the rest of the device or the rest of the layers. For example, SIMS can be used to determine the composition, doping type, and distribution relative to the InP substrate on which the device is fabricated of each layer.

[0006] One disadvantage of flip-chip bonding is that additional steps are usually required in order to obtain a viable device. For example, in a multi-layer structure comprising a quantum well active layer, the P-doped layer should have as high a doping as possible in order to ensure a good ohmic contact between the metal bonding pad and the P-doped III-V layer.

[0007] However, in order to minimise optical losses, the doping concentration should decrease as it approaches the quantum well active layer. Therefore, usually, the P-doped layer is grown last on top of the multi-layer structure in order to avoid diffusion of the dopant towards the quantum well active layer. However, this is not feasible for a flip-chip based approach and therefore additional steps are required to provide a good level of ohmic contact.

[0008] Additionally, in the context of III-V based lasers, a waveguide is usually fabricated on the P-doped layer as the efficiency of the resulting device is improved. This is because P-carriers have a significantly lower mobility compared to N-carriers. N-carriers in an N-doped region can have 25 times greater mobility than P-carriers and this allows the N-carriers to easily escape and result in lower efficiency. When using a flip-chip process, it is required that the waveguide is on the N-doped layer and therefore the problem discussed arises. SUMMARY

[0009] In a first aspect, embodiments of the present application provide a method of fabricating a III-V based optoelectronic device on a silicon-on-insulator wafer, the silicon-on-insulator wafer comprising a silicon device layer, a substrate and an insulator layer between the substrate and the silicon device layer, wherein the method comprises the steps of:

[0010] providing a device test sample formed from a plurality of III-V based layers;

[0011] providing the silicon-on-insulator wafer, the wafer comprising a cavity having a bonding region;

[0012] transferring the device test sample into the cavity and bonding a layer of the device test sample to the bonding region, leaving a channel around one or more sides of the device test sample;

[0013] filling the channel with a bridge waveguide material; and

[0014] performing one or more etching steps on the device test sample, the silicon-on-insulator wafer and / or the channel to provide a III-V semiconductor based waveguide in the device test sample, one or more bridge waveguides in the channel and a silicon waveguide in the silicon-on-insulator wafer.

[0015] The method results in an optoelectronic device that induces less loss when an optical signal passes therethrough, as the bridge waveguides reduce optical loss between the III-V semiconductor-based waveguides and the silicon waveguides. As noted above, the resulting optoelectronic device also outperforms optoelectronic devices manufactured via flip-chip bonding processes.

[0016] The method can have any of the following optional features, or any combination thereof, to the extent that the optional features are compatible.

[0017] By lateral can be meant the side of the device sample that directly faces one or more sidewalls of the cavity. The one or more etching steps can include etching the bridge waveguide material, i.e., the now-filled channel, to provide the bridge waveguides.

[0018] The optoelectronic device can be any of the following: a III-V semiconductor-based distributed Bragg reflector laser; a III-V semiconductor distributed feedback laser; a laser using a III-V semiconductor-based gain medium; a III-V semiconductor electro-absorption modulator (EAM); a III-V semiconductor-based semiconductor optical amplifier; a III-V semiconductor-based photodetector; and a III-V semiconductor-based externally modulated laser.

[0019] The III-V semiconductor-based layer can include an optically active layer formed of any of the following materials: InGaAsP, AlInGaAs, and InGaNAs. The optically active layer can be formed of a bulk material, or can include multiple quantum wells.

[0020] The method can include a step performed prior to filling the channel: lining the channel with an anti-reflective lining. The channel can be lined such that a portion of the anti-reflective lining covering the floor of the channel has an upper surface aligned with the upper surface of the insulator layer.

[0021] The method can also include a step performed after filling the channel with the bridge waveguide material: aligning an upper surface of the bridge waveguide material with an upper surface of the silicon device layer.

[0022] The geometry of the III-V semiconductor-based waveguide, the geometry of the one or more bridge waveguides in the channel, and the geometry of the silicon waveguide adjacent to the one or more bridge waveguides can be substantially the same.

[0023] The method advantageously eliminates the need for a T-junction interface between waveguide components, which can significantly reduce optical loss.

[0024] The same etch hard mask can be used to etch the Group III-V semiconductor based waveguide, the one or more bridge waveguides, and the silicon waveguide. This ensures that the various waveguides are self-aligned, which further reduces optical losses.

[0025] The method can include forming one or more electrical bonding pads on the silicon-on-insulator wafer. This eliminates the need to form the electrical bonding pads on the Group III-V device die, and thereby saves space. In addition, the method improves device speed by minimizing parasitic capacitance.

[0026] The bridge waveguide material can be formed from amorphous silicon. The Group III-V layer can include a layer formed from InGaAsP, InP, or InGaAs.

[0027] The method can also include etching a reflective facet adjacent to an end of the Group III-V semiconductor based waveguide distal from the bridge waveguide, such that the optoelectronic device is operable as a laser. The method can also include etching a grating into the silicon waveguide, such that the optoelectronic device is operable as a distributed Bragg reflector laser.

[0028] The optoelectronic device can be operable as an electro-absorption modulator. The Group III-V semiconductor based waveguide can be straight or U-shaped, and the silicon waveguide can be an input waveguide, and the silicon-on-insulator layer can also be etched to provide an output waveguide, the input waveguide and the output waveguide optically coupled to respective legs of the Group III-V semiconductor based waveguide by respective bridge waveguides. The Group III-V semiconductor based waveguide can be L-shaped or substantially L-shaped, the silicon waveguide can be an input waveguide, and the silicon-on-insulator wafer can also be etched to provide an output waveguide, the input waveguide and the output waveguide optically coupled to respective legs of the Group III-V semiconductor based waveguide by respective bridge waveguides. The method can include making a waveguide taper in each of the input waveguide and the output waveguide, the waveguide taper tapering an optical mode from a first optical mode distal from the one or more bridge waveguides for emission / reception by the optoelectronic device to a second optical mode proximate to the one or more bridge waveguides for guidance through the optoelectronic device. The second optical mode can be weaker than the first optical mode. The taper can be a vertical taper, as the height of the optical mode changes from a first height to a second height.

[0029] The cavity can have a parallelogram shape. Thus, one or more interfaces between the input waveguide and / or output waveguide and the corresponding one or more bridge waveguides are at an angle with respect to the direction of guidance. This can reduce reflections from the interfaces, and thus optical reflections.

[0030] In a second aspect, embodiments of the present application provide an optoelectronic device manufactured according to the method of the first aspect, the optoelectronic device comprising any one, or any combination, of the optional features set out with reference to the first aspect to the extent that they are compatible.

[0031] In a third aspect, embodiments of the present application provide an optoelectronic device comprising: a silicon-on-insulator wafer comprising: a silicon waveguide located within a silicon device layer, a substrate, and an insulator layer between the substrate and the silicon device layer; a III-V semiconductor-based waveguide located within a cavity of the silicon-on-insulator wafer; and a bridge waveguide optically coupling the silicon waveguide located within the silicon device to the III-V semiconductor-based waveguide located within the cavity; wherein the III-V semiconductor-based waveguide is a multilayer structure obtained or obtainable by a process of epitaxially growing a series of layers, and wherein the layer of the multilayer structure furthest from the cavity is grown last in the process.

[0032] Such an optoelectronic device induces less loss when an optical signal passes therethrough, as the bridge waveguide reduces optical loss between the III-V semiconductor-based waveguide and the silicon waveguide. As noted above, the resulting optoelectronic device also outperforms an optoelectronic device manufactured via a flip-chip bonding process.

[0033] The optoelectronic device of the third aspect can have any one, or any combination, of the optional features set out with reference to the first aspect to the extent that they are compatible.

[0034] The device can comprise one or more anti-reflection linings located between the bridge waveguide and the III-V semiconductor-based waveguide and / or between the bridge waveguide and the silicon waveguide. The linings can be formed from silicon nitride.

[0035] The geometry of the III-V semiconductor-based waveguide, the geometry of the bridge waveguide, and the geometry of the silicon waveguide adjacent to the bridge waveguide can be substantially the same.

[0036] The III-V semiconductor-based waveguide can be electrically connected to one or more electrical bonding pads located on the silicon-on-insulator wafer.

[0037] The bridge waveguide can be formed from amorphous silicon.

[0038] The optoelectronic device can include a reflective facet adjacent to an end of the III-V semiconductor-based waveguide distal from the bridge waveguide such that the optoelectronic device is operable as a laser. The silicon waveguide can include a grating such that the optoelectronic device is operable as a distributed Bragg reflector laser.

[0039] The optoelectronic device can be operable as an electro-absorption modulator, or a semiconductor amplifier.

[0040] The silicon waveguide can include a waveguide taper that tapers an optical mode from a first optical mode distal from the bridge waveguide for emission / reception by the optoelectronic device to a second optical mode proximal to the bridge waveguide for guiding through the optoelectronic device.

[0041] The cavity can have a parallelogram shape.

[0042] Other aspects of the application provide a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first aspect; a computer readable medium storing a computer program comprising code which, when run on a computer, causes the computer to perform the method of the first aspect; and a computer system programmed to perform the method of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0043] Embodiments of the application will now be described, by way of example, with reference to the accompanying drawings, in which:

[0044] Figures 1 (i) to (ii) (B) A method of fabricating a silicon-on-insulator wafer is shown;

[0045] Figures 2 (i) to (v) A method of fabricating a device test sample is shown;

[0046] Figures 3 (i) to (xxv) (A) A method of fabricating a III-V based optoelectronic device is shown;

[0047] Figures 4 (i) to (xvii) (D) A different method of fabricating a III-V based optoelectronic device is shown; and

[0048] Figure 5 An integrated photonic circuit integrating two III-V based optoelectronic devices is shown. DETAILED DESCRIPTION

[0049] Aspects and embodiments of the application will now be discussed with reference to the drawings. Other aspects and embodiments will be apparent to the skilled person.

[0050] Aspects and embodiments of the application will now be discussed with reference to the drawings. Other aspects and embodiments will be apparent to the skilled person.Figures 1 (i) to (ii) (B) A method of fabricating a silicon-on-insulator wafer is shown. In a first step, shown in Figure 1 (i), a silicon-on-insulator (SOI) wafer is provided. The SOI wafer comprises a silicon substrate 101, above which is a buried oxide layer 102 formed of silicon dioxide / SiO2. The buried oxide layer serves as an underlayer for the waveguide formed later. Above the buried oxide layer 102, i.e. on the side of the buried oxide layer opposite the substrate, is a device layer 103 (also referred to as a silicon-on-insulator layer). The device layer has a thickness of about 3000 nm / 3 pm as measured from the uppermost surface of the buried oxide layer to the uppermost layer of the device layer. The buried oxide layer has a thickness of about 400 nm.

[0051] In a subsequent step, shown along the cross-section in Figure 1 (ii) (A), a portion of the device layer 103 and the buried oxide 102 is etched. The area to be etched is defined by a mask, and the unmasked portion is etched down to the silicon substrate. That is, the etching is performed such that the upper surface of the substrate 101 is exposed. This etching defines a cavity 105 having sidewalls 105a / 105b and a floor 105c. In this example, the mask is provided as a silicon dioxide layer 104. The height of the silicon dioxide layer is chosen such that the top surface is flush with the top surface of the III-V device sample formed subsequently.

[0052] Figure 1 (ii) (B) shows the wafer of Figure 1 (ii) (A) from a top view. Notably, the cavity 105 has a parallelogram geometry, which provides one or more angled interfaces for the waveguide in the final device (which reduces optical reflections).

[0053] Figure 2 (i) shows a simplified schematic of a III-V based semiconductor stack 200 suitable for use as a III-V / Si based optoelectronic device. The stack has a plurality of layers from bottom most to top most:

[0054] 201 - a reusable indium phosphide (InP) substrate;

[0055] 202 - a sacrificial layer formed of InGaAs;

[0056] 203 - N-doped indium phosphide;

[0057] 204 - a III-V based optically active layer of multiple quantum wells or bulk;

[0058] 205 - P-doped indium phosphide; and

[0059] 206 - P-doped indium gallium arsenide, InGaAs.

[0060] In one example, layer 204 is a multiple quantum well layer (MQW) that allows the subsequently formed device to function as a distributed Bragg reflector (DBR) laser. Advantageously, the stack can include an etch stop to allow precise etching of the waveguide. For example, when a III-V based semiconductor stack is to be used to fabricate a laser, an InGaAsP layer of 20 nm of an etch stop layer above the III-V based optically active layers of the multiple quantum well or bulk can be used as the etch stop. After the III-V based stack 200 is provided, the stack is etched to provide a device coupon 210, and the device coupon is covered with a protective silicon nitride layer 207. This etching also exposes the sidewalls of the sacrificial layer 202, and notably, the silicon nitride cover 207 does not extend further than the bottom of the N-InP layer 203. The silicon nitride cover has a thickness of about 400 nm. The result of this etching, and the covering with silicon nitride, is shown in Figure 2(ii)(A), and the same stage is shown from a top-down perspective in Figure 2(ii)(B). As with the cavity 105 of the silicon-on-insulator wafer, the device coupon 210 has a parallelogram geometry.

[0061] Next, in a step shown in Figure 2(iii), a tethering photoresist 208 is provided around the device coupon 210. Notably, the tethering photoresist does not completely enclose the device coupon 210. Instead, the tether leaves the sacrificial layer 202 exposed on its sides. After the photoresist tether is provided, an etch is performed to remove the sacrificial layer. The first stage of this step is shown in Figure 2(iv), with the arrow indicating the direction of the etch, and the completed etch is shown in Figure 2(v), with the coupon hanging from the tether. This etch completes the fabrication steps of the III-V based device coupon 210, and prepares the device coupon for pick-up by a stamp in a microtransfer printing process.

[0062] After the III-V device coupon 210 and the cavity 105 are prepared, a stamp is used to pick up the III-V device coupon from the indium phosphide substrate 201. The device coupon is then printed onto the bed of the cavity 105, and the bonded SOI wafer with the device coupon is subjected to a 300 °C anneal for 1 to 15 hours. The result of this step is shown in Figure 3(i). Notably, in the example where the final device is a DBR laser, the distance from the left-hand side of the device coupon 210 to the nearest sidewall 105a of the cavity is between 10 μm and 100 μm. However, the distance from the right-hand side of the device coupon to the nearest sidewall 105b is about 6 μm ± 3 μm. In addition, as indicated by the dashed line, the uppermost or top surface of the P-InGaAs layer is aligned with the top surface of the silicon dioxide layer 104.

[0063] Next, in the step shown in Figure 3(ii)(A), the protective silicon nitride layer is removed. Thus, the uppermost surface of the device sample (the uppermost surface of the P-doped InGaAs layer) is aligned with the uppermost surface of the silicon dioxide layer 104. This step results in a channel 301 extending between the outer side of the device sample 210 and the sidewall of the cavity 105. Figure 3(ii)(B) shows this step from a top-down perspective. It can be seen that the distance between the upper (in this view) vertical edge of the device sample 210 and the nearest sidewall is about 15 μm ± 5 μm.

[0064] In a further step shown in Figure 3(iii), silicon nitride 302 (in some embodiments, Si3N4) is provided as an anti-reflective liner or coating (ARC) on the exposed surfaces of the now-bonded wafer and sample. The ARC has a thickness of at least 230 nm and no more than about 260 nm, and a refractive index of at least 2.5 and no more than about 2.8. The portion of the anti-reflective coating present on the floor of the cavity is etched away, so that the uppermost surface of the silicon nitride layer is aligned with the uppermost surface of the buried oxide layer 102. The result of this step is shown in Figure 3(iv).

[0065] After the anti-reflective coating is etched, as shown in Figure 3(v), bulk amorphous silicon 303 (a-Si) is deposited over the device. This deposit fills the channel 301, and also covers the uppermost surface of the device. Next, in the step shown in Figure 3(vi), the amorphous silicon is partially etched, so that only the portion surrounding the channel remains. This etching releases wafer stress, and prepares the wafer for the next step.

[0066] After the etching, a chemical mechanical planarization (CMP) process is performed, so that the uppermost surface of the amorphous silicon is aligned with the uppermost surface of the silicon nitride lining. The result of this CMP step is shown in Figure 3(vii). Next, the a-Si is trimmed so that the top surface of the a-Si is aligned with the top surface of the adjacent device layer 103. This is shown in Figure 3(viii). In effect, this step provides a bridge waveguide 304, since the device layer 103 of the wafer is now optically coupled to the device sample 210. Further etching / layer deposition provides further definition to the bridge waveguide, as described below.

[0067] After the trimming step, further silicon nitride 302 is provided to fill the channel (also referred to as a trench). The result of this step is shown in Figure 3(ix). As a result of the bulk deposition of silicon nitride, all of the exposed surfaces of the device are covered. Thus, in a subsequent step shown in Figure 3(x), a further CMP process is performed to flatten the upper surface of the device. The CMP process is performed until the top surface of the silicon dioxide layer 104 and the top surface of the P-InGaAs layer are exposed.

[0068] Next, in a metallization step, a p-contact seed metal layer 305 is provided in contact with the upper surface of the P-InGaAs layer. The result of this step is shown in Figure 3(xi). After the p-contact seed metal layer is provided, further silicon dioxide 104 is disposed over the upper surface of the device, which is then capped with a silicon nitride layer 307. The result of this step is shown in Figure 3(xii).

[0069] Figure 3(xiii) shows the subsequent manufacturing stage from a cross-sectional view (top) and a plan view (bottom). Photoresist 308 is provided and patterned in the manner shown in the plan view. The photoresist defines the waveguide to be etched, and covers the sides of the device sample. For clarity, the plan view has removed the silicon nitride 307 and silicon dioxide layer 104.

[0070] Figure 3(xiv) shows a plan view of the device after dry etching is used to remove the silicon nitride 307 layer that is not covered by the photoresist 308. Figures 3 (xiv) (A) to (D) are cross-sectional views along lines A-A' to D-D' respectively. Notably, in Figure 3(xiv)(C), the important result of the dry etching can be seen. The etching is performed until the silicon dioxide layer 104, and thus leaves a rectangular portion of the silicon nitride 307 that is located above the p-contact seed metal layer. The photoresist 308 is then removed.

[0071] Next, as shown in Figure 3(xv), further photoresist 309 is disposed over the device sample and some of the surrounding area of the SOI wafer. The uncovered portions are then dry etched to remove any exposed areas of silicon dioxide, the result of which is shown in Figures 3 (xv) (A) to (D) are cross-sectional views along lines A-A' to D-D' respectively. Notably, in Figure 3(xv)(A), Figure 3(xv)(B) and Figure 3(xv)(D), it can be seen that the etching removes portions of the silicon dioxide that are not covered by the silicon nitride 307 layer or the further photoresist 309. Thus, the top surface of the device layer 103 is exposed, as is the top surface of the silicon nitride 302 and the silicon nitride 302.

[0072] The etching is continued using the same photoresist 309, as in the step shown in Figure 3(xvi). The etching now selectively removes the silicon nitride, and uses the silicon dioxide as a hard mask. The result of this step is shown in Figure 3(xvi) and Figures 3 (xvi) (A) to (D)The result of this step is shown in (again, the corresponding cross-sections). Notably, the silicon nitride layer 307 has been completely removed, as shown in Figure 3(xvi)(A), Figure 3(xvi)(B) and Figure 3(xvi)(D). It is also noted that the etch extends partially into the silicon nitride 302 used to line the channel. This results in an inverted ‘T’ shape as shown in Figure 3(xvi)(D), where a small silicon nitride ridge or rib extends from the base of the silicon nitride, which is capped by the silicon dioxide 104.

[0073] The etching is again continued, this time selectively etching silicon and amorphous silicon. The silicon dioxide is again used as a hard mask. The result of this step is shown in Figure 3(xvii) and Figures 3 (xvii) (A) to (D) The result of this step is shown in (again, the corresponding cross-sections). As shown in Figure 3(xvii)(A) and Figure 3(xvii)(B), this time the silicon device layer 103 and the a-Si portion 303 are etched to provide an inverted ‘T’ shape. Each has a small ridge or rib of silicon or a-Si extending from the corresponding base. Both are capped by the silicon dioxide 104. The a-Si portion 303 is also capped by the portion of silicon nitride 302 between the silicon dioxide and the a-Si portion.

[0074] Notably, this etching step (geometrically) defines the a-Si portion of the one or more silicon waveguides and bridge waveguides. In this example, there is only a single silicon waveguide in the device layer 103, as the device is intended to be used as a laser (and thus only needs to have an output waveguide). Of course, in other examples, there can be two or more waveguides in the device layer.

[0075] In a final etching step using photoresist 309, another selective etch is performed, which removes the silicon nitride (using the silicon dioxide as a hard mask). This etch only affects the silicon nitride adjacent to the a-Si, i.e. adjacent to the cavity sidewalls 105a / b. The result of this etch is shown in Figure 3(xviii) and Figures 3 (xviii) (A) to (D) Figure 3(xviii)(D). It is noted that the height of the underlying silicon nitride 307 portion, which is not covered by the silicon dioxide 104, has been further reduced. The height of this silicon nitride portion is substantially equal to the height of the underlying portion in the device layer 103 and the a-Si portion 303.

[0076] The photoresist 309 is then removed, and further photoresist 310 is disposed over portions of the device on either side of the cavity. This is shown in Figure 3(xix) and Figures 3 (xix) (A) to (D)In Figure 3(xix)(C), the result of this step is shown, with the trenches 311 shown extending through the silicon nitride layer 307, the silicon dioxide 104, and the various layers of the device sample. The etching is performed so that the strips of the top surface of the MQW layer are exposed by the trenches 311. The etching defines the waveguide within the device sample.

[0077] The photoresist 310 is then removed, as is the uppermost layer of exposed silicon dioxide 104 and silicon nitride 302 (i.e., the layer on the upper side of the silicon dioxide 104). The result of this step is shown in Figure 3(xx) and Figure 3(xx)(A). Figures 3 (xx) (A) to (D) The result of this step is shown in Figure 3(xx)(C), again in cross-section. Note that, as shown in Figure 3(xx)(C), the silicon nitride layer 307 and some of the layers of the device sample extend above the top surface of the device layer 103.

[0078] After this step, a backside facet 312 is etched into the device sample. This is shown in Figure 3(xxi). The backside facet 312 is on the opposite side of the bridge waveguide from the output waveguide formed in the device sample. In some embodiments, where a DBR laser is being fabricated, another step is performed, shown in Figure 3(xxi')(A), in which a grating 313 is etched into a portion of the output waveguide. Figure 3(xxi')(A) shows this grating in cross-section along line A-A'.

[0079] After the backside facet is provided, and in embodiments, after the grating is provided, an overlayer 314 of silicon dioxide is provided over the exposed surfaces of the device. After the overlayer 314 is provided, etching is performed to provide an N-contact via 315 that extends down through the device to expose the upper surface of the N-doped layer of InP 203. This is shown in Figure 3(xxii), which is a cross-section along line C-C' given earlier. After the N-contact via 315 is etched, n-contact seed metal 316 is provided that electrically contacts the N-doped InP layer. This is shown in Figure 3(xxiii). Next, as shown in Figure 3(xxiv), additional silicon dioxide 314 is deposited, opening the N-contact via 315 and a P-contact via 317, so that the top surfaces of the P and N contact seed metal layers are exposed.

[0080] Next, in the metallization step shown in Figure 3(xxv)(top view) and Figure 3(xxv)(A)(cross-section along line A-A'), P and N contacts 319 and 320 are provided. In addition, the backside facet is metallized, providing a highly reflective backside facet 318.

[0081] This step completes the fabrication of the III-V based laser integrated with a silicon based platform. As can be seen in Figure 3(xxv), the output waveguide 330 is optically coupled to the waveguide 334 within the III-V device coupon by a bridge waveguide 332. Thus, by using a bridge waveguide to overcome inaccuracies in positioning the device coupon within the cavity, the gap between the waveguide in the device coupon and the output waveguide is filled.

[0082] Figures 4 (i) to (xvii) (D) The various fabrication steps of the different methods are illustrated. The steps up to, but not including, Figure 4(i) and Figure 4(i)(A) (a cross-section along line A-A’ of Figure 4(i)) essentially mirror those illustrated and so these steps are not repeated here. Figures 3 (i) to (x)

[0083] Figure 4(i) illustrates the device coupon having been bonded to the cavity of a silicon-on-insulator wafer according to the method discussed previously. The silicon dioxide layer 104 is omitted for clarity. It can be seen that the uppermost layer of the device coupon (in this case a P-doped InGaAs layer 206) is exposed. The device coupon is surrounded by a layer of silicon nitride 302 and amorphous silicon 303. The step of providing P-contact seed metal 401 has been performed. It is noted that, as best seen in Figure 4(i) which is a plan view, the P-contact seed metal 401 has a C or crescent shape due to the shape of the waveguides which are subsequently formed.

[0084] After the P-contact seed metal 401 has been provided, further silicon dioxide 104 is deposited over the device, followed by a layer of silicon nitride 402. This is illustrated in Figure 4(ii). The device is now ready for waveguide fabrication. Next, as shown in Figure 4(iii) (the upper half of which is a cross-section along line A-D and the lower half of which is a plan view), photoresist 403 is provided and patterned. The patterned photoresist 403 defines the width of the input and output waveguides which will be optically coupled to respective bridge waveguides. A curved or U-shaped waveguide is defined within the device coupon, which can reflect the C or crescent shape of the P-contact seed metal in terms of curvature.

[0085] After the photoresist has been provided, the silicon nitride 402 which is not covered by the photoresist 403 is etched away via dry etching. The silicon dioxide 104 acts as an etch stop. The result of this etching is illustrated in Figure 4(iv) (a plan view), and Figures 4 (iv) (A) to (D) (being cross-sections along line A to D respectively). As can be seen in the cross-sections, a small portion of the silicon nitride 402 is left just under the photoresist 403.

[0086] ​The photoresist 403 is then removed, and a further photoresist 404 is disposed on the device in an area at least including the device test sample, and also a portion of the device between the two branches of the previous photoresist 403, in order to enhance the isolation between the input waveguide and the output waveguide. This is shown in Figure 4(v). A dry etch is then performed, which removes the silicon dioxide 104 that is not covered by the photoresist 404 or the silicon nitride 402. In Figures 4 (v) (A) to (D) the results of the etch can be seen in (again, cross-sections along lines A to D, respectively). Using the same photoresist 404, a selective dry etch is then performed to remove the exposed silicon nitride 302. In this case, the silicon dioxide 104 acts as a hard mask, and so, as shown in Figures 4(vi) and Figures 4 (vi) (A) to (D) (vi)(B), a portion of the silicon nitride 302 is left under the upper silicon dioxide 104 portion. As before, this etch results in the silicon nitride 302 region having an inverted T shape with a rib or ridge extending from the base portion. The rib or ridge is under the silicon dioxide 104 cap. After this step, a further dry etch is performed using the same photoresist 404. This further dry etch selectively etches away the silicon or a-Si, and uses the silicon dioxide as a hard mask. The results of this further dry etch are shown in Figures 4(vii) and Figures 4 (vii) (A) to (D) (vii)(B). This step defines the a-Si portions of the input waveguide and output waveguide, and the bridge waveguide, provided in the silicon device layer 104. This is most clearly visible in Figures 4(vii)(A) and 4(vii)(B). In a final dry etch using the photoresist 404, the silicon nitride 302 is selectively etched away, as shown in Figures 4(viii) and Figures 4 (viii) (A) to (D) (viii)(B). As most clearly visible in Figure 4(viii)(D), this defines the silicon nitride portion of the bridge waveguide.

[0087] The photoresist 404 is then removed, and a further photoresist 405 is applied, as shown in Figures 4(ix) and Figures 4 (ix) (A) to (D) (ix)(B). The photoresist 405 encapsulates the previously formed waveguides, and covers the III-V based device test sample. After the application of the photoresist 405, a dry etch is used to remove all of the silicon dioxide 104 that is not covered by the photoresist. The most obvious result of this step is shown in Figure 4(ix)(C), in which the silicon dioxide previously covering the silicon nitride lining has been removed. After the silicon dioxide etch, a selective silicon nitride dry etch is performed to reduce the height of the silicon nitride lining to approximately 1 pm. This is shown in Figures 4(x) and Figures 4 (x) (A) to (D) (x)(B), and most obviously in Figure 4(x)(C).

[0088] Next, a further dry etch is performed using the same photoresist 405. This time the dry etch selectively etches away the silicon and the a-Si, leaving the uncoated device layer 103 and amorphous silicon 303 flush with respect to the silicon nitride underlay 302, to form a step for the electrode pad later. This is shown in Figure 4(xi) and Figures 4 (xi) (A) to (D) most clearly in Figure 4(xi)(C).

[0089] The photoresist 405 is then removed, and a further photoresist 406 is provided, which covers most of the device bars of the III-V device coupon. This is shown in Figure 4(xii). Etching is then performed using the silicon nitride 402 as a hard mask, which geometrically defines waveguide ridges or ribs 407 within the III-V device coupon. The etching extends down through the layers of the III-V device coupon, stopping shortly after it enters the N-doped InP layer.

[0090] The photoresist 406 is then removed, along with any exposed silicon dioxide. A further layer of silicon dioxide 104 is then provided over the entire device. The result of this step is shown in Figure 4(xiii) and Figures 4 (xiii) (A) to (D) it should be noted that in Figure 4(xiii) the silicon dioxide has been omitted for clarity. Next, in the steps shown in Figure 4(xiv) and Figures 4 (xiv) (A) to (D) A waveguide taper is formed in the silicon waveguide in the device layer 103. This is most clearly visible in Figure 4(xiv)(A), where a waveguide taper 409 formed from silicon extends from the device layer 103. In this example, the waveguide taper tapers from a height of about 3 μm (far from the III-V device coupon waveguide, and close to the edge of the wafer) to a height of about 1 μm (close to the III-V device coupon waveguide).

[0091] After the waveguide taper has been formed, further silicon dioxide 104 is provided on the exposed surfaces of the device, vias are formed, and N-contact seed metal 410 is provided in electrical contact with the N-doped InP layer of the III-V device coupon. The result of this step is shown in Figure 4(xv) and Figures 4 (xv) (A) to (D) in particular Figure 4(xv)(A) shows the silicon dioxide and Figure 4(xv)(C) shows the N-contact seed metal 410. The silicon dioxide provided forms a passivation layer 411, which also acts as a capping layer for at least the a-Si and SiN portions of the bridge waveguide.

[0092] Next, in Figure 4(xvi) and Figures 4 (xvi) (A) to (D)In the steps shown, an isolation trench 412 is etched into the III-V device test piece on the side of the waveguide ridge / rib opposite the N-contact seed metal 410. This is most clearly visible in Figure 4 (xvi) (C). Following this, further silicon dioxide is provided to line the isolation trench 412. A via is etched to expose the upper surface of the previously formed N-contact seed metal and P-contact seed metal. P-contacts 413 and N-contacts 414 are then provided, which are electrically connected to the P-contact seed metal and N-contact seed metal respectively. The results of these steps are shown in Figures 4 (xvii) and Figures 4 (xvii) (A) to (D) (xviii) (again, cross-sectional views).

[0093] This completes the fabrication of a III-V based electro-absorption modulator (EAM) integrated with a silicon platform, located within a waveguide ridge or rib 407. In use, light enters the device from one of the silicon waveguides 420 and 422. The optical mode is converted by the waveguide tapers discussed previously, and the light is coupled into the waveguide ridge or rib 407 containing the III-V based EAM by a corresponding one of the bridge waveguides 424 and 426 (formed of a-Si and SiN). A driver (not shown) applies a voltage to one or both of the P-contacts 413 and N-contacts 414 in order to modulate the light passing through the III-V based EAM. The light then exits via the other bridge waveguide through the silicon waveguide.

[0094] In Figures 4 (iv) to (xvii) Figure 4 (xix), a cross-sectional view along lines A, B and D shows one of the two silicon waveguides or bridge waveguides. Both the input and output silicon waveguides can be located on one side of the III-V device test piece with a U-shaped waveguide as shown in the above figures. However, the input and output silicon waveguides can be located on opposite sides of the III-V device test piece with straight waveguides. Alternatively, the input and output silicon waveguides can be located on either side of the III-V device test piece with L-shaped waveguides; or the input and output silicon waveguides can be located on either side of the III-V device test piece with waveguides forming an angle of 90 degrees to 180 degrees. Of course, it will be appreciated that the same process can occur in the other silicon waveguide and bridge waveguide, but these views have been omitted for the sake of brevity.

[0095] Figure 5 A photonic integrated circuit (PIC) 500 is shown, comprising a III-V based laser 501 fabricated using the method discussed with respect to Figures 3 (i) to (xxv) (A) a III-V based laser 501 fabricated using the method discussed with respect to Figures 4 (i) to (xvii) (D)The method discussed produces a III-V based EAM 502. Thus, the PIC can be used as a modulator transmitter. An unmodulated optical signal can be produced by a laser 501 and provided to the EAM 502. The EAM can then modulate the signal and provide it to a chip output waveguide 503 for subsequent transmission. In Figure 5 In the interest of clarity, a top passivation layer (formed of silicon dioxide in some embodiments) is omitted in the above description and in the figures shown in top view.

[0096] Generally, in the above description and in the figures shown in top view, one or more upper layers can be omitted for clarity.

[0097] While the application has been described in connection with the exemplary embodiments described above, it will be evident to those skilled in the art that many

[0098] List of features

[0099] 101 silicon substrate 105c bed

[0100] 102 buried oxide 200 III-V stack

[0101] layer

[0102] 103 silicon device layer 201 InP substrate

[0103] 104 silicon dioxide 202 sacrificial layer

[0104] 105 cavity 203 N-doped InP

[0105] 105a one or more layers

[0106] side wall 204 optically active layer

[0107] 105b one or more 205 P-doped InP

[0108] side wall layer

[0109] 206 P-doped 503 chip output waveguide

[0110] InGaAs layer

[0111] 207 SiN protective layer

[0112] 208 photoresist tether

[0113] object

[0114] 210 SiN passivation

[0115] device

[0116] sample

[0117] 301 channel

[0118] 302 silicon nitride

[0119] 303 alpha-silicon fill

[0120] 304 bridge waveguide

[0121] 305 P-contact seed

[0122] metal layer

[0123] 307 silicon nitride layer

[0124] 308, 309, 310 photoresist

[0125] 311 trench

[0126] 312 backside reflective facet

[0127] facet

[0128] 313 grating

[0129] 314 overburden layer

[0130] 315 N-contact via

[0131] 316 N-contact seed

[0132] metal layer

[0133] 317 P-contact via

[0134] 318 highly reflective backside reflective facet

[0135] facet

[0136] 319 P-contact

[0137] 320 N-contact

[0138] 401 P-contact seed

[0139] metal

[0140] 402 silicon nitride

[0141] 403, 404, 405, 406 photoresist

[0142] 407 waveguide ridge / rib

[0143] 409 waveguide tapers

[0144] 410 n-contact seed

[0145] metal

[0146] 411 overcoat

[0147] 412 isolation trench

[0148] 413 p-contact

[0149] 414 n-contact

[0150] 500 pic

[0151] 501 laser

[0152] 502 eam

Claims

1. A method of fabricating a III-V based optoelectronic device on a silicon-on- insulator wafer, the silicon-on-insulator wafer comprising a silicon device layer, a substrate, and an insulator layer between the substrate and the silicon device layer, wherein the method comprises the steps of: providing a device coupon formed of a plurality of III-V based layers; providing the silicon-on-insulator wafer, the wafer comprising a cavity having a bonding region; transferring the device coupon into the cavity and bonding a layer of the device coupon to the bonding region, leaving a channel around one or more sides of the device coupon; lining the channel with an anti-reflective liner; filling the channel with a bridge waveguide material; and performing one or more etching steps on the device coupon, the silicon-on- insulator wafer, and / or the channel to provide a III-V semiconductor based waveguide in the device coupon, one or more bridge waveguides in the channel, and a silicon waveguide in the silicon-on-insulator wafer, wherein the anti-reflective liner is aligned along a top surface of a bed of the cavity with a top surface of the insulator layer, and the anti-reflective liner is also between the bridge waveguide and the III-V semiconductor based waveguide and between the bridge waveguide and the silicon waveguide, and the bridge waveguide is above the anti-reflective liner along the top surface of the bed of the cavity, wherein the anti-reflective liner is silicon nitride, a thickness of the silicon nitride liner is at least 230 nanometers and no greater than 260 nanometers, and a refractive index of the silicon nitride liner is at least 2.5 and no greater than 2.8, and wherein the method further comprises: etching the silicon nitride liner so that a top surface of the silicon nitride liner is aligned with a top surface of the insulator layer; then depositing bulk amorphous silicon over the device so that the amorphous silicon fills the channel and covers an uppermost surface of the device; then etching the amorphous silicon down so that only the portion surrounding the channel is left; then performing a chemical mechanical planarization process so that an uppermost surface of the amorphous silicon is aligned with an uppermost surface of the silicon nitride liner; then trimming the amorphous silicon in the channel so that a top surface of the amorphous silicon is aligned with a top surface of the silicon device layer, thereby providing the bridge waveguide; then depositing additional silicon nitride in bulk over the device to fill the channel; and then performing another chemical mechanical planarization process on the silicon nitride to flatten an upper surface of the device.

2. The method of claim 1, wherein the channel is lined so that a portion of the anti- reflective liner that lines a bed of the channel has an upper surface that is aligned with an upper surface of the insulator layer.

3. The method of claim 1, further comprising the step, after filling the channel with the bridge waveguide material, of aligning an upper surface of the bridge waveguide material with an upper surface of the silicon device layer. ​ ​ ​ ​ ​ ​ 4. The method of claim 1, wherein the geometry of the III-V semiconductor-based waveguide, the geometry of the one or more bridge waveguides in the channel, and the geometry of the silicon waveguide adjacent to the one or more bridge waveguides are substantially the same.

5. The method of claim 1, wherein the same etch hard mask is used to etch the III-V semiconductor-based waveguide, the one or more bridge waveguides, and the silicon waveguide.

6. The method of claim 1, comprising the steps of: One or more electrical bonding pads are formed on the silicon wafer on the insulator.

7. The method of claim 1, wherein the bridge waveguide material is formed of amorphous silicon.

8. The method of claim 1, further comprising the step of: Etching a reflective facet adjacent to the end of the III-V semiconductor-based waveguide away from the bridge waveguide enables the optoelectronic device to operate as a laser.

9. The method of claim 8, further comprising the step of: A grating is etched into the silicon waveguide, enabling the optoelectronic device to operate as a distributed Bragg reflector laser.

10. The method of claim 1, wherein the optoelectronic device is operable as an electroabsorption modulator.

11. The method of claim 10, wherein the waveguide based on the III-V semiconductor is U-shaped, the silicon waveguide is an input waveguide, and the silicon-on-insulator wafer is further etched to provide an output waveguide, the input waveguide and the output waveguide being optically coupled to corresponding branches of the III-V semiconductor-based waveguide via corresponding bridge waveguides.

12. The method of claim 10, wherein the waveguide based on the III-V semiconductor is L-shaped or substantially L-shaped, the silicon waveguide is an input waveguide, and the silicon-on-insulator wafer is further etched to provide an output waveguide, the input waveguide and the output waveguide being optically coupled to corresponding branches of the III-V semiconductor-based waveguide via corresponding bridge waveguides.

13. The method of claim 11 or 12, further comprising the step of: A waveguide cone is fabricated in each of the input waveguide and the output waveguide, the waveguide cone causing the optical mode to taper from a first optical mode for transmission / reception of the optoelectronic device that is far from the one or more bridge waveguides to a second optical mode for guiding the optoelectronic device that is close to the one or more bridge waveguides.

14. The method of claim 13, wherein the second optical mode is weaker than the first optical mode.

15. The method of claim 1, wherein the cavity has a parallelogram shape.

16. An optoelectronic device manufactured according to the method of any of the preceding claims.

17. An optoelectronic device, the optoelectronic device comprising: A silicon-on-insulator wafer, the silicon-on-insulator wafer comprising: A silicon waveguide, a substrate, and an insulating layer located within a silicon device layer; A waveguide based on a III-V semiconductor, wherein the waveguide is located within a cavity of the silicon-on-insulator wafer; and One or more anti-reflective liners; A bridge waveguide that optically couples the silicon waveguide located within the silicon device to the III-V semiconductor-based waveguide located within the cavity; wherein the III-V semiconductor-based waveguide is a multilayer structure obtained or obtainable by a process of epitaxially growing a series of layers, and wherein a layer of the multilayer structure furthest from the cavity is grown last in the process, wherein the one or more anti-reflective liners are aligned along a top surface of the bed of the cavity with a top surface of the insulator layer, and the one or more anti-reflective liners are also located between the bridge waveguide and the III-V semiconductor-based waveguide and between the bridge waveguide and the silicon waveguide, and the bridge waveguide is located above the one or more anti-reflective liners along the top surface of the bed of the cavity, wherein the anti-reflective liner is silicon nitride, a thickness of the silicon nitride liner is at least 230 nanometers and no greater than 260 nanometers, and a refractive index of the silicon nitride liner is at least 2.5 and no greater than 2.8, and a top surface of the silicon nitride liner is aligned with a top surface of the insulator layer, the bridge waveguide is formed of amorphous silicon, an uppermost surface of the amorphous silicon is aligned with an uppermost surface of the silicon nitride liner, a top surface of the amorphous silicon is aligned with a top surface of the silicon device layer, thereby providing the bridge waveguide.

18. The optoelectronic device of claim 17, wherein a geometry of the III-V semiconductor-based waveguide, a geometry of the bridge waveguide, and a geometry of the silicon waveguide adjacent to the bridge waveguide are substantially identical.

19. The optoelectronic device of claim 17, wherein the III-V semiconductor-based waveguide is electrically connected to one or more electrical bonding pads located on the silicon-on-insulator wafer.

20. The optoelectronic device of claim 17, the optoelectronic device comprising a reflective facet adjacent to an end of the III-V semiconductor-based waveguide furthest from the bridge waveguide, such that the optoelectronic device is operable as a laser.

21. The optoelectronic device of claim 20, wherein the silicon waveguide comprises a grating, such that the optoelectronic device is operable as a distributed Bragg reflector laser.

22. The optoelectronic device of claim 17, wherein the optoelectronic device is operable as an electro-absorption modulator.

23. The optoelectronic device of claim 17, wherein the silicon waveguide comprises a waveguide taper that tapers an optical mode from a first optical mode used for transmission / reception by the optoelectronic device furthest from the bridge waveguide to a second optical mode used for guiding through the optoelectronic device proximate to the bridge waveguide.

24. The optoelectronic device of claim 17, wherein the cavity has a parallelogram shape.

Images