Semiconductor device and method for forming the same

Abstract

A semiconductor device includes: a gate stack; a gate spacer located on a sidewall of the gate stack; a source / drain region adjacent to the gate stack; a silicide; and a source / drain contact electrically connected to the source / drain region through the silicide. The silicide includes: a conformal first portion, the conformal first portion is in the source / drain region, the conformal first portion includes metal and silicon; and a conformal second portion, the conformal second portion is above the conformal first portion, the conformal second portion is further disposed on the sidewall of the gate spacer, the conformal second portion includes metal, silicon and nitrogen. Embodiments of the present invention also relate to a method of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used, for example, in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the material layers using photolithography to form circuit components and elements on the material layers.

[0003] The semiconductor industry has been increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a gate stack; a gate spacer located on the sidewall of the gate stack; and a source / drain region adjacent to the gate stack. A silicide comprises: a conformal first portion extending into the source / drain region, the conformal first portion comprising metal and silicon; a conformal second portion located above the conformal first portion, the conformal second portion further disposed on the sidewall of the gate spacer, the conformal second portion comprising metal, silicon and nitrogen. The semiconductor device further comprises: a source / drain contact electrically connected to the source / drain region through the silicide.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a gate stack located above a channel region of a transistor; a gate spacer located on a sidewall of the gate stack; a source / drain region adjacent to the channel region; and a silicide extending into the source / drain region. The silicide comprises: a titanium silicon portion, wherein a ratio of a minimum thickness of the titanium silicon portion to a maximum thickness of the titanium silicon portion is in a range of 3.5:1 to 5:1; and a silicon nitride titanium portion, on the silicon nitride titanium portion, wherein a ratio of a minimum thickness of the silicon nitride titanium portion to a maximum thickness of the silicon nitride titanium portion is in a range of 1:1 to 1.5:1. The semiconductor device further comprises: a source / drain contact, wherein the source / drain contact is electrically connected to the source / drain region through the silicide.

[0006] According to another aspect of an embodiment of the present invention, a method for forming a semiconductor is provided, comprising: patterning an opening through an interlayer dielectric layer, wherein the opening exposes a surface of a source / drain region; and forming a silicide in the opening. Wherein, forming the silicide comprises: performing a first conformal deposition process to form a first metal-containing portion on the source / drain region; performing a second conformal deposition process to form a second metal-containing portion on the first metal-containing portion, wherein the process parameters of the first conformal deposition process are different from those of the second conformal deposition process; and performing a passivation process on the second metal-containing portion. The method for forming a semiconductor also comprises: forming a source / drain contact in the opening above the silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A three-dimensional view of an example of a FinFET is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B and Fig. 22Cis a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig. 17C and Fig. 18C is a schematic diagram of a deposition process according to some embodiments.

[0011] Fig.23 A deposition chamber is shown in accordance with some embodiments.

[0012] Fig.24 The thicknesses of layers deposited according to some embodiments are shown.

[0013] Fig.25A , Fig.25B , Fig.26A and Fig.26B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which another component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly.

[0016] Various embodiments include conformal silicide in the source / drain regions. Conformal silicide may allow for reduced source / drain contact resistance (R csd ). For example, by including conformal silicide in both NMOS and PMOS finFET transistors, it has been observed that the R per fin of the finFET transistor csdThe conformal silicide can be formed by depositing a metal (e.g., titanium, etc.) using a conformal deposition process (such as plasma enhanced chemical vapor deposition (PECVD)). Due to the conformal deposition process, the excess metal material protrusions on the sidewalls of the source / drain contact openings can be controlled, thereby eliminating a separate sidewall cleaning step for removing undesirable metal protrusions. The metal can also be deposited at a sufficient temperature to intermix with the crystalline material of the source / drain region, which eliminates the need for a separate annealing step after deposition. Therefore, the embodiment method can reduce the manufacturing steps, which advantageously increases manufacturing efficiency and reduces costs.

[0017] Figure 1 A three-dimensional view of an example of a FinFET according to some embodiments is shown. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude above and between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only the semiconductor substrate or the semiconductor substrate including the isolation regions. In addition, although the fin 52 is shown as a single continuous material with the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0018] The gate dielectric layer 92 is along the sidewalls and over the top surface of the fin 52, and the gate electrode 94 is over the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction, for example, of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects of use in planar devices such as planar FETs.

[0020] Figures 2 to 16B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Show Figure 1 Reference cross section AA is shown except for multiple fins / FinFETs. Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A It is along Figure 1 The reference section AA is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 14C , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A It is along Figure 1 Similar to cross section BB is shown, except multiple fins / FinFETs are shown. Fig. 10C , Fig. 10D , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B and Fig. 22B It is along Figure 1 Reference cross section BB is shown except for the plurality of fins / FinFETs.

[0021] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type dopant or an n-type dopant) or undoped. Generally speaking, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium in phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0022] The substrate 50 may be a portion of a wafer 10, such as a silicon wafer. For example, various structures for a plurality of dies may be formed together on the wafer 10. Subsequently, a sawing process may be applied to the wafer 10 to separate each die from other dies in the wafer 10.

[0023] Substrate 50 has region 50N and region 50P. Region 50N can be used to form n-type devices such as NMOS transistors, for example, n-type FinFETs. Region 50P can be used to form p-type devices such as PMOS transistors, for example, p-type FinFETs. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between region 50N and region 50P.

[0024] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral atom beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0025] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning processes or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes, allowing the formation of patterns with, for example, spacings smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fin 52.

[0026] exist Figure 4In the embodiment shown, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, and post-curing to convert it into another material (such as an oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as discussed above may be formed over the liner.

[0027] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where a mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surface of the mask or the fin 52, respectively, is flush with the insulating material 54.

[0028] exist Figure 6 Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI region 56 may have a planar surface, a convex surface, a concave surface (such as a depression), or a combination thereof as shown. By appropriate etching, the top surface of STI region 56 may be formed to be flat, convex, and / or concave. STI region 56 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of insulating material 54 (e.g., etching the material of insulating material 54 at a faster rate than the material of fin 52). For example, oxide removal may be used, which is performed using, for example, dilute hydrofluoric (dHF) acid.

[0029] about Figures 2 to 6The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, in Figure 5 In some embodiments, the fin 52 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such embodiments, the fin 52 includes a recessed material and an epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments in which a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, although in situ doping and implant doping may be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si x Ge 1-x , where x may be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0031] Further in Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a p-well may be formed in the region 50N, and an n-well may be formed in the region 50P. In some embodiments, a p-well or an n-well is formed in both the region 50N and the region 50P.

[0032] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed in region 50N over fin 52 and STI region 56. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10 18 cm -3 , such as between about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0033] After 50P is implanted, a photoresist is formed in region 50P over fin structure 52 and STI region 56. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration may be equal to or less than 10 18 cm -3 , such as between about 10 16 cm -3 and about 10 18 cm -3 The photoresist may be removed after implantation, such as by an acceptable ashing process.

[0034] After implantation of regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0035] exist Figure 7In the embodiment of the present invention, a pseudo dielectric layer 60 is formed on the fin 52. The pseudo dielectric layer 60 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 62 is formed above the pseudo dielectric layer 60, and a mask layer 64 is formed above the pseudo gate layer 62. The pseudo gate layer 62 may be deposited above the pseudo dielectric layer 60 and then planarized, such as by CMP. The mask layer 64 may be deposited above the pseudo gate layer 62. The pseudo gate layer 62 may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polycrystalline-silicon / polysilicon), polycrystalline silicon germanium (poly-crystalline silicon-germanium / poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The pseudo gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 may be made of other materials with high etch selectivity relative to the etching of the isolation region. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that the dummy dielectric layer 60 is shown to cover only the fin 52 for the purpose of illustration only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, thereby extending between the dummy gate layer 62 and the STI region 56.

[0036] FIG. 8A to FIG. 22B Various additional steps in the fabrication of example devices are shown. FIG. 8A to FIG. 22B Components in either region 50N or region 50P are shown. For example, FIG. 8A to FIG. 16B The structure shown is applicable to both region 50N and region 50P. The differences in structure, if any, between region 50N and region 50P are described in the text of each figure.

[0037] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 (see Figure 7 ) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from the adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0038] Further in Fig. 8A and Figure 8B In the process, a gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0039] After forming the gate sealing spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. Figure 6 Similar to the implantation discussed in , a mask (such as a photoresist) may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask (such as a photoresist) may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into exposed fins 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping level between about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implantation damage and activate implanted impurities.

[0040] exist Fig.9A and Fig. 9B , a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 may be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

[0041] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the gate sealing spacer 80 may not be etched before forming the gate spacer 86, thereby producing an "L-shaped" gate sealing spacer, a spacer may be formed and removed, etc.). In addition, different structures and steps may be used to form n-type and p-type devices. For example, an LDD region for an n-type device may be formed before forming the gate sealing spacer 80, and an LDD region for a p-type device may be formed after forming the gate sealing spacer 80.

[0042] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52 to apply stress in the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also penetrate the fins. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit a subsequently formed gate of the resulting FinFET.

[0043] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the region 50N may have surfaces that protrude from the corresponding surfaces of the fin 52 and may have facets.

[0044] The epitaxial source / drain regions 82 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the region 50P can also have a surface that protrudes from the corresponding surface of the fin 52 and can have a small facet.

[0045] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The source / drain regions may have a thickness between about 10 19 cm -3 and about 10 21 cm -3The n-type impurities and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0046] Due to the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets result in the merging of adjacent source / drain regions 82 of the same FinFET, such as Fig. 10C In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated, such as Fig. 10D As shown. Fig. 10C and Fig. 10D In the illustrated embodiment, gate spacers 86 are formed covering portions of the sidewalls of fins 52, extending over STI regions 56 to prevent epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material to allow epitaxial growth regions to extend to the surface of STI regions 56.

[0047] exist Fig.11A and Fig. 11B In the embodiment, a first interlayer dielectric layer (ILD) 88 is deposited on Fig. 10A and Fig. 10B 88 is formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., whose etching rate is different from the etching rate of the material overlying the first ILD 88.

[0048] exist Fig. 12A and Fig. 12BIn the process of planarizing, a planarization process such as CMP may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and the portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0049] exist Fig.13A and Fig. 13B In the etching step, the dummy gate 72 and the mask 74 (if present) are removed to form a groove 90. The portion of the dummy dielectric layer 60 in the groove 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains and is exposed through the groove 90. In some embodiments, the dummy dielectric layer 60 is removed from the groove 90 in the first area of ​​the tube core (e.g., the core logic area) and remains in the groove 90 in the second area of ​​the tube core (e.g., the input / output area). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each groove 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0050] exist Fig.14A and Fig. 14B In the process, a gate dielectric layer 92 and a gate electrode 94 for replacing a gate are formed. Fig. 14C Shows Fig. 14BDetailed view of region 89 of fin 52. Gate dielectric layer 92 is conformally deposited in recess 90, such as deposited on the top surface and sidewalls of fin 52 and on the sidewalls of gate seal spacer 80 / gate spacer 86. Gate dielectric layer 92 may also be formed on the top surface of first ILD 88. According to some embodiments, gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments in which a portion of dummy gate dielectric layer 60 remains in recess 90, gate dielectric layer 92 includes the material of dummy gate dielectric layer 60 (e.g., SiO2).

[0051] The gate electrode 94 is deposited over the gate dielectric layer 92 and fills the rest of the recess 90. The gate electrode 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig. 14B A single-layer gate electrode 94 is shown in FIG. 1 , but the gate electrode 94 may include any number of liner layers 94A, any number of work function regulating layers 94B and filling materials 94C, such as Fig. 14C As shown. After filling the recess 90, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 92 and the gate electrode 94 material that are above the top surface of the ILD 88. The gate electrode 94 material and the remaining portion of the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack 98". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0052] The formation of gate dielectric layer 92 in region 50N and region 50P may be performed simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 may be performed simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by different processes, such that gate dielectric layer 92 may be a different material, and / or gate electrode 94 in each region may be formed by different processes, such that gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0053] FIG. 15A to FIG. 22B Various intermediate process steps for forming conformal source / drain silicide and source / drain contacts are shown according to various embodiments. Fig.15A, Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A Shown along with Figure 1 The cross section along line BB is similar to the cross section except for the region between two adjacent gate stacks 98 . Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B and Fig. 22B Shown along with Figure 1 Although the cross section of the line CC is similar to the cross section of Fig. 10B A merged source / drain configuration is similar, but various embodiments may also be applied to Fig. 10C Similar separated source / drain regions (see, for example, Fig. 22C , which shows an embodiment source / drain contact 114 and conformal silicide 104 formed on unmerged epitaxial source / drain regions 82. In such embodiments, separate source / drain contacts may be formed to contact each of the separate source / drain regions. Alternatively, a common source / drain contact may be formed to contact two or more of the separate source / drain regions.

[0054] refer to Fig.15A and Fig. 15B , two gate stacks 98 are separated by the first ILD 88 and the CESL 97, and an epitaxial source / drain region 82 is formed between the two gate stacks 98. Fig. 15B In the merged source / drain configuration of the present invention, a void 91 may exist in a region below the epitaxial source / drain region 82 (e.g., a region below the merged boundary of the epitaxial source / drain region 82). The void 91 may be formed due to a deposition process used to form the first ILD 88. For example, the void may be formed by controlling the flow of a precursor gas into a region below the merged boundary of the epitaxial source / drain region 82. In alternative embodiments, the void may be omitted. In other alternative embodiments, the first ILD 88 may be completely omitted from below the merged boundary of the epitaxial source / drain region 82. For example, the void 91 may extend continuously between adjacent gate spacers 86, and the void 91 may extend from the epitaxial source / drain region 82 to the STI 56.

[0055] exist Fig.16A and Fig. 16BIn the embodiment, an opening 100 is formed to the source / drain epitaxial region 82. The opening 100 may be formed using acceptable photolithography techniques and etching techniques (e.g., a wet etching process and / or a dry etching process). The etching may be anisotropic. The opening 100 may be formed by etching the ILD 88 to expose the CESL 87. Then, the portion of the CESL 87 in the opening 100 may also be removed. The etchant used to etch the ILD 88 and the CESL 87 may be the same or different. Forming the opening 100 may further include etching the epitaxial source / drain region 82 so that the opening extends lower than the bottom of the gate stack 98. By over-etching the epitaxial source / drain region 82, the subsequently formed source / drain contact (see Fig.22A and Fig. 22B ) may be embedded into the epitaxial source / drain contacts 82 for a secure electrical connection.

[0056] exist Fig.17A and Fig. 17B In the embodiment, a first portion 104A of a silicide 104 is formed on the exposed area of ​​the epitaxial source / drain region 82 using a conformal deposition process 102 (see Fig.19A and Fig.19B ). The conformal deposition process 102 may be, for example, a PECVD process, which may be performed in a deposition chamber such as the deposition chamber 250 (see Fig.23 ). refer to Fig.23 , the deposition chamber 250 includes a radio frequency (RF) generator 252 (e.g., connected to ground and power), an RF controller 254, a showerhead 256, a wafer stage 258, a wall 260, and a controller 262. The showerhead 256 dispenses precursor chemicals into the deposition chamber 250, and the RF generator 252 converts the precursor chemicals into a plasma form, as controlled by the RF controller 254. The controller 262 may be used to control / stabilize the current applied to the wafer 10. In some embodiments, the controller 262 may include an impedance heater for the wafer stage 258. The wafer 10 is placed on the wafer stage 258. In some embodiments, the wafer stage 258 may include an electrostatic chuck. The wafer stage 258 may be connected to a voltage source that charges the wafer stage 258 and attracts plasma ions (e.g., precursor chemicals charged by the RF generator 252) to the top surface of the wafer 10 during the deposition process. The wall 260 of the deposition chamber 250 may also be grounded. Fig.23 An example deposition chamber is shown. However, other types of deposition chambers may also be used.

[0057] Fig. 17C The conformal deposition process 102 is schematically shown. Fig. 17C As shown, showerhead 256 distributes precursor chemicals 204 into a deposition chamber (e.g., Fig.23104 is a deposition chamber 250. In embodiments where the silicide 104 is titanium silicide, the precursor chemicals 204 may include titanium tetrachloride (TiCl4), hydrogen (H2), and argon (Ar). It has been observed that titanium is a desirable metal for forming silicides because it has a lower Schottky barrier height (SBH) and improved silicon consumption compared to other metals (e.g., nickel). In other embodiments, different metals (e.g., nickel, cobalt, etc.) may be deposited for silicided epitaxial source / drain regions 82. In such embodiments, the precursor chemicals 204 may be adjusted accordingly.

[0058] For example, using RF generator 252 (see Fig.23 ) excites the precursor chemical 204 and converts it into plasma 206. In an embodiment where the silicide 104 is titanium silicide, the precursor chemical 204 (e.g., including TiCl4, H2, and Ar) may be primarily converted into titanium trichloride (TiCl3), hydrogen ions (H * ) and argon ions (Ar *+ ), but titanium dichloride (TiCl2) and residual TiCl4 may also be present. For example, the plasma 206 may contain a greater amount of TiCl3 than TiCl2 or TiCl4, and most of the titanium chloride in the plasma 206 is TiCl2. The plasma 206 may further react at temperature, and thus a chlorine reduction reaction mechanism may then occur to deposit a titanium layer on the wafer 10, while generating hydrogen chloride (HCl) and argon as byproducts. The byproducts (e.g., HCl and argon) may be purged from the plasma converter by a pump.

[0059] TiCl3+H * +Ar *+ →Ti+HCl+Ar *

[0060] In various embodiments, the conformal deposition process 102 may be performed at a sufficiently high temperature to trigger the above-described chemical reaction of the plasma 206. For example, the processing temperature during the conformal deposition process 102 is at least about 400° C. The relatively high processing temperature (e.g., at least about 400° C.) is also high enough to cause the deposited titanium layer to intermix with the silicon molecules at the exposed surface of the epitaxial source / drain regions 82, which forms titanium silicide (e.g., the first portion 104A) according to a subsequent reaction mechanism. Therefore, a separate annealing step is not required to form the silicide, which increases manufacturing convenience and reduces cost.

[0061] Ti+Si→TiSi

[0062] During the conformal deposition process 102, the power, pressure, and / or gas flow of the RF generator 252 may be controlled to be relatively low. Thus, TiCl4 may be primarily converted to TiCl3 rather than titanium dichloride (TiCl2). For example, during the conformal deposition process 102, a LF power in the range of about 80 W to about 500 W; a HF power in the range of about 100 W to about 600 W; a pressure of about 4 Torr to about 10 Torr; and a gas flow rate of about 5 standard cubic centimeters per minute (sccm) to about 100 sccm may be used. It has been observed that the use of TiCl3 provides a deposition / etching type process that is selective to the crystal surface of the epitaxial source / drain region 82. Thus, the first portion 104A of the silicide 104 may be selectively grown on the epitaxial source / drain region 82 without significantly growing on other exposed surfaces of the wafer 10 (e.g., surfaces of the gate spacer 86, the gate stack 98, or the first ILD 88).

[0063] Furthermore, the conformal deposition process 102 may be a self-limiting process such that once the first portion 104A grows to thickness T1, the deposition process self-terminates. In some embodiments, thickness T1 may be in the range of about 2 nm to about 4 nm. The first portion 104A produced by the conformal deposition process 102 may be substantially conformal. For example, thickness T1 may be substantially uniform across the first portion 104A regardless of the underlying angle of the surface of the epitaxial source / drain region 82 on which the first portion 104A is deposited. For example, Fig.24 Experimental data plotting the thickness of a titanium silicide layer formed using an embodiment deposition method is shown. The x-axis corresponds to the angle of the underlying surface, and the y-axis corresponds to the thickness of the deposited titanium silicide. As shown by the root mean square (RMS) line of the experimental data, the thickness of the titanium silicide formed using the embodiment method is relatively uniform regardless of the angle of the underlying surface.

[0064] Reference again Fig. 17C , in some embodiments, the thickness T1 ranges from about 1.71 nm (e.g., at the thinnest point) to about 3.69 nm (e.g., at the thickest point). Due to process limitations, there may still be a difference between the minimum thickness of the first portion 104A and the maximum thickness of the first portion 104A. However, the first portion 104A can be conformal. For example, the ratio of the minimum thickness of the first portion 104A to the maximum thickness of the first portion 104A can be in the range of about 3.5:1 to about 5:1. It has been observed that by forming a silicide having a thickness variation within the above range, the source / drain contact resistance may be reduced due to the improved coverage of the silicide on the epitaxial source / drain region 82. In addition, the improved coverage of the silicide does not depend on the underlying angle of the surface of the source / drain region on which the silicide is formed.

[0065] Since the conformal deposition process 102 is a self-limiting process, a second deposition process may be performed to increase the thickness of the silicide and further reduce the source / drain contact resistance, such as 18A to 18C shown. Fig.18A and Fig.18B FIG. 1 shows a cross-sectional view of applying a second conformal deposition process 106 on the wafer 10 to form a second portion 104B of the silicide 104 (see FIG. 1 ). Fig.19A and Fig.19B ). The second portion 104B is formed on the first portion 104A. The conformal deposition process 106 may be performed in-situ as the conformal deposition process 102 (eg, in the same deposition chamber).

[0066] Fig. 18C The conformal deposition process 106 is schematically shown. Fig. 18C As shown, showerhead 256 continues to dispense precursor chemicals 204 into the deposition chamber (e.g., Fig.23 The precursor chemical 204 may be the same as the precursor chemical used during the conformal deposition process 102.

[0067] For example, using RF generator 252 (see Fig.23 ) excites the precursor chemical 204 and converts it into plasma 208. In an embodiment where the silicide 104 is titanium silicide, the precursor chemical 204 (e.g., including TiCl4, H2, and Ar) may be primarily converted into titanium dichloride (TiCl2), hydrogen ions (H * ) and argon ions (Ar *+ ), but TiCl3 and residual TiCl4 may also be present. For example, plasma 208 may contain a greater amount of TiCl2 than TiCl3 or TiCl4, and a majority of the titanium chloride in plasma 208 is TiCl2. Plasma 208 may further react at temperature, resulting in a subsequent chlorine reduction reaction mechanism that deposits a titanium layer on the exposed surface of wafer 10 while generating hydrogen chloride (HCl) as a byproduct.

[0068] TiCl2+H * +Ar *+ →Ti+HCl

[0069] In various embodiments, the conformal deposition process 106 may be performed at a temperature high enough to trigger a chemical reaction of the plasma 206. For example, the processing temperature during the conformal deposition process 106 is at least about 400°C.

[0070] During the conformal deposition process 106, the power, pressure, and / or gas flow of the RF generator 252 may be increased compared to the conformal deposition process 102. Thus, TiCl4 may be converted primarily into TiCl2, rather than TiCl3. For example, during the conformal deposition process 106, the following may be used: LF power in the range of about 80 W to about 500 W; HF power in the range of about 700 W to about 1500 W; pressure in the range of about 1 Torr to about 3 Torr; and gas flow rate in the range of about 5 sccm to about 100 sccm. It has been observed that by using TiCl2 as a reactant, the conformal deposition process 106 is not selective for the crystal surfaces of the epitaxial source / drain regions 82. Thus, titanium may be deposited on all exposed surfaces of the wafer 10, including the surfaces of the gate spacers 86, the gate stack 98, and the first ILD 88.

[0071] The relatively high processing temperature (e.g., at least about 400° C.) of the conformal deposition process 106 is also high enough to cause the titanium layer to continue to intermix with silicon molecules at the exposed surfaces of the epitaxial source / drain regions 82 and the first portion 104A, which produces titanium silicide according to a subsequent reaction mechanism. Therefore, no separate annealing step is required to form the silicide 104, which increases manufacturing convenience and reduces costs. For example, no additional annealing step is performed between the conformal deposition process 106 and the formation of the source / drain contacts 114 (see FIG. 22A to FIG. 22C ).

[0072] Ti+Si→TiSi

[0073] In addition, the chlorine-containing byproducts of the conformal deposition process 102 and / or 106 may react with the silicon nitride material of the gate spacer and break the bonding between the silicon molecules and the nitrogen molecules. Therefore, the titanium layer on the gate spacer 86 may also intermix with the silicon molecules to form titanium silicide on the gate spacer 86. In addition, the metal layer 104C in contact with the ILD 88 may react with the silicon oxide material of the ILD 88 to form a titanium oxide layer. Therefore, the portion of the metal layer 104C in contact with the ILD 88 may be converted into titanium oxide instead of titanium silicide.

[0074] The conformal deposition process 106 may be timed so that once the second portion 104B grows to a desired thickness T2, the deposition process terminates. The thickness T2 may be less than the thickness T1 of the first portion 104A. For example, in some embodiments, the thickness T2 may be in the range of about 1 nm to about 2 nm. The second portion 104B may be substantially conformal. For example, the thickness T2 across the second portion 104B is substantially uniform, regardless of the underlying angle of the surface on which the second portion 104B is grown. Due to process limitations, there may still be a difference between the minimum thickness of the second portion 104B and the maximum thickness of the second portion 104B. However, the second portion 104B may be conformal. For example, the ratio of the minimum thickness of the second portion 104B to the maximum thickness of the second portion 104B may be in the range of about 1:1 to about 1.5:1. It has been observed that by forming the silicide with a thickness variation within the above range, the source / drain contact resistance may be reduced due to the improved coverage of the silicide, which does not depend on the underlying angle of the surface of the source / drain region on which the silicide is formed. In addition, by forming a thin conformal silicide layer only on the sidewalls of the opening 100, the appearance of unnecessary protrusions on the sidewalls of the opening 100 can be avoided. In various embodiments, the mouth of the opening 100 remains relatively wide even after the second portion 104B is deposited. Therefore, before the source / drain contact is formed, it is not necessary to remove the silicide layer (e.g., the second portion 104B) from the sidewalls of the opening 100, which advantageously increases manufacturing convenience and reduces manufacturing costs.

[0075] After either or both of the conformal deposition processes 102 and 106, a purge step may be performed to remove byproducts from the deposition chamber. For example, when the silicide 104 is titanium silicide, chlorine-containing byproducts are produced. Excessive chlorine content in the silicide may cause harmful effects, such as increased source / drain contact resistance. Therefore, hydrogen can be pumped into the deposition chamber to remove byproducts from the surface of the chamber and wafer 10. In some embodiments, after the purge, trace amounts of chlorine molecules may remain in the first portion 104A and / or the second portion 104B. For example, less than about 0.5 atomic % chlorine may remain in the first portion 104A and / or the second portion 104B of the silicide. However, it has been observed that the chlorine content within this range is not sufficient to increase the source / drain contact resistance in the complete device.

[0076] Fig.19A and Fig.19B10. In some embodiments, the passivation process 108 may be performed in situ (e.g., in the same process chamber) using the conformal deposition processes 102 and 106. In some embodiments, the passivation process includes introducing a gas mixture containing ammonia and nitrogen into the deposition chamber. The ammonia and nitrogen are then converted into a plasma (e.g., using an RF generator 252, see Fig.23 ) to provide nitrogen ions. The nitrogen ions react with the exposed surface of the second portion 104B to form a nitride portion 104D. The combination of the nitride portion 104D and the first portion 104A is a silicide 104 for the epitaxial source / drain region 82. In an embodiment in which the silicide 104 is titanium silicide, the nitride portion 104D can be a titanium silicon nitride (TSN) layer on the epitaxial source / drain region 82 and the gate spacer 86, and the nitride portion 104D can be a titanium oxynitride layer on the ILD 88. The nitride portion 104D can have a thickness T2 in the range of, for example, about 1 nm to about 2 nm. A passivation process 108 can be performed to prevent oxidation of the silicide 104 in subsequent processing steps. It has been found that by forming a nitride layer in the above range, oxidation can be advantageously prevented without significantly increasing contact resistance.

[0077] Due to process limitations, there may still be a difference between the minimum thickness of the nitride portion 104D and the maximum thickness of the nitride portion 104D. However, the nitride portion 104D may be conformal. For example, the ratio of the minimum thickness of the nitride portion 104D to the maximum thickness of the nitride portion 104D may be in the range of about 2:1 to about 3:1. It has been observed that by forming a conformal nitride portion 104D, an excess overhang on the sidewall of the opening may be avoided, thereby eliminating the need for an etch-back process for removing the nitride portion 104D from the sidewall of the opening, which increases manufacturing convenience and reduces costs.

[0078] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, the liner 110 is deposited on the silicide 104. In some embodiments, the liner 110 may include a diffusion barrier layer, an adhesion layer, a combination thereof, etc. The liner 110 may include titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, a combination thereof, etc., and the liner 110 may be deposited using a conformal process such as CVD, PECVD, ALD, etc. The liner 110 may have a thickness T3, which may be in the range of about 1 nm to about 2 nm, such as about 1.2 nm.

[0079] Also like Fig. 20A and Fig. 20BAs shown, the rest of the opening 100 may be filled with metal 112. The metal 112 may be formed, for example, by first depositing a seed layer (e.g., using CVD, PECVD, ALD, etc.) and then performing an electroplating process. The metal 112 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc.

[0080] After electroplating, a planarization process such as CMP may be performed to remove excess material from the surface of the ILD 88 and the gate stack 98, such as Fig.21A and Fig.21B The remaining liner 110 and the conductive material 112 form source / drain contacts 114, which are electrically connected to the epitaxial source / drain regions 82 through the silicide 104. Since the silicide 104 is formed using a conformal deposition process, a reduced source / drain contact resistance (R csd For example, by including conformal silicide in both NMOS and PMOS finFET transistors, it has been observed that the R per fin of the finFET transistor csd Reduce from about 0.2kΩ to about 0.4kΩ.

[0081] exist Fig.22A and Fig. 22B In some embodiments, the second ILD 120 is deposited over the first ILD 88. In some embodiments, the second ILD 120 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 120 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD and PECVD. According to some embodiments, before the second ILD 120 is formed, the gate stack 98 (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is optionally recessed so that a groove is formed directly above the gate stack and between the opposing portions of the gate spacer 86, such as Fig.22A and Fig. 22B As shown. A gate mask 96 (comprising one or more layers of dielectric materials such as silicon nitride, silicon oxynitride, combinations thereof, etc.) is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 88. A subsequently formed gate contact 118 penetrates the gate mask 96 to contact the top surface of the recessed gate electrode 94. The recessing of the gate stack 98 and the formation of the gate mask 96 may be completed before or after the formation of the silicide 104 and / or the source / drain contacts 114.

[0082] According to some embodiments, a gate contact 118 and a second level source / drain contact 116 are formed through the second ILD 120. An opening for the source / drain contact 116 is formed through the second ILD 120, and an opening for the gate contact 118 is formed through the second ILD 120 and the gate mask 96. These openings can be formed using acceptable photolithography techniques and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 120. The remaining liner and conductive material form the source / drain contact 116 and the gate contact 118 in the opening. The source / drain contact 116 is physically and electrically coupled to the epitaxial source / drain region 82 through the source / drain contact 114, and the gate contact 118 is physically and electrically coupled to the gate electrode 94 of the gate stack 98. The source / drain contact 116 and the gate contact 118 can be formed in different processes, or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 116 and the gate contact 118 can be formed in different cross-sections, which can avoid shorting of the contacts.

[0083] Fig. 22C An alternative embodiment is shown in which source / drain contacts 114 and silicide 104 are formed on a single, unmerged epitaxial source / drain region 82 . Fig. 22C The various components are similar to Fig. 22B , where like reference numerals denote like elements formed using like processes. However, epitaxial source / drain regions 82 are unmerged source / drain regions that are not connected to any adjacent source / drain regions (eg, regions grown on adjacent fins).

[0084] Various example processes may also be used to form the silicide 104 and source / drain contacts 114 after the second ILD 120 is deposited. For example, FIG. 25A to FIG. 26B Such an embodiment is shown. Fig.25A and Fig.25B Similar to the corresponding Fig.16A and Fig. 16B , where the same reference numerals represent the same elements formed using the same process. Fig.25A and Fig.25B, source / drain contact openings 122 are patterned through both the first ILD 88 and the second ILD 120 using acceptable photolithography and etching processes. In this embodiment, the openings 122 are patterned after the second ILD 120 is deposited. In addition, although the second ILD 120 is shown as directly contacting the first ILD 88, one or more intermediate layers (e.g., etch stop layers) may be formed between the first ILD 88 and the second ILD 120. The openings 122 are etched through these intermediate layers.

[0085] exist Fig.26A and Fig.26B In the above, use FIG. 17A to FIG. 19B A similar process is described above to form silicide 104 (including first portion 104A and nitride portion 104D) on the exposed surface of epitaxial source / drain region 82. Nitride portion 104D of silicide 104 may be further formed on the sidewalls of opening 122, such as on the sidewalls of gate spacer 86, on the sidewalls of first ILD 88, and on the sidewalls of second ILD 120. FIG. 20A to FIG. 22C A similar process is described to form source / drain contacts 114 on the silicide 104 . In some embodiments, the source / drain contacts 114 may include a conformal liner 110 .

[0086] Various embodiments described herein include conformal silicide in the source / drain regions. Conformal silicide may allow for reduced source / drain contact resistance (R csd ). For example, by including conformal silicide in both NMOS and PMOS finFET transistors, it has been observed that the R per fin of the finFET transistor csd Reduced from about 0.2 kΩ to about 0.4 kΩ. Conformal silicide can be formed by depositing a metal (e.g., titanium, etc.) using a conformal deposition process. The conformal deposition process may include a plasma process, which may include a selective process combined with a non-selective process. Due to the conformal deposition process, the excess metal material protrusions on the sidewalls of the source / drain contact openings can be controlled, thereby eliminating a separate sidewall cleaning step for removing undesirable metal protrusions. The metal can also be deposited at a sufficient temperature to intermix with the crystalline material of the source / drain region, which eliminates the need for a separate annealing step after deposition. Therefore, the embodiment method can reduce the manufacturing steps, which advantageously increases manufacturing efficiency and reduces costs.

[0087] In some embodiments, a device includes: a gate stack; a gate spacer on a sidewall of the gate stack; a source / drain region adjacent to the gate stack; a silicide including: a conformal first portion extending into the source / drain region, the conformal first portion comprising metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising metal, silicon, and nitrogen; and a source / drain contact electrically connected to the source / drain region to the silicide. In some embodiments, the metal is titanium, the conformal first portion comprises titanium silicon (TiSi), and the conformal second portion comprises titanium silicon nitride (TSN). In some embodiments, the thickness of the conformal first portion is in the range of 2 nm to 4 nm. In some embodiments, the thickness of the conformal second portion is in the range of 1 nm to 2 nm. In some embodiments, the source / drain contact comprises: a liner; and a metal, the metal being above the liner. In some embodiments, the silicide comprises chlorine. In some embodiments, the chlorine in the silicide is less than 0.5 atomic percent.

[0088] In some embodiments, a device includes: a gate stack, the gate stack is above a channel region of a transistor; a gate spacer, the gate spacer is on a sidewall of the gate stack; a source / drain region, the source / drain region is adjacent to the channel region; a silicide, the silicide extends into the source / drain region, the silicide includes: a titanium silicon portion, wherein the ratio of the minimum thickness of the titanium silicon portion to the maximum thickness of the titanium silicon portion is in the range of 3.5:1 to 5:1; and a silicon titanium nitride portion, the silicon titanium nitride portion is on the titanium silicon portion, wherein the ratio of the minimum thickness of the silicon titanium nitride portion to the maximum thickness of the silicon titanium nitride portion is in the range of 1:1 to 1.5:1; and a source / drain contact, the source / drain contact is electrically connected to the source / drain region through the silicide. In some embodiments, the silicon titanium nitride portion is above the silicon titanium nitride portion and extends along the side of the silicon titanium nitride portion. In some embodiments, the silicon titanium nitride portion extends along the sidewall of the gate spacer. In some embodiments, the device further comprises a first interlayer dielectric layer (ILD) surrounding the gate stack, wherein the silicide extends along the sidewalls of the first ILD. In some embodiments, the device further comprises a second ILD above the first ILD and the gate stack, wherein the silicide extends along the sidewalls of the second ILD.

[0089] In some embodiments, a method includes: patterning an opening through an interlayer dielectric (ILD), wherein the opening exposes a surface of a source / drain region; forming a silicide in the opening, wherein forming the silicide includes: performing a first conformal deposition process to form a first metal-containing portion on the source / drain region; performing a second conformal deposition process to form a second metal-containing portion on the first metal-containing portion, wherein the process parameters of the first conformal deposition process are different from the second conformal deposition process; and performing a passivation process on the second metal-containing portion; and forming a source / drain contact in the opening over the silicide. In some embodiments, the first conformal deposition process and the second conformal deposition process are each performed at a temperature of at least 400° C. In some embodiments, no annealing process is performed between the second conformal deposition process and forming the source / drain contact. In some embodiments, the first conformal deposition process and the second conformal deposition process each include using a TiCl4 precursor, wherein the first conformal deposition process includes a first plasma process that converts a majority of the TiCl4 precursor into TiCl3, and wherein the second conformal deposition process includes a second plasma process that converts a majority of the TiCl4 precursor into TiCl2. In some embodiments, the second conformal deposition process has a higher power, pressure, gas flow, or a combination thereof than the first conformal deposition process. In some embodiments, a passivation process is performed to convert the second metal-containing portion into a nitride. In some embodiments, the method further comprises performing a purge process to remove byproducts of the first conformal deposition process or the second conformal deposition process. In some embodiments, the opening exposes a sidewall of the gate spacer, the second conformal deposition process forms the second metal-containing portion on the sidewall of the gate spacer, and the second metal-containing portion is not removed from the sidewall of the gate spacer.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a gate stack; a gate spacer located on a sidewall of the gate stack; a source / drain region adjacent to the gate stack; Silicides, including: a conformal first portion extending into the source / drain region, the conformal first portion comprising metal and silicon; and a conformal second portion located above the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen, the silicide comprising chlorine; and A source / drain contact is electrically connected to the source / drain region through the silicide.

2. The semiconductor device according to claim 1, wherein The metal is titanium, the conformal first portion comprises titanium silicon (TiSi), and the conformal second portion comprises titanium silicon nitride (TSN).

3. The semiconductor device according to claim 1, wherein The conformal first portion has a thickness in a range of 2 nm to 4 nm.

4. The semiconductor device according to claim 1, wherein The conformal second portion has a thickness in the range of 1 nm to 2 nm.

5. The semiconductor device according to claim 1, wherein The source / drain contact comprises: Padding; and A metal is located above the pad.

6. The semiconductor device according to claim 1, wherein The conformal first portion and the conformal second portion each contain chlorine.

7. The semiconductor device according to claim 6, wherein: The chlorine in the silicide is less than 0.5 atomic %.

8. A semiconductor device comprising: a gate stack located above a channel region of the transistor; a gate spacer located on a sidewall of the gate stack; a source / drain region adjacent to the channel region; A silicide extending into the source / drain region, the silicide comprising: a titanium silicon portion, wherein a ratio of a minimum thickness of the titanium silicon portion to a maximum thickness of the titanium silicon portion is in a range of 1:3.5 to 1:5; and a titanium silicon nitride portion, the titanium silicon nitride portion being located on the titanium silicon portion, wherein a ratio of a minimum thickness of the titanium silicon nitride portion to a maximum thickness of the titanium silicon nitride portion is in a range of 1:1 to 1:1.5; and A source / drain contact is electrically connected to the source / drain region through the silicide.

9. The semiconductor device according to claim 8, wherein: The titanium silicon nitride portion extends over the titanium silicon portion and along sides of the titanium silicon portion.

10. The semiconductor device according to claim 8, wherein The titanium silicon nitride portion extends along sidewalls of the gate spacer. 11 . The semiconductor device according to claim 8 , further comprising a first interlayer dielectric layer surrounding the gate stack, wherein the silicide extends along a sidewall of the first interlayer dielectric layer.

12. The semiconductor device according to claim 11, further comprising a second interlayer dielectric layer located above the first interlayer dielectric layer and the gate stack, wherein The silicide extends along a sidewall of the second interlayer dielectric layer.

13. A method of forming a semiconductor device, comprising: patterning openings through the interlayer dielectric layer, wherein the openings expose surfaces of the source / drain regions; Forming a silicide in the opening, wherein forming the silicide comprises: performing a first conformal deposition process to form a first metal-containing portion on the source / drain region; performing a second conformal deposition process to form a second metal-containing portion on the first metal-containing portion, wherein a process parameter of the first conformal deposition process is different from a process parameter of the second conformal deposition process, and the first conformal deposition process and the second conformal deposition process are each performed at a temperature of at least 400° C.; and performing a passivation process on the second metal-containing portion; and Source / drain contacts are formed in the openings over the silicide.

14. The method according to claim 13, wherein: The first metal-containing portion comprises titanium.

15. The method according to claim 13, wherein: No annealing process is performed between the second conformal deposition process and the forming of the source / drain contacts.

16. The method according to claim 13, wherein: The first conformal deposition process and the second conformal deposition process each include using a TiCl4 precursor, wherein the first conformal deposition process includes a first plasma process that converts a majority of the TiCl4 precursor into TiCl3, and wherein the second conformal deposition process includes a second plasma process that converts a majority of the TiCl4 precursor into TiCl2.

17. The method according to claim 16, wherein: The second conformal deposition process has a higher power, pressure, gas flow, or a combination thereof than the first conformal deposition process.

18. The method according to claim 13, wherein: The passivation process is performed to convert the second metal-containing portion into a nitride. 19 . The method of claim 13 , further comprising performing a purge process to remove byproducts of the first conformal deposition process or the second conformal deposition process.

20. The method according to claim 13, wherein: The opening exposes sidewalls of the gate spacer, wherein the second conformal deposition process forms the second metal-containing portion on the sidewalls of the gate spacer, and wherein the second metal-containing portion is not removed from the sidewalls of the gate spacer.

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