Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising: a plurality of device regions and an isolation region between adjacent device regions, the device region having a fin, the device region and the isolation region having an isolation structure, and the isolation structure covering a portion of the sidewall surface of the fin; forming a work function layer across the fin on the isolation region and the device region; after forming the work function layer, forming a segment on the surface of the isolation structure on the isolation region, and the segment penetrates the work function layer; after forming the segment, forming a gate layer across the fin on the device region, and the gate layer covers the sidewall surface of the segment. The method is conducive to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the control ability of the traditional planar metal-oxide semiconductor field effect transistor (MOSFET) on the channel current becomes weak, resulting in serious leakage current. The fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of the semiconductor substrate, a gate structure covering part of the top surface and sidewall of the fin, and source and drain doping regions in the fin on both sides of the gate structure. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has a stronger short channel suppression capability and a stronger operating current, and is now widely used in various semiconductor devices.

[0003] However, when the size of the device is further reduced, for example, in the case of a fin field effect transistor, the difficulty of forming a partition in the gate structure will increase, thereby hindering the improvement of the overall circuit performance brought about by the miniaturization of the device.

[0004] The performance of the semiconductor structure formed by the existing fin field effect transistor (Fin FET) needs to be improved urgently. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising: a plurality of device regions and an isolation region located between adjacent device regions, the device region having a fin, the device region and the isolation region having an isolation structure, and the isolation structure covering a portion of the side wall surface of the fin; forming a work function layer across the fin on the isolation region and the device region; after forming the work function layer, forming a segment on the surface of the isolation structure on the isolation region, and the segment runs through the work function layer; after forming the segment, forming a gate layer across the fin on the device region, and the gate layer covers the side wall surface of the segment.

[0007] Optionally, a top surface of the segment is higher than a top surface of the fin.

[0008] Optionally, the method for forming the segmentation segment includes: forming a sacrificial layer on the substrate, the sacrificial layer covering the surface of the work function layer; forming a first opening in the sacrificial layer and the work function layer, the first opening exposing the substrate surface of the isolation region; forming a segmentation material film in the first opening and on the surface of the sacrificial layer, the segmentation material film filling the first opening; flattening the segmentation material film until the surface of the sacrificial layer is exposed, and forming the segmentation segment in the first opening.

[0009] Optionally, the material of the split material film includes an insulating material.

[0010] Optionally, the method for forming the sacrificial layer includes: before forming the work function layer, forming a dummy gate structure across the fin on the substrate, the dummy gate structure being located on the surface of the isolation structure; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the dummy gate structure; removing the dummy gate structure to form a second opening in the dielectric; and filling the second opening with a sacrificial film material to form a sacrificial layer.

[0011] Optionally, the material of the sacrificial layer is different from the material of the work function layer.

[0012] Optionally, the method for forming the first opening includes: forming a mask layer on the surface of the sacrificial layer, the mask layer exposing the surface of the sacrificial layer on the isolation area; using the mask layer as a mask, etching the sacrificial layer and the work function layer until the surface of the substrate is exposed, thereby forming the first opening in the sacrificial layer and the work function layer.

[0013] Optionally, it also includes: after forming the second opening and before forming the work function layer, forming a gate dielectric layer on the top surface and side wall surface of the fin exposed by the second opening; after forming the gate dielectric layer, forming the work function layer and a sacrificial layer located on the surface of the work function layer on the surface of the gate dielectric layer; forming the first opening in the sacrificial layer and the work function layer, and the bottom of the first opening exposes the surface of the gate dielectric layer.

[0014] Optionally, the method further includes: etching the gate dielectric layer exposed at the bottom of the first opening to form a third opening in the gate dielectric layer; and forming the segmentation segment in the first opening and the third opening.

[0015] Optionally, the material of the gate dielectric layer includes silicon oxide or high-K dielectric material.

[0016] Optionally, the method for forming the gate layer includes: forming a gate material film on the surface of the work function layer, the surface of the segment, and the surface of the dielectric layer at the bottom of the second opening, wherein the gate material film covers the side wall surface of the segment; flattening the gate material film until the top surface of the segment is exposed, and forming the gate layer in the second opening, wherein the gate layer is located on the surface of the work function layer.

[0017] Optionally, the material of the gate layer includes: polysilicon or metal.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0019] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a segment is formed on the isolation region; after the segment is formed, a gate layer across the fin is formed on the device region. Since the isolation region is located between adjacent device regions and the gate layer covers the sidewall surface of the segment, the segment located on the isolation region can separate the gate layer on the adjacent device region, thereby meeting the process requirements.

[0020] Furthermore, the material of the sacrificial layer includes: amorphous silicon, amorphous carbon, polycrystalline silicon, silicon oxycarbide or silicon oxyhydrogen carbide. The sacrificial layer is etched by an existing etching process, so that the etching process difficulty of forming the first opening in the sacrificial layer is relatively low, and it is not easy to generate residues in the first opening. Furthermore, the process difficulty of filling the first opening of the sacrificial layer with an isolation material to form a segment is reduced, and less residue is conducive to improving the morphology and filling effect of the segment formed in the first opening, so that the isolation effect of the segment formed is better, so that the performance of the formed semiconductor structure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 5 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0022] Figures 6 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] As described in the background art, the performance of existing semiconductor structures is poor.

[0024] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 5 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0025] Please refer to Figure 1, providing a substrate 100, wherein the substrate 100 includes: a device region I and an isolation region II, wherein the isolation region II is located between adjacent device regions I, wherein the device region I has a fin 110, wherein the device region I and the isolation region II have an isolation structure 111, and wherein the isolation structure 111 covers a portion of the sidewall surface of the fin 110.

[0026] Please refer to Figure 2 and Figure 3 , Figure 3 For Figure 1 Based on the schematic diagram, Figure 3 for Figure 2 A cross-sectional schematic diagram along the A-A1 tangent direction shows that a dielectric layer 120 is formed on the substrate 100 , and a first opening 121 is provided in the dielectric layer 120 , wherein a portion of the top surface and the sidewall surface of the fin 110 and the surface of the isolation structure 111 are exposed in the first opening 121 .

[0027] Please refer to Figure 4 , Figure 4 For Figure 3 Based on the schematic diagram, an initial gate structure 130 is formed in the first opening 121 , and the initial gate structure 130 spans a portion of the top surface and the sidewall surface of the fin 110 .

[0028] Please refer to Figure 5 , Figure 5 For Figure 4 Based on the schematic diagram, a second opening (not shown in the figure) is formed in the initial gate structure 130, so that the initial gate structure 130 forms a gate structure 140, and the second opening exposes the surface of the isolation structure 111 on the isolation region II and the side wall surface of the gate structure 140; a segmentation segment 150 is formed in the second opening.

[0029] In the above method, a second opening is formed in the initial gate structure 130, and the second opening exposes the surface of the isolation structure 211 on the isolation region II; a segmentation segment 150 is formed in the second opening, so that the segmentation segment 150 on the isolation region II can effectively isolate the gate structure 140 on the adjacent device region I to meet specific process requirements.

[0030] However, since the initial gate structure 130 includes: an initial gate dielectric layer (not shown in the figure), an initial work function layer (not shown in the figure) located on the surface of the initial gate dielectric layer, and an initial gate electrode layer (not shown in the figure) located on the surface of the initial work function layer, and the material of the initial gate electrode layer includes: metal, such as copper. Due to the current difficulty in etching metal, on the one hand, it is not easy to form the second opening in the initial gate structure 130; on the other hand, it is easy to have residues in the second opening, thereby affecting the isolation effect of the segmentation segment 150 formed in the second opening, and even generating leakage current.

[0031] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a work function layer across the fin on the isolation region and the device region; after forming the work function layer, forming a segment on the surface of the isolation structure on the isolation region, and the segment penetrates the work function layer; after forming the segment, forming a gate layer across the fin on the device region, and the gate layer covers the sidewall surface of the segment. By forming the gate layer after forming the segment, the process difficulty is reduced, and the performance of the formed semiconductor structure is improved.

[0032] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figures 6 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0034] A substrate is provided, comprising: a plurality of device regions and an isolation region between adjacent device regions, wherein the device region has a fin, the device region and the isolation region have an isolation structure, and the isolation structure covers a part of the sidewall surface of the fin.

[0035] Please refer to Figure 6 , providing a substrate 200, wherein the substrate 200 includes: a plurality of device regions I and a partition region II located between adjacent device regions I.

[0036] The material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0037] Please continue to refer to Figure 6 A fin 210 is formed on the device region I, and an isolation structure 211 is formed on the device region I and the isolation region II, and the isolation structure 211 covers a portion of the sidewall surface of the fin 210 .

[0038] In this embodiment, the method for forming the fin 210 includes: forming a fin material film on the substrate 200 ; and patterning the fin material film to form the fin 210 on the substrate 200 .

[0039] In other embodiments, the base and the fin may be formed by patterning a substrate, thereby forming a base and a fin located on the base.

[0040] The number of the fins 210 located on the device region I is one or more.

[0041] In this embodiment, the number of the fins 210 respectively located on one of the device regions I is two.

[0042] The material of the isolation structure 211 is an insulating material, which includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride.

[0043] In this embodiment, the material of the isolation structure 211 is silicon oxide.

[0044] The isolation structure 211 is used to achieve electrical isolation between different devices.

[0045] Next, a dielectric layer is formed on the substrate 200, wherein the dielectric layer has a second opening, and the second opening exposes a portion of the top surface and the sidewall surface of the fin 210. For details on the process of forming the dielectric layer and the second opening in the dielectric layer, please refer to Figures 7 to 9 .

[0046] Please refer to Figure 7 and Figure 8 , Figure 8 For Figure 6 Based on the schematic diagram, Figure 7 for Figure 8 A cross-sectional schematic diagram along the A2-A3 tangent direction shows that a dummy gate structure 220 is formed on the substrate 200 across the fin 210, and the dummy gate structure 220 is located on the surface of the isolation structure 211; a dielectric layer 230 is formed on the substrate 200, and the dielectric layer 230 covers the side walls of the dummy gate structure 220.

[0047] The dummy gate structure 220 is used in a gate-last process to prepare for the subsequent formation of a gate structure.

[0048] The method for forming the pseudo gate structure 220 includes: forming a pseudo gate dielectric material film covering the surface of the fin 210 on the substrate 200; forming a pseudo gate electrode material film (not shown in the figure) on the pseudo gate dielectric material film; forming a patterned layer on the surface of the pseudo gate electrode material film, wherein the patterned layer covers a portion of the pseudo gate electrode material film; using the patterned layer as a mask, etching the pseudo gate dielectric material film and the pseudo gate electrode material film until the surface of the isolation structure 211 is exposed, thereby forming a pseudo gate structure 220 across the fin 210 on the substrate 200.

[0049] It should be noted that the top surface of the dielectric layer 230 is higher than the top surface of the fin 210 .

[0050] Please refer to Fig. 9 , Fig. 9 For Figure 8 Based on the schematic diagram, the dummy gate structure 220 is removed, and a second opening 231 is formed in the dielectric layer 230 .

[0051] The second opening 231 provides a space for subsequently forming a sacrificial layer.

[0052] The second opening 231 exposes a portion of the top surface and the sidewall surface of the fin 210 .

[0053] The process of removing the dummy gate structure 220 includes: one or a combination of dry etching process and wet etching process.

[0054] In this embodiment, the process for removing the dummy gate structure 220 is a combination of a dry etching process and a wet etching process.

[0055] Please refer to Fig.10 A gate dielectric layer 241 is formed on the top surface and the sidewall surface of the fin 210 exposed by the second opening 231 .

[0056] The gate dielectric layer 241 is a part of a gate structure formed subsequently.

[0057] The gate dielectric layer 241 may be made of silicon oxide or a high-K dielectric material. The high-K (greater than 3.9) dielectric material may be made of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0058] In this embodiment, the gate dielectric layer 241 is made of a high-K dielectric material, such as hafnium oxide.

[0059] In other embodiments, before forming the gate dielectric layer, the method for forming the semiconductor structure further includes: forming an interface layer on the top surface and sidewall surface of the fin exposed by the second opening. The interface layer is beneficial to improving interface defects, thereby improving the performance of the formed semiconductor structure.

[0060] Please refer to Fig.11 After forming the gate dielectric layer 241 , the work function layer 242 is formed on the surface of the gate dielectric layer 241 .

[0061] The work function layer 242 is used to adjust the threshold voltage of the formed device.

[0062] The material of the work function layer 242 includes titanium nitride, titanium aluminum or tantalum nitride.

[0063] In this embodiment, the semiconductor structure is a P-type device, and the material of the work function layer is titanium nitride or tantalum nitride. In other embodiments, the semiconductor structure is an N-type device, and the material of the work function layer is titanium aluminum.

[0064] After the work function layer 242 is formed, a segment is formed on the surface of the isolation structure 211 on the isolation region II, and the segment runs through the work function layer 212. For the specific process of forming the segment, please refer to Figure 12 to Figure 14 .

[0065] Please refer to Fig.12 , a sacrificial layer 250 is formed on the substrate 200 , and the sacrificial layer 250 covers the surface of the work function layer 242 .

[0066] In this embodiment, the method for forming the sacrificial layer 250 includes: filling a sacrificial film material in the second opening 231 , thereby forming the sacrificial layer 250 .

[0067] The formation process of the sacrificial layer 250 includes: a chemical vapor deposition process, a physical vapor deposition process or a spin coating process.

[0068] The material of the sacrificial film is different from that of the work function layer 242 .

[0069] The material of the sacrificial film is different from that of the work function layer 242. Accordingly, the material of the formed sacrificial layer 250 is different from that of the work function layer 242. This ensures that when the sacrificial layer 250 is subsequently removed to expose the second opening 231, no etching damage will be caused to the work function layer 242 exposed at the bottom of the second opening 231, thereby ensuring that the work function layer 242 has a certain thickness, so that the performance of the formed semiconductor structure is better.

[0070] The material of the sacrificial film includes: amorphous silicon, amorphous carbon, polysilicon, silicon oxycarbide or silicon oxyhydrocarbide.

[0071] The material of the sacrificial layer 250 includes: amorphous silicon, amorphous carbon, polycrystalline silicon, silicon oxycarbide or silicon oxyhydrogen carbide. The sacrificial layer 250 is etched by the existing etching process, so that the etching process difficulty of forming the first opening 251 in the sacrificial layer 250 is relatively low, and it is not easy to generate residues in the first opening 251. Furthermore, the subsequent process difficulty of filling the first opening 251 of the sacrificial layer 250 with isolation material to form a segment is reduced, and less residue is conducive to improving the morphology and filling effect of the segment formed in the first opening 251, so that the isolation effect of the formed segment is better, so that the performance of the formed semiconductor structure is improved.

[0072] In this embodiment, the material of the sacrificial film is amorphous silicon, and accordingly, the material of the sacrificial layer 250 is amorphous silicon. The amorphous silicon is used as the sacrificial film material, and the amorphous silicon is an organic material with fluidity, which can be well filled in the second opening 231; on the other hand, the surface of the formed sacrificial layer 250 is relatively flat, so that a mask layer can be directly formed on the surface of the sacrificial layer 250 for patterning processing, thereby saving process steps.

[0073] It should be noted that, in this embodiment, the top surface of the sacrificial layer 250 is flush with the top surface of the dielectric layer 230 , and the top surface of the sacrificial layer 250 is higher than the top surface of the fin 210 .

[0074] Please refer to Fig.13 , a mask layer 260 is formed on the surface of the sacrificial layer 250, and the mask layer 260 exposes the surface of the sacrificial layer 250 on the isolation region II; using the mask layer 260 as a mask, the sacrificial layer 250 and the work function layer 242 are etched until the surface of the substrate 200 is exposed, and a first opening 251 is formed in the sacrificial layer 250 and the work function layer 242.

[0075] The first opening 251 provides space for subsequently forming a segment.

[0076] The process of etching the sacrificial layer 250 and the work function layer 242 includes: a dry etching process and a wet etching process or a combination of the two.

[0077] In this embodiment, the process of etching the sacrificial layer 250 and the work function layer 242 is a dry etching process, and the etching gas used to etch the sacrificial layer 250 includes: SF6, Cl2 or HBr; the etching gas used to etch the work function layer 242 includes: Cl2, BCl3 or CH4.

[0078] In this embodiment, the method for forming the semiconductor structure further includes: etching the gate dielectric layer 241 exposed at the bottom of the first opening 251 to form a third opening 252 in the gate dielectric layer 241 .

[0079] The third opening 252 and the first opening 251 together provide space for the subsequent formation of segmented segments.

[0080] The process of etching the gate dielectric layer 241 includes: a dry etching process and a wet etching process, or a combination of the two.

[0081] In this embodiment, after the first opening 251 and the third opening 252 are formed, the mask layer 260 is removed.

[0082] Please refer to Fig.14 , a splitting material film (not shown in the figure) is formed in the first opening 251 and on the surface of the sacrificial layer 250, and the splitting material film fills the first opening 251; the splitting material film is flattened until the surface of the sacrificial layer 250 is exposed, and the splitting segment 270 is formed in the first opening 251.

[0083] Specifically, in this embodiment, the dividing material film is formed in the first opening 251 and the third opening 252 , so that the formed dividing segment 270 is located in the first opening 251 and the third opening 252 .

[0084] The material of the dividing material film includes: insulating material.

[0085] The insulating material includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride.

[0086] The process for forming the segmentation material film includes: chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0087] In this embodiment, the formation process of the segmentation material film is an atomic layer deposition process. The atomic layer deposition process can form a dense and high-quality film layer, so that the formed segmentation segment 270 can have a good isolation effect on the gate structure on the adjacent device area I.

[0088] In this embodiment, the top surface of the sacrificial layer 250 is higher than the top surface of the fin 210 , so that the top surface of the segmentation segment 270 formed after planarizing the segmentation material film is higher than the top surface of the fin 210 .

[0089] Since the top surface of the gate structure formed subsequently is higher than the top surface of the fin 210 , the top surface of the segment 270 is higher than the top surface of the fin 210 to ensure that the segment 270 can fully isolate the gate structure on the adjacent device region I.

[0090] After forming the segment 270, a gate layer is formed on the device region I across the fin 210, and the gate layer covers the sidewall surface of the segment 270. For the specific process of forming the gate layer, please refer to Figure 15 to Figure 16 .

[0091] Please refer to Fig.15 After forming the segmentation segment 270 , the sacrificial layer 250 is removed to expose the second opening 231 in the dielectric layer 230 .

[0092] Specifically, the second opening 231 exposes the surface of the dividing segment 270 .

[0093] The process of removing the sacrificial layer 250 includes: one or a combination of dry etching, wet etching and ashing.

[0094] In this embodiment, the material of the sacrificial layer 250 is amorphous silicon, and thus the sacrificial layer 250 is removed by an ashing process, which is simple and helps to improve production efficiency.

[0095] Please refer to Fig.16 A gate material film (not shown in the figure) is formed on the surface of the work function layer 242 at the bottom of the second opening 231, the surface of the segment 270, and the surface of the dielectric layer 230, and the gate material film covers the side wall surface of the segment 270; the gate material film is flattened until the top surface of the segment 270 is exposed, and the gate layer 280 is formed in the second opening 231, and the gate layer 280 is located on the surface of the work function layer 242.

[0096] The gate dielectric layer 241 , the work function layer 242 located on the surface of the gate dielectric layer 241 , and the gate layer 280 located on the surface of the work function layer 242 together constitute a gate structure.

[0097] The segmentation segment 270 is formed on the isolation region II; after the segmentation segment 270 is formed, a gate layer 280 is subsequently formed on the device region II across the fin 210. Since the isolation region II is located between adjacent device regions I, and the gate layer 280 covers the sidewall surface of the segmentation segment 270, the segmentation segment 270 located on the isolation region II can separate the gate layer 280 on the adjacent device region I, thereby meeting the process requirements.

[0098] Thus, a gate structure spanning the fin 210 is formed in the first opening 231 through the gate-last process, and the segmentation segment 270 on the isolation region II fully isolates the gate structure located on the device region I.

[0099] The material of the gate layer 280 includes polysilicon or metal.

[0100] The metal material includes: one or a combination of copper, tungsten, cobalt, aluminum, titanium, titanium nitride, and tantalum.

[0101] In this embodiment, the material of the gate layer 280 is tungsten.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising: a plurality of device regions and an isolation region located between adjacent device regions, the device region having a fin, the device region and the isolation region having an isolation structure, and the isolation structure covering a portion of the sidewall surface of the fin; forming a work function layer across the fin on the isolation region and the device region; After forming the work function layer, forming a segment on the surface of the isolation structure on the isolation region, and the segment runs through the work function layer; After forming the segmentation segment, forming a gate layer across the fin portion on the device region, wherein the gate layer covers the sidewall surface of the segmentation segment; The method for forming the segmentation segment comprises: forming a sacrificial layer on the substrate, the sacrificial layer covering the surface of the work function layer; forming a first opening in the sacrificial layer and the work function layer, the first opening exposing the substrate surface of the isolation region; forming a segmentation material film in the first opening and on the surface of the sacrificial layer, the segmentation material film filling the first opening; flattening the segmentation material film until the surface of the sacrificial layer is exposed, and forming the segmentation segment in the first opening; The method for forming the sacrificial layer comprises: before forming the work function layer, forming a dummy gate structure across the fin on the substrate, the dummy gate structure being located on the surface of the isolation structure; forming a dielectric layer on the substrate, the dielectric layer covering the sidewall of the dummy gate structure; forming a second opening in the dielectric by removing the dummy gate structure; filling the second opening with a sacrificial film material, thereby forming a sacrificial layer; The material of the sacrificial layer is amorphous silicon; the process of etching the sacrificial layer is a dry etching process, and the etching gas for etching the sacrificial layer includes SF6, Cl2 or HBr.

2. The method for forming a semiconductor structure according to claim 1, wherein: A top surface of the segment is higher than a top surface of the fin.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the partition material film includes an insulating material.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer is different from that of the work function layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening includes: forming a mask layer on the surface of the sacrificial layer, the mask layer exposing the surface of the sacrificial layer on the isolation area; using the mask layer as a mask, etching the sacrificial layer and the work function layer until the substrate surface is exposed, thereby forming the first opening in the sacrificial layer and the work function layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the second opening and before forming the work function layer, forming a gate dielectric layer on the top surface and the sidewall surface of the fin exposed by the second opening; After forming the gate dielectric layer, the work function layer and the sacrificial layer located on the surface of the work function layer are formed on the surface of the gate dielectric layer; the first opening is formed in the sacrificial layer and the work function layer, and the bottom of the first opening exposes the surface of the gate dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: Etching the gate dielectric layer exposed at the bottom of the first opening to form a third opening in the gate dielectric layer; The segment is formed in the first opening and the third opening.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the gate dielectric layer includes silicon oxide or high-K dielectric material.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the gate layer includes: forming a gate material film on the surface of the work function layer, the surface of the segment, and the surface of the dielectric layer at the bottom of the second opening, wherein the gate material film covers the side wall surface of the segment; flattening the gate material film until the top surface of the segment is exposed, and forming the gate layer in the second opening, wherein the gate layer is located on the surface of the work function layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate layer includes: polysilicon or metal.

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