Multi-gate device and method for forming the same

Abstract

The present invention relates to a multi-gate device and a method for forming the same. An exemplary device includes a channel layer, a first epitaxial source / drain component, and a second epitaxial source / drain component disposed above a substrate. The channel layer is disposed between the first epitaxial source / drain component and the second epitaxial source / drain component. A metal gate is disposed between the first epitaxial source / drain component and the second epitaxial source / drain component. The metal gate is disposed above and in physical contact with at least two sides of the channel layer. A source / drain contact is disposed above the first epitaxial source / drain component. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source / drain component and the source / drain contact. The doped crystalline semiconductor layer is disposed above and in physical contact with at least two sides of the first epitaxial source / drain component. In some embodiments, the doped crystalline semiconductor layer has a CuO electrode of less than about 1x10 ‑9 Ω‑cm 2 The contact resistivity.

Description

Technical Field

[0001] Embodiments of the present application relate to a multi-gate device and a method for forming the same. Background Art

[0002] Multi-gate devices have been introduced to meet the growing demands of the integrated circuit (IC) industry for smaller and faster electronic devices that can simultaneously support an increasing number of increasingly complex and sophisticated functions. Multi-gate devices have a gate extending partially or fully around a channel region to provide access to the channel region on at least two sides. Exemplary multi-gate devices include fin field effect (FinFET) transistors, gate-all-around (GAA) transistors (e.g., nanowire-based transistors), and / or other three-dimensional (3D) transistors, all of which may be referred to as non-planar transistors. Multi-gate devices enable large-scale scaling of IC technology and have been observed to improve gate control, increase gate-channel coupling, reduce off-state current, and / or reduce short channel effects (SCEs) while seamlessly integrating with conventional IC manufacturing processes. Typically, scaling of multi-gate devices has been limited only by lithography techniques to define IC components at ever-decreasing geometries, but recently, as geometries have been reduced to enable multi-gate devices using faster operating speeds (e.g., by reducing the distance that electrical signals travel), parasitic resistance-capacitance (RC) delays have become a significant challenge, negating some of the advantages achieved by scaling and limiting further scaling of multi-gate devices. For example, reducing the source / drain contact size has resulted in an increase in source / drain contact resistance (i.e., the resistance to current flow at a metal-semiconductor contact interface, such as the resistance between a source / drain component comprising a semiconductor and a source / drain contact comprising a metal). One solution to reducing source / drain contact resistance is to reduce the contact resistivity at the metal-semiconductor contact interface. However, current contact resistivity reduction methods are incompatible with the manufacture of non-planar transistors. Therefore, although existing source / drain contact structures for multi-gate devices and methods for manufacturing existing source / drain contact structures are generally sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the invention

[0003] An embodiment of the present application provides a device comprising: a channel layer, a first epitaxial source / drain component, and a second epitaxial source / drain component, which are arranged above a substrate, wherein the channel layer is arranged between the first epitaxial source / drain component and the second epitaxial source / drain component; a metal gate, which is arranged between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the metal gate is arranged above at least two sides of the channel layer and in physical contact with the at least two sides; a source / drain contact, which is arranged above the first epitaxial source / drain component; and a doped crystalline semiconductor layer, which is arranged between the first epitaxial source / drain component and the source / drain contact, wherein the doped crystalline semiconductor layer is arranged above at least two sides of the first epitaxial source / drain component and in physical contact with the at least two sides of the first epitaxial source / drain component.

[0004] An embodiment of the present application provides a device, comprising: an n-type channel layer, a first p-type epitaxial source / drain component, and a second p-type epitaxial source / drain component, arranged above a substrate, wherein the n-type channel layer is arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component; a metal gate, arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component, wherein the metal gate is arranged above at least two sides of the n-type channel layer and in physical contact with the at least two sides; and a first gallium-doped crystalline germanium layer, arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. A first p-type epitaxial source / drain component is disposed above at least two sides of the first p-type epitaxial source / drain component and in physical contact with the at least two sides of the first p-type epitaxial source / drain component, and a second gallium-doped crystalline germanium layer is disposed above at least two sides of the second p-type epitaxial source / drain component and in physical contact with the at least two sides of the second p-type epitaxial source / drain component, wherein the first gallium-doped crystalline germanium layer separates the first p-type epitaxial source / drain component from the first source / drain contact, and the second gallium-doped crystalline germanium layer separates the second p-type epitaxial source / drain component from the second source / drain contact.

[0005] An embodiment of the present application provides a method, comprising: forming a source / drain contact opening in a dielectric layer, the opening exposing a source / drain component of a multi-gate device; performing a deposition process to form a doped amorphous semiconductor layer above the multi-gate device, wherein the doped amorphous semiconductor layer partially fills the source / drain contact opening and surrounds the source / drain component of the multi-gate device; performing an annealing process to crystallize at least the portion of the doped amorphous semiconductor layer surrounding the source / drain component, thereby forming a doped crystalline semiconductor layer surrounding the source / drain component of the multi-gate device; and forming a source / drain contact in the remaining portion of the source / drain contact opening.

[0006] Embodiments of the present application provide a multi-gate device with reduced contact resistivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for fabricating source / drain contacts for a multi-gate device according to various aspects of the present invention.

[0009] FIG. 2A to FIG. 17A and Figure 2B to Figure 1 7B (wherein, FIG. 8B is collectively referred to as Figure 8B-1 , Figure 8B-2 , Figure 8B-3 , and FIG. 17B collectively refers to Figure 17B-1 , Figure 17B-2 and Figure 17B-3 ),and Fig. 9C According to various aspects of the present invention, at various stages of manufacture (e.g. Figure 1 A partial or overall partial perspective view of a multi-gate device (at a manufacturing stage associated with the method in FIG. 1 ).

[0010] FIG. 18A to FIG. 1 8C (wherein FIG. 18C is collectively referred to as Figure 18C-1 , Figure 18C-2 and Figure 18C-3 ) is a partial perspective view of a multi-gate device according to various aspects of the present invention, which can be partially or completely manufactured using this method Figure 1 source / drain contacts. DETAILED DESCRIPTION

[0011] The present invention relates generally to multi-gate devices and, more particularly, to source / drain contact structures for multi-gate devices.

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, for the convenience of describing the present invention, spatial relative terms, such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "upward", "downward", "below", "top", "bottom" and the like and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to describe the relationship between one component and another component. Spatial relative terms are intended to cover different orientations of devices including components. In addition, as understood by those of ordinary skill in the art, when describing a numerical value or a numerical range with "about", "approximately", etc., the term is intended to cover a numerical value within a reasonable range, which takes into account the changes inherently produced by manufacturing devices. For example, based on known manufacturing tolerances associated with manufacturing a component, the component has a characteristic, value, or range of values ​​associated with a value that encompasses a reasonable range of the described value, such as within + / -10% of the described value. For example, a material layer with a thickness of "about 5nm" may have a size range between 4.5nm and 5.5nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / -10%. Further, the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Recently, parasitic resistance-capacitance (RC) delay has become a significant challenge as the geometry of integrated circuit (IC) components has been reduced to achieve multi-gate devices with faster operating speeds (e.g., by reducing the distance that electrical signals propagate), thereby offsetting certain advantages achieved by shrinking multi-gate devices and limiting further shrinking of multi-gate devices. For example, reducing the source / drain contact size has resulted in source / drain contact resistance (i.e., the resistance to current flow at a metal-semiconductor contact interface, such as the resistance between a source / drain component comprising a semiconductor and a source / drain contact comprising a metal). Increasing the dopant level (e.g., dopant concentration) at the metal-semiconductor contact interface can reduce the contact resistivity at the metal-semiconductor contact interface, thereby reducing the source / drain contact resistance and improving performance. Current methods for increasing the dopant level at the metal-semiconductor contact interface to reduce the contact resistivity are typically performed during source / drain contact formation. In an example method, after forming a source / drain contact opening exposing a source / drain component, an ion implantation process is performed on a semiconductor material of a metal-semiconductor contact interface, which semiconductor material may be a portion of the source / drain component and / or a semiconductor layer formed above the source / drain component before the ion implantation process, to increase the doping level of a dopant in the semiconductor material before forming the source / drain contact. In another example method, after forming a source / drain contact opening exposing the source / drain component, before forming the source / drain contact, a doped epitaxial layer is grown from the source / drain component by an epitaxial growth process (epi process), wherein a dopant having a dopant level higher than that in the source / drain component is introduced into the epitaxial material by an ion implantation process during the epi process (i.e., in situ) or after the epi process. However, both of these example methods are incompatible with the manufacture of non-planar transistors because each method typically requires a high thermal budget, such as a process temperature greater than about 350°C. These high thermal budget processes may damage the channel of the multi-gate device, for example, by undesirably relaxing or increasing strain in the channel region of the multi-gate device and / or undesirably diffusing dopants within the multi-gate device, thereby altering desired device performance characteristics of the multi-gate device.

[0014] The present invention proposes to insert a doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, between the source / drain components and the source / drain contacts of a multi-gate device to reduce the contact resistivity. The doped crystalline semiconductor layer is formed without performing an ion implantation process and without performing an epitaxial growth process. For example, after forming a source / drain contact opening to expose the source / drain components of the multi-gate device, a doped amorphous semiconductor layer is deposited over the source / drain components and an annealing process (e.g., laser annealing) is performed to crystallize the doped amorphous semiconductor layer to form a doped crystalline semiconductor layer, thereby forming the proposed doped crystalline semiconductor layer. The deposition process in-situ dopes the semiconductor material so that a separate doping process (e.g., ion implantation process) is not performed to introduce dopants into the semiconductor material. In some embodiments, the deposition process is a physical vapor deposition process that implements a dopant target (e.g., a gallium target). In some embodiments, the deposition process is an atomic layer deposition process that implements a dopant precursor (e.g., a gallium precursor). The deposition process may be performed at a low temperature, such as less than or equal to about 350° C., to minimize any damage and / or modification to the components of the multi-gate device. Thereafter, source / drain contacts are formed in the source / drain contact openings and over the doped crystalline semiconductor layer such that the metal-semiconductor contact interface includes an interface between the source / drain contacts and the doped crystalline semiconductor layer. It has been observed that the contact resistivity at the metal-semiconductor contact interface with the doped crystalline semiconductor layer fabricated by the methods disclosed herein is less than the contact resistivity at the metal-semiconductor contact interface fabricated by current methods, such as methods of increasing the doping level by ion implantation and / or by introducing dopants during epitaxial growth. In some embodiments, the dopant level of the dopant (e.g., gallium) in the doped crystalline semiconductor layer is greater than the solid solubility limit of the dopant, and the dopant has been observed to significantly reduce the contact resistivity and, in some embodiments, provide a contact resistivity of less than or equal to about 1x10 -9 Ω-cm 2 In some embodiments, the doped crystalline semiconductor layer does not contain carbon, which current methods introduce to reduce the contact resistivity, but at the risk of deactivating dopants (particularly p-type dopants) in the source / drain components. The proposed source / drain contact fabrication techniques for reducing contact resistivity are compatible with and seamlessly integrated into conventional multi-gate device fabrication. Details of the proposed source / drain contact structures for multi-gate devices and corresponding fabrication methods are described herein in the following pages and / or figures.

[0015] Figure 11 is a flow chart of a method 100 for manufacturing a source / drain contact for a multi-gate device according to various aspects of the present invention. At box 110, the method 100 includes forming a source / drain contact opening in a dielectric layer, the opening exposing a source / drain component of the multi-gate device. At box 115, the method 100 includes performing a deposition process to form a doped amorphous semiconductor layer above the multi-gate device. The doped amorphous semiconductor layer partially fills the source / drain contact opening and surrounds the source / drain component of the multi-gate device. In some embodiments, the doped amorphous semiconductor layer is a gallium-doped amorphous germanium layer. The doped amorphous semiconductor layer is formed without performing an ion implantation process and without performing an epitaxial process. At box 120, the method 100 includes performing an annealing process to crystallize at least a portion of the doped amorphous semiconductor layer surrounding the source / drain component, thereby forming a doped crystalline semiconductor layer surrounding the source / drain component of the multi-gate device. In some embodiments, the doped amorphous semiconductor layer is a gallium-doped crystalline germanium layer. In some embodiments, method 100 implements block 125, which includes removing a remaining portion of the doped amorphous semiconductor layer from above the multi-gate device. In some embodiments, the remaining portion of the doped amorphous semiconductor layer is removed by a dry etching process that selectively removes the doped amorphous semiconductor layer relative to the doped crystalline semiconductor layer. At block 130, method 100 includes forming a source / drain contact in the remaining portion of the source / drain contact opening. The doped crystalline semiconductor layer separates the source / drain contact from the source / drain components of the multi-gate device. In some embodiments, the multi-gate device is a fin field effect transistor (FinFET) having a metal gate that surrounds a channel region of a fin extending from a substrate (i.e., a fin-shaped channel layer). In such embodiments, depending on the configuration of the fin and the epitaxial source / drain components, the doped crystalline semiconductor layer may also surround the source / drain region of the fin. In some embodiments, the multi-gate device is a gate-all-around (GAA) transistor having a metal gate that surrounds a channel region of a semiconductor layer suspended above and separated from a substrate (e.g., nanowires, nanorods, nanosheets, and / or other types of nanostructures). In such embodiments, the doped crystalline semiconductor layer may further surround the source / drain region of the suspended semiconductor layer. In some embodiments, the multi-gate device is any type of transistor having a metal gate that physically contacts at least two sides of the channel layer. In such embodiments, the doped crystalline semiconductor layer may further physically contact at least two sides of the source / drain region and / or source / drain features of the multi-gate device. Additional steps may be provided before, during, and after method 100, and certain steps described may be moved, replaced, or eliminated for additional embodiments of method 100. The following discussion illustrates various embodiments of multi-gate-based integrated circuit devices that may be manufactured according to method 100.

[0016] FIG. 2A to FIG. 17A , Figure 2B to Figure 17B (Figure 8B is collectively referred to as Figure 8B-1 , Figure 8B-2 and Figure 8B-3 , Figure 17B collectively refers to Figure 17B-1 , Figure 17B-2 and Figure 17B-3 )and Fig. 9C are various manufacturing stages according to various aspects of the present invention (e.g. Figure 1 Partial or overall schematic diagram of a multi-gate device 200 (associated with the method 100 in FIG. 1 ). In particular, FIG. 2A to FIG. 17A is a top view of the multi-gate device 200 in the XY plane, Figure 2B to Figure 1 7B and Fig. 9C 2 and 3 are respectively the planes of the multi-gate device 200 in the YZ plane. Fig.17A (is a metal gate cross-sectional view) line G-G' or FIG. 2A to FIG. 17A (which is a source / drain cross-sectional view). In the depicted embodiment, the multi-gate device 200 is processed to include a fin field effect transistor (FinFET), although the present invention covers embodiments in which the multi-gate device 200 is processed as an all-around gate (GAA) transistor. The multi-gate device 200 may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs, CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable elements, or combinations thereof. The multi-gate device 200 may be included in a microprocessor, memory, and / or other IC devices. In some embodiments, the multi-gate device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof. For clarity, the multi-gate device 200 has been simplified. FIG. 2A to FIG. 17A , Figure 2B to Figure 1 7B and Fig. 9C , to better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0017] Go to Figure 2A and Figure 2B, the multi-gate device 200 includes a substrate (wafer) 202. In the depicted embodiment, the substrate 202 includes silicon. Alternatively or additionally, the substrate 202 includes another basic semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Optionally, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the multi-gate device 200, the substrate 202 may include various doped regions. In some embodiments, the substrate 202 includes a p-type doped region (referred to as a p-type well) and / or an n-type doped region (referred to as an n-type well). For example, a portion of the substrate 202 of an n-type transistor corresponding to the multi-gate device 200 may include a p-type well, and a portion of the substrate 202 of a p-type transistor corresponding to the multi-gate device 200 may include an n-type well. The n-type well is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type well is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly on and / or in the substrate 202, for example, providing a p-type well structure, an n-type well structure, a double well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and / or other suitable doping processes may be performed to form the various doped regions.

[0018] Turning to FIG. 3 , a fin manufacturing process is performed to form a fin structure 210 above the substrate 202 . For example, a plurality of fins, such as fin 212A and fin 212B (also referred to as fin structures, fin elements, fin active areas, etc.) extend from the substrate 202 , each of the plurality of fins having a portion of a patterned layer 215 (also referred to as a patterned hard mask layer) disposed thereon after the fin manufacturing process. The present invention covers embodiments in which the fin structure 210 includes more fins or a single fin extending from the substrate 202 . The fins 212A, 212B extend substantially parallel to each other along the x-direction, each fin having a length defined in the x-direction, a width defined in the y-direction, and a height defined in the z-direction. In some embodiments, the fins 212A, 212B are part of the substrate 202 . For example, in the depicted embodiment, where the substrate 202 includes silicon, the fins 212A, 212B include silicon. Optionally, the fins 212A, 212B are defined in a material layer disposed above the substrate 202 , such as a semiconductor material layer. The semiconductor material may be silicon, germanium, silicon germanium, III-V semiconductor materials, other suitable semiconductor materials, or combinations thereof. For example, in some embodiments, before performing the fin manufacturing process, a germanium layer is formed over the substrate 202, for example, by an epitaxial growth process, and the fins 212A, 212B are formed from the germanium layer (i.e., the fins 212A, 212B include germanium). In some embodiments, the germanium layer is doped with a p-type dopant, an n-type dopant, or a combination thereof. In some embodiments, the fins 212A, 212B each include a semiconductor layer stack disposed over the substrate 202. Depending on the design requirements of the multi-gate device 200, the semiconductor layers of the semiconductor layer stack may include the same or different materials, dopants, etching rates, composition atomic percentages, composition weight percentages, thicknesses, and / or configurations.

[0019] A combination of deposition, lithography, and / or etching processes are performed to define fins 212A, 212B extending from substrate 202. For example, forming fins 212A, 212B includes depositing a mask layer (or a material layer disposed above substrate 202) over substrate 202, performing a lithography process to pattern the mask layer (thereby forming a patterned mask layer, such as patterned layer 215), and performing an etching process to transfer the pattern defined in the patterned mask layer to substrate 202 (or a material layer disposed thereon). The lithography process may include forming a photoresist layer (e.g., by spin coating) over mask layer / substrate 202, performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light), wherein the mask blocks, transmits, and / or reflects radiation to the photoresist layer depending on the mask pattern and / or mask type (e.g., binary mask, phase shift mask, or EUV mask) of the photoresist, so that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, during the development process, depending on the characteristics of the photoresist layer and the characteristics of the solution used in the development process, the exposed portions of the photoresist layer undergo chemical changes, and the exposed (or unexposed) portions of the photoresist layer dissolve. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. The etching process may use the patterned photoresist layer as an etching mask to remove portions of the substrate 202. In the depicted embodiment, where a patterned photoresist layer is formed over the mask layer, the first etching process may remove portions of the mask layer to form a patterned mask layer (i.e., patterned layer 215), and the second etching process may use the patterned layer 215 as an etching mask to remove portions of the substrate 210. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. In some embodiments, the etching process is a dry etching process, wherein the duration of the dry etching process is adjusted to achieve the desired height of the fins 212A and fins 212B (i.e., a timed dry etching process). After the etching process, the patterned photoresist layer is removed, for example, by a photoresist stripping process or other suitable process.Optionally, the fin structure 210 is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process), a spacer-dielectric (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. Such processes may also provide, for example, Figure 3A and Figure 3B The fin structure 210 is shown. In some embodiments, a directed self-assembly (DSA) technique is performed while patterning the substrate 202. In addition, in some embodiments, the exposure process may perform maskless lithography, electron beam (e-beam) writing, and / or ion beam writing to pattern the photoresist layer.

[0020] Go to Figure 4A and Figure 4B , an isolation feature 220 is formed above and / or in the substrate 202 to separate and isolate various regions of the multi-gate device 200, such as the fin 212A and the fin 212B. The isolation feature 220 includes an insulator material that fills the trenches defined by the fins 212A and 212B, so that the isolation feature 220 defines the fins 212A and 212B and electrically isolates them from other active regions (such as other fins) of the multi-gate device 200. The isolation feature 220 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation / insulation and / or insulating materials (for example, including silicon, oxygen, nitrogen, carbon or other suitable isolation components) or combinations thereof. Figure 4A and Figure 4B, the isolation feature 220 includes a liner layer 222 and an oxide layer 224. The liner layer 222 is arranged along the surface of the multi-gate device 200 defining the isolation trench, such as the sidewalls of the fins 212A, 212B and the top surface of the substrate 202, and the oxide layer 224 (also referred to as a body dielectric and / or a body dielectric layer) is arranged above the liner layer 222. In some embodiments, the liner layer 222 is a dielectric liner (e.g., a silicon nitride liner and / or a silicon oxide liner). In some embodiments, the liner layer 222 is a silicon liner. In some embodiments, the liner layer 222 is a doped liner, including, for example, borosilicate glass (BSG) and / or phosphosilicate glass (PSG). In some embodiments, the liner layer 222 and / or the oxide layer 224 include multiple layers, such as a dielectric liner and a silicon liner or a first dielectric liner and a second dielectric liner. In some embodiments, the oxide layer 224 includes silicon and oxygen (e.g., SiO2), and can therefore be referred to as a silicon oxide layer. In some embodiments, oxide layer 224 includes multiple layers. In some embodiments, forming isolation feature 220 includes performing a first deposition process to form a liner layer over multi-gate device 200, the liner layer partially filling the trench defined by fins 212A, 212B, wherein the liner layer extends continuously over substrate 202 and fin structure 210 (e.g., the liner layer extends continuously over a top surface of substrate 202, sidewalls of fins 212A, 212B, sidewalls of patterned layer 215, and a top surface of patterned layer 215 without interruption); performing a second deposition process to form an oxide layer over the liner layer filling the remaining portion of the trench, wherein the second deposition process overfills the trench so that the thickness of the oxide layer is greater than the height of fin structure 210 (e.g., the oxide layer is formed over the top surface of patterned layer 215 and / or fins 212A, 212B); and performing a planarization process to remove any of the liner layer and / or oxide layer disposed over and / or on the top surface of fin structure 210. The first deposition process and the second deposition process may implement chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), flowable CVD (FCVD), high density plasma CVD (HDPCVD), high aspect ratio deposition (HARP), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other deposition methods, or combinations thereof. In some embodiments, the first deposition process implements ALD to form a liner layer, and the second deposition process implements FCVD, HPCVD, and / or HARP to form an oxide layer. In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process that removes excess liner and oxide layers and / or planarizes top surfaces of the isolation features 220 and / or the fins 212A, 212B.In the depicted embodiment, the fins 212A, 212B serve as a planarization stop layer, so that the planarization process removes the patterned layer 215 disposed above the fins 212A, 212B and is performed until the fins 212A, 212B are reached and exposed. In some embodiments, the top surface of the isolation feature 220 and the top surface of the fins 212A, 212B are substantially flat after the planarization process. The isolation feature 220 can be configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, and / or other suitable isolation structures.

[0021] Go to Figure 5A and Figure 5B, the isolation features 220 are recessed (e.g., by an etching process) so that the fins 212A and 212B extend (protrude) from between the isolation features 220. For example, the isolation features 220 surround the bottom portions of the fins 212A and 212B, thereby defining an upper fin active area 230U (generally referring to the portion of the fins 212A and 212B extending from the top surface of the isolation features 220) and a lower fin active area 230L (generally referring to the portion of the fins 212A and 212B surrounded by the isolation features 220, which extends from the top surface of the substrate 202 to the top surface of the isolation features 220. In some embodiments, the etching process recesses the isolation features 220 until a desired (target) height of the upper fin active area 230U is reached. For example, along the z-direction between the top surface of the isolation features 220 and the fins The fin height FH of the upper fin active area 230U is defined between the respective top surfaces of fins 212A, 212B. In some embodiments, the fin height FH is about 40 nm to about 80 nm. The etching process is configured to selectively remove the isolation features 220 relative to the fins 212A, 212B. In other words, the etching process substantially removes the isolation features 220, but does not remove or substantially removes the fins 212A, 212B. For example, an etchant is selected for the etching process that etches the dielectric material (i.e., the isolation features 220) including silicon at a higher rate than the semiconductor material (i.e., the fins 212A, 212B) (i.e., relative to the dielectric material including silicon). The etching process is a dry etching process, a wet etching process, or a combination thereof. Various parameters of the etching process may be adjusted to achieve selective etching of the isolation member 220, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the second etching gas, the ratio of the concentration of the carrier gas to the etching gas, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the second wet etching component in the wet etching solution, the power of the RF source, the bias voltage, the pressure, the duration of the etching process, the etching time, the etching temperature, the etching pressure, the etching time ... The temperature maintained in the processing chamber during the process, the thickness of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters, or combinations thereof. In some embodiments, the etching process is a dry etching process, wherein the duration of the dry etching process is adjusted to achieve the desired height of the fin 212A and the fin 212B (i.e., a timed dry etching process). In some embodiments, the etching process includes multiple steps (stages). In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the fins 212A, 212B but has openings therein that expose the isolation features 220.

[0022] Go to Fig. 6A and Figure 6B, dummy gate stacks, such as dummy gate stacks 240A, dummy gate stacks 240B, and dummy gate stacks 240C, are formed on portions of the fins 212A, 212B and above the isolation features 220. The dummy gate stacks 240A-240C extend longitudinally in a direction different from (e.g., orthogonal to) the length direction of the fins 212A, 212B. For example, the dummy gate stacks 240A-240C extend substantially parallel to each other in the y-direction while having a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. The fins 212A, 212B each have one or more channel regions (C) and source / drain (S / D) regions defined along their length (here, along the x-direction), wherein each channel region is arranged between corresponding source / drain regions. The dummy gate stacks 240A-240C are arranged between and inserted into the source / drain regions of the fins 212A, 212B, wherein the channel regions of the fins 212A, 212B are located below the dummy gate stacks 240A-240C. In the YZ plane, the gate stacks 240A-240C surround the top surface and sidewall surface of the upper fin active region 230U of the fins 212A, 212B. In the XZ plane, the gate stacks 240A-240C are arranged above the top surface of the corresponding channel region of the fins 212A, 212B. Fig. 6A and Figure 6B In the embodiment, the pseudo gate stack 240A is arranged above each channel region of the fin 212A, the pseudo gate stack 240B is arranged above each channel region of 212B, and the pseudo gate stack 240C is arranged above each channel region of the fin. The corresponding channel regions of the gate 212A and the fin 212B, wherein the pseudo gate stack 240C extends over the fins 212A and 212B without interruption. Each of the pseudo stacks 240A-240C may include a pseudo gate dielectric, a pseudo gate electrode and / or a hard mask. The pseudo gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials or a combination thereof. In some embodiments, the pseudo gate dielectric includes an interface layer (including, for example, silicon oxide) and a high-k dielectric layer arranged above the interface layer. The pseudo gate electrode includes a suitable pseudo gate material, such as polysilicon. In some embodiments, the pseudo gate stacks 240A-240C may therefore be referred to as polysilicon (PO) gate stacks. The hard mask layer includes silicon oxide, silicon carbide, silicon nitride, other suitable hard mask materials, or combinations thereof. In some embodiments, the dummy gate stacks 240A-240C include many other layers, such as capping layers, interface layers, diffusion layers, barrier layers, or combinations thereof.

[0023] The dummy gate stacks 240A-240C are formed by a deposition process, a photolithography process, an etching process, other suitable processes or a combination thereof. For example, a first deposition process is performed to form a dummy gate dielectric layer above the multi-gate device 200, a second deposition process is performed to form a dummy gate electrode layer above the dummy gate dielectric layer, and a third deposition process is performed to form a hard mask layer above the dummy gate electrode layer. The deposition process includes CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods or a combination thereof. A gate patterning process (including, for example, various photolithography processes, etching processes and / or cleaning processes, such as those described herein) is then performed to pattern the hard mask layer, the dummy gate electrode layer and / or the dummy gate dielectric layer to form the dummy gate stacks 240A-240C, such as Fig. 6A and Figure 6B As shown. In some embodiments, the gate patterning process may include a gate cutting process that separates the dummy gate stack extending above the two fins 212A, 212B into discrete dummy gate stacks, each of which is arranged above the fin 212A or the fin 212B, such as the dummy gate stack 240A and the dummy gate stack 240B. In some embodiments, the gate patterning process defines a target gate spacing (spacing) between the dummy gate stacks, such as the spacing (or distance) along the x-direction between directly adjacent dummy gate stacks. For example, the gate patterning process defines the gate spacing (spacing) between the dummy gate stack 240C and the dummy gate stack 240A and the dummy gate stack 240B, respectively. The present invention contemplates any number of dummy gate stacks and / or dummy gate stack configurations, and it is noted that the dummy gate stacks 240A-240C are provided for illustration.

[0024] Go to Fig. 7A and Figure 7B, a gate spacer 245 is formed along the sidewalls of the dummy gate stacks 240A-240C, thereby forming a gate structure 250A-250C (collectively referred to as the dummy gate stacks 240A-240C and the gate spacers 245). The gate spacers 245 are arranged adjacent to the corresponding dummy gate stacks 240A-240C (i.e., along their sidewalls). The gate spacers 245 are formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and / or silicon oxynitride carbon). For example, a dielectric layer including silicon and nitrogen (e.g., Si3N4), such as a silicon nitride layer, is deposited above the multi-gate device 200 and etched (e.g., anisotropically etched) to form a gate spacer 245. In some embodiments, the gate spacer 245 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the dummy gate stacks 240A-240C. In such embodiments, each set of spacers may include materials with different etching rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) is deposited and etched to form a first set of spacers adjacent to the sidewalls of the dummy gate stacks 240A-240C, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) is deposited and etched to form a second set of spacers adjacent to the first set of spacers.

[0025] Go to Fig. 8A and FIG. 8B (referenced together Figure 8B-1 , Figure 8B-2 and Figure 8B-3 ), forming epitaxial source / drain features 255 over the source / drain regions of the fins 212A, 212B. For example, a semiconductor material is epitaxially grown on and / or from the source / drain regions of the fins 212A, 212B to form the epitaxial source / drain features 255. In some embodiments, for example Figure 8B-1As shown in , a source / drain etch is performed on the source / drain regions of the fins 212A, 212B to form source / drain recesses, and an epitaxial source / drain feature 255 is grown over and / or from the source / drain regions of the fins 212A, 212B to fill the source / drain recesses. In the depicted embodiment, after the source / drain etch, the top surfaces of the source / drain regions of the fins 212A, 212B are below the top surface of the isolation feature 220 relative to the top surface of the substrate 202. In some embodiments, the etching process completely removes the source / drain regions of the fins 212A, 212B to expose the substrate 202. In some embodiments, after the source / drain etch, the top surfaces of the source / drain regions of the fins 212A, 212B are above and / or substantially coplanar with the top surfaces of the isolation feature 220. In some embodiments, the source / drain etch is configured to selectively etch the fins 212A, 212B while performing minimal (to no) etching of the gate structures 250A-250C and / or the isolation features 220. Figure 8B-2 and Figure 8B-3 , epitaxial source / drain features 255 are epitaxially grown from the source / drain regions of the fins 212A, 212B without performing a source / drain etch. In such embodiments, the epitaxial source / drain features 255 surround the source / drain regions of the fins 212A, 212B (e.g., covering the top surfaces and sidewalls of the fins 212A, 212B). The epitaxial growth parameters may be controlled to achieve different profiles of the epitaxial source / drain features 255, such as rectangular and / or square profiles ( Figure 8B-2 ) or diamond outline ( Figure 8B-3 ).

[0026] The epitaxial process may implement a CVD deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the components of the fins 212A, 212B. The epitaxial source / drain features 255 are doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors, the epitaxial source / drain features 255 include silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form Si:C, Si:P, or Si:C:P epitaxial source / drain features). In some embodiments, for p-type transistors, the epitaxial source / drain features 255 include silicon germanium, which may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form Si:Ge:B epitaxial source / drain features). In some embodiments, for a p-type transistor, the epitaxial source / drain features 255 include germanium, which may be doped with boron, gallium, indium, other p-type dopants, or combinations thereof (e.g., forming Ge:B or Ge:Ga epitaxial source / drain features). In some embodiments, the epitaxial source / drain features 255 include more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or dopant concentrations. In some embodiments, the epitaxial source / drain features 255 include materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel region of the transistor of the multi-gate device 200. In some embodiments, the epitaxial source / drain features 255 are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in-situ doping). In some embodiments, the epitaxial source / drain features 255 are doped by an ion implantation process after epitaxial growth. In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate the fins 212A, 212B, the epitaxial source / drain features 255, heavily doped source / drain (HDD) regions (which may be formed in the fins 212A, 212B and / or the remaining portions of the epitaxial source / drain features), and / or lightly doped source / drain (LDD) regions (which may be formed in the fins 212A, 212B and / or the remaining portions of the epitaxial source / drain features).

[0027] Go to Fig. 9A , Fig. 9B (along Fig. 9A The line G-G' is intercepted) and Fig. 9C (along Fig. 9AA dielectric layer 260 is formed over the epitaxial source / drain features 255, the gate structures 250A-250C, the isolation structures 220, the fins 212A, 212B, and the substrate 202. The dielectric layer 260 is disposed between adjacent gate structures 250A-250C. The dielectric layer 260 may include an interlayer dielectric (ILD) layer disposed over a contact etch stop layer (CESL), wherein the CESL is disposed between the ILD layer and the gate structures 250A-250C, the isolation features 220, and the fins 212A, 212B. The ILD layer includes dielectric materials, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), PSG, BSG, boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer includes a dielectric material having a dielectric constant less than the dielectric constant of silicon dioxide (e.g., k < 3.9) (i.e., a low-k dielectric material). In some embodiments, the ILD layer includes a dielectric material having a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as SiO2 (e.g., porous silicon dioxide), silicon carbide (SiC) and / or a carbon-doped oxide (e.g., a SiCOH-based material (having, for example, Si-CH3 bonds)), each of which is tuned / configured to exhibit a dielectric constant less than 2.5. The CESL includes a material different from the ILD layer, such as a dielectric material different from the dielectric material of the ILD layer. The ILD layer and / or the CESL may include a multilayer structure having multiple dielectric materials. In the depicted embodiment, the ILD layer includes silicon and oxygen (eg, SiCOH, SiO Xor other materials including silicon and oxygen), and the CESL includes nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, SiCO, metal nitrides and / or metal carbonitrides). The dielectric layer 260 is formed by a deposition process such as CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods or combinations thereof. In some embodiments, forming the dielectric layer 260 includes: depositing the CESL over the multi-gate device 200 by ALD and / or CVD; depositing an ILD layer over the CESL by FCVD, HARP and / or HDP; and performing a CMP process and / or other planarization process until reaching the dummy gate stacks 240A-240C (exposing their top surfaces). In some embodiments, the planarization process removes the hard mask layer of the dummy gate stacks 240A-240C to expose the dummy gate electrodes of the dummy gate stacks 240A-240C. In some embodiments, the planarization process provides a substantially planar surface for the ILD layer, CESL, and dummy gate stacks 240A- 240C.

[0028] Go to FIG. 10A to FIG. 12A and FIG. 10B to FIG. 12B , a gate replacement process is performed to replace the dummy gate stacks 240A to 240C with metal gate stacks. Fig. 10A and Fig. 10B, a gate opening 265 is formed in the gate structure 250A-250C by removing the dummy gate stack 240A-240C to expose the channel region of the fin 212A, 212B. The etching process is configured to selectively remove the dummy gate stack 240A-240C relative to the dielectric layer 260, the gate spacer 245, the isolation feature 220 and / or the fin 212A, 212B. In other words, the etching process substantially removes the dummy gate stack 240A-240C, but does not remove or substantially removes the dielectric layer 260, the gate spacer 245, the isolation feature 220 and / or the fin 212A, 212B. For example, an etchant is selected for etching polysilicon (i.e., dummy gate stacks 240A-240C) at a higher rate than semiconductor material (e.g., fins 212A, 212B) and / or dielectric material (i.e., dielectric layer 260, gate isolation layer 245, and / or isolation layer 220), such as a semiconductor material including silicon and / or a dielectric material including silicon (i.e., the etchant has a high etching selectivity relative to polysilicon). The etching process is a dry etching process, a wet etching process, or a combination thereof. Various parameters of the etching process can be adjusted to achieve selective etching of the pseudo gate stack 240A-240C, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the second etching gas, the ratio of the concentration of the carrier gas to the etching gas, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the second wet etching component in the wet etching solution, the power of the RF source, the bias voltage, the pressure, the duration of the etching process, the temperature maintained in the processing chamber during the etching process, the thickness of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters or combinations thereof. In some embodiments, the etching process includes multiple steps. For example, the etching process can alternately use etchants to remove the various layers of the pseudo gate stack 240A-240C respectively. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 260 and / or the gate spacer 245 and only has openings that expose the pseudo gate stack 240A-240C.

[0029] Go to Fig.11A and Fig. 11B, a gate dielectric layer 270 is formed over the multi-gate device 200, wherein the gate dielectric layer 270 partially fills the gate trench 265 and surrounds the channel region of the fins 212A and 212B. The gate dielectric layer 270 covers the exposed surfaces of the fins 212A and 212B, so that the gate dielectric layer 270 is arranged along the top surface and sidewalls of the channel region of the fins 212A and 212B. In some embodiments, the gate dielectric layer 270 is further arranged over the isolation component 220 and the dielectric layer 260. The gate dielectric layer 270 includes a high-k dielectric layer, which includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k≈3.9). For example, the high-k dielectric layer includes HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials of the metal gate stack, or combinations thereof. The high-k dielectric layer is formed by any process described herein, such as ALD, CVD, PVD, an oxidation-based deposition process, other suitable processes or combinations thereof. For example, the ALD process deposits the high-k dielectric layer. In some embodiments, the ALD process is a conformal deposition process such that the thickness of the high-k dielectric layer is substantially uniform (conformal) over various surfaces of the multi-gate device 200. In some embodiments, the gate dielectric layer 270 includes an interface layer disposed between the high-k dielectric layer and the fins 212A, 212B. The interface layer includes a dielectric material, such as SiO2, HfSiO, SiON, other dielectric materials including silicon, other suitable dielectric materials, or combinations thereof. The interface layer is formed by any process described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interface layer is formed by exposing the exposed surfaces of the fins 212A and 212B to a chemical oxidation process of hydrofluoric acid. In some embodiments, the interface layer is formed by a thermal oxidation process that exposes the exposed surfaces of the fins 212A and 212B to an oxygen and / or air environment. In some embodiments, the interface layer is formed after forming the high-k dielectric layer. For example, in some embodiments, after forming the high-k dielectric layer, the multi-gate device 200 is annealed in an oxygen and / or nitrogen environment (e.g., nitrous oxide).

[0030] Go to Fig. 12A and Fig. 12B, processing proceeds to form the metal gate stacks (also referred to as metal gates and / or high-k / metal gates) of the gate structures 250A-250C. The metal gate stacks, each including a respective gate dielectric and a respective gate electrode, are configured to achieve desired functionality according to the design requirements of the multi-gate device 200. In the depicted embodiment, the metal gate stack of the gate structure 250A includes a gate dielectric 270A and a gate electrode 272A, the metal gate stack of the gate structure 250B includes a gate dielectric 270B and a gate electrode 272B, and the metal gate stack of the gate structure 250C includes a gate dielectric 270C and a gate electrode 272C. The gate electrodes 272A-272C are arranged above the respective gate dielectrics 270A-270C and surround the respective channel regions of the fins 212A, 212B. For example, the gate electrodes 272A-272C are arranged along the top surfaces and sidewalls of the channel regions of the fins 212A, 212B. In some embodiments, forming the metal gate stack includes depositing a gate electrode layer (e.g., by ALD, CVD, PVD, electroplating, other suitable processes, or combinations thereof) over the gate dielectric layer 270, wherein the gate electrode layer fills the remaining portion of the gate opening 265, and performing a planarization process to remove excess gate material from the multi-gate 200. For example, the planarization process removes portions of the gate electrode layer and the gate dielectric layer 270 disposed above the top surface of the dielectric layer 260 and the top surface of the gate spacer 245, wherein the remaining portions of the gate electrode layer and the gate dielectric layer 270 fill the gate opening 265 to form gate electrodes 272A-272C and gate dielectrics 270A-270C, thereby providing a metal gate stack for the gate structures 250A-250C. The metal gate stack may include numerous other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some embodiments, the CMP process is performed until the top surface of the dielectric layer 260 is reached (exposed), such that the top surfaces of the gate structures 250A- 250C are substantially planar with the top surface of the dielectric layer 260 .

[0031] The gate electrodes 272A-272C include a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TiTaN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the gate electrodes 272A-272C include a work function layer and a body conductive layer. The work function layer is a conductive layer adjusted to have a desired work function (e.g., an n-type work function or a p-type work function), and the body conductive layer is a conductive layer formed above the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or fill) conductive layer includes a suitable conductive material, such as Al, W, Ti, Ta, polysilicon, Cu, a metal alloy, other suitable materials, or combinations thereof. Since the gate structure 250C spans across the fins 212A, 212B, each of the fins may correspond to a different transistor region, and thus the gate structure 250C may have different layers in each transistor region. For example, the number, configuration, and / or material of the layers of the gate dielectric 270C and / or gate electrode 272C corresponding to one transistor region (e.g., the gate dielectric and / or gate electrode corresponding to the fin 212A) may be different from the number, configuration, and / or material of the gate dielectric 270C and / or gate electrode 272C corresponding to another transistor region (e.g., corresponding to the fin 212B).

[0032] Go to Fig.13A and Fig. 13B, a dielectric layer 275 is formed over the multi-gate device 200, and a patterning process is performed to form a source / drain contact (plug) opening 280 extending vertically through the dielectric layer 275 and the dielectric layer 260 to expose the epitaxial source / drain feature 255. The dielectric layer 275 is similar to the dielectric layer 260, and thus may be configured and formed similarly to the dielectric layer 260 as described above. In some embodiments, the patterning process includes performing a photolithography process to form a patterned mask layer over the dielectric layer 275, wherein the patterned mask layer has an opening therein that exposes portions of the dielectric layer 275 and the dielectric layer 270 covering the epitaxial source / drain feature 255, and the patterning process includes performing an etching process to remove the exposed portions of the dielectric layer 275 and the dielectric layer 260 to expose the epitaxial source / drain feature 255. The photolithography process may include forming a photoresist layer (e.g., by spin coating) over the dielectric layer 275, performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., UV light, DUV light, or EUV light), wherein the mask blocks, transmits, and / or reflects radiation to the photoresist layer according to the mask pattern and / or mask type (e.g., binary mask, phase shift mask, or EUV mask) of the photoresist, so that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, the exposed portion of the photoresist layer undergoes chemical changes during the development process, and the exposed (or unexposed) portion of the photoresist layer dissolves, depending on the characteristics of the photoresist layer and the characteristics of the solution used in the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing and / or ion beam writing. In some embodiments, the patterned photoresist layer is used as an etching mask during the etching process to remove the exposed portion of the dielectric layer 275 and / or the dielectric layer 260. In some embodiments, before forming the photoresist layer, the patterned photoresist layer is formed above the mask layer formed above the dielectric layer 275, and the patterned photoresist layer is used as an etching mask to remove a portion of the mask layer, thereby forming a patterned mask layer. In such embodiments, the patterned mask layer is used as an etching mask to remove the exposed portion of the dielectric layer 275 and / or the dielectric layer 260. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process selectively etches the dielectric layer 275 and / or the dielectric layer 260 relative to the patterned mask layer, the epitaxial source / drain component 255, and the isolation component 220. In some embodiments, after the etching process, the patterned mask layer is removed from over dielectric layer 275 (eg, by a photoresist stripping process). In some embodiments, the patterned mask layer is removed by the etching process.

[0033] Go to Fig.14A and Fig. 14B , a deposition process is performed to form a doped amorphous layer 285 over the multi-gate device 200, such that the doped amorphous layer 285 partially fills the source / drain contact opening 280. The doped amorphous layer 285 covers the exposed surfaces of the dielectric layer 260, the epitaxial source / drain features 255, and the isolation features 220. In the depicted embodiment, the doped amorphous layer 285 surrounds the epitaxial source / drain features 255, such that the doped amorphous layer 285 is arranged on the top surface and sidewalls of the epitaxial source / drain features 255. The doped amorphous layer 285 has a thickness t. In some embodiments, the thickness t is about 1 nm to about 20 nm. In some embodiments, the doped amorphous layer 285 is conformally deposited over the multi-gate device 200, such that the thickness t is substantially uniform over the exposed surface of the multi-gate device 200. For example, the thickness t along the sidewalls of the dielectric layer 260 is substantially the same as the thickness t along the sidewalls of the epitaxial source / drain features 255 and / or the thickness t along the sidewalls of the epitaxial source / drain features 255 is substantially the same as the thickness t along the top surface of the epitaxial source / drain surface 255. In some embodiments, the thickness t of the doped amorphous layer 285 varies over the exposed surface of the multi-gate device 200, such that the doped amorphous layer 285 is not a conformal layer. The doped amorphous layer 285 includes a semiconductor material having an amorphous structure (in other words, a material having a disordered atomic structure), such as amorphous germanium, amorphous silicon, amorphous silicon germanium, and / or another amorphous semiconductor material. In some embodiments, the doped amorphous layer 285 and the epitaxial source / drain features 255 include the same material, but have different atomic structures. For example, both the doped amorphous layer 285 and the epitaxial source / drain features 255 include germanium, but the doped amorphous layer 285 includes amorphous germanium (e.g., a-Ge), while the epitaxial source / drain features 255 include crystalline germanium (e.g., c-Ge). In some embodiments, the fins 212A, 212B include a semiconductor material having a crystalline structure (in other words, a material having an ordered atomic structure), such as crystalline silicon (e.g., c-Si), crystalline germanium, and / or crystalline silicon germanium (c-SiGe). Depending on the design requirements of the multi-gate device 200, the doped amorphous layer 285 includes an n-type dopant, a p-type dopant, or a combination thereof. P-type dopants include boron (B), gallium (Ga), indium (In), other p-type dopants, or a combination thereof. N-type dopants include arsenic (As), phosphorus (P), antimony (Sb), other n-type dopants, or a combination thereof. In the depicted embodiment, the doped amorphous layer 285 includes amorphous germanium doped with gallium, and thus may be referred to as a gallium-doped amorphous germanium (a-Ge:Ga) layer.

[0034] The deposition process implemented to form the doped amorphous layer 285 is PVD, ALD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods or combinations thereof. The doped amorphous layer 285 is not formed using an ion implantation process (e.g., a semiconductor layer is bombarded with doping ions such as gallium ions to form the doped amorphous layer 285) because the present invention recognizes that the ion implantation process (and the processing associated therewith) that is typically implemented to reduce contact resistivity is incompatible with the manufacture of multi-gate devices such as the multi-gate device 200. Specifically, the high temperature annealing process that is typically required after the ion implantation process to activate the dopant can damage the gate structure of the multi-gate device, such as the gate stack, and / or inadvertently cause the dopant to diffuse into the channel of the multi-gate device. In addition, due to the three-dimensional geometry of the source / drain region of the multi-gate device, the ions (dopants) from the ion implantation process cannot uniformly reach the top and bottom of the source / drain region, so that the dopant concentration at the top of the source / drain region may be greater than the dopant concentration at the bottom of the source / drain region and / or along its sidewalls, thereby limiting the reduction of the contact resistivity. In addition, the ion implantation process usually implements a photoresist layer (mask) to cover the area that should not be implanted by the ion implantation process, and the photoresist layer (e.g., due to its thickness) limits the angle at which the ion implantation process can implant the dopant into the source / drain region, resulting in a non-uniform dopant concentration in the source / drain region of the multi-gate device. In fact, the present invention proposes to use an in-situ doping deposition process to form the doped amorphous layer 285, wherein the dopant is introduced into the semiconductor material when the semiconductor material is deposited above the multi-gate device 200. In some embodiments, the deposition process is a low temperature deposition process. For example, the wafer temperature during the deposition process is less than or equal to about 350°C. In some embodiments, the doped amorphous layer 285 is formed by low temperature PVD, wherein the temperature in the process chamber is about room temperature (e.g., about 20° C. to about 25° C.) to about 350° C. In some embodiments, the low temperature PVD is a co-sputtering process, wherein at least a germanium-containing target and a gallium-containing target are bombarded with high energy ions (e.g., ions of a plasma) to sputter germanium and gallium onto the exposed surface of the multi-gate device 200. In some embodiments, the co-sputtering process is a reactive magnetron sputtering process. In some embodiments, the doped amorphous layer 285 is formed by low temperature ALD, wherein the temperature in the process chamber is about 150° C. to about 350° C. Low temperature ALD uses a germanium-containing precursor and a gallium-containing precursor. In some embodiments, the germanium-containing precursor is tetrakis(dimethylamino)germane (TDMAGe), other suitable germanium-containing precursors, or combinations thereof.In some embodiments, the gallium-containing precursor is gallium (III) acetylacetonate (Ga(acac)3), tris(dimethylamide)dimeric gallium Ga2(NMe2)6, cyclo(triamino-hexamethyltrigallium) ([(CH3)2GaNH2]3), dimethylgallium isopropoxide (Me2GaOiPr), tris(isopropoxy)gallium (Ga(OiPr)3), trimethylgallium (TMGa), tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium (Ga(TMHD)3), other suitable gallium-containing precursors, or combinations thereof. In some embodiments, during the deposition process, the gallium-containing precursor reacts with an oxygen-containing precursor (which may be referred to as a reactant precursor), such as O2, H2O, O3, and / or O2 plasma. For example, Ga(acac)3 reacts with H2O and / or O3. In another example, Ga2(NMe2)6 reacts with H2O. In another example, [(CH3)2GaNH2]3 reacts with O2 plasma. In another example, Me2GaOiPr is reacted with H2O. In another example, Ga(OiPr)3 is reacted with H2O. In another example, TMGa is reacted with O3 or O2 plasma. In another example, Ga(TMHD)3 is reacted with O2 plasma. In some embodiments, the deposition process is a nano-lamination process, wherein the doped amorphous layer 258 is a nano-laminate.

[0035] Go to Fig.15A and Fig. 15B, an annealing process is performed on the doped amorphous layer 285 to convert (crystallize) the doped amorphous semiconductor material (i.e., semiconductor material having an amorphous structure) into a doped crystalline semiconductor material (i.e., semiconductor material having a crystalline structure), thereby forming a doped crystalline (crystallized) layer 285'. The annealing process crystallizes at least a portion of the doped amorphous layer 285 disposed over the semiconductor surface, such as the epitaxial source / drain features 255. In some embodiments, the annealing process crystallizes the portion of the doped amorphous layer 285 disposed over the semiconductor surface, but not the portion of the doped amorphous layer 285 disposed over the dielectric surface. In such embodiments, the doped crystalline layer 285' is disposed over the epitaxial source / drain features 255, while the doped amorphous layer 285 remains disposed over the dielectric layer 260 and / or the isolation features 220. In some embodiments, the annealing process crystallizes the portion of the doped amorphous layer 285 disposed over the dielectric layer 260 and / or the isolation features 200. In some embodiments, the annealing process crystallizes the entire doped amorphous layer 285 such that the doped crystalline layer 285' covers the entire multi-gate device 200 (i.e., the epitaxial source / drain features 255, the dielectric layer 260, and the isolation features 220 of the depicted embodiment). In the case where the doped amorphous layer 285 is a gallium-doped amorphous germanium layer, the annealing process crystallizes the gallium-doped amorphous germanium (in other words, rearranges its atomic structure) such that the doped crystalline layer 285' is a gallium-doped crystalline germanium layer (in other words, the gallium-doped germanium has an ordered atomic structure). Any suitable annealing process may be implemented as long as the temperature of the annealing process is sufficient to crystallize the doped amorphous layer 285. In some embodiments, the annealing process is a laser annealing process that uses a laser beam to provide localized heating of a material, which may activate dopants in the doped crystalline layer 285 and / or the doped amorphous layer 285. In some embodiments, the laser annealing process is a millisecond laser annealing process that exposes the doped amorphous layer 285 to a laser pulse for a time period of milliseconds (ms). In some embodiments, the millisecond laser annealing process exposes the doped amorphous layer 285 to heat having a temperature of about 750° C. to about 900° C. In some embodiments, the laser annealing process is a nanosecond laser annealing process that exposes the doped amorphous layer 285 to laser pulses for a nanosecond (ns) period of time. In some embodiments, the nanosecond laser annealing process exposes the doped amorphous layer 285 to heat having a temperature greater than about 900° C.

[0036] It has been observed that the proposed deposition and annealing process provides a doped crystalline layer 285 overlying the epitaxial source / drain features 255, which increases the dopant level at the metal-semiconductor interface, thereby reducing the contact resistivity compared to the contact resistivity exhibited by conventional metal-semiconductor contact interfaces. In addition, performing the deposition and annealing process after the gate replacement process (particularly during source / drain contact formation) can prevent (or minimize) the deactivation of dopants in the doped crystalline layer 285 during subsequent processing, thereby ensuring the integrity and maintenance of the dopant level required to reduce the contact resistivity. In some embodiments, the dopant concentration of a dopant such as gallium in the doped crystalline layer 285' is about 1x10 20 Dopant / cm 3 (cm -3 ) to about 5x10 21 cm -3 In some embodiments, the doped crystalline layer 285' includes a dopant concentration, such as a gallium concentration, that is higher than the solid solubility. For example, the dopant concentration, such as the gallium concentration, is greater than or equal to about 1x10 21 cm -3 It has been observed that a dopant content greater than the solid solubility of the dopant (e.g., the solid solubility of gallium) can achieve a reduction in contact resistivity that is not achievable with current source / drain contact fabrication techniques. In some embodiments, the doped crystalline layer 285' has a thickness of less than about 1x10 -9 Ω-cm 2 Contact resistivity (ρ c ). In some embodiments, the doped crystalline layer 285' has a dopant concentration greater than the dopant concentration of the epitaxial source / drain features 255 (and / or the fins 212A, 212B, for example, in embodiments where the multi-gate device 200 does not include the epitaxial source / drain features 255). In some embodiments, the doped amorphous layer 285 and the epitaxial source / drain features 255 are doped with the same dopant (e.g., both are Ga). In some embodiments, the doped amorphous layer 285 and the epitaxial source / drain features 255 are doped with different dopants (e.g., the doped amorphous layer 285 is doped with Ga, while the epitaxial source / drain features 255 are doped with B). In some embodiments, the doped amorphous layer 285 and / or the epitaxial source / drain features 255 are doped with Ga and B.

[0037] Go to Fig.16A and Fig. 16BIn some embodiments, any remaining portion of the doped amorphous layer 285 may be removed from the multi-gate device 200 by an etching process. For example, the etching process removes portions of the doped amorphous layer 285 that remain on dielectric surfaces of the multi-gate device 200, such as portions above the dielectric layer 260 and / or the isolation features 220. The etching process is configured to selectively remove the doped amorphous layer 285 relative to the doped crystalline layer 285' and / or the dielectric material (e.g., the dielectric layer 260 and / or the isolation features 220). In other words, the etching process substantially removes the doped crystalline layer 285', but does not remove or substantially removes the doped crystalline layer 285'. For example, an etchant is selected for the etching process that etches the doped amorphous semiconductor material (i.e., the doped amorphous layer 285) at a higher rate than the doped crystalline semiconductor material (i.e., the doped crystalline layer 285') (i.e., the etchant has a high etching selectivity relative to the amorphous semiconductor material (e.g., gallium-doped amorphous germanium)). The etching process is a dry etching process, a wet etching process, or a combination thereof. Various parameters of the etching process may be adjusted to achieve selective etching of the doped amorphous layer 285, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the second etching gas, the ratio of the concentration of the carrier gas to the etching gas, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the second wet etching component in the wet etching solution, the power of the RF source, the bias voltage, the pressure, the duration of the etching process, the temperature maintained in the process chamber during the etching process, the thickness of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters or combinations thereof. In some embodiments, the etching process is a dry etching process configured to etch gallium-doped amorphous germanium without or with minimal etching of gallium-doped crystalline germanium. In some embodiments, the etching process is not omitted. Fig.16A and Fig. 16B The associated processing results in the multi-gate device 200 including both the doped crystalline layer 285 ′ and any remaining portion of the doped amorphous layer 285 .

[0038] Go to Fig.17A and FIG. 17B (referenced together Figure 17B-1 , Figure 17B-2 and Figure 17B-3), a source / drain contact 290 to the epitaxial source / drain feature 255 is formed in the remaining portion of the source / drain contact opening 290. The source / drain contact 290 surrounds the corresponding epitaxial source / drain feature 255 and is separated from its corresponding epitaxial source / drain feature 255 by the doped crystalline layer 285'. Each of the source / drain contacts 290 includes a contact barrier layer (and / or liner) layer 292 and a contact body layer 294 disposed above the contact barrier layer 292. The contact barrier layer 292 and the contact body layer 294 each include one or more conductive materials. In some embodiments, the contact barrier layer 292 includes a material that promotes adhesion between the dielectric material (here, the dielectric layer 260 and / or the isolation feature 220) and the contact body layer 294, and between the doped crystalline layer 285' and the contact body layer 294. The material of the contact barrier layer 292 can further prevent the metal component (e.g., metal atoms / ions) source / drain contact 290 from diffusing into the surrounding dielectric material. In some embodiments, the contact barrier layer 292 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy, other suitable components configured to promote and / or enhance adhesion between the metal material and the dielectric material and / or prevent the metal component from diffusing from the metal material to the dielectric material, or a combination thereof. For example, the contact barrier layer 292 includes tantalum, tantalum nitride, aluminum tantalum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium tantalum nitride, silicon titanium nitride, titanium aluminum, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or a combination thereof. In another example, the contact barrier layer includes silicon doped with phosphorus. The contact layer 294 includes tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal composition, an alloy thereof, or a combination thereof. In the depicted embodiment, the contact layer 294 includes tungsten, ruthenium and / or cobalt. In some embodiments, the source / drain contact 290 is formed by performing a first deposition process to form a contact barrier material over the multi-gate device 200 that partially fills the source / drain contact opening 280, and performing a second deposition process to form a contact material over the contact barrier layer material, wherein the contact material fills the remaining portion of the source / drain contact opening 280. The first deposition process and the second deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, chemical plating, other suitable deposition methods, or combinations thereof. A CMP process and / or other planarization process is performed to remove excess contact material and / or contact barrier material, for example, from over the top surface of the dielectric layer 275 , resulting in source / drain contacts 290 (ie, contact barrier layer 292 and contact layer 294 ).The CMP process may planarize the source / drain contacts 290 and the dielectric layer 275 so that the top surface of the dielectric layer 275 and the top surface of the source / drain contacts 290 are substantially planar.

[0039] In some embodiments, source / drain contacts 290, dielectric layer 275, and dielectric layer 260 form part of a multi-layer interconnect (MLI) component. In some embodiments, dielectric layer 275 and dielectric layer 260 form two bottom layers (e.g., ILD1 and ILD0, respectively) of the MLI component. The MLI component electrically couples various devices (e.g., p-type transistors and / or n-type transistors, resistors, capacitors, and / or inductors of the multi-gate device 200) and / or elements (e.g., gate electrodes and / or epitaxial source / drain features of p-type transistors and / or n-type transistors of the multi-gate device 200) so that the various devices and / or elements can operate according to the design requirements of the multi-gate device 200. In some embodiments, the multi-gate device 200 has: a first transistor including a gate structure 250A disposed between respective epitaxial source / drain features 255 and surrounding respective channel regions of the fin 212A; a second transistor including a gate structure 250B disposed between respective epitaxial source / drain features 255 and surrounding respective channel regions of the fin 212B; a third transistor including a gate structure 250C disposed between respective epitaxial source / drain features 255 and surrounding respective channel regions of the fin 212A; and a fourth transistor including a gate structure 250C disposed between respective epitaxial source / drain features 255 and surrounding respective channel regions of the fin 212B. At least one of the first transistor, the second transistor, the third transistor, or the fourth transistor is a p-type transistor. In some embodiments, the p-type transistor includes an n-type channel arranged between p-type source / drain regions, wherein the n-type channel includes n-doped crystalline germanium or n-doped crystalline silicon (e.g., the channel region of fins 212A, 212B), and the source / drain region includes p-doped crystalline germanium or p-doped crystalline silicon germanium (boron doped and / or gallium doped in some embodiments). In such embodiments, the doped crystalline layer 285' includes gallium-doped crystalline germanium, which reduces the contact resistivity of the p-type transistor, thereby reducing the parasitic source / drain resistance and improving the performance of the p-type transistor. The MLI component includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components, such as device-level contacts and / or vias, and / or horizontal interconnect components, such as wires. Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI component. During operation, the interconnect component is configured to route signals between and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to elements of the device and / or multi-gate device 200. Fabrication may continue with forming additional portions of the MLI component, such as one or more gate contacts, vias, and / or conductive lines.

[0040] In some embodiments, when one or more transistors of the multi-gate device 200 are configured as gate all around (GAA), the metal gate stacks of the gate structures 250A-250C (i.e., the gates 272A-272C and the gate dielectrics 270A-270C) are arranged along the top surface, bottom surface, and sidewalls of the channel layer of the transistor. FIG. 18A to FIG. 1 8C (Figure 18C is collectively referred to as Figure 18C-1 , Figure 18C-2 and Figure 18C-3 ), which are useful in manufacturing according to various aspects of the present invention Figure 1 A partial perspective view of part or all of a multi-gate device 300 manufactured by a method for forming source / drain contacts of the GAA. In such an embodiment, before performing the fin manufacturing process of FIG. 3 , a semiconductor layer stack is formed above the substrate 202, and the fin 212A and the fin 212B both include the semiconductor layer stack. In a further improvement of such an embodiment, during the gate replacement process, before forming the gate dielectric layer 270, a channel release process is performed to selectively remove the first layer of the semiconductor layer stack relative to the second layer of the semiconductor layer stack, so that the second layer of the semiconductor layer stack of the fins 212A, 212B is suspended above the substrate 202 in the channel region of the GAA. For example, in FIG. 18A to FIG. 1 In FIG. 8C, semiconductor layer 312A and semiconductor layer 312B (both of which may be referred to as suspended channel layers) are suspended above substrate 202. Therefore, a metal gate stack (here gate electrodes 272A-272C and gate dielectrics 270A-270C) surrounds semiconductor layers 312A, 312B. In some embodiments, the metal gate stack partially surrounds semiconductor layers 312A, 312B. In a further improvement of such embodiments, when forming epitaxial source / drain features 255, the semiconductor layer stack of fins 212A, 212B may be subjected to source / drain etching as when forming FinFETs, so that the source / drain regions of GAA are similar to those of the gate electrodes 272A-272C and gate dielectrics 270A-270C. Figure 18C-1 In some embodiments, a channel release process is performed to selectively remove a first layer of the semiconductor layer stack relative to a second layer of the semiconductor layer stack, thereby suspending the second layer of the semiconductor layer stack of the fins 212A, 212B above the substrate 202 in the source / drain region of the GAA. For example, Figure 18C-2 or Figure 18C-3 As shown, the semiconductor layer 312A and the semiconductor layer 312B may also be suspended above the substrate 202 in the source / drain region of the GAA. In such embodiments, the epitaxial source / drain features 255 surrounding the suspended semiconductor layers 312A, 312B in the source / drain region of the GAA may be merged together, for example Figure 18C-2 As shown, or may not be combined together, for example Figure 18C-3Thus, in a GAA, the doped crystalline layer 285 may surround the epitaxial source / drain features 255 and the suspended semiconductor layers 312A, 312B, as shown. Figure 18C-2 As shown, or surrounding the epitaxial source / drain features 255 and the suspended semiconductor layers 312A, 312B, as Figure 18C-3 As shown. Depending on the design considerations of the multi-gate device 300, the present invention encompasses other configurations of the epitaxial source / drain features 255 and the doped crystalline layer 285'. The present invention further encompasses embodiments in which the multi-gate device 300 does not include the epitaxial source / drain features 255, such that the doped amorphous layer 285' is directly disposed on and in physical contact with the suspended semiconductor layers 312A, 312B. In some embodiments, Figure 18C-2 and Figure 18C-3 In the embodiment, the multi-gate device 300 does not include the epitaxial source / drain features 255, and the doped amorphous layer 285' is directly disposed on the suspended semiconductor layers 312A, 312B in the source / drain region of the GAA. In such embodiments, the doped amorphous layer 285' surrounds the suspended semiconductor layers 312A, 312B. In further refinements of such embodiments, the doped amorphous layer 285' surrounding the suspended semiconductor layers 312A, 312B may be merged together between the suspended semiconductor layers 312A, 312B, or may not be merged together between the suspended semiconductor layers 312A, 312B, depending on design and / or process considerations.

[0041] As can be seen from the previous description, the multi-gate device described in the present invention provides advantages over conventional multi-gate devices. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages in this article, and no specific advantages are required for all embodiments. The present invention provides many different embodiments. An exemplary device includes a channel layer, a first epitaxial source / drain component, and a second epitaxial source / drain component arranged above a substrate. The channel layer is arranged between the first epitaxial source / drain component and the second epitaxial source / drain component. The device also includes: a metal gate, arranged between the first epitaxial source / drain component and the second epitaxial source / drain component. The metal gate is arranged above at least two sides of the channel layer and in physical contact with it. The device also includes: a source / drain contact, arranged above the first epitaxial source / drain component. The device also includes: a doped crystalline semiconductor layer, arranged between the first epitaxial source / drain component and the source / drain contact. The doped crystalline semiconductor layer is arranged above at least two sides of the first epitaxial source / drain component and in physical contact with it. In some embodiments, the doped crystalline semiconductor layer is a gallium-doped crystalline germanium layer. In some embodiments, the doped crystalline semiconductor layer has a thickness of less than about 1×10 -9 Ω-cm 2 Contact resistivity (ρc ). In some embodiments, the doped crystalline semiconductor layer includes a p-type dopant and does not contain carbon. In some embodiments, the channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the fin, the first epitaxial source / drain component surrounds a first source / drain region of the semiconductor fin, and the second epitaxial source / drain component surrounds a second source / drain region of the semiconductor fin, and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component. In some embodiments, the channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the fin, the first epitaxial source / drain component is arranged above the first source / drain region of the semiconductor fin, and the second epitaxial source / drain component is arranged above the second source / drain region of the semiconductor fin, and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component.

[0042] In some embodiments, the channel layer is a channel region of a suspended semiconductor layer disposed above the substrate. In such embodiments, the metal gate surrounds the channel region of the suspended semiconductor layer. In such embodiments, the first epitaxial source / drain component surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain component surrounds a second source / drain region of the suspended semiconductor layer, and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component and the first source / drain region of the suspended semiconductor layer. In some embodiments, the channel layer is a channel region of a suspended semiconductor layer disposed above the substrate. In such embodiments, the metal gate surrounds the channel region of the suspended semiconductor layer. In such embodiments, the first epitaxial source / drain component surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain component surrounds a second source / drain region of the suspended semiconductor layer, and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component and the first source / drain region of the suspended semiconductor layer.

[0043] Another exemplary device includes: an n-type channel layer, a first p-type epitaxial source / drain component, and a second p-type epitaxial source / drain component, arranged above a substrate. The n-type channel layer is arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. A metal gate is arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. The metal gate is arranged above and in physical contact with at least two sides of the n-type channel layer. A first gallium-doped crystalline germanium layer is arranged above and in physical contact with at least two sides of the first p-type epitaxial source / drain component, and a second gallium-doped crystalline germanium layer is arranged above and in physical contact with at least two sides of the second p-type epitaxial source / drain component. The first gallium-doped crystalline germanium layer separates the first p-type epitaxial source / drain component from a first source / drain contact, and the second gallium-doped crystalline germanium layer separates the second p-type epitaxial source / drain component from a second source / drain contact. In some embodiments, the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component each include p-doped crystalline germanium. In such embodiments, the first dopant concentration of gallium in the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer is greater than the second dopant concentration of p-type dopant in the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. In some embodiments, the first p-type epitaxial source / drain component is arranged above the first source / drain region of the fin, and the second p-type epitaxial source / drain component is arranged above the second source / drain region of the fin, and the fin includes p-doped crystalline silicon. In some embodiments, the first p-type epitaxial source / drain component is arranged above the first source / drain region of the fin, the second p-type epitaxial source / drain component is arranged above the second source / drain region of the fin, and the fin includes p-doped crystalline germanium. In some embodiments, the n-type channel layer includes n-doped crystalline germanium. In some embodiments, the n-type channel layer includes n-doped crystalline silicon. In some embodiments, the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer each contain no carbon.

[0044] An exemplary method includes: forming a source / drain contact opening in a dielectric layer, the opening exposing a source / drain component of a multi-gate device; performing a deposition process to form a doped amorphous semiconductor layer above the multi-gate device, wherein the doped amorphous semiconductor layer partially fills the source / drain contact opening and surrounds the source / drain component of the multi-gate device; performing an annealing process to crystallize at least a portion of the doped amorphous semiconductor layer surrounding the source / drain component, thereby forming a doped crystalline semiconductor layer surrounding the source / drain component of the multi-gate device; and forming a source / drain contact in a remaining portion of the source / drain contact opening. In some embodiments, the depositing the amorphous layer includes performing an atomic layer deposition process of a gallium precursor. In some embodiments, the depositing the amorphous layer includes performing a physical vapor deposition process of a gallium target. In some embodiments, the method further includes removing a remaining portion of the doped amorphous semiconductor layer from above the multi-gate device, and then forming the source / drain contact in a remaining portion of the source / drain contact opening. In some embodiments, performing the annealing process includes performing a laser annealing process. In some embodiments, a source / drain contact opening is formed after performing a gate replacement process, wherein the dummy gate is replaced with a metal gate.

[0045] An embodiment of the present application provides a device comprising: a channel layer, a first epitaxial source / drain component, and a second epitaxial source / drain component, which are arranged above a substrate, wherein the channel layer is arranged between the first epitaxial source / drain component and the second epitaxial source / drain component; a metal gate, which is arranged between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the metal gate is arranged above at least two sides of the channel layer and in physical contact with the at least two sides; a source / drain contact, which is arranged above the first epitaxial source / drain component; and a doped crystalline semiconductor layer, which is arranged between the first epitaxial source / drain component and the source / drain contact, wherein the doped crystalline semiconductor layer is arranged above at least two sides of the first epitaxial source / drain component and in physical contact with the at least two sides of the first epitaxial source / drain component.

[0046] In some embodiments, the doped crystalline semiconductor layer is a gallium-doped crystalline germanium layer. In some embodiments, the doped crystalline semiconductor layer has a thickness of less than about 1×10 -9 Ω-cm 2 Contact resistivity (ρ c). In some embodiments, the doped crystalline semiconductor layer includes a p-type dopant and does not contain carbon. In some embodiments, the channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the fin; the first epitaxial source / drain component surrounds a first source / drain region of the semiconductor fin, and the second epitaxial source / drain component surrounds a second source / drain region of the semiconductor fin; and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component. In some embodiments, the channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the fin; the first epitaxial source / drain component is arranged above the first source / drain region of the semiconductor fin, and the second epitaxial source / drain component is arranged above the second source / drain region of the semiconductor fin; and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component. In some embodiments, the channel layer is a channel region of a suspended semiconductor layer disposed above the substrate, wherein the metal gate surrounds the channel region of the suspended semiconductor layer; the first epitaxial source / drain component surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain component surrounds a second source / drain region of the suspended semiconductor layer; and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component and the first source / drain region of the suspended semiconductor layer. In some embodiments, the channel layer is a channel region of a suspended semiconductor layer disposed above the substrate, wherein the metal gate surrounds the channel region of the suspended semiconductor layer; the first epitaxial source / drain component surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain component surrounds the second source / drain region of the suspended semiconductor layer; and the doped crystalline semiconductor layer surrounds the first epitaxial source / drain component and the first source / drain region of the suspended semiconductor layer.

[0047] An embodiment of the present application provides a device, comprising: an n-type channel layer, a first p-type epitaxial source / drain component, and a second p-type epitaxial source / drain component, arranged above a substrate, wherein the n-type channel layer is arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component; a metal gate, arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component, wherein the metal gate is arranged above at least two sides of the n-type channel layer and in physical contact with the at least two sides; and a first gallium-doped crystalline germanium layer, arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. A first p-type epitaxial source / drain component is disposed above at least two sides of the first p-type epitaxial source / drain component and in physical contact with the at least two sides of the first p-type epitaxial source / drain component, and a second gallium-doped crystalline germanium layer is disposed above at least two sides of the second p-type epitaxial source / drain component and in physical contact with the at least two sides of the second p-type epitaxial source / drain component, wherein the first gallium-doped crystalline germanium layer separates the first p-type epitaxial source / drain component from the first source / drain contact, and the second gallium-doped crystalline germanium layer separates the second p-type epitaxial source / drain component from the second source / drain contact.

[0048] In some embodiments, the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component each include p-doped crystalline germanium; and wherein the first dopant concentration of gallium in the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer is greater than the second dopant concentration of the p-type dopant in the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component. In some embodiments, the first p-type epitaxial source / drain component is disposed over a first source / drain region of a fin, and the second p-type epitaxial source / drain component is disposed over a second source / drain region of the fin; and the fin includes p-doped crystalline silicon. In some embodiments, the first p-type epitaxial source / drain component is disposed over a first source / drain region of a fin, and the second p-type epitaxial source / drain component is disposed over a second source / drain region of the fin; and the fin includes p-doped crystalline germanium. In some embodiments, the n-type channel layer includes n-doped crystalline germanium. In some embodiments, the n-type channel layer includes n-doped crystalline silicon. In some embodiments, the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer each contain no carbon.

[0049] An embodiment of the present application provides a method, comprising: forming a source / drain contact opening in a dielectric layer, the opening exposing a source / drain component of a multi-gate device; performing a deposition process to form a doped amorphous semiconductor layer above the multi-gate device, wherein the doped amorphous semiconductor layer partially fills the source / drain contact opening and surrounds the source / drain component of the multi-gate device; performing an annealing process to crystallize at least the portion of the doped amorphous semiconductor layer surrounding the source / drain component, thereby forming a doped crystalline semiconductor layer surrounding the source / drain component of the multi-gate device; and forming a source / drain contact in the remaining portion of the source / drain contact opening.

[0050] In some embodiments, depositing the amorphous layer comprises performing an atomic layer deposition process of a gallium precursor. In some embodiments, depositing the amorphous layer comprises performing a physical vapor deposition process of a gallium target. In some embodiments, further comprising removing a remaining portion of the doped amorphous semiconductor layer from above the multi-gate device before forming the source / drain contact in the remaining portion of the source / drain contact opening. In some embodiments, performing the annealing process comprises performing a laser annealing process.

[0051] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present invention.

Claims

1. A multi-gate device having: A channel layer, a first epitaxial source / drain component, and a second epitaxial source / drain component are arranged above the substrate, wherein: The channel layer is disposed between the first epitaxial source / drain feature and the second epitaxial source / drain feature; a metal gate disposed between the first epitaxial source / drain component and the second epitaxial source / drain component, wherein the metal gate is disposed over and in physical contact with at least two sides of the channel layer; a source / drain contact disposed over the first epitaxial source / drain feature; and a doped crystalline semiconductor layer disposed between the first epitaxial source / drain component and the source / drain contact, wherein: the doped crystalline semiconductor layer is disposed over and in physical contact with the first sidewall, the second sidewall, and the top of the first epitaxial source / drain feature, The doped crystalline semiconductor layer has a uniform thickness over the first sidewall, the second sidewall, and the top.

2. The multi-gate device according to claim 1, wherein: The doped crystalline semiconductor layer is a gallium-doped crystalline germanium layer.

3. The multi-gate device according to claim 1, wherein: The doped crystalline semiconductor layer has a thickness less than about 1 x 10 -9 Ω-cm 2 Contact resistivity (ρ c ).

4. The multi-gate device according to claim 1, wherein: The doped crystalline semiconductor layer includes a p-type dopant and does not contain carbon.

5. The multi-gate device according to claim 1, wherein: The channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the semiconductor fin; The first epitaxial source / drain feature surrounds a first source / drain region of the semiconductor fin, and the second epitaxial source / drain feature surrounds a second source / drain region of the semiconductor fin; and The doped crystalline semiconductor layer surrounds the first epitaxial source / drain feature.

6. The multi-gate device according to claim 1, wherein: The channel layer is a channel region of a semiconductor fin extending from the substrate, and the metal gate surrounds the semiconductor fin; The first epitaxial source / drain feature is disposed over a first source / drain region of the semiconductor fin, and the second epitaxial source / drain feature is disposed over a second source / drain region of the semiconductor fin; and The doped crystalline semiconductor layer surrounds the first epitaxial source / drain feature.

7. The multi-gate device according to claim 1, wherein: The channel layer is a channel region of a suspended semiconductor layer arranged above the substrate, wherein the metal gate surrounds the channel region of the suspended semiconductor layer; The first epitaxial source / drain feature surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain feature surrounds a second source / drain region of the suspended semiconductor layer; and The doped crystalline semiconductor layer surrounds the first epitaxial source / drain features and the first source / drain region of the suspended semiconductor layer.

8. The multi-gate device according to claim 1, wherein: The channel layer is a channel region of a suspended semiconductor layer arranged above the substrate, wherein the metal gate surrounds the channel region of the suspended semiconductor layer; The first epitaxial source / drain feature surrounds a first source / drain region of the suspended semiconductor layer, and the second epitaxial source / drain feature surrounds a second source / drain region of the suspended semiconductor layer; and The doped crystalline semiconductor layer surrounds the first epitaxial source / drain features and the first source / drain region of the suspended semiconductor layer.

9. A multi-gate device, comprising: an n-type channel layer, a first p-type epitaxial source / drain component, and a second p-type epitaxial source / drain component, arranged above the substrate, wherein the n-type channel layer is arranged between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component; a metal gate disposed between the first p-type epitaxial source / drain component and the second p-type epitaxial source / drain component, wherein the metal gate is disposed over and in physical contact with at least two sides of the n-type channel layer; and a first gallium-doped crystalline germanium layer disposed over and in physical contact with at least two sides of the first p-type epitaxial source / drain component and a second gallium-doped crystalline germanium layer disposed over and in physical contact with at least two sides of the second p-type epitaxial source / drain component, wherein the first gallium-doped crystalline germanium layer separates the first p-type epitaxial source / drain component from a first source / drain contact and the second gallium-doped crystalline germanium layer separates the second p-type epitaxial source / drain component from a second source / drain contact.

10. The multi-gate device according to claim 9, wherein: The first p-type epitaxial source / drain feature and the second p-type epitaxial source / drain feature each include p-doped crystalline germanium; and Wherein a first dopant concentration of gallium in the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer is greater than a second dopant concentration of p-type dopant in the first p-type epitaxial source / drain feature and the second p-type epitaxial source / drain feature.

11. The multi-gate device according to claim 10, wherein: The first p-type epitaxial source / drain feature is disposed over a first source / drain region of a fin, and the second p-type epitaxial source / drain feature is disposed over a second source / drain region of the fin; and The fin includes p-doped crystalline silicon.

12. The multi-gate device according to claim 10, wherein The first p-type epitaxial source / drain feature is disposed over a first source / drain region of a fin, and the second p-type epitaxial source / drain feature is disposed over a second source / drain region of the fin; and The fin includes p-doped crystalline germanium.

13. The multi-gate device according to claim 9, wherein: The n-type channel layer includes n-doped crystalline germanium.

14. The multi-gate device according to claim 9, wherein: The n-type channel layer includes n-doped crystalline silicon.

15. The multi-gate device according to claim 9, wherein: Each of the first gallium-doped crystalline germanium layer and the second gallium-doped crystalline germanium layer does not contain carbon.

16. A method of forming a multi-gate device, comprising: forming source / drain contact openings in the dielectric layer, the openings exposing source / drain features of the multi-gate device; performing a deposition process to form a doped amorphous semiconductor layer over the multi-gate device, wherein the doped amorphous semiconductor layer partially fills the source / drain contact openings and surrounds the source / drain features of the multi-gate device; performing an annealing process to crystallize at least a portion of the doped amorphous semiconductor layer surrounding the source / drain features, thereby forming a doped crystalline semiconductor layer surrounding the source / drain features of the multi-gate device; and Source / drain contacts are formed in remaining portions of the source / drain contact openings.

17. The method for forming a multi-gate device according to claim 16, wherein: The performing a deposition process to form the doped amorphous semiconductor layer includes performing an atomic layer deposition process using a gallium precursor.

18. The method for forming a multi-gate device according to claim 16, wherein: The performing a deposition process to form the doped amorphous semiconductor layer includes performing a physical vapor deposition process using a gallium target.

19. The method of forming a multi-gate device of claim 16, further comprising removing a remaining portion of the doped amorphous semiconductor layer from over the multi-gate device before forming the source / drain contacts in the remaining portions of the source / drain contact openings.

20. The method for forming a multi-gate device according to claim 16, wherein: The performing the annealing process includes performing a laser annealing process.

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