Isolation structure of a semiconductor device and manufacturing method thereof

Abstract

The present application provides an isolation structure for a semiconductor device and a manufacturing method thereof. The isolation structure includes: a substrate, a deep trench located in the substrate, a first oxide layer located on the surface of the deep trench, and polysilicon located on the first oxide layer. The first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer. A sidewall is located on the sidewall of the polysilicon that protrudes above the first oxide layer, and the sidewall covers at least the first oxide layer at the top of the deep trench. The sidewall can protect the oxide layers on both sides of the top of the deep trench from being corroded, prevent the adverse effects on device characteristics caused by the loss of the oxide layers on both sides of the top of the deep trench, and save the process cost. Since the finally formed isolation structure retains the sidewall and does not remove the sidewall, it is possible to avoid the adverse effects on device performance caused by the too-thin oxide layer remaining near the deep trench, and provide a sufficient process window for the semiconductor process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to an isolation structure of a semiconductor device and a manufacturing method thereof. Background Art

[0002] Deep Trench Isolation (DTI) technology uses an insulating medium in a deep trench to isolate devices on both sides of the deep trench structure. Different devices can be formed on both sides of the deep trench structure, so that different devices do not affect each other. Specifically, the substrate can be etched first to obtain a trench, and then an oxide layer is formed by a deposition or furnace tube oxidation process. The oxide layer covers the sidewalls and the bottom surface of the trench and is also formed on the surface of the substrate. Then, polysilicon is filled in the trench, and the oxide layer on the surface of the substrate is removed to obtain the deep trench structure. The deep trench structure can be used for LDMOS transistors, bipolar devices, medium and low voltage MOS transistors, etc.

[0003] However, when removing the oxide layer on the surface of the substrate by dry etching or wet etching, the oxide layer on the top sidewalls of the deep trench structure is easily damaged, which will affect the device performance. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide an isolation structure of a semiconductor device and a manufacturing method thereof, which can protect the oxide layer on the top sidewalls of the deep trench structure when removing the oxide layer on the surface of the substrate, avoid its damage, and avoid the impact on the device performance.

[0005] In a first aspect, an embodiment of this application provides an isolation structure of a semiconductor device, including:

[0006] A substrate;

[0007] A deep trench located in the substrate;

[0008] A first oxide layer located on the surface of the deep trench and polysilicon located on the first oxide layer; the first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer;

[0009] A sidewall located on the sidewalls of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench.

[0010] Optionally, the lateral dimension at the bottom of the sidewall is greater than or equal to the width of the deep trench.

[0011] Optionally, the lateral dimension of the polysilicon protruding above the first oxide layer is greater than or equal to the lateral dimension of the polysilicon in the deep trench.

[0012] Optionally, the sidewall is silicon nitride or a stack of silicon oxide and silicon nitride.

[0013] Optionally, the lateral dimension of the polysilicon protruding above the first oxide layer is smaller than the lateral dimension of the polysilicon in the deep trench.

[0014] Optionally, the material of the sidewall is silicon oxide.

[0015] Optionally, the polysilicon protrudes 0 - 1 μm above the substrate surface.

[0016] Optionally, the depth of the deep trench is 5 - 50 μm; the width of the deep trench is 1 - 5 μm.

[0017] Optionally, the isolation structure is applied to at least LDMOS transistors, bipolar devices, or medium - low voltage MOS transistors.

[0018] In a second aspect, an embodiment of the present application provides a method for manufacturing an isolation structure of a semiconductor device, including:

[0019] Providing a substrate; forming a deep trench in the substrate, forming a first oxide layer on the surface of the deep trench and the substrate surface, and filling polysilicon in the deep trench;

[0020] Removing a part of the thickness of the first oxide layer on the substrate surface to make the polysilicon protrude above the first oxide layer;

[0021] Forming a sidewall on the sidewalls of the part of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench;

[0022] Using the sidewall as a mask to remove the first oxide layer outside the sidewall.

[0023] Optionally, forming a sidewall on the sidewalls of the part of the polysilicon protruding above the first oxide layer includes:

[0024] Forming a sidewall material covering the polysilicon and the first oxide layer by a deposition process;

[0025] Performing anisotropic etching on the sidewall material to form a sidewall on the sidewalls of the part of the polysilicon protruding above the first oxide layer.

[0026] Optionally, the sidewall material includes one of silicon oxide and silicon nitride or a stack of both.

[0027] Optionally, forming a sidewall on the sidewalls of the part of the polysilicon protruding above the first oxide layer includes:

[0028] Performing surface oxidation on the part of the polysilicon exceeding the first oxide layer, and using the silicon oxide on the sidewalls of the polysilicon as the sidewall of the part of the polysilicon protruding above the first oxide layer.

[0029] Optionally, the polysilicon protrudes 0 - 1 μm above the substrate surface.

[0030] Optionally, the depth of the deep trench is 5 - 50 μm; the width of the deep trench is 1 - 5 μm.

[0031] Optionally, the isolation structure is applied to at least LDMOS transistors, bipolar devices, or medium - low voltage MOS transistors.

[0032] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages: The present application provides an isolation structure of a semiconductor device and a manufacturing method thereof. The isolation structure includes: a substrate, a deep trench located in the substrate, a first oxide layer located on the surface of the deep trench, and polysilicon located on the first oxide layer. The first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer. A sidewall is located on the sidewall of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench. The sidewall can protect the oxide layers on both sides of the top of the deep trench from being corroded, prevent the adverse effects on the device performance caused by the loss of the oxide layers on both sides of the top of the deep trench, and save the process cost. And if the remaining film of the first oxide layer near the deep trench is too thin, it will affect the device performance. The retention of the sidewall provides a sufficient process window for this process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 Shows a flowchart of a manufacturing method of an isolation structure of a semiconductor device provided by an embodiment of the present application;

[0035] Figures 2 - 6 Shows a schematic diagram of the structure during the formation of an isolation structure of a semiconductor device provided by an embodiment of the present application.

[0036] Figure 7A Shows a schematic diagram of a semiconductor structure after an active region process provided by an embodiment of the present application;

[0037] Figure 7B Shows another schematic diagram of a semiconductor structure after an active region process provided by an embodiment of the present application;

[0038] Figure 8A Shows another schematic diagram of a semiconductor structure after an active region process provided by an embodiment of the present application;

[0039] Figure 8B FIG. shows a schematic diagram of another semiconductor structure processed through an active region process provided by an embodiment of the present application. Detailed implementation manners

[0040] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings.

[0041] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0042] Secondly, the present application will be described in detail in conjunction with the schematic diagrams. When describing the embodiments of the present application in detail, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0043] As described in the background art, the Deep Trench Isolation (DTI) technology uses the insulating medium in the deep trench to isolate the devices on both sides of the deep trench structure, so that different devices will not affect each other. Specifically, the substrate can be etched first to obtain a trench, and then an oxide layer is formed by a deposition process or a furnace tube oxidation process. The oxide layer covers the sidewalls and the bottom surface of the trench and is also formed on the substrate surface. Then, polysilicon is filled in the trench, and the oxide layer on the substrate surface is removed to obtain the deep trench structure. The deep trench structure can be used for LDMOS transistors, bipolar devices, medium and low voltage MOS transistors, etc.

[0044] However, when removing the oxide layer on the substrate surface by dry etching or wet etching, the oxide layer on the top sidewalls of the deep trench structure is easily damaged, which will affect the device performance.

[0045] Based on the above technical problems, the present application provides an isolation structure for a semiconductor device and a manufacturing method thereof. The isolation structure includes: a substrate, a deep trench located in the substrate, a first oxide layer located on the surface of the deep trench, and polysilicon located on the first oxide layer. The first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer. A sidewall is located on the sidewalls of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench. The sidewall can protect the oxide layers on both sides of the top of the deep trench from being etched away, prevent the adverse effects on the device performance caused by the loss of the oxide layers on both sides of the top of the deep trench, and save the process cost. And if the remaining film of the oxide layer near the deep trench is too thin, it will affect the device performance. The retention of the sidewall provides a sufficient process window for this process.

[0046] To better understand the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0047] Exemplary method

[0048] See Figure 1 , which is a flowchart of a method for manufacturing a semiconductor device isolation structure provided by an embodiment of the present application. As Figure 1 shown, it may include:

[0049] S101: Provide a substrate; form a deep trench in the substrate, form a first oxide layer on the surface of the deep trench and the surface of the substrate, and fill polysilicon in the deep trench.

[0050] S102: Remove a part of the thickness of the first oxide layer on the surface of the substrate to make the polysilicon protrude above the first oxide layer.

[0051] See Figure 2 shown, which is a schematic diagram of the structure during the formation of a semiconductor device isolation structure provided by an embodiment of the present application. Provide a substrate 101. The substrate 101 provided by the embodiment of the present application is a semiconductor substrate, for example, it can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. In this embodiment, the substrate 101 is a bulk silicon substrate.

[0052] Form a deep trench in the substrate 101, form a first oxide layer 102 on the surface of the deep trench and the surface of the substrate 101, and fill polysilicon 103 in the deep trench.

[0053] In the embodiment of the present application, when the polysilicon is formed, it covers the surface of the first oxide layer 102 and is also filled in the deep trench. First, the polysilicon on the surface of the first oxide layer 102 is removed by a chemical mechanical polishing process or an etching process. At this time, the first oxide layer 102 remains on the surface of the substrate 101, and the deep trench is filled with polysilicon 103.

[0054] Remove a part of the thickness of the first oxide layer 102 on the surface of the substrate 101 to make the polysilicon 103 protrude above the first oxide layer 102.

[0055] Optionally, a part of the first oxide layer 102 on both sides of the polysilicon 103 can be etched away by wet etching, so that the polysilicon 103 in the deep trench is exposed, forming a polycrystalline column as shown in Figure 2 . Specifically, the polysilicon 103 can be 0-1 μm higher than the surface of the substrate 101; the depth of the deep trench can be 5-50 μm, and the width of the deep trench can be 1-5 μm.

[0056] S103: Form sidewalls on the sidewalls of the polysilicon that are higher than the first oxide layer, and the sidewalls cover at least the first oxide layer on the top of the deep trench.

[0057] Refer to Figure 3 . As shown, a sidewall material 105 covering the polysilicon 103 and the first oxide layer 102 can be formed by a deposition process. Among them, the sidewall material 105 can be silicon nitride, or a stack of silicon nitride and silicon oxide (deposit a layer of silicon nitride first, and then deposit a layer of silicon oxide). For example, silicon nitride or silicon oxynitride can be deposited on the surface of the substrate 101 by thin film deposition, and then a layer of silicon oxide can be deposited using the PECVD process (Plasma Enhanced Chemical Vapor Deposition), forming a stack of O-N structure (oxide-nitride structure).

[0058] Refer to Figure 3 and Figure 4 . As shown, the sidewall material 105 can be anisotropically etched to form sidewalls 104 on the sidewalls of the polysilicon 103 that are higher than the first oxide layer 102. Optionally, if the sidewalls 104 formed by a single deposition process and anisotropic etching are not sufficient to completely cover the first oxide layer 102 on both sidewalls of the deep trench opening, multiple deposition processes and anisotropic etching can be performed to ensure that the bottom of the sidewalls 104 can completely cover the first oxide layer 102 on both sidewalls of the deep trench opening.

[0059] Refer to Figure 4 . As shown, sidewalls 104 are formed on the sidewalls of the polysilicon 103 that are higher than the first oxide layer 102, and the sidewalls 104 cover at least the first oxide layer on the top of the deep trench. In the embodiments of the present application, during the formation of the sidewalls 104, only the sidewalls on the surface of the deep trench are retained, and the sidewall material above the polysilicon 103 is etched away.

[0060] S104: Using the sidewalls as a mask, remove the first oxide layer outside the sidewalls.

[0061] Optionally, refer to Figure 5As shown, anisotropic etching can be used to etch the polysilicon 103 back to be flush with the surface of the sidewall 104, and then the first oxide layer 102 on the substrate surface can be completely etched away by wet etching.

[0062] Optionally, as an alternative method for forming the sidewall, referring to Figure 6 As shown, in step S103, the polysilicon 103 that is higher than the first oxide layer 102 can be directly surface-oxidized, and the silicon oxide 106 on the sidewall after oxidizing the polysilicon 103 is used as the sidewall of the polysilicon 103 sidewall that is higher than the first oxide layer 102. Since the volume of the silicon oxide 106 after oxidation becomes larger than the original volume, the first oxide layer 102 on both sidewalls of the deep trench opening can be covered.

[0063] See Figure 7A As shown, it is a schematic diagram of a semiconductor structure after the active region process provided by an embodiment of the present application. Figure 7A The field oxide layer 110 and the deep trench are arranged at intervals in

[0064] Optionally, the field oxide layer 110 can also be arranged in contact with the deep trench. See Figure 7B As shown, the embodiment of the present application does not make specific limitations here, and it can be set by those skilled in the art according to the actual situation.

[0065] In another optional embodiment, see Figure 8A As shown, Figure 8A The shallow trench isolation structure and the deep trench are arranged at intervals in

[0066] Optionally, the shallow trench isolation structure can also be arranged in contact with the deep trench. See Figure 8B As shown, the embodiment of the present application does not make specific limitations here, and it can be set by those skilled in the art according to the actual situation.

[0067] The present application provides a manufacturing method for an isolation structure of a semiconductor device. The method includes: providing a substrate, forming a deep trench in the substrate, forming a first oxide layer on the surface of the deep trench and the substrate surface, filling the deep trench with polysilicon, removing a part of the thickness of the first oxide layer on the substrate surface so that the polysilicon is higher than the first oxide layer, forming a sidewall on the sidewall of the polysilicon that is higher than the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench. Using the sidewall as a mask, the first oxide layer outside the sidewall is removed. Thus, while removing the first oxide layer on the substrate surface, the sidewall can protect the first oxide layers on both sides of the top of the deep trench from being etched away, preventing the adverse effects on the device performance caused by the loss of the oxide layers on both sides of the top of the deep trench, and saving the process cost.

[0068] Exemplary isolation structure

[0069] See Figure 5As shown in the figure, it is a schematic diagram of an isolation structure of a semiconductor device provided by an embodiment of the present application, including:

[0070] A substrate 101; a deep trench located in the substrate 101, a first oxide layer 102 located on the sidewall and bottom wall of the deep trench, and polysilicon 103 located in the deep trench, the polysilicon 103 being located on the first oxide layer 102 and filling the deep trench; the first oxide layer 102 also covering the surfaces of the substrate 101 on both sides of the deep trench; the polysilicon 103 protruding above the substrate, and the polysilicon 103 protruding above the first oxide layer 102;

[0071] A sidewall 104 located on the sidewall of the polysilicon 103 protruding above the first oxide layer 102, the sidewall covering the first oxide layer 102 on both sides of the deep trench, and the lateral dimension of the bottom of the sidewall 104 being greater than or equal to the width of the deep trench.

[0072] Optionally, the lateral dimension of the polysilicon protruding above the first oxide layer is greater than or equal to the lateral dimension of the polysilicon in the deep trench, and the sidewall is a silicon nitride or a stack of silicon oxide and silicon nitride.

[0073] Optionally, the lateral dimension of the polysilicon protruding above the first oxide layer is less than the lateral dimension of the polysilicon in the deep trench, and the material of the sidewall is silicon oxide.

[0074] Optionally, in addition to the above isolation structure, the semiconductor device provided by the embodiment of the present application may further include a field oxide layer and a shallow trench isolation structure. The field oxide layer and the shallow trench isolation structure may either be in contact with the deep trench or be spaced apart from the deep trench. A field oxide layer or a shallow trench isolation structure is formed on the surface of the substrate. The shallow trench isolation structure includes a shallow trench, a second oxide layer covering the surface of the shallow trench, and a silicon oxide material filled in the shallow trench.

[0075] The present application provides an isolation structure of a semiconductor device, including a substrate, a deep trench located in the substrate, a first oxide layer located on the surface of the deep trench, and polysilicon located on the first oxide layer. The first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer. A sidewall is located on the sidewall of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer at the top of the deep trench. Since the finally formed isolation structure retains the sidewall and does not remove the sidewall, it is possible to avoid the adverse effect on the device performance caused by the too thin remaining film of the first oxide layer near the deep trench, providing a sufficient process window for the semiconductor process.

[0076] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiment of the isolation structure, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiment.

[0077] The above description is only the preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. An isolation structure of a semiconductor device, characterized in that, Comprising: A substrate; A deep trench located in the substrate; A first oxide layer located on the surface of the deep trench and the surface of the substrate, and polysilicon is located on the first oxide layer on the surface of the deep trench; The first oxide layer and the polysilicon protrude above the substrate, and the polysilicon protrudes above the first oxide layer; A sidewall located on the sidewalls of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench; Using the sidewall as a mask, removing the first oxide layer outside the sidewall.

2. The isolation structure according to claim 1, wherein The lateral dimension at the bottom of the sidewall is greater than or equal to the width of the deep trench.

3. The isolation structure according to claim 2, wherein The lateral dimension of the polysilicon protruding above the first oxide layer is greater than or equal to the lateral dimension of the polysilicon in the deep trench.

4. The isolation structure according to claim 3, wherein The sidewall is silicon nitride, or silicon oxide, or a stack of silicon oxide and silicon nitride.

5. The isolation structure according to claim 2, wherein The lateral dimension of the polysilicon protruding above the first oxide layer is less than the lateral dimension of the polysilicon in the deep trench.

6. The isolation structure according to claim 5, wherein The material of the sidewall is silicon oxide.

7. The isolation structure according to any one of claims 1-6, characterized in that, The polysilicon protrudes 0 - 1 μm above the surface of the substrate.

8. The isolation structure according to any one of claims 1-6, characterized in that, The depth of the deep trench is 5 - 50 μm; the width of the deep trench is 1 - 5 μm.

9. The isolation structure according to any one of claims 1-6, characterized in that, The isolation structure is applied to at least LDMOS transistors, bipolar devices, or medium - low voltage MOS transistors.

10. A manufacturing method of an isolation structure of a semiconductor device, characterized in that, Comprising: Providing a substrate; Forming a deep trench in the substrate, forming a first oxide layer on the surface of the deep trench and the surface of the substrate, and filling polysilicon in the deep trench; Removing a part of the thickness of the first oxide layer on the surface of the substrate to make the polysilicon protrude above the first oxide layer; Forming a sidewall on the sidewalls of a part of the polysilicon protruding above the first oxide layer, and the sidewall covers at least the first oxide layer on the top of the deep trench; Using the sidewall as a mask, removing the first oxide layer outside the sidewall.

11. The method according to claim 10, characterized in that, The forming a sidewall on the sidewalls of a part of the polysilicon protruding above the first oxide layer includes: Forming a sidewall material covering the polysilicon and the first oxide layer by a deposition process; Performing anisotropic etching on the sidewall material to form a sidewall on the sidewalls of a part of the polysilicon protruding above the first oxide layer.

12. The method according to claim 11, wherein The sidewall material includes one of silicon oxide and silicon nitride or a stack of both.

13. The method according to claim 10, characterized in that, The forming a sidewall on the sidewalls of a part of the polysilicon protruding above the first oxide layer includes: Performing surface oxidation on the part of the polysilicon exceeding the first oxide layer, and using the silicon oxide on the sidewalls of the polysilicon as the sidewall on the sidewalls of a part of the polysilicon protruding above the first oxide layer.

14. The method according to any one of claims 10 to 13, characterized in that The polysilicon protrudes 0 - 1 μm above the surface of the substrate.

15. The method according to any one of claims 10 to 13, characterized in that The depth of the deep trench is 5 - 50 μm; the width of the deep trench is 1 - 5 μm.

16. The method according to any one of claims 10 to 13, characterized in that The isolation structure is applied to at least LDMOS transistors, bipolar devices, or medium - low voltage MOS transistors.

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