Adjustable Soft Turn-Off and Current Booster of Gate Driver

Abstract

A device controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges a control node for a first time length in response to a first signal through a first node, the first signal indicating a first level of a control signal and the absence of a fault condition. A second circuit discharges the control node for a second time length in response to a second signal through a second node, the second signal indicating a second level of the control signal and the absence of a fault condition. A third circuit includes a current amplifier and is configured as a soft turn-off path to discharge the control node for a third time length in response to the first signal through the first node, the first signal indicating the presence of a fault condition. The third time length is different from the second time length.

Description

Technical Field

[0001] This application relates to circuits, and more particularly to control circuits for high-power applications. Background Art

[0002] In a typical control application, a processor system provides one or more control signals to control a load system. During normal operation, there may be a large DC or transient voltage difference between the domain of the processor system and the domain of the load system, so an isolation barrier is required between the processor system and the load system. For example, one domain may be "grounded" at a voltage that differs (switches) by hundreds or thousands of volts relative to earth ground. Thus, the intermediate system includes isolation that prevents harmful current from flowing between the processor system and the load system. Although the isolation prevents the processor system from being coupled to the load system through a direct conduction path, an isolation communication channel allows communication between the two systems using optical (optoisolators), capacitive, inductive (transformers), or electromagnetic techniques. In at least one embodiment, the isolation communication channel blocks DC signals and passes only AC signals. The intermediate system typically uses a voltage converter and an output driver to provide control signals at a voltage level suitable for the load system.

[0003] Reference Figure 1 , in an exemplary AC motor control application, a processor 100, which can be a microprocessor, a microcontroller, or other suitable processor device, operates in a first domain (i.e., VDD1, e.g., 5 volts (V)), and provides one or more signals to a high-power load system operating in a second domain (i.e., VDD3, e.g., 600V). Each system 102 includes an isolation barrier 130 and an isolation communication channel for safely transmitting control signals from the processor 100 to a driver 106, which drives high-power drive devices 108 and 109 of a three-phase inverter that delivers three-phase power to an AC motor 120. Exemplary high-power drive devices include power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN) MOSFETs, silicon carbide power MOSFETs, or other suitable devices capable of delivering high current in a short period of time.

[0004] The voltage converter 104 converts the available supply voltage from VDD3 to a voltage level (i.e., VDD2, e.g., about 15V) that can be used by the high side of the system 102 and the driver 106. Note that in other embodiments, a single voltage converter 104 converts one supply voltage from a first voltage level (e.g., VDD3) to multiple other voltage levels (e.g., VDD1 and VDD2) and / or provides multiple outputs of a specific voltage (e.g., multiple VDD2 outputs corresponding to multiple systems 102). The driver 106 provides switching control signals at the levels required to drive the devices 108 or 109 of the three-phase AC inverter at their respective high powers. The load motor requires three-phase power at a high power level. The system 102 corresponding to the high-power device (high-side inverter device) coupled to VDD3 is "grounded" at a voltage at a high voltage level that is different from the earth ground by VDD3. The typical high-power drive devices 108 and 109 of the three-phase AC inverter for driving the AC motor 120 require a relatively large turn-on voltage (e.g., a voltage in the range of dozens of volts) and are vulnerable to fault conditions that may damage these devices. Therefore, flexible techniques for handling fault conditions without damaging the high-power drive devices or the loads controlled by those devices are desired. SUMMARY OF THE INVENTION

[0005] In at least one embodiment of the present invention, an apparatus for controlling a high-power drive device external to a package of a gate driver circuit includes a first circuit coupled between a first node and a control node. The first circuit is configured to charge the control node for a first time length in response to a first signal passing through the first node, the first signal indicating a first level of a control signal and the absence of a fault condition. The apparatus includes a second circuit coupled between a second node and the control node. The second circuit is configured to discharge the control node for a second time length in response to a second signal passing through the second node, the second signal indicating a second level of the control signal and the absence of a fault condition. The apparatus includes a third circuit coupled between the first node and the control node. The third circuit includes a current amplifier and is configured as a soft turn-off path to discharge the control node for a third time length in response to the first signal passing through the first node, the first signal indicating the presence of a fault condition. The third time length is different from the second time length.

[0006] In at least one embodiment of the present invention, a method for controlling a high-power drive device external to a package of a gate drive circuit includes: in response to the absence of a fault condition and a first level of a control signal, charging a control node using a first node for a first time length. The method includes discharging the control node using a second node for a second time length in response to a second level of the control signal and the absence of a fault condition. The second time length is different from the first time length. The method includes discharging the control node using the first node for a third time length in response to the presence of a fault condition. The third time length is different from the second time length. Discharging the control node for the third time length includes: attenuating the voltage on the control node using a passive component; and amplifying a first current through the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be better understood by reference to the accompanying drawings, and many of its objects, features, and advantages will be apparent to those skilled in the art.

[0008] Figure 1 A functional block diagram of an exemplary motor control system is shown.

[0009] Figure 2 A functional block diagram of a portion of an exemplary motor control system including a fault detection circuit and a driver control circuit is shown. Figure 1 of an exemplary motor control system is shown.

[0010] Figures 3A - 3C is shown Figure 2 of the voltage waveform of the switch node of the motor control system.

[0011] Figure 4 Details of an exemplary control signal of a gate drive circuit according to at least one embodiment of the present invention are shown. Figure 2 of a gate drive circuit according to at least one embodiment of the present invention are shown.

[0012] Figure 5A and Figure 5B A functional block diagram of a portion of a motor control system with adjustable soft turn-off according to various embodiments of the present invention is shown.

[0013] Figure 6 A functional block diagram of a portion of a motor control system with adjustable soft turn-off and a current booster according to at least one embodiment of the present invention is shown.

[0014] Figure 7 A functional block diagram of a portion of a packaged driver integrated circuit product with cost-reduced adjustable soft turn-off and a current booster according to at least one embodiment of the present invention is shown.

[0015] Figure 8A functional block diagram of a portion of a packaged driver integrated circuit product with adjustable soft shutdown, a current booster, and additional features in accordance with at least one embodiment of the present invention is shown.

[0016] Like reference numerals are used to represent like or identical items in the different figures. Detailed Description

[0017] Referring Figure 2 , in an exemplary motor control application, a processor 100 operates in a first voltage domain (i.e., VDD1, e.g., 5V), and provides one or more signals to a high-power load system operating in a second domain (i.e., VDD3, e.g., several hundred volts). A driver product 200 includes an isolation barrier 230 and a communication channel for safely transmitting control signals from the processor 100 across the isolation barrier 230 to drive high-power drive devices 108 and 109 of a three-phase AC inverter for delivering three-phase power to an AC motor 120. In an exemplary embodiment, the driver product 200 includes a plurality of integrated circuits configured as a multi-chip module in a single package. For example, the driver product 200 includes a primary-side integrated circuit 201 and a secondary-side integrated circuit 203. The primary-side integrated circuit 201 receives control signals from the processor 100 and transmits the signals across the isolation barrier 230 to the secondary-side integrated circuit 203. In such an embodiment, the terminals 250, 252, 254, ……, 270 are pins of the package of the multi-chip module and are coupled to external components (e.g., discrete resistors and capacitors) and the processor 100.

[0018] The driver product 200 includes an isolation barrier 230 that isolates domains on a first side (e.g., the primary-side integrated circuit 201) and a second side (e.g., the secondary-side integrated circuit 203) of the driver product 200, the first side operating using VDD1 (e.g., a voltage less than ten volts) and the second side operating using VDD2 (e.g., several tens of volts). The isolation communication channel facilitates communication between the primary-side integrated circuit 201 and the secondary-side integrated circuit 203. Any suitable communication technology that does not use a conductive path between the two sides can be used, e.g., optical, capacitive, inductive, or electromagnetic technology. The isolation communication channel facilitates transmitting control signals from the processor 100 to the secondary-side integrated circuit 203 via the primary-side integrated circuit 201.

[0019] Although other communication protocols can be used, an exemplary isolation communication channel uses digital modulation (e.g., on-off keying modulation) to transmit one or more digital signals between the primary-side integrated circuit 201 and the secondary-side integrated circuit 203. Generally, on-off keying modulation is a form of amplitude shift keying modulation that represents digital data as the presence or absence of a carrier or having a carrier frequency fc An oscillating signal (e.g., 500 MHz - 1 GHz). The presence of a carrier within a specified duration is represented as binary 1, while the absence of a carrier within the same duration is represented as binary 0. This type of signaling is robust for isolation applications because the logical "0" state transmits the same signal as when the primary side is powered off and the device moderately returns to its default state (e.g., nothing). This behavior is advantageous in driver applications because even when the primary side is powered off, the driven load device is not accidentally turned on. However, other types of signals (e.g., pulse width modulation signals or other types of amplitude shift keying modulation signals) can be used for the isolation communication channel. The digital modulation scheme used can be determined based on the performance specifications of the target application (e.g., signal resolution) and the environment (e.g., probability of transient events).

[0020] The secondary - side integrated circuit 203 includes a driver 221 that generates one or more output control signals based on a control signal CTL received from the primary - side integrated circuit 201, and the primary - side integrated circuit 201 generates an output control signal based on a control signal received from the processor 100 via the terminal 254. The driver 221 provides corresponding signals to the terminals 264 and 266. The buffer 219 generates control signals at appropriate signal levels to control the pull - up device and the pull - down device of the driver 221 respectively. The buffer 219 can generate one control signal or two separate control signals for the pull - up device 292 and the pull - down device 296 based on the received control signal CTL. Resistor R H independent of resistor R L to adjust the pull - up strength linearly related to 1 / R H Resistor R L adjusts the pull - down strength linearly related to 1 / R L Although the received control signal CTL is shown as a single - ended signal based on the input control signal CTL received from the processor 100 at the terminal 254, it should be noted that in other embodiments, the input control signal IN and the received control signal CTL are differential signals. Generally, in other embodiments, signals shown as single - ended signals herein can be implemented as differential signals, and in other embodiments, signals shown as differential signals herein can be implemented as single - ended signals.

[0021] The pull - up strength and the pull - down strength of the output control signal provided to the control terminal of the high - power drive device 108 can be independently adjusted using one or more passive components from the on - resistance R of the pull - up device 292 coupled to the terminal 264. DS(ON) For example, resistor R H adjusts the pull - up strength. Resistor R LAdjust the pull - down strength of the signal provided to the gate of the high - power drive device 108 via terminal 266 such that its strength is different from the pull - up strength of the signal provided to the gate of the high - power drive device 108. In a typical configuration, the pull - up time tr is slower than the pull - down time tf1, and the resistors R H and R L vary in resistance according to the specifications of the embodiments of the high - power drive device 108 (e.g., power MOSFET, IGBT, GaN MOSFET, silicon carbide power MOSFET, etc.).

[0022] In at least one embodiment, an isolated communication channel feeds voltage information or fault information from the secondary - side integrated circuit 203 back to the primary - side integrated circuit 201. The primary - side integrated circuit 201 or the processor 100 uses this information to adjust operating parameters or generate one or more fault indicators, which can be used to automatically handle faults by correspondingly controlling the output driver 221. For example, the secondary - side integrated circuit 203 includes a module (e.g., desaturation detector 214) that detects fault conditions associated with the high - power drive device and can also detect user - initiated faults received from the processor 100. The fault indicator can be used by the secondary - side integrated circuit 203 to prevent damage to the high - power drive device, the load system, or the user of the load system. Additionally, the secondary - side integrated circuit 203 can send a fault indication or associated diagnostic information to the primary - side integrated circuit 201 and / or the processor 100.

[0023] In at least one embodiment, the secondary - side integrated circuit 203 includes desaturation fault protection for high - power semiconductor devices, which prevents short - circuit current events that could damage the high - power drive device 108. The fault may be due to abnormal inverter gate - driver behavior, driver supply - voltage problems, power - stage short - circuits, or insufficient gate - drive signals due to other excessive currents or power consumption in the high - power drive device. These events can significantly increase power consumption, leading to rapid overheating and damage to the corresponding high - power drive device. For example, when a short - circuit current condition occurs in the exemplary motor - drive application of Figure 1 and Figure 2 (i.e., both devices of an individual inverter are conducting), a large current flows through the high - power drive devices 108 and 109 and may damage the high - power drive devices 108 and 109. Therefore, fault - detection techniques detect this desaturation condition. The driver product 200 can send its indicator to the processor 100, and the driver product 200 or the processor 100 can trigger the shutdown of the corresponding high - power drive device.

[0024] The desaturation fault protection reduces or shuts off the overcurrent during a fault condition. In a typical application, terminal 262 is coupled to an external resistor and diode, and the external resistor and diode are coupled to the terminals of the high-power drive device 108 (e.g., the collector terminal of an IGBT or the drain terminal of a MOSFET). The desaturation detection circuit 214 senses when the collector-emitter voltage (or drain-source voltage, as the case may be) of the high-power drive device 108 exceeds a predetermined threshold level (e.g., 7V). Note that the predetermined threshold level of the desaturation detection circuit 214 can be adjusted externally based on the forward voltage of one or more diodes coupled to the desaturation resistor coupled to terminal 262 or based on the resistance of the desaturation resistor R DSAT of the desaturation resistor. Additionally, a delay time can be introduced by coupling a capacitor (not shown) between terminal 262 and an external power node.

[0025] Typically, the under-voltage lockout detector 212 prevents an insufficient voltage from being applied to the control terminal of the high-power drive device 108 by forcing the output on terminal 264 to be at a low voltage during power-up of the driver product 200. The under-voltage lockout detector 212 detects when the supply voltage (e.g., VDD2 sensed using terminal 260) exceeds a first predetermined under-voltage lockout threshold voltage and generates an indication thereof, which can be used to disable the lockout condition. The under-voltage lockout detector 212 also detects when the supply voltage is below a second predetermined under-voltage lockout threshold, which can be different from the first under-voltage lockout threshold voltage, to provide a noise margin for under-voltage lockout voltage detection. The indicator generated by the under-voltage lockout detector 212 can be provided to the processor 100 using terminal 252.

[0026] Due to the charging of the Miller capacitor (e.g., in other embodiments of the high-power device 108, the collector-gate parasitic capacitor of an IGBT device or the drain-gate parasitic capacitor of a MOSFET), the Miller clamp 220 reduces the effect of parasitic conduction of the high-power drive device 108. The gate-collector coupling can cause parasitic conduction of the device 108 in response to a high transient voltage (e.g., a gate voltage spike) generated when the high-power drive device 108 turns off. A gate voltage spike is generated when turning on another high-power drive device coupled to the high-power drive device 108. For example, when turning on the upper high-power drive device 109, the corresponding lower high-power drive device 108 coupled to the upper high-power drive device 109 experiences a voltage change dV CE / dt, this voltage change causes current to flow into the gate drive terminal coupled to the lower high-power drive device 108. The Miller clamp 220 senses this current using terminal 268, which is coupled to the gate of the lower high-power drive device 108. This current creates a voltage drop across any gate resistance and increases the gate-emitter voltage of the corresponding lower high-power drive device. If the gate-emitter voltage exceeds the device threshold voltage (e.g., 2V), the high-power drive device 108 conducts. A similar parasitic conduction event occurs when the high-power drive device 108 is conducting and the corresponding upper high-power drive device 109 is in the off state.

[0027] The Miller clamp 220 couples terminal 268 to ground via a low-resistance switch that prevents or inhibits the Miller capacitor current from generating a voltage sufficient to turn on the high-power drive device. In some embodiments of the driver product 200, the Miller clamp 220 is not required because a large enough gate capacitor coupled between the gate and emitter of each high-power drive device 108 shunts any Miller current and raises the transient level required for the parasitic conduction device. However, such embodiments increase the gate charging voltage required to reach the threshold voltage of the high-power drive device 108, increase the driver power, and increase the switching losses of the high-power drive device 108. In other embodiments of the driver product 200, the secondary-side integrated circuit 203 is referred to as a negative voltage rather than ground by coupling terminal 270 to a negative power supply (e.g., -5V). This configuration provides additional voltage margin to increase the likelihood that the parasitic conduction transient does not raise the control terminal of the high-power drive device 108 above its threshold voltage. However, this configuration may require additional cost for generating the negative voltage.

[0028] When a fault condition is detected by a module on the secondary - side integrated circuit 203, the fault logic 216 generates a control signal FAULT, which can initiate the turn - off of the high - power drive device 108. The fault logic 216 reports the fault condition to the processor 100 via the primary - side integrated circuit 201. Alternatively, the fault logic 216 only reports the fault condition to the primary - side integrated circuit 201, and the high - power drive device 108 continues to operate. Then, the primary - side integrated circuit 201 reports the fault condition to the processor 100. Since the system may include multiple high - power drive devices (e.g., six high - power drive devices in the exemplary motor - control application described herein), turning off only one of these devices may damage the high - power drive device or the load. Therefore, in response to detecting a fault, the processor 100 may initiate the turn - off of the high - power drive device 108 only after detecting a predetermined number of faults or meeting other conditions within a specific time period. In at least one embodiment, the processor 100 initiates the turn - off of the high - power drive device 108 independently of any fault detection of the driver product 200 (e.g., based on fault detection from another driver product 200 associated with another high - power drive device 108 or 109).

[0029] The sudden turn - off of the high - power drive device 108 may cause large dI / dt induced voltage spikes. Such voltage spikes may damage the drive circuit or the load. Therefore, in response to a fault condition, the processor 100 or the driver product 200 uses the device 298 to initiate a soft turn - off of the high - power drive device 108. The device 298 discharges the control node coupled to the gate terminal of the high - power drive device 108 at a rate with a longer fall - time than the conventional fall - time of the output control signal. For example, the fault logic 216 receives indicators from the undervoltage lock - out detector 212 and the desaturation detection circuit 214, and generates a control signal FAULT based on these indicators to initiate the soft turn - off.

[0030] In an embodiment of the gate - drive product 200 including a terminal coupled to the pull - up device 292 and a pin coupled to the pull - down device 296, the soft turn - off is achieved by coupling the pull - down device 298 to the pull - up device 292. The pull - down device 298 is a switch smaller than the pull - down device 296. Therefore, the signal provided to the high - power drive device has a pull - up strength linearly related to 1 / (R H ||R SS ), a pull - down strength linearly related to 1 / R L , and a soft - turn - off pull - down strength based on . Generally, the pull - up speed or the pull - down speed is linearly related to . In this embodiment of the driver product 200, in applications where the strength of the pull - down device 298 provides a sufficiently low soft - turn - off pull - down strength, the soft - turn - off impedance R SSAdditionally, the diode may not be included. Although the soft - turn - off impedance R SS affects both the rise time and the soft - turn - off time of the control signal, the configuration of the three external resistors and the two terminals provides three degrees of freedom to program the rise time, fall time, and soft - turn - off fall time of the control signal provided to the gate of the high - power drive device 108. Thus, the soft - turn - off fall time of the control signal can be adjusted independently of the conventional fall time and independently of the rise time. In at least one embodiment, a diode is coupled between terminal 264 and resistor R H . Note that in other embodiments, different configurations of the rise time, fall time, and soft - turn - off fall time are achieved by terminal 264 and 266, pull - up device 292, pull - down devices 296 and 298, and the passive elements between the high - power drive device 108 and terminals 264 and 266. For example, terminal 264, pull - up device 292, pull - down device 298, and the passive element coupled between terminal 264 and the high - power drive device 108 can be configured to achieve the rise time and fall time of the control signal in the absence of a fault condition, and terminal 266, pull - down device 296, and the passive element coupled between terminal 266 and the high - power drive device 108 can be configured to achieve the soft - turn - off fall time. In such an embodiment, the soft - turn - off fall time of the control signal can be adjusted independently of the conventional fall time to have an intensity different from that of the rise time.

[0031] In Figures 3A - 3C exemplary waveforms of the voltage associated with the high - power drive device 108 for three - phase power applications are shown. Figure 3A The switching voltage on terminal 264 is shown when the driver product 200 drives the high - side switch of an inverter (e.g., high - power device 109) and terminal 270 is coupled to node 290 (i.e., the driver product 200 is "grounded" at a voltage that differs from earth ground by VDD2 (e.g., hundreds or thousands of volts)). Figure 3B The voltage on terminal 264 is shown, which is generated by the driver product 200 when driving the corresponding low - side switch of an inverter (e.g., high - power device 108) and terminal 270 is coupled to earth ground. Figure 3C The voltage on terminal 264 is shown, which is generated by the driver product 200 when driving the low - side switch of an inverter (e.g., high - power device 108) and terminal 270 is coupled to - VSS2.

[0032] Figure 4An exemplary waveform of the voltage provided to the control terminal of the high-power drive device 108 is shown. In the absence of a fault condition, the voltage on the gate of the high-power drive device 108 has a rise time tr and a fall time tf1. When the pull-down device 298 is enabled, the soft turn-off fall time of terminal 264 is tf2 (e.g., where tf2 > tf1). At the Miller clamp threshold voltage VMCT (e.g., VSSB + 2V), the Miller clamp 220 couples terminal 268 to ground via a low-resistance switch that prevents or inhibits the Miller capacitor current from generating a voltage sufficient to turn on the high-power drive device.

[0033] In different embodiments, the high-power drive device 108 (e.g., IGBT and SiC MOSFET) has different characteristics and short-circuit protection requirements, which require flexibility in the external circuit coupled between the driver product 200 and the high-power device 108 to achieve the target performance of each embodiment. Generally, compared to a comparable IGBT drive device, the SiC MOSFET has an increased intrinsic switching speed, lower heat dissipation capacity, longer service life, and smaller surge current capacity. In response to a short-circuit event, the collector current of the IGBT increases, and the IGBT rapidly transitions from the saturation operating region to the active operating region. The collector current and its power consumption are self-limiting and become independent of the collector-emitter voltage V CE . In contrast, the SiC MOSFET transitions from the linear operating region to the saturation operating region. The voltage at which the SiC MOSFET transitions from the linear region to the saturation region is much higher than the voltage at which a comparable IGBT transitions from the saturation operating region to the active operating region. The drain current of the SiC MOSFET continuously increases as VDS increases, and the SiC MOSFET may be damaged before reaching the transition point, which makes the short-circuit protection of the SiC MOSFET different from that of the IGBT. The short-circuit detection time of the SiC MOSFET needs to be long enough to avoid false triggering (e.g., noise generated due to the fast switching speed of the SiC MOSFET), but fast enough to protect the SiC MOSFET. Therefore, the soft turn-off time applicable to the IGBT is not applicable to the SiC MOSFET. Additionally, since the SiC MOSFET has a smaller physical size, the time it can withstand an overcurrent condition before damaging the device is shorter (e.g., the overcurrent detection and turn-off response time of an exemplary IGBT is approximately 4 microseconds, and the overcurrent detection and turn-off response time of an exemplary SiC MOSFET is approximately 1 microsecond).

[0034] Traditional soft - turn - off techniques include a capacitor (e.g., a 10 nF capacitor) for controlling the soft - turn - off timing. However, this capacitor has an adverse effect on the turn - on and turn - off timing control between the gate driver and the switching device. Charging this capacitor consumes power and affects the turn - on and turn - off rates of high - power driving devices. Traditional current - boosting techniques use complementary bipolar transistor pairs between the gate driver and the switching device to increase the turn - on or turn - off current at the expense of the traditional soft - turn - off path. Additionally, some applications require additional current - driving capabilities, e.g., applications where multiple high - power driving devices are coupled in parallel for power conversion equipment with a higher output power rating, where a single high - power driving device cannot provide the required load current. Therefore, the soft - turn - off technique should be flexible and compatible with the current - boosting technique.

[0035] Figure 2 Embodiments of do not provide much flexibility for the user to adjust the soft - turn - off fall time tf2 and do not provide flexibility to increase the strength of soft - turn - off. Additionally, Figure 2 The implementation of sinks all current from the gate of the high - power driving device 108 through the driver product 200 to ground. In some embodiments, this current may exceed the capabilities of the driver product 200 or cause the temperature to rise and exceed the capabilities of the devices configured for soft - turn - off in the driver product 200. Traditional techniques for increasing adjustable soft - turn - off flexibility (e.g., using trim bits inside the driver product 200) increase the complexity of the driver product 200 and may not provide the targeted flexibility.

[0036] Figures 5A - 8 Exemplary embodiments of a flexible soft - turn - off technique that is compatible with various embodiments of high - power driving devices 108 (e.g., IGBTs and SiC MOSFETs) and is compatible with the current - boosting technique are described. Figure 2 The resistor R of H and the soft - turn - off impedance R Ss in parallel combination are Figure 5A replaced by Figure 5B and the circuit 502 of. A current amplifier (e.g., bipolar transistor Q3) is externally coupled to the driver product 200 and increases the flexibility of the soft - turn - off impedance. Adding the transistor Q3 to the soft - turn - off impedance R SS provides full control over the soft - turn - off impedance. In an exemplary embodiment, the soft - turn - off impedance R SS (e.g., 2 Ω - 1 kΩ), the transistor Q3, and the resistor R B (e.g., 100 Ω) provide an adjustable soft - turn - off speed. The soft - turn - off impedance R SS can be selected such that the high - power driving device 108 is soft - turned off at a target rate (e.g., a rate that reduces or minimizes voltage spikes while maintaining the short - circuit duration within the switching device specifications).

[0037] In the absence of a fault condition (e.g., a desaturation condition), and in response to a control signal received by the driver product 200 having a first level (e.g., a level for turning on the high-power drive device 108), the circuit 502 conducts current from the terminal 264 through the diode and the resistor R H , and conducts it to the gate of the high-power drive device 108, thereby charging the gate of the high-power drive device 108 to turn on the high-power drive device 108. In the presence of a fault condition, the driver product 200 sinks the current received from the high-power drive device 108 via the terminal 264 to -VSS2, thereby softly disabling the high-power drive device 108. The circuit 502 conducts current from the gate of the high-power drive device through the resistor R H and the soft turn-off impedance R SS and conducts it into the emitter of the transistor Q3. The transistor Q3 amplifies the base current by the gain of the transistor Q3 to quickly discharge the gate of the high-power drive device 108 by sinking the collector current directly to the power supply node -VSS2 and sinking a smaller base current to the power supply node -VSS2 via the driver product 200. Figure 5B An embodiment of the circuit 502 is shown. The circuit 502 uses the same resistor as the resistor R H to turn on the high-power drive device 108 in the absence of a fault condition, and uses the same resistor as the resistor R L to turn off the high-power drive device 108. In this embodiment, the amount of time taken to charge the gate of the high-power drive device 108 to turn it on in the absence of a fault condition is the same as the amount of time taken to discharge the gate of the high-power drive device 108 to turn it off in the absence of a fault condition.

[0038] The value of the soft turn-off impedance R SS can be selected to softly turn off the high-power drive device 108 at a rate that reduces or minimizes the voltage spike while keeping the short-circuit duration within the limits of the embodiment of the high-power drive device 108. The circuit 502 can be configured to use the soft turn-off impedance R SS to attenuate the signal. The gain β of the transistor Q3 can be selected such that the current sunk to ground increases by a small change in the base current and a small increase in the amount of current sunk to ground through the driver product 200. Below the threshold voltage of the transistor Q3, no base current flows from the transistor Q3 into the terminal 264, and the transistor Q3 does not amplify the base current. Instead, below the threshold voltage of the transistor Q3, no current flows between the collector and the emitter of the transistor Q3 to the power supply node -VSS2. Table 1 shows the R of different gate-controlled power switch devices H, R L and R SS Example values of

[0039]

[0040] Table 1

[0041] The flexible soft - turn - off technology is compatible with the current boost technology used in high - power applications. Refer to Figure 6 , the current booster 604 amplifies the current generated by the driver product 200. In at least one embodiment, the current booster 604 includes a push - pull amplifier coupled between the circuit 502 and the terminals 264 and 266. The circuit 502 provides an adjustable soft - turn - off impedance without affecting the current booster 604. In the absence of a fault and in response to a control signal received by the driver product 200 that has a value for turning on the high - power drive device 108, the current booster 604 amplifies the base current of the transistor Q1 received from the terminal 264 via the diode D2 and the resistor R H to charge the gate of the high - power drive device 108, thereby turning on the high - power drive device 108.

[0042] In the absence of a fault and in response to a control signal received by the driver product 200 that has a value for turning off the high - power drive device 108 via the terminal 266, the driver product 200 sinks the base current of the transistor Q2 to the power supply node - VSS2 via the resistor R2 and the terminal 266. The current - boost circuit 604 amplifies the base current of the transistor Q2 to produce a current flowing from the gate of the high - power drive device 108 via the resistor R L into the emitter of Q2, and a current flowing directly from the collector of the transistor Q2 to the power supply node - VSS2, and a current flowing indirectly via the base of the transistor Q2, the resistor R2, the terminal 266, and the driver product 200 to the power supply node - VSS2, thereby disabling the high - power drive device 108. The resistor R3 reduces or minimizes the output voltage drop across the p - n junctions of the transistor Q1 and the transistor Q2 in the forward - conduction mode of the current - boost circuit 604.

[0043] In the presence of a fault condition, the driver product 200 sinks the current received via the terminal 264, the resistor R B and the terminal 264 to softly disable the high - power drive device 108. The circuit 502 draws current from the gate of the high - power drive device 108 through the resistor R L and the soft - turn - off impedance R SSConducted into the emitter of transistor Q3. Transistor Q3 amplifies the base current according to the gain of transistor Q3 to directly discharge the gate of high-power drive device 108 to the power supply node -VSS2 via the collector of transistor Q3, and indirectly via the base of transistor Q3, resistor R B , terminal 264 and driver product 200 discharge the gate of high-power drive device 108 to the power supply node -VSS2, thereby softly turning off high-power drive device 108.

[0044] Referring to Figure 7 , a cost-reducing embodiment of the adjustable soft turn-off and current boost technology combines the transistors of the adjustable soft turn-off circuit with the turn-off path of the current boost circuit. In addition to the soft turn-off path, transistor Q2 is also included in the turn-off path of the current booster. The resulting soft turn-off impedance R SS is R B / β Q2 , where β Q2 is the gain of transistor Q2.

[0045] Referring to Figure 8 , the above-described embodiment of the adjustable soft turn-off and current booster 604 is compatible with additional features. For example, an embodiment of current booster 604 implemented using transistors Q1 and Q2 and an adjustable soft turn-off circuit is incorporated into an embodiment including a desaturation detection acceleration circuit. An embodiment of the desaturation detection acceleration circuit includes resistor R I . The desaturation threshold adjuster includes resistor R DSAT and N diodes, which are configured for the target desaturation threshold of high-power drive device 108. Additionally, a robust external Miller clamp includes transistor Q4, and transistor Q4 amplifies the Miller clamp current passing through terminal 268 of driver product 200. Since transistor Q4 is closer to high-power drive device 108, transistor Q4 enhances the clamping ability by reducing the parasitic capacitance associated with the interconnection to high-power drive device 108.

[0046] Therefore, a flexible soft turn-off technology has been described, which retains the soft turn-off function when implemented using current boost technology in applications that require additional current drive capabilities. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. For example, although the invention has been described in embodiments where driver product 400 is used in motor applications, those skilled in the art should understand that the teachings herein can be used in other applications. Various variations and modifications can be made to the embodiments disclosed herein based on the description set forth herein without departing from the scope of the invention set forth in the appended claims.

Claims

1. An apparatus for controlling a high-power driving device external to a package of a gate driver circuit, the apparatus comprising: A first circuit, coupled between a first node and a control node, the first circuit being configured to charge the control node for a first time length in response to a first signal through the first node, the first signal indicating a first level of a control signal and the absence of a fault condition; A second circuit, coupled between a second node and the control node, the second circuit being configured to discharge the control node for a second time length in response to a second signal through the second node, the second signal indicating a second level of the control signal and the absence of the fault condition; And A third circuit, coupled between the first node and the control node, the third circuit including a current amplifier and being configured as a soft turn-off path to discharge the control node for a third time length in response to the first signal through the first node, the first signal indicating the presence of the fault condition, the third time length being different from the second time length.

2. The apparatus according to claim 1, Among them, The third circuit further includes a resistor coupled between the current amplifier and the control node.

3. The apparatus according to claim 1, further comprising: A current boosting circuit, coupled to the first circuit, the second circuit, and the third circuit, Wherein, the current boosting circuit is configured to amplify a first current received from the first node and provided by the current boosting circuit to the control node, and is configured to amplify a second current provided by the current boosting circuit to the second node.

4. The apparatus according to claim 1, further comprising: A current boosting circuit, including the current amplifier, Wherein, the current boosting circuit is configured to amplify a first current received from the first node and provided by the current boosting circuit to the control node, amplify a second current provided by the current boosting circuit to the second node, and amplify a third current provided to the first node.

5. The apparatus according to claim 1, 2, 3, or 4, further comprising: The gate driver circuit includes: A driver, configured to control the high-power driving device at least partially based on a first reference voltage, a second reference voltage, and the control signal; A fault circuit, configured to generate a fault indicator based on a voltage between terminals of the high-power driving device, the fault condition being at least partially based on the fault indicator; A first terminal, coupled to the first node, and configured to charge the control node of the high-power driving device for the first time length in response to the first level of the control signal and the absence of the fault condition, and configured to discharge the control node for the third time length in response to the presence of the fault condition; and A second terminal, coupled to the second node, and configured to discharge the control node for the second time length.

6. The apparatus according to claim 1, 2, 3, or 4, Among them, The control node is coupled to the gate terminal of the high-power drive device, and the device further comprises: A fourth circuit, coupled between a third node and the control node, the fourth circuit including a second current amplifier configured to clamp the control node in response to a voltage at the control node dropping below a predetermined threshold voltage.

7. A method for controlling a high-power drive device external to a package of a gate drive circuit, the method comprising: Charging a control node using a first node for a first time length in response to a first level of a control signal and in the absence of a fault condition; And Discharging the control node using a second node for a second time length in response to a second level of the control signal and in the absence of the fault condition; And Discharging the control node using the first node for a third time length in response to the presence of the fault condition, the third time length being different from the second time length, wherein discharging the control node for the third time length includes: Attenuating a voltage at the control node using a passive element; and Amplifying a first current passing through the first node.

8. The method according to claim 7, further comprising: Sensing a second voltage between terminals of the high-power drive device; And Determining the fault condition at least in part based on the second voltage.

9. The method according to claim 8, further comprising: Receiving the control signal from a first voltage domain through a circuit in a second voltage domain, wherein charging the control node further responds to the control signal having a first signal level, and discharging the control node for the second time length further responds to the control signal having a second signal level.

10. The method according to claim 7, 8 or 9, Among them, The first time length is based on a first passive element, the second time length is based on a second passive element, and wherein the third time length is based on a third passive element.

11. The method according to claim 7, 8 or 9, wherein, The first node is coupled to a first terminal of the gate drive circuit, and the second node is coupled to a second terminal of the gate drive circuit.

12. The method according to claim 7, 8 or 9, wherein The amplified first current flows into a ground node.

13. The method according to claim 12, wherein, The first current flows into the ground node via the gate drive circuit, and the amplified first current flows directly into the ground node.

14. The method according to claim 7, 8 or 9, wherein Charging the control node for the first time length includes: Generating a second current passing through the first node in response to the absence of the fault condition; and Amplifying the second current to charge the control node for the first time length.

15. The method according to claim 7, 8 or 9, wherein Discharging the control node for the second time length includes: Generating a second current passing through the second node in response to the level of the control signal and in the absence of the fault condition; and Amplifying the second current to discharge the control node for the second time length.

16. The method according to claim 7, 8 or 9, wherein The control node is coupled to the gate terminal of the high-power driving device, and the method further includes: in response to the voltage on the control node dropping below a predetermined threshold voltage, amplifying the current through a third node to clamp the control node to the ground voltage.

17. An apparatus for controlling a high-power driving device, the apparatus comprising: A first node; A second node; A control node; Means for charging the control node over a first time period in response to a first signal through the first node, and discharging the control node over a second time period by amplifying the first signal through the first node; And Means for discharging the control node over a third time period in response to a second signal through the second node, wherein the third time period is different from the second time period.

18. The apparatus according to claim 17, wherein, The means for discharging the control node includes means for amplifying the second signal through the second node.

19. The apparatus according to claim 17 or 18, further comprising: Means for generating the first signal and the second signal in a first voltage domain based on a control signal received from a second voltage domain, and generating a fault signal in the first voltage domain based on the current through the high-power driving device.

20. The apparatus according to claim 17 or 18, further comprising: The high-power driving device; And Means for amplifying the current through a third node to clamp the control node to the ground voltage in response to the voltage on the control node dropping below a predetermined threshold voltage, wherein the control node is coupled to the gate terminal of the high-power driving device.

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