Method for reducing power consumption of image sensor and image sensor

Abstract

The present invention provides a method for reducing the power consumption of an image sensor and an image sensor thereof. The method for reducing the power consumption of an image sensor comprises: by means of capacitive coupling, achieving that a comparator current (I2) when a non-quantized pixel unit outputs a reference signal and an image signal is smaller than a comparator current (I1) when a quantized pixel unit outputs a reference signal and an image signal. The method for reducing the power consumption of an image sensor and the image sensor thereof provided by the present invention can reduce the power consumption of the image sensor.

Description

Technical Field

[0001] The present invention relates to the field of CMOS image sensors, and in particular to a method for reducing power consumption of an image sensor and an image sensor. Background Art

[0002] CMOS image sensors are widely used in various portable devices, and low power consumption is a very important indicator for portable devices. Therefore, reducing the power consumption of CMOS image sensors is an important research direction. Single-slope analog-to-digital converters (single-slope ADCs) are often used in CMOS image sensors, and comparators are their core components.

[0003] Figure 1 and Figure 2 Shown respectively are the common structures and timing control diagrams of two-stage comparators. Figure 1 In the two-stage comparator shown, the reference signal Vramp and the output pxd of the pixel unit (pixel) are coupled to the differential input pair tubes M1 and M2 of the first-stage comparator through the DC isolation capacitors C1 and C2 respectively, sw1 and sw2 are automatic zeroing switches, M3 and M4 are load tubes, Mb is the tail current source tube of the first-stage comparator, and its gate includes a sampling switch sw4 and a voltage holding capacitor Cb. The sampling switch sw4 is used to sample the initial value of the gate voltage Vbin of the tail current tube. One end of the voltage holding capacitor Cb is connected to the gate of the tail current source tube Mb, and the other end is grounded to maintain the gate voltage Vbin of the tail current source. The second stage of the comparator is the amplification stage, which includes an input tube M6 and a tail current source tube M5, wherein the switch sw3 is the second-stage automatic zeroing switch.

[0004] Figure 2 The control signal EQ1 is the control signal of the first-stage automatic zeroing switches sw1 and sw2 of the comparator, and the control signal EQ2 is the control signal of the second-stage automatic zeroing switch sw3 of the comparator, which is used to automatically clear the two-stage comparator before the comparator quantizes the output signal of the pixel unit. The control signal TX is the control signal of the gate of the transmission tube in the pixel unit, which is used to assist in explaining the output moment of the image signal of the pixel unit. The control signal sw is the control waveform of the sampling switch sw4 of the gate voltage Vbin of the first-stage tail current source tube of the two-stage comparator. When it is high, Vbin is connected to the Vbias voltage generated by the external bias voltage generating unit, and Vbias is introduced into the gate of the tail current source. When it is low, the connection between Vbin and Vbias is disconnected, and Vbin is maintained on the voltage holding capacitor Cb. The waveform signal Vramp is the comparator reference signal, which is coupled to one end of the differential input pair tube of the first stage of the two-stage comparator through the DC isolation capacitor C1, and is used to quantify the reference signal and image signal output by the pixel unit. Figure 1The two-stage comparator can be divided into five time periods from t1 to t5 within a working cycle, that is, within a row operation time: t1 is the stabilization time of the reference signal ref output by the pixel unit and the automatic clearing, t2 is the quantization time of the reference signal ref output by the pixel unit, t3 is the stabilization time of the image signal sig output by the pixel unit when tx is turned on and the pixel unit outputs, t4 is the quantization time of the image signal sig output by the pixel unit, and t5 is the row blank time. The row blank time t5 is not necessary. Because the gate voltage Vbin of the tail current source of the comparator is constant during the entire row operation time, the current Icmp1 of the comparator is also constant. If the power consumption of the comparator is to be reduced, the current Icmp1 of the comparator must be reduced, which will cause the comparator to convert the reference signal (ref) and the image signal (sig) output by the pixel unit to be slower, increase the conversion time, and thus cause the frame rate to drop, which is unacceptable.

[0005] Therefore, it is necessary to provide a solution for a low-power image sensor without reducing the frame rate. Summary of the invention

[0006] The present invention provides a solution for a low-power image sensor without reducing a frame rate. The method for reducing the power consumption of an image sensor implements, by means of capacitive coupling, a comparator current (I2) when a non-quantized pixel unit outputs a reference signal and an image signal is smaller than a comparator current (I1) when a quantized pixel unit outputs a reference signal and an image signal, thereby reducing the power consumption of the image sensor.

[0007] Preferably, the current size is adjusted by controlling the change of the voltage on the lower plate of the voltage holding capacitor, so that the comparator current (I2) when the non-quantized pixel unit outputs a reference signal and an image signal is smaller than the comparator current (I1) when the quantized pixel unit outputs a reference signal and an image signal, thereby reducing the power consumption of the image sensor.

[0008] Preferably, the relationship between the comparator current (I2) when the non-quantized pixel unit outputs the reference signal and the image signal and the comparator current (I1) when the quantized pixel unit outputs the reference signal and the image signal is: I2≤0.8I1.

[0009] Preferably, the current when the quantized pixel unit outputs is increased by setting the initial current when the non-quantized pixel unit outputs.

[0010] Preferably, by setting the initial current of the quantized pixel unit when outputting, the current of the non-quantized pixel unit when outputting is pulled down.

[0011] Preferably, when stacked transistors are provided in the comparator current source, the gate voltage of the stacked transistors changes in the same direction as the gate voltage of the tail current source, thereby preventing the gate voltage of the stacked transistors from limiting the change of the tail current.

[0012] The present invention also provides an image sensor, including a single-slope analog-to-digital converter, the single-slope analog-to-digital converter including a comparator unit, the comparator unit including a differential input pair structure with a tail current source, wherein the gate of the tail current source includes a sampling switch and a voltage holding capacitor, the sampling switch is used to sample the initial value of the gate voltage, and the voltage holding capacitor is suitable for adjusting the lower plate voltage of the voltage holding capacitor through the switch, thereby adjusting the gate voltage of the tail current tube.

[0013] Preferably, the lower plate of the voltage holding capacitor is connected to one end of two parallel first switches and second switches, and the other ends of the first switch and the second switch are respectively connected to two different voltage sources or voltage generating circuits.

[0014] Preferably, the tail current source is a stacked structure, including a first tail current source tube and a second tail current source tube, the gate of the first tail current source tube is connected to a first voltage holding capacitor, the gate of the second tail current source tube is connected to a second voltage holding capacitor, the lower plates of the first voltage holding capacitor and the second voltage holding capacitor are connected to two parallel third switches and one end of a fourth switch, and the other ends of the third switch and the fourth switch are respectively connected to two different voltage sources or voltage generating circuits.

[0015] Preferably, the tail current source is a stacked structure, including a first tail current source tube and a second tail current source tube, the gate of the first tail current source tube is connected to a first voltage holding capacitor, the gate of the second tail current source tube is connected to a second voltage holding capacitor, the lower plate of the first voltage holding capacitor is connected to one end of two parallel fifth switches and a sixth switch, the other ends of the fifth switch and the sixth switch are respectively connected to two different voltage sources or voltage generating circuits, the lower plate of the second voltage holding capacitor is connected to one end of two parallel seventh switches and an eighth switch, the other ends of the seventh switch and the eighth switch are respectively connected to two different voltage sources or voltage generating circuits.

[0016] The method proposed by the present invention for reducing the power consumption of a CMOS image sensor by dynamically controlling the tail current of a comparator only requires adding a small amount of circuits and simple controls to a common structure, thereby effectively controlling the increase in chip area and circuit complexity.

[0017] In addition, because a large current is maintained when quantizing ref and sig, the conversion rate is not affected, and thus the frame rate is not affected. In other words, the overall power consumption of the CMOS image sensor is reduced at a very low cost while maintaining a high frame rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0019] Figure 1 It is a structural schematic diagram of a two-stage comparator in a single slope analog-to-digital converter in a CMOS image sensor in the prior art;

[0020] Figure 2 It is a timing control diagram of a two-stage comparator in a single slope analog-to-digital converter in a CMOS image sensor in the prior art;

[0021] Figure 3 This is a schematic structural diagram of a two-stage comparator in a single slope analog-to-digital converter in a CMOS image sensor in the first embodiment of the present invention;

[0022] Figure 4 A timing control diagram of a two-stage comparator in a single slope analog-to-digital converter in a CMOS image sensor in the first embodiment of the present invention;

[0023] Figure 5 It is a structural schematic diagram of a two-stage comparator in a single slope analog-to-digital converter in a CMOS image sensor in the second embodiment provided by the present invention;

[0024] Figure 6 It is a schematic diagram of the structure of a two-stage comparator in a single-slope analog-to-digital converter in a CMOS image sensor in the third embodiment provided by the present invention.

[0025] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0026] In the following specific description of the preferred embodiments, reference will be made to the attached drawings which constitute a part of the present invention. The attached drawings show by way of example specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0027] The technical solution of the present invention provides a method for reducing the power consumption of an image sensor. By means of capacitive coupling, a comparator current (I2) when a non-quantized pixel unit outputs a reference signal and an image signal is achieved to be smaller than a comparator current (I1) when a quantized pixel unit outputs a reference signal and an image signal, thereby reducing the power consumption of the image sensor.

[0028] Specifically, the current size is adjusted by controlling the change of the voltage of the lower plate of the voltage holding capacitor, so that the comparator current (I2) when the non-quantized pixel unit outputs a reference signal and an image signal is smaller than the comparator current (I1) when the quantized pixel unit outputs a reference signal and an image signal, thereby reducing the power consumption of the image sensor.

[0029] Specifically, the relationship between the comparator current (I2) when the non-quantized pixel unit outputs a reference signal and an image signal and the comparator current (I1) when the quantized pixel unit outputs a reference signal and an image signal is: I2≤0.8I1.

[0030] Specifically, the comparator includes a differential input pair structure with a tail current source, wherein the gate of the tail current source includes a sampling switch and a voltage holding capacitor, the sampling switch is used to sample the initial value of the gate voltage, the upper plate of the voltage holding capacitor is connected to the gate of the tail current source, and the lower plate can select different voltage sources or voltage generating circuits through two switches.

[0031] Specifically, by setting the initial current of the non-quantized pixel unit when outputting, the current of the quantized pixel unit when outputting is increased.

[0032] Specifically, by setting the initial current of the quantized pixel unit when outputting, the current of the non-quantized pixel unit when outputting is pulled down.

[0033] Specifically, when a stacked tube is provided in the comparator current source, the gate voltage of the stacked tube changes in the same direction as the gate voltage of the tail current source, thereby preventing the gate voltage of the stacked tube from limiting the change of the tail current.

[0034] The present invention is described in detail below in conjunction with specific embodiments:

[0035] Embodiment 1

[0036] In the present embodiment, an image sensor is provided, including a single-slope analog-to-digital converter, the single-slope analog-to-digital converter including a comparator unit, the comparator unit including a tail current source, the gate of a tail current tube of the tail current source being connected to a voltage holding capacitor, the voltage holding capacitor being suitable for adjusting the lower plate voltage of the voltage holding capacitor through a switch, thereby adjusting the gate voltage of the tail current tube.

[0037] In this embodiment, the lower plate of the voltage holding capacitor is connected to one end of two parallel first switches and second switches, and the other ends of the first switch and the second switch are respectively connected to two different voltage sources or voltage generating circuits.

[0038] Specific reference Figure 3 and Figure 4 , Figure 3 The comparator circuit structure capable of implementing the above functions is shown. Figure 4 is Figure 3 the timing control diagram of the shown circuit.

[0039] Figure 3 and Figure 1 Compared with Figure 1 , only the part marked by the dashed line is modified, and the other parts are the same as Figure 1 , which will not be elaborated here. Compared with

[0040] , the lower plate of the gate voltage holding capacitor Cb is no longer connected to the fixed ground potential, but can be connected to different voltages V1 and V2 through two switches swv1 and swv2.

[0041] Such as Figure 4 shown, the control waveforms of the first switch swv1 and the second switch swv2 are Vc and Vcb respectively. When quantifying ref and sig in the ADC, the control signal Vc of the first switch swv1 is low, and the control signal Vcb of the second switch swv2 is high, disconnecting the connection between the voltage signal V1 and the lower plate of the voltage holding capacitor Cb, and connecting the voltage signal V2 to the lower plate of the voltage holding capacitor Cb. And at other times, the control signal Vc of the first switch swv1 is high, and the control signal Vcb of the second switch swv2 is low, disconnecting the connection between the voltage signal V2 and the lower plate of the voltage holding capacitor Cb, and connecting the voltage signal V1 to the lower plate of the voltage holding capacitor Cb.

[0042] In this way, because the voltage V1 < V2, as Figure 4 shown, it causes the gate voltage Vbin of the tail current source and the control signal Vcb of the second switch swv2 to have the same change waveform, so that the current Icmp1 flowing through the comparator also changes in the same direction as the waveform of the control signal Vcb. When quantifying ref and sig, Icmp1 is I2, and at other times, Icmp1 is I1, where I1 < I2. The total average current is less than I2. And in order to achieve the same conversion time, Figure 1The tail current Icmp1 in the structure shown must be I2. Because its current is constant, the total average current is I2. So in comparison, the new structure can reduce the total average current of the comparator, thereby reducing power consumption. Among them, the current ratio of I1 and I2 can be flexibly changed by the capacitance value of the voltage sampling capacitor Cb and the selection of the high and low levels V1 and V2 connected to the lower plate of the voltage sampling capacitor Cb through the first switch swv1 and the second switch swv2.

[0043] In this embodiment, the power consumption of the CMOS image sensor is reduced by dynamically controlling the comparator tail current Icmp1. Specifically, when the ADC quantizes the reference signal (ref) and the image signal (sig) output by the pixel unit, the comparator maintains a large current to speed up the flipping speed and maintain a high frame rate. At other times, because the response speed of the comparator is not a bottleneck, a small current can be used to reduce power consumption.

[0044] The current size is adjusted by controlling the change of the lower plate voltage of the voltage holding capacitor, so that the comparator current (I2) when the non-quantized pixel unit outputs a reference signal and an image signal is smaller than the comparator current (I1) when the quantized pixel unit outputs a reference signal and an image signal, thereby reducing the power consumption of the image sensor.

[0045] Embodiment 2

[0046] In this embodiment, a stacked tube is provided in the comparator current source, and the gate voltage of the stacked tube changes in the same direction as the gate voltage of the tail current source, thereby avoiding the gate voltage of the stacked tube limiting the change of the tail current. The stacked tube is provided to reduce the channel modulation effect of the tail current source and increase the stability of the tail current source.

[0047] Figure 5 This is a schematic diagram of the structure of a two-stage comparator in a single-slope analog-to-digital converter in a CMOS image sensor provided in this embodiment. Figure 5 and Figure 1 Compared with the previous example, only the dotted line part is changed, and the other parts are the same as Figure 1 The consistency is not repeated here.

[0048] like Figure 5 As shown, the tail current source is a stacked structure, including a first tail current source tube Mcs and a second tail current source tube Mb, the gate of the first tail current source tube Mcs is connected to the first voltage holding capacitor Ccs, the gate of the second tail current source tube Mb is connected to the second voltage holding capacitor Cb, the lower plates of the first voltage holding capacitor Ccs and the second voltage holding capacitor Cb are connected to one end of two parallel third switches swv1 and fourth switches swv2, and the other ends of the third switch swv1 and the fourth switch swv2 are respectively connected to two different voltage sources or voltage generating circuits V1 and V2.

[0049] Figure 5 Shown is how power reduction can be achieved in a structure containing cascode (stacked) tubes. Figure 5 and Figure 3 Compared with the 100V 2 ... Figure 5 As shown in the dashed box. The control signals of the sampling switch sw5 and the sampling switch sw4 can be Figure 4 The same control signal sw is used to control, or it is divided into two control signals, but the control signal and sw waveform are similar. The other control signals of the circuit are Figure 3 The only difference is that when the control signals Vc and Vcb change, Vbin and Vcsin will change in the same direction as Vcb. In this way, the tail current will not be limited by the voltage of Vcsin.

[0050] The current ratio of I1 and I2 can be flexibly changed by the capacitance value of Cb and the selection of the high and low voltage levels V1 and V2 connected to the capacitor Cb through the switch.

[0051] Embodiment 3

[0052] like Figure 6 , which is a schematic diagram of the structure of a two-stage comparator in a single-slope analog-to-digital converter in a CMOS image sensor provided in this embodiment. Figure 6 and Figure 1 Compared with the previous example, only the dotted line part is changed, and the other parts are the same as Figure 1 The consistency is not repeated here.

[0053] Figure 6In the embodiment, the tail current source is a stacked structure, including a first tail current source tube Mcs and a second tail current source tube Mb, the gate of the first tail current source tube Mcs is connected to a first voltage holding capacitor Ccs, the gate of the second tail current source tube Mb is connected to a second voltage holding capacitor Cb, the lower plate of the first voltage holding capacitor Ccs is connected to one end of two parallel fifth switches swv3 and sixth switches swv4, the other ends of the fifth switches swv3 and sixth switches swv4 are respectively connected to two different voltage sources or voltage generating circuits V3 and V4, the lower plate of the second voltage holding capacitor Cb is connected to one end of two parallel seventh switches swv1 and eighth switches swv2, the other ends of the seventh switches swv1 and eighth switches swv2 are respectively connected to two different voltage sources or voltage generating circuits V1 and V2. The control switches swv1 and swv3 can be used Figure 4 The control signal Vc in the control switch swv2 and swv4 can be controlled by Figure 4 It is controlled by the control signal Vcb.

[0054] The method proposed by the present invention for reducing the power consumption of a CMOS image sensor by dynamically controlling the tail current of a comparator only requires adding a small amount of circuits and simple controls to a common structure, thereby effectively controlling the increase in chip area and circuit complexity.

[0055] In addition, because when the reference signal ref signal output by the quantized pixel unit and the image signal sig signal output by the pixel unit (ie Figure 2 or Figure 4 The high current is maintained during the time t2 and t4 in the image sensor, which will not affect the conversion rate and thus the frame rate. In other words, the overall power consumption of the CMOS image sensor is reduced at a very low cost while maintaining a high frame rate.

[0056] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The words first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A method for reducing power consumption of an image sensor, characterized in that: An image sensor includes a single slope analog-to-digital converter, the single slope analog-to-digital converter includes a comparator unit, the comparator unit includes a differential input pair structure with a tail current source, wherein the gate of the tail current source includes a sampling switch and a voltage holding capacitor, the sampling switch is used to sample the initial value of the gate voltage, the upper plate of the voltage holding capacitor is connected to the gate of the tail current source, and the lower plate selects different voltage sources or voltage generating circuits through two switches, and controls the voltage holding capacitor to hold the voltage. The current size is adjusted according to the change of the lower plate voltage, so that the comparator current when the non-quantized pixel unit outputs the reference signal and the image signal is smaller than the comparator current when the quantized pixel unit outputs the reference signal and the image signal, so as to reduce the power consumption of the image sensor.

2. The method for reducing power consumption of an image sensor according to claim 1, wherein: The relationship between the comparator current I2 when the non-quantized pixel unit outputs the reference signal and the image signal and the comparator current I1 when the quantized pixel unit outputs the reference signal and the image signal is: I2≤0.8I1.

3. The method for reducing power consumption of an image sensor according to claim 1, wherein: By setting the initial current of the non-quantized pixel unit when outputting, the current of the quantized pixel unit when outputting is increased.

4. The method for reducing power consumption of an image sensor according to claim 1, wherein: By setting the initial current of the quantized pixel unit output, the current of the non-quantized pixel unit output is pulled down.

5. The method for reducing power consumption of an image sensor according to claim 1, wherein: When stacked tubes are provided in the comparator current source, the gate voltage of the stacked tubes changes in the same direction as the gate voltage of the tail current source, thereby preventing the gate voltage of the stacked tubes from limiting the change of the tail current.

6. An image sensor comprising a single slope analog-to-digital converter, characterized in that: The single-slope analog-to-digital converter includes a comparator unit, which includes a differential input pair structure with a tail current source, wherein the gate of the tail current source includes a sampling switch and a voltage holding capacitor, the sampling switch is used to sample the initial value of the gate voltage, the upper plate of the voltage holding capacitor is connected to the gate of the tail current source, and the lower plate selects different voltage sources or voltage generating circuits through two switches, and the current size is adjusted by controlling the change of the voltage on the lower plate of the voltage holding capacitor, so that the comparator current when the non-quantized pixel unit outputs a reference signal and an image signal is smaller than the comparator current when the quantized pixel unit outputs a reference signal and an image signal.

7. The image sensor according to claim 6, wherein: The lower plate of the voltage holding capacitor is connected to one end of two parallel first switches and second switches, and the other ends of the first switch and the second switch are respectively connected to two different voltage sources or voltage generating circuits.

8. The image sensor according to claim 6, wherein: The tail current source is a stacked structure, including a first tail current source tube and a second tail current source tube, the gate of the first tail current source tube is connected to a first voltage holding capacitor, the gate of the second tail current source tube is connected to a second voltage holding capacitor, the lower plates of the first voltage holding capacitor and the second voltage holding capacitor are connected to one end of two parallel third switches and a fourth switch, and the other ends of the third switch and the fourth switch are respectively connected to two different voltage sources or voltage generating circuits.

9. The image sensor according to claim 6, wherein: The tail current source is a stacked structure, including a first tail current source tube and a second tail current source tube, the gate of the first tail current source tube is connected to a first voltage holding capacitor, the gate of the second tail current source tube is connected to a second voltage holding capacitor, the lower plate of the first voltage holding capacitor is connected to one end of two parallel fifth switches and a sixth switch, the other ends of the fifth switch and the sixth switch are respectively connected to two different voltage sources or voltage generating circuits, the lower plate of the second voltage holding capacitor is connected to one end of two parallel seventh switches and an eighth switch, the other ends of the seventh switch and the eighth switch are respectively connected to two different voltage sources or voltage generating circuits.

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