Integration of passive components at wafer level

Abstract

The present disclosure relates to the integration of passive devices at the wafer level. The present disclosure describes a semiconductor device including an integrated circuit (500) coupled to a first semiconductor substrate (100) using a first set of passive devices (e.g., inductors) (102) located on the first substrate. A second semiconductor substrate (200) can be coupled to the first substrate using a second set of passive devices (e.g., capacitors) (202). An interconnector (104) in the substrate can allow interconnection between the substrate and the integrated circuit. The passive devices can be used to provide voltage regulation to the integrated circuit. The substrate and the integrated circuit can be coupled using a metal coating (106, 502).

Description

[0001] This application is a divisional application of the PCT application entering the Chinese national phase, whose international application date is August 4, 2015, national application number is 201580044816.7, and invention name is “Integration of Wafer-Level Passive Devices”. Background Art 1. Technical Field

[0003] Embodiments described herein relate to systems and methods for implementing power supply regulation in semiconductor devices. More particularly, embodiments described herein relate to semiconductor devices having integrated passive devices for voltage regulation.

[0004] 2. Description of Related Art

[0005] Power delivery and power conservation are increasingly becoming considerations for performance scaling of integrated circuit devices such as system-on-chip (SoC) devices, central processing units (CPUs), and graphics processing units (GPUs). Faster delivery of power to a device can increase the speed and power of the device while saving power by reducing losses during power transitions (e.g., powering on / off of a device). Without the development of more efficient power delivery and power conservation systems or techniques, further performance scaling may be limited. Therefore, methods and systems for including voltage regulating components (e.g., passive devices such as inductors and / or capacitors) on or near an integrated circuit chip are being developed for further performance scaling.

[0006] One method that has been developed to integrate voltage regulation on an integrated circuit chip is to form the voltage regulating components on the chip during the process used to manufacture the chip (e.g., forming the inductor and capacitor during the CMOS process used to form the integrated circuit). However, forming the inductor and capacitor during the CMOS process requires a complex process that may increase cost, additional processing time, require more masks, and / or more components. Due to the complexity involved in forming the inductor and capacitor on the integrated circuit chip during the CMOS process, the yield loss of such an integrated circuit chip can be high, which results in additional manufacturing time and cost. In addition, because the inductor and capacitor are formed during the CMOS process, the specifications of the inductor and capacitor are limited by the CMOS process parameters.

[0007] Another approach developed for including voltage regulation components on or near an integrated circuit chip is to provide packaged discrete inductors and capacitors with the integrated circuit chip. However, providing packaged inductors and capacitors can require a large amount of fixed space for the components, involve difficult physical routing, and be electrically incapable of coping with electrical losses. Summary of the invention

[0008] In some embodiments, the semiconductor device includes an integrated circuit coupled to a first semiconductor substrate. The integrated circuit and the first substrate can be coupled using a metal coating (metallization) formed on the integrated circuit and the first substrate. The first substrate may include a first group of passive devices (e.g., an inductor) located on the substrate. The second semiconductor substrate may be coupled to the first substrate so that the first substrate is located between the integrated circuit and the second substrate. The first substrate and the second substrate may be coupled using a metal coating formed on the first substrate and the second substrate. The second substrate may include a second group of passive devices (e.g., a capacitor). In some embodiments, an electrically insulating material fills the space between the integrated circuit and the first substrate around the metal coating and between the first substrate and the second substrate around the metal coating. In some embodiments, the substrate includes an interconnector providing interconnection between the substrate and the integrated circuit. These interconnectors can connect passive devices and integrated circuits to provide voltage regulation for the integrated circuit.

[0009] In some embodiments, the pillars are coupled to active surfaces of the integrated circuit on the periphery of the first and second substrates. The pillars can provide direct connections to input / output terminals on the integrated circuit. Thus, input / output from the integrated circuit can occur directly without routing through the substrates using passive devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The features and advantages of the methods and apparatus of the embodiments of the present disclosure will be more fully understood by reference to the following detailed description of presently preferred but merely exemplary implementations of the embodiments of the present disclosure when taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A cross-sectional side view illustration of an embodiment of a semiconductor substrate having passive devices and interconnects formed thereon is shown.

[0012] Figure 2 A cross-sectional side view illustration of another embodiment of a semiconductor substrate having passive devices and interconnects formed thereon is shown.

[0013] Figure 3 A cross-sectional side view illustration of an embodiment of a metal coating formed on a semiconductor substrate is shown.

[0014] Figure 4 A cross-sectional side view illustration of another embodiment of a metal film formed on a semiconductor substrate is shown.

[0015] Figure 5 A cross-sectional side view illustration of an embodiment of a semiconductor substrate having a metal cap coupled to an integrated circuit is shown.

[0016] Figure 6A cross-sectional side view illustration of an embodiment of a semiconductor substrate coupled to an integrated circuit is shown.

[0017] Figure 7 A cross-sectional side view illustration of an embodiment of a semiconductor substrate coupled to an integrated circuit is shown, wherein an electrically insulating material fills a gap between the substrate and the integrated circuit and a portion of the substrate is removed.

[0018] Figure 8 A cross-sectional side view illustration of an embodiment of a semiconductor substrate coupled to a baseplate coupled to an integrated circuit is shown.

[0019] Fig. 9 A cross-sectional side view illustration of an embodiment of a semiconductor substrate coupled to a substrate coupled to an integrated circuit is shown, wherein an electrically insulating material fills a space between the substrates.

[0020] Fig.10 A cross-sectional side view illustration of an embodiment of a semiconductor device is shown.

[0021] Fig.11 A cross-sectional side view illustration of an embodiment of a semiconductor substrate having separation lines is shown.

[0022] Fig.12 A cross-sectional side view illustration of another embodiment of a semiconductor substrate having separation lines is shown.

[0023] Fig.13 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown in which a post is coupled to a metal capping film located on a peripheral portion of the integrated circuit.

[0024] Fig.14 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown in which a pillar and a semiconductor substrate are coupled to the integrated circuit.

[0025] Fig.15 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown with a pillar and a semiconductor substrate coupled to the integrated circuit and with a portion of the substrate and the pillar removed.

[0026] Fig.16 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown wherein a pillar and a semiconductor substrate are coupled to the integrated circuit, another semiconductor substrate is coupled to the semiconductor substrate, and a pillar extension is coupled to the pillar.

[0027] Fig.17 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown in which a pillar and a semiconductor substrate are coupled to the integrated circuit, another semiconductor substrate is coupled to the semiconductor substrate, and a pillar extension is coupled to the pillar surrounded by an electrically insulating material.

[0028] Fig.18 A cross-sectional side view illustration of an embodiment of an integrated circuit is shown wherein a pillar and a semiconductor substrate are coupled to the integrated circuit, another semiconductor substrate is coupled to the semiconductor substrate, and a pillar extension is coupled to the pillar, wherein a portion of the another semiconductor substrate and the pillar extension are removed.

[0029] Fig.19 A cross-sectional side view illustration of another embodiment of a semiconductor device is shown.

[0030] Although the embodiments described in the present disclosure may be subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and described in detail herein. The drawings may not be to scale. It should be understood that the drawings and detailed description thereof are not intended to limit the invention to the specific forms disclosed, but rather, the invention is intended to cover all modifications, equivalent forms and alternative forms falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0031] Figure 1 A cross-sectional side view illustration of an embodiment of a semiconductor substrate having passive devices and interconnects formed thereon is shown. The substrate 100 can be a semiconductor substrate, such as but not limited to a silicon substrate or a silicon wafer. In certain embodiments, a passive device 102 is formed on or in the substrate 100. In certain embodiments, the passive device 102 is an inductor. For example, the passive device 102 can be a thin film inductor.

[0032] In certain embodiments, the interconnect 104 is formed in the substrate 100. The interconnect 104 may be a partial via or other three-dimensional interconnect formed in the substrate 100 that is filled with a conductive material (e.g., a metal such as copper). For example, the interconnect 104 may be a copper pillar or a copper / solder pillar in the substrate 100. The passive device 102 and / or the interconnect 104 may have a selected maximum depth in the substrate 100. The selected maximum depth may allow for portions of the passive device 102 and / or the interconnect 104 to be exposed during subsequent processing of the substrate 100 (e.g., exposed after removing a bottom portion of the substrate).

[0033] Figure 2 A cross-sectional side view illustration of another embodiment of a semiconductor substrate having passive devices and interconnects formed thereon is shown. Substrate 200 can be a semiconductor substrate, such as, but not limited to, a silicon substrate or a silicon wafer. In certain embodiments, passive device 202 is formed on or in substrate 200. In certain embodiments, passive device 202 is a capacitor. For example, passive device 202 can be a trench capacitor.

[0034] In certain embodiments, the interconnect 104 is formed in the substrate 200. The passive device 202 and / or the interconnect 104 may have a selected maximum depth in the substrate 200. The selected maximum depth may allow for portions of the passive device 202 and / or the interconnect 104 to be exposed during subsequent processing of the substrate 200 (e.g., exposed after removing a bottom portion of the substrate).

[0035] Figure 3 A cross-sectional side view illustration of an embodiment of a metal coating 106 formed on a substrate 100 is shown. Figure 4 A cross-sectional side view illustration of an embodiment of a metal coating 106 formed on a substrate 200 is shown. In some embodiments, the metal coating 106 includes a metal film patterned on a surface of the substrate 100 and / or a surface of the substrate 200. For example, the metal coating 106 can be copper patterned on a surface of the substrate 100 and / or the substrate 200. The metal coating 106 can include pads or other terminals connected to the passive devices 102, 202 and / or the interconnect 104.

[0036] In certain embodiments, such as Figure 3 As described above, the substrate 100 having the metal coating 106 is coupled to the integrated circuit by using the metal coating. Figure 5 A cross-sectional side view illustration of a substrate 100 having a metal coating 106 coupled to an integrated circuit 500 is shown. The integrated circuit 500 may include, but is not limited to, a system on a chip (SoC), a graphics processing unit (GPU), a central processing unit (CPU), a coprocessor, a bridge processor, and any other primary, secondary, or peripheral semiconductor processor utilizing voltage regulation. For example, the integrated circuit 500 may be a power-consuming semiconductor device (e.g., a device having current consuming elements such as a SOC). In certain embodiments, the integrated circuit 500 is formed using a CMOS (complementary metal oxide semiconductor) process. However, it should be understood that other processes known in the art may be used to form the integrated circuit 500.

[0037] In some embodiments, metal coating 502 is formed on integrated circuit 500. Metal coating 502 can be coupled to surface 504 (e.g., active side) of integrated circuit 500. Active surface 504 can include terminals or connections to active circuits in integrated circuit 500. In some embodiments, metal coating 502 has a pattern that mirrors metal coating 106 on substrate 100, such as Figure 5 shown.

[0038] In some embodiments, the integrated circuit 500 is located on a carrier. The carrier can support multiple integrated circuits. In some embodiments, the semiconductor substrate 100 is a semiconductor wafer that is sized to be coupled to all multiple integrated circuits on the carrier (e.g., in a wafer-level process, the semiconductor (wafer) substrate is coupled to the integrated circuits). Then, during subsequent processing, the semiconductor substrate 100 (e.g., semiconductor wafer) is separated (e.g., cut) to form different devices. Coupling multiple integrated circuits 500 and semiconductor substrate 100 in a wafer-level process can provide a high-yield process.

[0039] In some embodiments, semiconductor substrate 100 and / or semiconductor substrate 200 are separate substrates that are differently coupled to integrated circuit 500 (e.g., the semiconductor substrate is sized to match the integrated circuit). Different semiconductor substrates can be formed by cutting or otherwise separating semiconductor wafers to form different semiconductor substrates. The different semiconductor substrates can then be coupled to separate integrated circuits 500 (via a carrier or off a carrier). In certain embodiments, since different semiconductor substrates are coupled to separate integrated circuits, it may be possible to allow only the resulting semiconductor substrates and integrated circuits to be coupled. Coupling only the resulting semiconductor substrates and integrated circuits can increase the overall yield of the processes described herein.

[0040] Figure 6 5 shows a cross-sectional side view illustration of a substrate 100 coupled to an integrated circuit 500. In some embodiments, as Figure 6 As shown, the substrate 100 is coupled to the integrated circuit by coupling the metal coating 106 to the metal coating 502 to form a combined metal coating 506. The metal coating 506 can be formed using known techniques in the art for bonding metal coatings. For example, the metal coating 506 can be formed using copper / solder / copper technology or copper pillar technology.

[0041] In some embodiments, after semiconductor substrate 100 is coupled to integrated circuit 500, electrically insulating material 508 is filled into the space (gap) between the upper surface of the substrate and the lower (active) surface of the integrated circuit, such as Figure 7 As shown. The electrically insulating material 508 may fill the space (gap) between the semiconductor substrate 100 and the integrated circuit 500 around the metal film 600. The electrically insulating material 508 may be, for example, a polymer or epoxy material, such as an underfill material or an encapsulation material. The underfill material may include, but is not limited to, a capillary underfill material used in a flip chip bonding process, such as a fast curing underfill material or a thin underfill material. The encapsulation material may include, but is not limited to, a polymer or a mold compound, such as overmolding or exposed injection molding.

[0042] In certain embodiments, such as Figure 7As shown, the (lower) portion of the semiconductor substrate 100 is removed. The lower portion of the semiconductor substrate 100 can be removed, for example, by thinning the substrate using techniques known in the art (e.g., CMP (chemical mechanical polishing) or grinding). In some embodiments, removing the lower portion of the semiconductor substrate 100 exposes at least some of the interconnects 104 located on the lower surface of the substrate. In some embodiments, removing the lower portion of the semiconductor substrate 100 exposes at least some of the passive devices 102 and at least some of the interconnects 104.

[0043] In some embodiments, a redistribution layer (RDL) 510 is located at the lower portion of the substrate 100. The RDL 510 may include one or more wiring layers. The wiring may be, for example, copper wires or other suitable electrical conductors that redistribute the connections located on one side of the RDL 510 to other moved (e.g., horizontally shifted) locations on the other side of the RDL (e.g., the wiring interconnects the horizontally offset connections (terminals) located at the top and bottom of the RDL). Therefore, the RDL 510 can be used to redistribute the connections of the interconnector 104 and / or the passive device 102.

[0044] In some embodiments, the RDL 510 is made as a part of the semiconductor substrate 100 and is exposed after removing the lower portion of the semiconductor substrate. In some embodiments, the RDL 510 is formed on the lower surface of the semiconductor substrate 100 after removing the lower portion of the semiconductor substrate.

[0045] In some embodiments, after removing the lower portion of the semiconductor substrate 100, a metal coating 512 is formed on the lower surface of the semiconductor substrate, such as Figure 8 The metal coating 512 may be formed directly on the lower surface of the semiconductor substrate 100 or on the surface of the RDL 510 (eg, Figure 7 In some embodiments, metal coating 512 can be formed as part of RDL 510 (eg, the RDL includes a metal coating on a lower surface of the RDL).

[0046] The metal coating 512 can be used to couple the semiconductor substrate 100 to the semiconductor substrate 200, such as Figure 8 In some embodiments, semiconductor substrate 200 is a semiconductor wafer that is sized to be coupled to all of the multiple integrated circuits on a carrier (e.g., in a wafer-level process, the semiconductor (wafer) substrate is coupled to the integrated circuits along with semiconductor substrate 100). In some embodiments, semiconductor substrate 200 is a separate substrate that is coupled to semiconductor substrate 100 differently (e.g., the semiconductor substrate is sized to match integrated circuit 500).

[0047] In some embodiments, the metal coating 512 is coupled to the metal coating 106 located on the semiconductor substrate 200 to form a combined metal coating 514, such as Fig. 9 As shown. The metal coating 514 can be formed using known techniques in the art for bonding metal coatings. In some embodiments, after the semiconductor substrate 100 is coupled to the semiconductor substrate 200, the electrically insulating material 508 is filled into the space (gap) between the lower surface of the semiconductor substrate 100 and the upper surface of the semiconductor substrate 200, as shown. Fig. 9 The electrically insulating material 508 may fill the space (gap) between the semiconductor substrate 100 and the semiconductor substrate 200 surrounding the metal coating 514 .

[0048] In certain embodiments, such as Fig.10 As shown, the (lower) portion of the semiconductor substrate 200 is removed. The lower portion of the semiconductor substrate 200 can be removed, for example, by thinning the substrate using techniques known in the art. In some embodiments, removing the lower portion of the semiconductor substrate 200 exposes at least some of the interconnects 104 located on the lower surface of the substrate. In some embodiments, removing the lower portion of the semiconductor substrate 200 exposes at least some of the passive devices 202 and at least some of the interconnects 104.

[0049] In some embodiments, a redistribution layer (RDL) 520 is located at a lower portion of the substrate 200. The RDL 520 can be used to redistribute the connection portions of the interconnectors 104 and / or the passive devices 202. In some embodiments, the RDL 520 is made as a part of the semiconductor substrate 200 and is exposed after removing the lower portion of the semiconductor substrate. In some embodiments, the RDL 520 is formed on the lower surface of the semiconductor substrate 200 after removing the lower portion of the semiconductor substrate.

[0050] In some embodiments, after removing the lower portion of the semiconductor substrate 200, a metal coating 522 is formed on the lower surface of the semiconductor substrate, such as Fig.10As shown. The metal coating 522 may be formed directly on the lower surface of the semiconductor substrate 200 or on the surface of the RDL 520. In some embodiments, the metal coating 522 may be made as part of the RDL 520 (e.g., the RDL includes a metal coating on the lower surface of the RDL). The metal coating 522 may provide a terminal for connecting to the semiconductor substrate 200, the semiconductor substrate 100, and / or the integrated circuit 500. The semiconductor substrate 200 may be directly coupled to the metal coating 522. The integrated circuit 500 and the semiconductor substrate 100 may be coupled to the metal coating 522 using one or more interconnectors 104 (in both substrates) and / or the RDL on the substrate. The metal coating 522 may then be used to couple the integrated circuit 500, the semiconductor substrate 100, and / or the semiconductor substrate 200 to, for example, another device, a package, or a printed circuit board.

[0051] In certain embodiments, the integrated circuit 500, the semiconductor substrate 100, the semiconductor substrate 200, and their intermediate components form a semiconductor device 1000, such as Fig.10 As shown. For the wafer-level process described herein, the semiconductor device 1000 can be formed by removing the integrated circuit 500 from the carrier and separating (cutting) the structure including the semiconductor wafer for the semiconductor substrate 100 and the semiconductor substrate 200 along the selected boundary to form different semiconductor devices including independent integrated circuits. In some embodiments, the integrated circuit 500 remains on the carrier during separation (cutting), and the semiconductor device 1000 is removed from the carrier after separation (cutting). In some embodiments, the semiconductor device 1000 can be further processed to be located in a package or other structure.

[0052] In certain embodiments, a semiconductor wafer including semiconductor substrate 100 , semiconductor substrate 200 is separated to form substrates having a width smaller than that of integrated circuit 500 . Fig.11 A cross-sectional side view illustration of an embodiment of a semiconductor substrate 100 having separation lines is shown. Fig.12 1 is a cross-sectional side view illustration of an embodiment of a semiconductor substrate 200 having a separation line. Before separating (cutting) the substrates, a metal coating 106 may be formed on the semiconductor substrate 100 and the semiconductor substrate 200. Fig.11 As shown, the semiconductor substrate 100 can be separated to form a semiconductor substrate 100'. Fig.12 As shown, the semiconductor substrate 200 may be separated to form a semiconductor substrate 200 ′.

[0053] Fig.13A cross-sectional side view illustration of an embodiment of an integrated circuit 500 is shown, wherein a post 550 is coupled to a metal coating 502 located on a peripheral portion of the integrated circuit. The post 550 may be, for example, a copper post or a post made of other suitable conductors. The post 550 may be made using electroplating (e.g., electroplated copper). In certain embodiments, the post 550 is coupled to an input / output terminal on an active surface 504 of the integrated circuit 500. The terminals on the active surface 504 that are not used for input / output may be used for power (voltage) regulation connections to the integrated circuit 500. The post 550 may have a height greater than the metal coating 502. For example, in one embodiment, the post 550 has a height of about 60 μm, while the metal coating 502 has a height of about 10 μm.

[0054] The pillars 550 may be formed at the peripheral portion to allow the semiconductor substrate 100' to be located inside the peripheral portion and connected to the metal coating 502 without the pillars 550, such as Fig.14 As shown. Pillar 550 is then positioned at the perimeter of semiconductor substrate 100'. Semiconductor substrate 100' can be coupled to integrated circuit 500 using metal coating 106 and metal coating 502 to form a combined metal coating 506 as described herein. Since semiconductor substrate 100' is coupled to integrated circuit 500 within the perimeter portion of the integrated circuit coupled to pillar 550, the substrate is coupled to the integrated circuit differently (e.g., the substrate is coupled at an individual process level rather than a wafer level process).

[0055] After semiconductor substrate 100' is coupled to integrated circuit 500, electrically insulating material 508 is filled into the space (gap) between the upper surface of the substrate and the lower (active) surface of the integrated circuit. Electrically insulating material 508 also surrounds semiconductor substrate 100' and pillars 550, such as Fig.14 shown.

[0056] In certain embodiments, such as Fig.15 As shown, the lower portion of the semiconductor substrate 100', the pillars 550, and the electrically insulating material 508 are removed. The lower portion can be removed, for example, by thinning the substrate using techniques known in the art (e.g., CMP or grinding). In some embodiments, the lower portion of the semiconductor substrate 100' is removed to expose at least some of the interconnects 104 located on the lower surface of the substrate. In some embodiments, the lower portion of the semiconductor substrate 100' is removed to expose at least some of the passive devices 102 and at least some of the interconnects 104. Fig.15 As shown, pillars 550 and electrically insulating material 508 are thinned to the same extent as semiconductor substrate 100', wherein at least a portion of the pillars are exposed on the surface of the electrically insulating material. In some embodiments, a redistribution layer (RDL) 510 is located at a lower portion of substrate 100'.

[0057] In some embodiments, after removing the semiconductor substrate 100', the pillar 550, and the lower portion of the electrically insulating material 508, the pillar extension 550' is coupled to the remaining portion of the pillar 550, such as Fig.16 As shown. The pillar extension 550' may be formed, for example, by electroplating. The pillar extension 550' may be formed at the periphery of the semiconductor substrate 100'.

[0058] In some embodiments, semiconductor substrate 200' is coupled to semiconductor substrate 100' within a perimeter portion formed by pillars 550 and pillar extensions 550', such as Fig.16 The semiconductor substrate 200' can be coupled to the semiconductor substrate 100' using the metal coating 106 and the metal coating 512 to form the combined metal coating 514 described herein.

[0059] After the semiconductor substrate 200' is coupled to the semiconductor substrate 100', an electrically insulating material 508 is filled into the space (gap) between the upper surface of the semiconductor substrate 200' and the lower surface of the semiconductor substrate 100', such as Fig.17 The electrically insulating material 508 also surrounds the semiconductor substrate 200' and the pillar extension 550'.

[0060] In certain embodiments, such as Fig.18 As shown, the semiconductor substrate 200', the pillar extension 550', and the lower portion of the electrically insulating material 508 are removed. In some embodiments, the lower portion of the semiconductor substrate 200' is removed to expose at least some of the interconnects 104 located on the lower surface of the substrate. In some embodiments, the lower portion of the semiconductor substrate 200' is removed to expose at least some of the passive devices 202 and at least some of the interconnects 104. In some embodiments, a redistribution layer (RDL) 520 is located at the lower portion of the substrate 200'.

[0061] like Fig.18 As shown, pillar extension 550' and electrically insulating material 508 are thinned to the same extent as semiconductor substrate 200', wherein at least a portion of the pillar extension is exposed on the surface of the electrically insulating material. Thus, pillar 550 and pillar extension 550' ("pillar") provide direct electrical connection to input / output terminals of integrated circuit 500, wherein the pillar has a height approximately equal to the height of a connector (e.g., terminal) located on the exposed surface of semiconductor substrate 200'.

[0062] In some embodiments, after removing the semiconductor substrate 200', the pillar extension 550' and the lower portion of the electrically insulating material 508, a metal coating 522 is formed on the lower portion of the semiconductor substrate, the pillar extension and the electrically insulating material, such as Fig.19As shown. In some embodiments, at least some of the metal coating 522 is in contact with the pillar extension 550'. The metal coating 522 can provide terminals for connecting to the semiconductor substrate 200', the semiconductor substrate 100' and / or the integrated circuit 500. The semiconductor substrate 200' can be directly coupled to the metal coating 522. The integrated circuit 500 can be coupled to the metal coating 522 using the pillar 550 and the pillar extension 550' (to provide direct input / output terminals for the integrated circuit) and / or the integrated circuit can be coupled to the metal coating using one or more interconnects 104 (in both substrates) and / or RDL on the substrate. The semiconductor substrate 100' can be coupled to the metal coating 522 using one or more interconnects 104 and / or RDL on the substrate. The metal coating 522 can then be used to couple the integrated circuit 500, the semiconductor substrate 100' and / or the semiconductor substrate 200' to, for example, another device, package or printed circuit board.

[0063] In certain embodiments, integrated circuit 500, semiconductor substrate 100', semiconductor substrate 200', pillar 550, pillar extension 550', and intermediate components thereof form semiconductor device 1000', such as Fig.19 In some embodiments, the semiconductor device 1000' can be further processed to be located in a package or other structure.

[0064] Although the semiconductor device 1000 and the semiconductor device 1000' are shown herein as semiconductor substrate 100 coupled between integrated circuit 500 and semiconductor substrate 200, such that passive device 102 (e.g., inductor) is closer to the integrated circuit than passive device 202 (e.g., capacitor). It should be understood that the position of the semiconductor substrate and / or passive devices can be changed as desired. For example, semiconductor substrate 200 can be first coupled to integrated circuit 500, such that semiconductor substrate 200 is coupled between the integrated circuit and semiconductor substrate 100. Another embodiment includes placing passive device 202 on semiconductor substrate 100 and placing passive device 102 on semiconductor substrate 200. Any of these embodiments can provide a semiconductor device having passive device 202 (e.g., capacitor) that is closer to the integrated circuit than passive device 102 (e.g., inductor).

[0065] As described herein, semiconductor devices 1000 and 1000' provide semiconductor devices that include voltage regulation components (e.g., passive devices such as inductors and capacitors) close to integrated circuits. Therefore, semiconductor devices 1000 and 1000' are able to perform voltage regulation performance that is close to or equivalent to on-chip voltage regulation type performance. Semiconductor devices 1000 and 1000' provide high voltage regulation performance that can be achieved in current semiconductor device forms in a small form factor device.

[0066] In addition, the semiconductor device 1000 and the semiconductor device 1000' are formed using a process that is less expensive than a chip formation process that integrates a voltage regulating component during a CMOS process and is easily integrated using current processes. Since both the substrate and the integrated circuit can be produced before coupling, the semiconductor device 1000 and the semiconductor device 1000' can also be manufactured with a high yield, especially when each substrate is coupled to each integrated circuit.

[0067] Utilizing semiconductor substrate 100 or 100' and semiconductor substrate 200 or 200' in semiconductor device 100 or semiconductor device 1000' also allows passive devices, such as inductors and capacitors, to be formed in a process separate from the CMOS process used to form integrated circuit 500. Separating these processes allows the passive devices to be made as any type of passive device desired and with any characteristics or specifications desired without affecting the CMOS process. The passive devices may have customized characteristics or specifications to provide semiconductor device 1000 or semiconductor device 1000' with better performance characteristics than other voltage regulation implementations. Furthermore, the passive devices may be tailored for different implementations.

[0068] Passive devices fabricated on separate substrates may also allow processing techniques used to form the passive devices to focus on fabricating better passive devices (e.g., fabricating an inductor or capacitor as close to ideal as possible). Focusing processing techniques on fabricating passive devices on a single substrate rather than fabricating these devices in conjunction with another process may provide improved reliability and operation for the passive devices. For example, near-ideal capacitors may have a smaller equivalent series resistance (ESR) and / or have a smaller parasitic capacitance from their anode or cathode terminals to ground.

[0069] Other modifications and alternative embodiments of various aspects of the embodiments described in this disclosure will be apparent to those skilled in the art in light of this specification. Therefore, this specification is understood to be exemplary only and is intended to be used to teach those skilled in the art the general manner of performing the embodiments. It should be understood that the forms of the embodiments shown and described herein will be considered as currently preferred embodiments. Elements and materials may be replaced by those shown and described herein, parts and processes may be reversed, and certain features of the embodiments may be utilized independently, all of which will be apparent to those skilled in the art after having benefited from this specification. Modifications may be made to the elements described herein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, comprising: An integrated circuit comprising an active surface, wherein the integrated circuit comprises a power-consuming semiconductor device; a first semiconductor substrate having an upper surface, the first semiconductor substrate being directly attached to the active surface of the integrated circuit using a first metal coating on the upper surface of the first semiconductor substrate, wherein the first semiconductor substrate includes a first type of passive devices in the first semiconductor substrate and a first set of interconnectors passing through the first semiconductor substrate, at least some of the first type of passive devices being located at the upper surface of the first semiconductor substrate and directly attached to at least some of the first metal coating on the upper surface of the first semiconductor substrate; and a second semiconductor substrate coupled to the first semiconductor substrate using a second metal coating, wherein the second semiconductor substrate includes a second type of passive device in the second semiconductor substrate and a second set of interconnectors passing through the second semiconductor substrate; The first type passive component and the second type passive component are different types of passive components, the first type passive component includes an inductor, and the second type passive component includes a capacitor. 2 . The device according to claim 1 , further comprising an electrically insulating material filling a space surrounding the first metal film and between the first semiconductor substrate and the integrated circuit. 3 . The device of claim 2 , wherein the electrically insulating material comprises a single electrically insulating material layer filling a space surrounding the first metal film and between the first semiconductor substrate and the integrated circuit. 4 . The device according to claim 1 , further comprising an electrically insulating material filling a space surrounding the second metal film and between the second semiconductor substrate and the first semiconductor substrate.

5. The device of claim 1 , wherein the active surface comprises terminals to active circuits in the integrated circuit, the device further comprising one or more pillars coupled to the active surface of the integrated circuit on the periphery of the first semiconductor substrate and the second semiconductor substrate, wherein the pillars provide input / output terminals for the integrated circuit, and wherein the terminals on the active surface include the input / output terminals and terminals for voltage regulation connections to the integrated circuit using first type passive devices and / or second type passive devices.

6. The device of claim 1 , wherein the first semiconductor substrate comprises a redistribution layer at a surface of the first semiconductor substrate coupled to the second semiconductor substrate, and wherein the redistribution layer redistributes connections on a first side of the redistribution layer to horizontally displaced connections on a second side of the redistribution layer. 7 . The device of claim 1 , wherein at least some of the first set of interconnectors interconnect the first metal film to the second metal film. 8 . The device of claim 1 , wherein the first semiconductor substrate and the second semiconductor substrate have a width substantially the same as a width of the integrated circuit.

9. The device according to claim 1, wherein the second semiconductor substrate is coupled to the first semiconductor substrate using the second metal coating on the upper surface of the second semiconductor substrate, and the device further comprises a third metal coating coupled to the lower surface of the second semiconductor substrate, wherein the third metal coating is coupled to the integrated circuit using at least one interconnector in the first group of interconnectors and at least one interconnector in the second group of interconnectors.

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