Dual-sided heat dissipation MOSFET packaging structure and manufacturing method thereof

Abstract

Disclosed is a MOSFET packaging structure with double-sided heat dissipation and a manufacturing method thereof. The structure includes a chip body, a first heat dissipation carrier, a packaging colloid and a second heat dissipation carrier. The chip body is turned over and bonded to the first heat dissipation carrier, and the source pad and the gate pad of the chip body are respectively conducted to the source island and the gate island of the first heat dissipation carrier; the packaging colloid is formed on the first heat dissipation carrier; the packaging colloid is provided with a first limiting hole communicating with the drain layer and a second limiting hole outside the drain layer, which communicates with the drain island of the first heat dissipation carrier; the second heat dissipation carrier is turned over and attached to the packaging colloid, and the first drain column of the second heat dissipation carrier is inserted into the first limiting hole to conduct the drain layer and the second heat dissipation carrier, and the second drain column is inserted into the second limiting hole to conduct the second heat dissipation carrier and the drain island of the first heat dissipation carrier. The double-sided heat dissipation MOSFET packaging structure of the present invention has the effects of high heat capacity on both sides of the device, low temperature rise under the impact of instantaneous high power, and the transistors in the chip are not easily overheated and burned out.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device packaging, and more particularly to a double-sided heat dissipation MOSFET packaging structure and a manufacturing method thereof. Background Art

[0002] MOSFET is short for Metal-Oxide-Semiconductor Field-Effect Transistor, which is a field-effect transistor widely used in analog circuits and digital circuits. The packaging of MOSFET chips, like the requirements of general semiconductor packaging, hopes that the packaging volume is as small as possible, that is, the area ratio of the chip in the packaging size is as large as possible. When the chip packaging ratio reaches more than 0.64 (the length and width of the packaging are within 1.2 times the length and width of the chip respectively), it can be called chip scale packaging (CSP). When the packaging volume is smaller, the heat dissipation problem needs to be solved immediately, and the problem of easy heat generation of power semiconductor devices is an element that needs to be considered at all times. In the existing prior art, a double-sided heat dissipation MOSFET packaging structure or some enhanced heat dissipation design methods have been proposed.

[0003] Chinese invention patent publication number CN108288607A discloses a Power MOSFET with enhanced heat dissipation and its design method. In the structural design of the MOSFET chip package, it includes a chip and leads. The leads are led out from the chip. A pad for the Source electrode is provided on the front surface of the Power MOSFET, and a pad for the Drain electrode is provided on the bottom surface of the Power MOSFET. The leads are respectively led out from the chip and electrically connected to the pads of the Source and Drain electrodes, that is, the leads are led out from the chip of the Power MOSFET and connected to the Source electrode pad. The area of the pad for the Source electrode on the front of the Power MOSFET is adapted to the area of the pad for the Drain electrode on the bottom surface. However, in the prior art, if the related technology of this patent is adopted, the leads are formed by the wire bonding process, and the bonding needles of the wire bonding can only be joined to the contacts in the same upward direction. When the bottom surface of the Power MOSFET is provided with the pad for the Drain electrode, the upper surface of the pad for the Source electrode provided on the front surface of the Power MOSFET is located on the top surface of the package, and the lower surface of the pad for the Source electrode is located inside the package and faces the MOSFET chip downward. The wire bonding pads of the MOSFET chip and the pad for the Source electrode are not in the same upward direction, and there is difficulty in wire bonding. There is no design in the current packaging process that can turn the bonding needle 180 degrees in the bonding direction during the bonding of the bonding needle; in addition, the leads are used for the conduction of electrical signals, and their too thin wire diameter is not conducive to heat dissipation. Therefore, there is a form of double-sided heat dissipation on the surface of the package, but there is a lack of a sufficiently good heat conduction mechanism inside the package, and only the epoxy resin layer with limited original heat conduction ability can be relied on for heat conduction inside the package. Further research finds that the resistance of the MOSFET chip package formed by wire bonding is usually above 0.3mR.

[0004] Chinese Patent Publication No. CN111477683A discloses a packaging structure for a power MOSFET chip. The front side of the MOSFET chip includes a gate and a source, and the back side includes a drain. A first conductor, such as a molybdenum heat sink, is electrically connected to the drain on the back side of the MOSFET chip in a face-to-face fitting manner. A second conductor, such as a molybdenum heat sink, is electrically connected to the source on the front side of the MOSFET chip through press-fit packaging in a face-to-face fitting manner. A stress buffer area is provided in the area on the front side of the MOSFET chip occupied by the source. The edge of the second conductor in contact with the source is located within the stress buffer area. The stress buffer area provided on the front side of the MOSFET chip is obviously unnecessary. The size of the loop-shaped contour of the stress buffer area is slightly smaller than the area of the region on the front side of the MOSFET chip occupied by the source. This is because in the packaging process, the chip is first mounted face-up on the first conductor, and then the second conductor is mounted on the face-up front side of the chip. Therefore, when the chip is mounted, the front side of the chip is adsorbed and contacted by the pick-and-place fixture, and when the second conductor is mounted, the second conductor directly presses on the front side of the chip. In these two operations, the front side of the chip with the source and gate circuit structures directly bears stress, and the transistor structure close to the front side of the chip is easily damaged. Especially in the current structure of the MOSFET chip, both the source and the gate are provided on the front side of the chip. In order to electrically connect a third conductor to the gate on the front side of the MOSFET chip (in the existing common technology, the third conductor is a bonding wire formed by wire bonding), the downward pressing of the second conductor needs to avoid the gate connection area, making it difficult for the second conductor to be evenly pressed on the front side of the chip. The uneven pressure is likely to cause local stress on the front side of the chip, and the transistors close to the front side of the chip are easily damaged.

[0005] Chinese Utility Model Patent Publication No. CN204464263U discloses a modular MOSFET packaging structure. It includes Chip I and Chip II encapsulated in a package body. The front-side redistribution metal layer II is connected to Chip I and Chip II respectively through the insulating layer openings on the upper surface of the package body. The front-side redistribution metal layer I is located outside the vertical area of the front side of Chip I. A part of the upper surfaces of the front-side redistribution metal layer I and the front-side redistribution metal layer II form pads respectively, and the protective layer exposes the pads. The metal connector I and the front-side redistribution metal layer I are arranged on the same side of Chip I. The metal connector II is arranged below Chip I, and the back-side redistribution metal layer connects the metal connector I and the metal connector II. In the related technology, a molding encapsulation technology with the chip attached on the front side and a manufacturing process of depositing metal layers on both sides of the wafer are adopted. The thermal volume of the extremely thin metal layer is not sufficient to achieve good double-sided heat dissipation of the package. Special packaging equipment is required in manufacturing, and the cost of the front-end equipment is relatively high. Moreover, the front side of the chip (also known as the processing surface or the active surface, that is, the IC processing surface of the semiconductor manufacturing process) is too close to the bonding surface of the packaging structure, and the protection of the front side of the chip is not as good as that of the traditional packaging structure. Summary of the Invention

[0006] One of the main objectives of the present invention is to provide a MOSFET packaging structure with double-sided heat dissipation, which has the effects of high heat capacity on both sides of the device, low temperature rise under the impact of instant high power, and the transistors in the chip are not easily overheated and burned out, and overcomes the problems of easy occurrence of lamination stress or insufficient heat capacity on the front side of the chip during the packaging process of the existing double-sided heat dissipation structure.

[0007] Another main objective of the present invention is to provide a manufacturing method of a MOSFET packaging structure with double-sided heat dissipation, achieving the effects of reducing the manufacturing difficulty and production process flow of the semiconductor packaging of the MOSFET chip under the double-sided heat dissipation architecture.

[0008] The third main objective of the present invention is to provide an electronic device, which can achieve the effect of more quickly exporting the heat inside the MOSFET chip.

[0009] One of the main objectives of the present invention is achieved through the following technical solutions:

[0010] A MOSFET packaging structure with double-sided heat dissipation is proposed, including:

[0011] A chip body, having a processing surface and an opposite back surface, with a source pad and a gate pad provided on the processing surface, and a drain layer provided on the back surface;

[0012] A first heat dissipation carrier wafer, for the flip and bonding of the chip body in a flip-chip bonding manner, and the source pad and the gate pad of the chip body are respectively conducted to the source island and the gate island of the first heat dissipation carrier wafer;

[0013] A first encapsulation colloid, formed on the first heat dissipation carrier wafer to seal the chip body; the first encapsulation colloid is provided with a first limiting hole communicating with the drain layer and a second limiting hole outside the drain layer, and the second limiting hole communicates with the drain island of the first heat dissipation carrier wafer;

[0014] A second heat dissipation carrier wafer, arranged on the first encapsulation colloid in a flip-chip bonding manner, with a first drain column and a second drain column that are mutually conducted provided on the inner surface of the second heat dissipation carrier wafer, the inner surface of the second heat dissipation carrier wafer is flipped towards the first encapsulation colloid, the first drain column is inserted into the first limiting hole to conduct the drain layer and the second heat dissipation carrier wafer; and, the second drain column is inserted into the second limiting hole to conduct the second heat dissipation carrier wafer and the drain island of the first heat dissipation carrier wafer, and the second heat dissipation surface of the second heat dissipation carrier wafer is parallel to the packaging bottom surface.

[0015] By adopting the above technical solution, the second heat dissipation carrier is disposed on the first encapsulation colloid in a flip-chip bonding manner, and the second heat dissipation surface of the second heat dissipation carrier is parallel to the encapsulation bottom surface. In the first flip-chip bonding of the second heat dissipation carrier, the first drain column of the second heat dissipation carrier conducts the drain layer of the chip body, and the second drain column of the second heat dissipation carrier conducts the drain island of the first heat dissipation carrier, so as to replace the bonding wire formed by wire bonding and have a high heat capacity. The second heat dissipation carrier can be used as an external heat sink during the encapsulation or / and testing process and can also be used as an internal heat sink of the finished encapsulation structure, eliminating the shortcomings of both internal and external heat sinks, combining the advantages of both internal and external heat sinks, and solving the problems that when directly using an internal heat sink, it is easy to generate pressing stress on the front side of the chip and difficult to encapsulate with mold compound, or when directly using an external heat sink, the internal thermal resistance in the encapsulation is high.

[0016] In a preferred embodiment of the present invention, it can be further configured that: the connection of the source pad to the source island and the connection of the gate pad to the gate island include coplanar soldering; the connection of the first drain column to the drain layer and the connection of the second drain column to the drain island include soldering with a height difference or a tight fit of metal column insertion; when using a tight fit of metal column insertion, a metal covering layer is formed on the upper surface of the first encapsulation colloid and the inner side walls and bottom of the first limiting hole and the second limiting hole, and the drain layer of the chip body and the drain island of the first heat dissipation carrier are electrically interconnected in advance before installing the second heat dissipation carrier.

[0017] By adopting the above preferred technical features, the connection of the first drain column of the second heat dissipation carrier to the drain layer of the chip body and the connection of the second drain column of the second heat dissipation carrier to the drain island of the first heat dissipation carrier include soldering with a height difference or a tight fit of metal column insertion. The first heat dissipation surface of the second heat dissipation carrier does not need to be parallel to the encapsulation bottom surface, allowing a larger encapsulation margin. When using a tight fit of metal column insertion, the metal covering layer is used to electrically interconnect the drain layer of the chip body and the drain island of the first heat dissipation carrier in advance before installing the second heat dissipation carrier. The second drain column can be used as a rough positioning, and the first drain column can be used as a fine positioning, so that the second heat dissipation carrier can be accurately positioned on the chip body.

[0018] In a preferred embodiment of the present invention, it can be further configured that: the encapsulation structure further includes a second encapsulation colloid formed on the first encapsulation colloid to surround and fix the periphery of the second heat dissipation carrier.

[0019] By adopting the above preferred technical features, the second heat dissipation carrier in the encapsulation process is transformed from an external heat sink to an internal heat sink of the finished product by using the second encapsulation colloid formed on the first encapsulation colloid.

[0020] In a preferred embodiment, the present invention can be further configured such that: the second encapsulation colloid and the second heat dissipation carrier together provide a flush encapsulation top surface, which is parallel to the encapsulation bottom surface provided by the first heat dissipation carrier.

[0021] By adopting the above preferred technical features, the second encapsulation colloid and the second heat dissipation carrier together provide a flush encapsulation top surface, which is parallel to the encapsulation bottom surface, so that the first encapsulation colloid is neither part of the encapsulation bottom surface nor part of the encapsulation top surface. The formation of the first encapsulation colloid has a wider encapsulation margin. The first encapsulation colloid only needs to be able to encapsulate the chip body and does not bear the requirement of encapsulation thickness. The thickness of the second heat dissipation carrier on the first encapsulation colloid can be used for readjusting the finished encapsulation thickness.

[0022] In a preferred embodiment, the present invention can be further configured such that: before the second encapsulation colloid is formed and cured, the second heat dissipation carrier is detachably separable from the first encapsulation colloid.

[0023] By adopting the above preferred technical features, since the second heat dissipation carrier is detachably separable from the first encapsulation colloid, the second heat dissipation carrier can be trimmed or replaced based on the test results as long as it is before the second encapsulation colloid is cured.

[0024] In a preferred embodiment, the present invention can be further configured such that: the gate island is located at the corner notch of the source island, and the drain island is located at the side of the source island away from the corner notch.

[0025] By adopting the above preferred technical features, by using the gate island located at the corner notch of the source island and the drain island located at the side of the source island away from the corner notch, the gate island and the drain island are separated by the source island in the encapsulation bottom surface, and the area of the drain island is larger than that of the gate island. The electromagnetic field effect of the electron flow flowing to the drain island on the gate island is greatly reduced. In addition, it also makes the gate island, the drain island and the source island all have at least two sides adjacent to at least two corresponding sides of the four peripheries of the encapsulation bottom surface, which is beneficial to the stability of each island of the first heat dissipation carrier in the encapsulation process.

[0026] In a preferred embodiment, the present invention can be further configured such that: the encapsulation structure is a flip-chip chip scale package (FC-CSP), and the second heat dissipation surface of the second heat dissipation carrier simultaneously exceeds and covers either the drain layer of the chip body or the source island of the first heat dissipation carrier; preferably, a plurality of the first drain pillars and a plurality of the second drain pillars are respectively arranged in individual array regions on the inner surface of the second heat dissipation carrier, and the length of the second drain pillar is greater than the length of the first drain pillar; more preferably, the array pattern of the first drain pillar or / and the second drain pillar is defined as the hidden identification code of the individual MOSFETs of the chip body.

[0027] By adopting the above preferred technical features, since both the chip body and the second heat sink carrier can be flip-chip bonded, the packaging structure of the semiconductor power device obtains the form of a flip-chip chip scale package (FC-CSP) with double-sided heat dissipation under the condition of reduced packaging size. Preferably, by using the partitioned array configuration of a plurality of first drain pillars and a plurality of second drain pillars, the longer second drain pillars can be used as rough positioning for mounting the second heat sink carrier, and the shorter first drain pillars can be used as fine positioning for mounting the second heat sink carrier, effectively transferring the heat generated by the chip operation to the top surface of the package. More preferably, by using the pattern of the partitioned array configuration of a plurality of first drain pillars and a plurality of second drain pillars as the hidden identification code for individual MOSFETs of the chip body, it is used to identify the manufacturing information of the chip body. For example, when the sizes of the chip bodies are different, most of the first drain pillars can be joined to the drain layer of the chip body to form a parallel conductor pillar connection, and a small number of the first drain pillars will not be joined to the drain layer of the chip body. It can be identified from the electron flow distribution that those first drain pillars are open connections, or it can be determined that those first limit holes are floating connections before mounting the second heat sink carrier.

[0028] The second main object of the present invention is achieved through the following technical solutions:

[0029] A manufacturing method of a MOSFET packaging structure with double-sided heat dissipation is proposed to manufacture the MOSFET packaging structure with double-sided heat dissipation that may be combined by any of the above technical solutions. The manufacturing method includes:

[0030] Prepare an isolated chip body, the chip body having a processing surface and a corresponding back surface, a source pad and a gate pad being provided on the processing surface, and a drain layer being provided on the back surface;

[0031] Flip the chip body in a flip-chip bonding manner and bond it to the first heat sink carrier, so that the source pad and the gate pad of the chip body are respectively conducted to the source island and the gate island of the first heat sink carrier;

[0032] Form a first encapsulation colloid on the first heat sink carrier to seal the chip body; the first encapsulation colloid is provided with a first limit hole communicating with the drain layer and a second limit hole outside the drain layer, and the second limit hole communicates with the drain island of the first heat sink carrier;

[0033] The single - separated second heat - dissipating carrier is flipped and flip - chip bonded onto the first encapsulation colloid. The inner surface of the second heat - dissipating carrier is provided with a first drain pillar and a second drain pillar that are electrically connected to each other. In a single flipping and bonding process, the first drain pillar is inserted into the first limiting hole to conduct the drain layer and the second heat - dissipating carrier; meanwhile, the second drain pillar is inserted into the second limiting hole to conduct the second heat - dissipating carrier and the drain island of the first heat - dissipating carrier.

[0034] By adopting the above - mentioned technical solution, by flipping the single - separated second heat - dissipating carrier and setting it on the first encapsulation colloid in a flip - chip bonding manner, it can share the packaging equipment with the flip - chip bonding process of the chip body and does not require a wire - bonding process. Moreover, the top surface of the package has good heat capacity, can carry out more heat from the chip, the packaging process is simple and does not require investment in special equipment. During the packaging process, it will not cause internal stress due to pressing on the processing surface (front side) of the chip body. There is no need to fabricate a silicon via structure inside the chip body, and the effective working area of the transistors inside the chip body can be effectively enlarged.

[0035] In a preferred example of the present invention, it can be further configured as follows:

[0036] During the process of installing the chip body, the connection of the source pad to the source island and the connection of the gate pad to the gate island include coplanar soldering; during the process of installing the second heat - dissipating carrier, the connection of the first drain pillar to the drain layer and the connection of the second drain pillar to the drain island include soldering with a height difference or a tight fit of metal pillar insertion; when using a tight fit of metal pillar insertion, a metal covering layer is formed on the upper surface of the first encapsulation colloid and the inner side walls and bottom of the first limiting hole and the second limiting hole, and the drain layer of the chip body and the drain island of the first heat - dissipating carrier are electrically interconnected in advance before installing the second heat - dissipating carrier;

[0037] Or / and, after forming the first encapsulation colloid, the gate island is located at the corner notch of the source island, and the drain island is located on the side of the source island away from the corner notch;

[0038] Or / and, after flipping and bonding the second heat - dissipating carrier, it further includes: forming a second encapsulation colloid on the first encapsulation colloid to surround and fix the periphery of the second heat - dissipating carrier;

[0039] Or / and, before the second encapsulation colloid is formed and cured, the second heat - dissipating carrier is detachable and separable relative to the first encapsulation colloid;

[0040] Or / and, after forming the second encapsulation colloid, the method further comprises: planarizing and grinding the second encapsulation colloid and the second heat dissipation carrier, so that the second encapsulation colloid and the second heat dissipation carrier jointly provide a flush encapsulation top surface, which is parallel to the encapsulation bottom surface provided by the first heat dissipation carrier;

[0041] Or / and, after the second packaging colloid is formed, it also includes: package singulation cutting, so that the packaging structure is constituted as a flip chip size package (FC-CSP), and the second heat dissipation surface of the second heat sink carrier is larger than and covers either the drain layer of the chip body and the source island of the first heat sink carrier.

[0042] The technical effects corresponding to the above-mentioned features can be achieved by adopting the above-mentioned preferred technical features and utilizing the above-mentioned corresponding structural features or a combination of their possible structural features.

[0043] The third main purpose of the present invention is achieved through the following technical solutions:

[0044] An electronic device is proposed, comprising: a printed circuit board and a double-sided heat dissipation MOSFET package structure which is bonded to the printed circuit board and is a possible combination of any of the above-mentioned technical solutions; the source island, the gate island and the drain island located on the bottom surface of the package of the double-sided heat dissipation MOSFET package structure are bonded to the printed circuit board by solder; and the second heat sink carrier is exposed on the top surface of the package of the double-sided heat dissipation MOSFET package structure.

[0045] By adopting the above technical solution, the electronic device can transfer the heat of the MOSFET package structure more quickly, and the second heat sink carrier not only serves as the drain intermediate connection but also serves as the heat dissipation of the package top surface.

[0046] In summary, the technical solution of the present invention includes at least one of the following technical effects that contribute to the prior art:

[0047] 1. The double-sided heat dissipation MOSFET package structure of the present invention can further reduce the internal resistance of the package. Electrically, the chip is flip-chip bonded on the second heat sink carrier to replace the original source / gate upward wire connection, and the second heat sink carrier is flip-chip bonded on the first package colloid to replace the original drain downward installation. In the DFN5*6 package form, the introduced resistance can be reduced to below 0.1mΩ, while the traditional package resistance connected by wire bonding is usually above 0.3mR.

[0048] 2. In the prior art, the MOSFET chip is packaged with the front side facing up, and the source is led out through the internal leads of the wire bonding. The leads are long and thin, and the transistors close to the front side of the chip are relatively far away from the bottom substrate, resulting in poor heat conduction in the package. The heat from the chip operation is mainly transferred to the substrate through the bottom of the package close to the back side of the chip, resulting in large thermal resistance. In addition, the heat on the upper and lower surfaces of the package is uneven, which easily generates regional hot spots and causes the chip to overheat and burn. The chip of the present invention adopts a flip chip combination (FLIP The chip adopts a heat dissipation (CHIP) method, in which the electrical connection of the source is directly connected to the external printed circuit board (PCB) through the first heat dissipation carrier at the bottom. The entire source of the chip is welded to the source island of the first heat dissipation carrier, with a large contact area, extremely low resistance, and a short heat transfer path. The heat from the operation of the transistor is directly transferred to the first heat dissipation carrier through the source on the front of the chip, achieving the effect of heat dissipation on the bottom surface of the package. The drain heat transmitted to the back of the chip is dissipated upward by the second heat dissipation carrier, achieving the effect of heat dissipation on the top surface of the package, and it is not easy to generate hot spots; the second heat dissipation carrier uses a double drain column to electrically connect the drain to the drain island of the first heat dissipation carrier, and the high current capacity of the semiconductor power device is greatly improved, which is more than 20% higher than the current transmission capacity of the same level chip under traditional packaging.

[0049] 3. In the prior art, the MOSFET packaging structure in the form of DFN (Dual Flat No-Lead) packaging usually has the plastic packaging material shell as the exposed surface, and the poor thermal conductivity is not conducive to heat dissipation. In the example structure of the present invention, the upper and lower surfaces of the package are both metal carriers. In addition to the heat conduction on the lower surface, the heat can also be dissipated from the upper surface of the package to the air, which can enhance the heat dissipation performance. The second heat dissipation carrier of the present application can be used as an external heat sink in the packaging and testing stage, and can be used as a built-in heat sink in the finished product stage, with better heat dissipation capacity and adjustable effect.

[0050] 4. In the prior art, the MOSFET packaging structure in the form of DFN DUAL COOL packaging is provided with a heat sink on the upper surface of the package, which is added by pressing a layer of built-in metal sheet before plastic packaging. The built-in heat sink is bonded to the carrier (or chip) by an adhesive. The bonding interface of the built-in heat sink is affected by the molding pressure. The thickness and inclination of the built-in heat sink are difficult to control, and the thermal conductivity effect is not ideal. In the exemplary structure of the present invention, the first limiting hole and the second limiting hole are used as through holes of the first packaging colloid to lead out the drain electrode. It is preferred to deposit a metal layer first as the conductive and heat dissipation connection of the second heat sink carrier. The production steps are simpler, compatible with the semiconductor packaging process, and easy to mass produce; combined with the second packaging colloid and the top surface leveling process, the overall packaging thickness and the inclination of the second heat sink carrier on the top surface of the package are easy to control.

[0051] 5. Under the condition of the same package outline dimensions, the chip area that can be encapsulated is larger than that of the traditional DFN package. Compared with the traditional CSP package, in the exemplary structure of the present invention, there is a second heat sink and the plastic encapsulant of the second encapsulation colloid on the top surface of the package, and the internal chip is not easily damaged physically, and it can be made into standard package dimensions, which is convenient for production.

[0052] 6. The metal substrate at the bottom and the metal substrate at the top together constitute the front and back heat dissipation of the device, realizing double-sided heat dissipation. And due to the addition of the metal substrate, compared with WLCSP (wafer-level chip scale package), the device has a higher heat capacity, lower temperature rise under the impact of instantaneous high power, and is not easily overheated and burned out.

[0053] 7. In the package of the exemplary structure of the present invention, the connection of the source and the gate inside the package is not through leads, but directly connected to the first heat dissipation carrier by flip-chip bonding. The connection of the drain is also not through leads, but the second heat dissipation carrier connects the first heat dissipation carrier and the chip by flip-chip bonding. The signal transmission path is short, the delay is small, and the inductive reactance is low, which is more conducive to the operation of high-frequency devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A cross-sectional schematic diagram showing the double-sided heat dissipation MOSFET package structure of some preferred embodiments of the present invention;

[0055] Figure 2 A schematic diagram of the bottom surface of the package showing the double-sided heat dissipation MOSFET package structure of some preferred embodiments of the present invention;

[0056] Figure 3 A schematic diagram of the top surface of the package showing the double-sided heat dissipation MOSFET package structure of some preferred embodiments of the present invention;

[0057] Figure 4 A cross-sectional schematic diagram showing flipping the chip body and bonding it to the first heat dissipation carrier by flip-chip bonding in the MOSFET packaging method of some preferred embodiments of the present invention;

[0058] Figure 5 A cross-sectional schematic diagram showing forming the first encapsulation colloid on the first heat dissipation carrier in the MOSFET packaging method of some preferred embodiments of the present invention;

[0059] Figure 6 A cross-sectional schematic diagram showing that the first encapsulation colloid is provided with a first limiting hole and a second limiting hole in the MOSFET packaging method of some preferred embodiments of the present invention;

[0060] Figure 7Cross-sectional schematic diagram showing the flipping of the isolated second heat sink on the first encapsulation colloid in the MOSFET encapsulation method according to some preferred embodiments of the present invention;

[0061] Figure 8 Cross-sectional schematic diagram showing the flip-chip bonding method for setting the second heat sink on the first encapsulation colloid in the MOSFET encapsulation method according to some preferred embodiments of the present invention;

[0062] Figure 9 Cross-sectional schematic diagram showing the formation of the second encapsulation colloid on the first encapsulation colloid in the MOSFET encapsulation method according to some preferred embodiments of the present invention;

[0063] Figure 10 Cross-sectional schematic diagram showing the double-sided heat dissipation MOSFET encapsulation structure according to some other preferred embodiments of the present invention;

[0064] Figure 11 Cross-sectional schematic diagram showing the formation of a metal covering layer on the first encapsulation colloid after opening the limiting holes in the double-sided heat dissipation MOSFET encapsulation method according to some other preferred embodiments of the present invention;

[0065] Figure 12 Cross-sectional schematic diagram showing the flipping of the isolated second heat sink on the first encapsulation colloid after forming a metal covering layer in the double-sided heat dissipation MOSFET encapsulation method according to some other preferred embodiments of the present invention.

[0066] Reference numerals: 10, chip body; 11, processing surface; 12, back surface; 13, source pad; 14, gate pad; 15, drain layer; 20, first heat sink; 21, source island; 21A, corner notch; 21B, side; 22, gate island; 23, drain island; 30, first encapsulation colloid; 31, first limiting hole; 32, second limiting hole; 40, second heat sink; 41, first drain post; 42, second drain post; 43, first heat dissipation surface; 44, second heat dissipation surface; 50, second encapsulation colloid; 51, encapsulation top surface; 60, solder; 70, metal covering layer. Detailed implementation manners

[0067] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments that are used to understand the inventive concept of the present invention, and cannot represent all embodiments, nor are they used as the sole embodiment for explanation. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art on the premise of understanding the inventive concept of the present invention fall within the scope of protection of the present invention.

[0068] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly. For the convenience of understanding the technical solution of the present invention, the double-sided heat dissipation MOSFET package structure and its manufacturing method of the present invention will be further described and explained in detail below, but it does not limit the scope of protection of the present invention.

[0069] The "flip-chip bonding" described in the specification refers to an object that can be flip-chip bonded by a flip-chip bonding machine. During manufacturing, the processing surface faces upward, and during installation, the processing surface faces downward. The object can be a chip or a heat sink. If it is a chip, the processing surface is the device formation surface; if it is a heat sink, the processing surface is the surface provided with heat conducting columns. For example, in the examples of the present invention, during semiconductor manufacturing of the chip, the processing surface 11 of the chip body 10 faces upward to fabricate devices such as transistors; during the packaging and installation of the chip, the processing surface 11 of the chip body 10 faces downward for bonding. During manufacturing of the second heat dissipation carrier 40, the inner surface of the second heat dissipation carrier 40 faces upward to set the drain columns 41 and 42; during the packaging and installation of the second heat dissipation carrier 40, the inner surface of the second heat dissipation carrier 40 faces downward for bonding.

[0070] The "heat dissipation carrier" described in the specification means that the heat dissipation exposure area on the corresponding packaging surface of a certain heat dissipation object is more than 60%. For example, the occupied area of the first heat dissipation carrier 20 on the packaging bottom surface is more than 60%, specifically more than 69.4% (as Figure 2 shown), usually not exceeding 100%; the occupied area of the second heat dissipation carrier 40 on the packaging top surface is more than 60%, specifically more than 69.4% (as Figure 3 shown), usually not exceeding 100%.

[0071] The figures shown include parts that are common to multiple embodiments, and the parts with differences or distinctions in the variation examples are described in text separately. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the following described individual technical features or any combination of them can be characterized in the same embodiment, or whether multiple technically mutually exclusive technical features can only be characterized in different variation embodiments respectively.

[0072] Figure 1 The cross-sectional schematic diagram of the double-sided heat dissipation MOSFET package structure showing some preferred embodiments of the present invention, Figure 2 The schematic diagram of the packaging bottom surface of the double-sided heat dissipation MOSFET package structure, Figure 3 The schematic diagram of the packaging top surface of the double-sided heat dissipation MOSFET package structure. Refer to Figures 1 to 3, in some preferred embodiments of the present invention, a MOSFET packaging structure with double-sided heat dissipation is proposed, including: a chip body 10, a first heat dissipation carrier 20 located below the chip body 10, a first packaging colloid 30 for sealing the chip body 10, and a second heat dissipation carrier 40 disposed on the first packaging colloid 30.

[0073] The chip body 10 has a processing surface 11 and an opposite back surface 12. An anode pad 13 and a gate pad 14 are disposed on the processing surface 11, and a drain layer 15 is disposed on the back surface 12. A transistor (not shown in the figure) is provided inside the chip body 10. The base material of the chip body 10 is semiconductor, specifically silicon, and may also include any semiconductor material such as SIC, GaN, Ga2O3, SiGe, or GaAs, or other III-V group or II-VI compounds. In the example, the processing surface 11 is the processing surface for forming devices in semiconductor technology, the back surface 12 is the surface opposite to the processing surface 11, the anode pad 13 and the gate pad 14 are usually made of metal, and the drain layer 15 can also be made of metal, preferably aluminum or other conductive metal materials. The anode pad 13, the gate pad 14, and the drain layer 15 are all made at the wafer level by semiconductor manufacturing processes and are formed into individual chip bodies 10 through die cutting. An electric bias voltage is applied through the gate pad 14 to form a gate field effect, so that the anode pad 13 and the drain layer 15 are conducted.

[0074] The first heat dissipation carrier 20 is used for the flip and bonding of the chip body 10 in a flip-chip bonding manner. The anode pad 13 and the gate pad 14 of the chip body 10 are respectively conducted to the anode island 21 and the gate island 22 of the first heat dissipation carrier 20. Specifically, solder 60 such as solder balls can be used to achieve the bonding between the pad and the island. The flip-chip bonding manner makes the processing surface 11 of the chip body 10 face the first heat dissipation carrier 20. In the example, the first heat dissipation carrier 20 further includes a drain island 23. An example distribution of the anode island 21, the gate island 22, and the drain island 23 is as Figure 2 shown. In terms of area comparison, the anode island 21 is larger than the drain island 23, and the drain island 23 is larger than the gate island 22. The anode island 21 is spaced between the drain island 23 and the gate island 22. The first heat dissipation carrier 20 is made of a metal material with good heat conduction, usually copper, iron, or their alloys. The lower surface of the first heat dissipation carrier 20 provides the packaging bottom surface. In the example, the thickness of the first heat dissipation carrier 20 accounts for 8-30% of the overall packaging thickness; the overall packaging thickness of the MOSFET packaging structure is about 200-700 µm (micrometers).

[0075] The first encapsulation colloid 30 is formed on the first heat dissipation carrier 20 to seal the chip body 10; the first encapsulation colloid 30 is provided with a first limiting hole 31 communicating with the drain layer 15 and a second limiting hole 32 outside the drain layer 15, and the second limiting hole 32 communicates with the drain island 23 of the first heat dissipation carrier 20. Usually, the first encapsulation colloid 30 is a thermosetting insulating material and is formed by a molding encapsulation method. The first limiting hole 31 and the second limiting hole 32 are preferably formed after the first encapsulation colloid 30 is formed by etching or laser; holes can also be formed during the formation process of the first encapsulation colloid 30.

[0076] The second heat dissipation carrier 40 is disposed on the first encapsulation colloid 30 in a flip-chip bonding manner. The inner surface of the second heat dissipation carrier 40 is provided with a first drain column 41 and a second drain column 42 that are electrically connected to each other. The inner surface of the second heat dissipation carrier 40 is turned towards the first encapsulation colloid 30. The first drain column 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40; and the second drain column 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20. The second heat dissipation surface 44 of the second heat dissipation carrier 40 is parallel to the encapsulation bottom surface. Specifically, solder 60 such as solder bumps or solder balls can be used to achieve the bonding between the columns and the pads. The second heat dissipation carrier 40 is made of a metal material with good thermal conductivity, usually copper, iron or their alloys. The upper surface (second heat dissipation surface 44) of the second heat dissipation carrier 40 provides part or all of the encapsulation top surface 51. Specifically, referring to Figure 7 , the second heat dissipation carrier 40 has a first heat dissipation surface 43 in the encapsulation process, which is the same as the back surface 12 of the chip body 10 and has the equipment applicability that can be picked up and installed by the same flip-chip bonder. In the example, the thickness of the main layer of the second heat dissipation carrier 40 accounts for 5-20% of the overall encapsulation thickness.

[0077] The principle of the above embodiment is: the second heat sink 40 is arranged on the first packaging colloid 30 by flip chip bonding, and the second heat dissipation surface 44 of the second heat sink 40 is parallel to the bottom surface of the package. In the first flip chip bonding of the second heat sink 40, the first drain column 41 of the second heat sink 40 is connected to the drain layer 15 of the chip body 10, and the second drain column 42 of the second heat sink 40 is connected to the drain island 23 of the first heat sink 20, so as to replace the welding wire formed by wire bonding and have high heat capacity. The second heat sink 40 can be used as an external heat sink in the packaging or / and testing process, and can also be used as a built-in heat sink of the finished packaging structure, eliminating the shortcomings of the inside and outside, and having both the advantages of the inside and outside, solving the problem of the prior art that the built-in heat sink is easy to cause pressing stress and mold sealing and glue filling difficulties on the front of the chip, or directly using the external heat sink in the package. The problem of high thermal resistance. In the semiconductor packaging process, it is not necessary to excessively require the upper surface of the first packaging colloid 30 to be parallel to the bottom surface of the package, and it is also not necessary to excessively require the first heat dissipation surface 43 of the second heat sink 40 to be parallel to the bottom surface of the package. In addition, since the first drain column 41 is inserted into the first limiting hole 3 and the second drain column 42 is inserted into the second limiting hole 32 , the internal stress of the second heat dissipation surface 44 will not cause the second heat dissipation carrier 40 to peel off.

[0078] For a better example, see Figure 1 The connection between the source pad 13 and the source island 21 and the connection between the gate pad 14 and the gate island 22 include welding on the same plane; Figure 1 , the connection between the first drain column 41 and the drain layer 15 and the connection between the second drain column 42 and the drain island 23 include high and low potential difference welding; or refer to Figure 10 , the first drain column 41 is connected to the connection of the drain layer 15 and the second drain column 42 is connected to the connection of the drain island 23. When the height difference of the metal column is welded, the bottom of the column and the bottom of the hole are connected with solder 60. Before the second heat sink 40 is installed, the drain layer 15 of the chip body 10 and the drain island 23 of the first heat sink 20 will not be electrically interconnected. After the second heat sink 40 is installed, the first drain column 41 of the second heat sink 40 is connected to the connection of the drain layer 15 of the chip body 10 and the second drain column 42 of the second heat sink 40 is connected to the drain island 23 of the first heat sink 20. The first heat dissipation surface 43 of the second heat sink 40 does not need to be parallel to the bottom surface of the package, allowing a larger package margin. The longer second drain column 42 can be used as a rough positioning, and the shorter first drain column 41 can be used as a fine positioning. The second heat sink 40 can be accurately positioned on the chip body 10. The first heat dissipation surface 43 of the second heat dissipation carrier 40 can be transformed into the second heat dissipation surface 44 by planarization grinding.

[0079] In a preferred example, referring again to Figure 1 , the encapsulation structure further includes a second encapsulation colloid 50 formed on the first encapsulation colloid 30 to surround and fix the periphery of the second heat dissipation carrier 40. By forming the second encapsulation colloid 50 on the first encapsulation colloid 30, the second heat dissipation carrier 40 in the encapsulation process is transformed from an external heat sink into a built-in heat sink of the finished product. In addition to restricting the movement of the second heat dissipation carrier 40, in a preferred example, the second encapsulation colloid 50 also has the function of adjusting the balance of the thermal expansion coefficients of the upper and lower layers of the encapsulation structure. For example, when the lower part of the encapsulation structure expands more due to heat than the upper part, a material or material with a larger thermal expansion coefficient is selected or formulated for the second encapsulation colloid 50 to achieve the upper and lower thermal expansion balance of the encapsulated product.

[0080] In a preferred example, referring again to Figure 1 , the second encapsulation colloid 50 and the second heat dissipation carrier 40 together provide a flat encapsulation top surface 51 that is parallel to the encapsulation bottom surface provided by the first heat dissipation carrier 20. By using the second encapsulation colloid 50 and the second heat dissipation carrier 40 together to provide a flat encapsulation top surface 51 that is parallel to the encapsulation bottom surface, the first encapsulation colloid 30 is neither part of the encapsulation bottom surface nor part of the encapsulation top surface 51. The first encapsulation colloid 30 has a wider encapsulation margin, and the first encapsulation colloid 30 only needs to be able to encapsulate the chip body 10 and does not bear the requirement of the encapsulation thickness. The thickness of the second heat dissipation carrier 40 on the first encapsulation colloid 30 can be used for readjusting the finished product encapsulation thickness.

[0081] In a preferred example, referring again to Figure 1 , Figure 7 , before the second encapsulation colloid 50 is formed and cured, the second heat dissipation carrier 40 is detachably separable from the first encapsulation colloid 30. By using the second heat dissipation carrier 40 to be detachably separable from the first encapsulation colloid 30, the second heat dissipation carrier 40 can be trimmed or replaced based on the test results as long as it is before the second encapsulation colloid 50 is cured.

[0082] In a preferred example, referring again to Figure 1 , Figure 2, the gate island 22 is located at the corner notch 21A of the source island 21, and the drain island 23 is located at the side 21B of the source island 21 away from the corner notch 21A. By using the gate island 22 located at the corner notch 21A of the source island 21 and the drain island 23 located at the side 21B of the source island 21 away from the corner notch 21A, the gate island 22 and the drain island 23 are separated by the source island 21 in the bottom surface of the package, and the drain island 23 has a larger area than the gate island 22. The electromagnetic field effect of the electron flow flowing to the drain island 23 on the gate island 22 is greatly reduced. In addition, the gate island 22, the drain island 23 and the source island 21 all have at least two sides 21B adjacent to at least two corresponding sides of the four peripheries of the bottom surface of the package, which is beneficial to the stability of each island of the first heat dissipation carrier 20 during the packaging process.

[0083] In a preferred example, the packaging structure is a flip-chip chip scale package (FC-CSP). The second heat dissipation surface 44 of the second heat dissipation carrier 40 is both larger than and covers either the drain layer 15 of the chip body 10 or the source island 21 of the first heat dissipation carrier 20. Preferably, a plurality of the first drain posts 41 and a plurality of the second drain posts 42 are respectively arranged in individual array areas on the inner surface of the second heat dissipation carrier 40, and the length of the second drain posts 42 is greater than the length of the first drain posts 41. More preferably, the array pattern of the first drain posts 41 or / and the second drain posts 42 is defined as the hidden identification code of individual MOSFETs of the chip body 10. By using both the chip body 10 and the second heat dissipation carrier 40 can be flip-chip bonded, the packaging structure of the semiconductor power device obtains the form of a flip-chip chip scale package (FC-CSP) with double-sided heat dissipation under the condition of reduced packaging size. Preferably, by using the partitioned array configuration of a plurality of the first drain posts 41 and a plurality of the second drain posts 42, the longer second drain posts 42 can be used for rough positioning of the installation of the second heat dissipation carrier 40, and the shorter first drain posts 41 can be used for fine positioning of the installation of the second heat dissipation carrier 40, effectively transferring the heat generated by the chip operation to the top surface 51 of the package. More preferably, by using the pattern of the partitioned array configuration of a plurality of the first drain posts 41 and a plurality of the second drain posts 42 as the hidden identification code of individual MOSFETs of the chip body 10, it is used to identify the manufacturing information of the chip body 10. For example, when the sizes of the chip bodies 10 are different, most of the first drain posts 41 can be joined to the drain layer 15 of the chip body 10 to form a parallel conductor column connection, and a small number of the first drain posts 41 will not be joined to the drain layer 15 of the chip body 10. It can be identified from the electron flow distribution which of the first drain posts 41 are empty connections, or it can be determined which of the first limit holes 31 are floating connections before installing the second heat dissipation carrier 40.

[0084] Refer to Figures 4 to 9 and Figure 1, the present invention also provides a manufacturing method for a double-sided heat dissipation MOSFET package structure for manufacturing the double-sided heat dissipation MOSFET package structure that may be combined with any of the above technical solutions. The manufacturing method includes the following steps.

[0085] Refer to Figure 4 , prepare an isolated chip body 10, specifically formed by wafer dicing. The chip body 10 has a processing surface 11 and a corresponding back surface 12. An anode pad 13 and a gate pad 14 are provided on the processing surface 11, and a drain layer 15 is provided on the back surface 12.

[0086] Refer to again Figure 4 , flip the chip body 10 in a flip-chip bonding manner and bond it to the first heat dissipation carrier 20. For example, use solder 60 to conduct the anode pad 13 and the gate pad 14 of the chip body 10 to the anode island 21 and the gate island 22 of the first heat dissipation carrier 20 respectively. The first heat dissipation carrier 20 is a unit in the form of a mother board in this step.

[0087] Refer to Figure 5 , form a first encapsulation colloid 30 on the first heat dissipation carrier 20 in a molding encapsulation manner to seal the chip body 10; the first encapsulation colloid 30 can be flat molding encapsulation, covering a mother board including a plurality of first heat dissipation carriers 20. After or simultaneously, refer to Figure 6 , the first encapsulation colloid 30 is provided with a first limiting hole 31 communicating with the drain layer 15 and a second limiting hole 32 outside the drain layer 15. The second limiting hole 32 communicates with the drain island 23 of the first heat dissipation carrier 20. When the formation of the first limiting hole 31 and the second limiting hole 32 is after the formation of the first encapsulation colloid 30, a mask laser drilling method can be adopted to burn through the plastic sealing material at the part that needs to be through-hole, exposing the chip Drain pole contact hole and the contact hole of the bottom metal substrate. In a preferred example but not limited, in this step, the first encapsulation colloid 30 is pre-cured, and a post-curing process is also performed on the first encapsulation colloid 30, which can be after installing the second heat dissipation carrier 40; or during the process of forming the second encapsulation colloid 50.

[0088] Refer to Figure 7 And Figure 8 , use a flip-chip bonding machine to flip the isolated second heat dissipation carrier 40 and set it on the first encapsulation colloid 30 in a flip-chip bonding manner. The inner surface of the second heat dissipation carrier 40 is provided with a mutually conductive first drain column 41 and a second drain column 42. In a single flip and bonding process (such as Figure 7As shown, the first drain column 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40; at the same time, the second drain column 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20. In the example, solder 60 can be used to complete the connection between the column and the bottom of the hole. Finally, single isolation cutting is performed to fabricate a discrete package structure of a semiconductor power device as shown in Figure 1 the discrete package structure of the semiconductor power device shown.

[0089] The basic principle of the embodiment is as follows: By flipping and singulating the second heat dissipation carrier 40 and arranging it on the first encapsulation colloid 30 in a flip-chip bonding manner, it can share the encapsulation equipment with the flip-chip bonding process of the chip body 10 and does not require a wire bonding process. Moreover, the encapsulation top surface 51 has good heat capacity, which can carry out more heat from the chip, and the encapsulation process is simple and does not require investment in special equipment. During the encapsulation process, the processing surface 11 (front surface) of the chip body 10 will not be pressed to cause internal stress. There is no need to fabricate a silicon via structure inside the chip body 10, and the effective working area of the transistors inside the chip body 10 can be effectively enlarged.

[0090] In a preferred example, referring again to Figure 4 , during the process of installing the chip body 10, the connection of the source pad 13 to the source island 21 and the connection of the gate pad 14 to the gate island 22 include coplanar soldering; referring again to Figure 7 and Figure 8 , during the process of installing the second heat dissipation carrier 40, the connection of the first drain column 41 to the drain layer 15 and the connection of the second drain column 42 to the drain island 23 include soldering with a height difference.

[0091] In a preferred example, referring to Figure 9 , after flipping and bonding the second heat dissipation carrier 40, it further includes: forming a second encapsulation colloid 50 on the first encapsulation colloid 30 to surround and fix the periphery of the second heat dissipation carrier 40; before the second encapsulation colloid 50 is formed and cured, the second heat dissipation carrier 40 is detachable and separable relative to the first encapsulation colloid 30. The material of the second encapsulation colloid 50 may include thermosetting epoxy resin.

[0092] In a preferred example, referring again to Figure 1 , after forming the second encapsulation colloid 50, it further includes: planarizing and grinding the second encapsulation colloid 50 and the second heat dissipation carrier 40 to jointly provide a flush encapsulation top surface 51 that is parallel to the encapsulation bottom surface provided by the first heat dissipation carrier 20.

[0093] In a preferred example, after the second encapsulation colloid 50 is formed, it further includes: encapsulation isolation cutting to make the encapsulation structure into a flip-chip chip scale package (FC-CSP), and the second heat dissipation surface 44 of the second heat dissipation carrier 40 is both larger than and covers either the drain layer 15 of the chip body 10 or the source island 21 of the first heat dissipation carrier 20.

[0094] Figure 10 The cross-sectional schematic diagram of a double-sided heat dissipation MOSFET encapsulation structure showing some other preferred embodiments of the present invention. A double-sided heat dissipation MOSFET encapsulation structure includes: a chip body 10, a first heat dissipation carrier 20 located below the chip body 10, a first encapsulation colloid 30 sealing the chip body 10, and a second heat dissipation carrier 40 disposed on the first encapsulation colloid 30.

[0095] Refer to Figure 10 , the chip body 10 has a processing surface 11 and an opposite back surface 12. An anode pad 13 and a gate pad 14 are disposed on the processing surface 11, and a drain layer 15 is disposed on the back surface 12. The first heat dissipation carrier 20 is for the flip and bonding of the chip body 10 in a flip-chip bonding manner, and the anode pad 13 and the gate pad 14 of the chip body 10 are respectively electrically connected to the source island 21 and the gate island 22 of the first heat dissipation carrier 20. The first encapsulation colloid 30 is formed on the first heat dissipation carrier 20 to seal the chip body 10; the first encapsulation colloid 30 is provided with a first limiting hole 31 communicating with the drain layer 15 and a second limiting hole 32 outside the drain layer 15, and the second limiting hole 32 communicates with the drain island 23 of the first heat dissipation carrier 20. The second heat dissipation carrier 40 is disposed on the first encapsulation colloid 30 in a flip-chip bonding manner. The inner surface of the second heat dissipation carrier 40 is provided with a first drain column 41 and a second drain column 42 that are electrically connected to each other. The inner surface of the second heat dissipation carrier 40 is turned towards the first encapsulation colloid 30. The first drain column 41 is inserted into the first limiting hole 31 to electrically connect the drain layer 15 and the second heat dissipation carrier 40; and the second drain column 42 is inserted into the second limiting hole 32 to electrically connect the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20, and the second heat dissipation surface 44 of the second heat dissipation carrier 40 is parallel to the encapsulation bottom surface.

[0096] As Figure 10 shown in the embodiment and as Figure 1The difference between the two embodiments shown is that the connection of the first drain column 41 to the drain layer 15 and the connection of the second drain column 42 to the drain island 23 adopt a tight fit of metal column insertion. A metal covering layer 70 is formed on the upper surface of the first encapsulation colloid 30 and the inner side walls and bottom of the first limiting hole 31 and the second limiting hole 32. Before installing the second heat dissipation carrier 40, the drain layer 15 of the chip body 10 is electrically interconnected with the drain island 23 of the first heat dissipation carrier 20 in advance. By using the tight fit of metal column insertion, the first heat dissipation surface 43 of the second heat dissipation carrier 40 does not need to be parallel to the encapsulation bottom surface, allowing a larger encapsulation margin. When the tight fit of metal column insertion is adopted and the metal covering layer 70 is used to electrically interconnect the drain layer 15 of the chip body 10 and the drain island 23 of the first heat dissipation carrier 20 in advance before installing the second heat dissipation carrier 40, the second drain column 42 can be used for rough positioning, the first drain column 41 can be used for fine positioning, and the second heat dissipation carrier 40 can be accurately positioned on the chip body 10. As long as the first drain column 41 is inserted into the hole wall of the first limiting hole 31, even if it does not press against the bottom of the first limiting hole 31, the electrical connection between the second heat dissipation carrier 40 and the drain layer 15 of the chip body 10 can be achieved.

[0097] In the encapsulation structure in the example of the present invention, the introduced resistance in the DFN5*6 encapsulation architecture can be reduced to less than 0.1 mΩ, while the encapsulation resistance of traditional wire bonding is usually above 0.3 mR. Based on the utilization of the second heat dissipation carrier 40, the high-current capacity of the device is greatly improved, which can be increased by more than 20% compared with the traditional encapsulation of the same chip.

[0098] Refer to Figure 11 and Figure 12 , in the example of the present invention, a manufacturing method of the aforementioned double-sided heat dissipation MOSFET encapsulation structure is also proposed. The pre-included steps can be as shown in Figures 4 to 6 until the first limiting hole 31 and the second limiting hole 32 are formed on the upper surface of the first encapsulation colloid 30; the post-included steps can be as shown in Figure 11 and Figure 12 .

[0099] In a preferred example, refer to Figure 11 , a metal covering layer 70 is formed on the upper surface of the first encapsulation colloid 30 and the inner side walls and bottom of the first limiting hole 31 and the second limiting hole 32 by means of metal precipitation. Then, refer to Figure 12 , use a flip-chip bonding machine to flip the isolated second heat dissipation carrier 40 and set it on the first encapsulation colloid 30 with a formed metal covering layer 70 in a flip-chip bonding manner. The inner surface of the second heat dissipation carrier 40 is provided with a first drain column 41 and a second drain column 42 that are electrically connected to each other. In a single flipping and bonding process (cooperate with reference toFigure 10 ), the first drain column 41 is inserted into the first limiting hole 31 to conduct the drain layer 15 and the second heat dissipation carrier 40; meanwhile, the second drain column 42 is inserted into the second limiting hole 32 to conduct the second heat dissipation carrier 40 and the drain island 23 of the first heat dissipation carrier 20. In a variant example, solder can be used to complete the connection between the column and the bottom of the hole. Finally, encapsulation and singulation cutting are performed to form an encapsulation structure as shown in Figure 10 .

[0100] In other examples of the present invention, an electronic device is further proposed. With reference to Figure 1 or Figure 10 , it includes: a printed circuit board (not shown in the figure) and a double-sided heat dissipation MOSFET encapsulation structure as described above and combined in any possible combination on the printed circuit board. The source island 21, the gate island 22, and the drain island 23 on the encapsulation bottom surface of the double-sided heat dissipation MOSFET encapsulation structure are bonded to the printed circuit board with solder, and the second heat dissipation carrier 40 is exposed on the encapsulation top surface 51 of the double-sided heat dissipation MOSFET encapsulation structure. The electronic device can transfer the heat of the MOSFET encapsulation structure more quickly. The second heat dissipation carrier 40 not only serves as an intermediate connection for the drain but also as heat dissipation for the encapsulation top surface 51.

[0101] The embodiments of this specific implementation manner are all preferred embodiments for conveniently understanding or implementing the technical solutions of the present invention, and do not limit the protection scope of the present invention accordingly. Any equivalent changes made according to the structure, shape, and principle of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A MOSFET packaging structure with double-sided heat dissipation, characterized in that, Comprising: A chip body having a processing surface and an opposite back surface, with a source pad and a gate pad provided on the processing surface, and a drain layer provided on the back surface; A first heat dissipation carrier for flipping and bonding the chip body in a flip-chip bonding manner, and the source pad and the gate pad of the chip body are respectively electrically connected to a source island and a gate island of the first heat dissipation carrier; A first encapsulation colloid formed on the first heat dissipation carrier to seal the chip body; the first encapsulation colloid is provided with a first limiting hole communicating with the drain layer and a second limiting hole outside the drain layer, and the second limiting hole communicates with a drain island of the first heat dissipation carrier; A second heat dissipation carrier disposed on the first encapsulation colloid in a flip-chip bonding manner, and a first drain pillar and a second drain pillar that are electrically connected to each other are provided on the inner surface of the second heat dissipation carrier. The inner surface of the second heat dissipation carrier is flipped towards the first encapsulation colloid. The first drain pillar is inserted into the first limiting hole to electrically connect the drain layer and the second heat dissipation carrier; and the second drain pillar is inserted into the second limiting hole to electrically connect the second heat dissipation carrier and the drain island of the first heat dissipation carrier. The second heat dissipation surface of the second heat dissipation carrier is parallel to the encapsulation bottom surface, and the connection between the solder finish column and the bottom of the hole is completed; the second heat dissipation carrier can be used as an external heat sink during the packaging and testing process and can also be used as an internal heat sink of the packaged structure finished product; Wherein, the lengths of the first drain pillar and the second drain pillar are different, the length of the second drain pillar is greater than the length of the first drain pillar, and the first drain pillar and the second drain pillar are respectively arranged in individual array regions on the inner surface of the second heat dissipation carrier to form a hidden identification code of the chip body; A small part of the first drain pillars are not connected to the drain layer of the chip body, and the unconnected first drain pillars are identified by the electron flow distribution, or it is determined which of the first limiting holes are floating connections before installing the second heat dissipation carrier.

2. The MOSFET packaging structure with double-sided heat dissipation according to claim 1, characterized in that The connection of the source pad to the source island and the connection of the gate pad to the gate island include coplanar soldering; the connection of the first drain pillar to the drain layer and the connection of the second drain pillar to the drain island include soldering with a height difference or a tight fit of metal pillar insertion; when using a tight fit of metal pillar insertion, a metal covering layer is formed on the upper surface of the first encapsulation colloid and on the inner side walls and the bottom of the first limiting hole and the second limiting hole, and the drain layer of the chip body and the drain island of the first heat dissipation carrier are electrically interconnected in advance before installing the second heat dissipation carrier.

3. The MOSFET packaging structure with double-sided heat dissipation according to claim 1, characterized in that, Further comprising: A second encapsulation colloid formed on the first encapsulation colloid to surround and fix the periphery of the second heat dissipation carrier.

4. The MOSFET package structure with double-sided heat dissipation according to claim 3, characterized in that, A flat encapsulation top surface is jointly provided by the second encapsulation colloid and the second heat dissipation carrier, and is parallel to the encapsulation bottom surface provided by the first heat dissipation carrier.

5. The MOSFET package structure with double-sided heat dissipation according to claim 3, characterized in that Before the second encapsulation colloid is formed and cured, the second heat dissipation carrier is detachable and separable relative to the first encapsulation colloid.

6. The MOSFET package structure with double-sided heat dissipation according to claim 1, characterized in that, The gate island is located at the corner notch of the source island, and the drain island is located at the side of the source island away from the corner notch.

7. The MOSFET package structure with double-sided heat dissipation according to any one of claims 1-6, characterized in that, The packaging structure is a flip-chip chip scale package (FC-CSP). The second heat dissipation surface of the second heat dissipation carrier is both larger than and covers either the drain layer of the chip body or the source island of the first heat dissipation carrier. The array patterns of the first drain pillar and the second drain pillar are defined as the hidden identification codes of individual MOSFETs of the chip body.

8. A manufacturing method of a MOSFET package structure with double-sided heat dissipation, characterized in that, Comprising: Preparing an isolated chip body, the chip body having a processing surface and a corresponding back surface, a source pad and a gate pad being provided on the processing surface, and a drain layer being provided on the back surface; Flipping the chip body in a flip-chip bonding manner and bonding it to the first heat dissipation carrier, so that the source pad and the gate pad of the chip body are respectively conducted to the source island and the gate island of the first heat dissipation carrier; Forming a first encapsulation colloid on the first heat dissipation carrier to seal the chip body; A first limiting hole communicating with the drain layer and a second limiting hole outside the drain layer are opened on the first encapsulation colloid, and the second limiting hole communicates with the drain island of the first heat dissipation carrier; Flipping the isolated second heat dissipation carrier and arranging it on the first encapsulation colloid in a flip-chip bonding manner. The inner surface of the second heat dissipation carrier is provided with a first drain pillar and a second drain pillar that are mutually conducted. In one flipping and bonding process, the first drain pillar is inserted into the first limiting hole to conduct the drain layer and the second heat dissipation carrier. At the same time, the second drain pillar is inserted into the second limiting hole to conduct the second heat dissipation carrier and the drain island of the first heat dissipation carrier, and the connection between the pillar and the bottom of the hole is completed with solder; Wherein, the lengths of the first drain pillar and the second drain pillar are different, the length of the second drain pillar is greater than the length of the first drain pillar, and the first drain pillar and the second drain pillar are respectively arranged in individual array areas on the inner surface of the second heat dissipation carrier to form the hidden identification code of the chip body; A small part of the first drain pillars are not bonded to the drain layer of the chip body, and the empty-connected first drain pillars are identified by the electron flow distribution, or it is determined which of the first limiting holes are floating-connected before installing the second heat dissipation carrier.

9. The manufacturing method of the double-sided heat dissipation MOSFET packaging structure according to claim 8, characterized in that: During the process of installing the chip body, the connection of the source pad to the source island and the connection of the gate pad to the gate island include coplanar soldering; during the process of installing the second heat sink carrier, the connection of the first drain pillar to the drain layer and the connection of the second drain pillar to the drain island include soldering with a height difference or a tight fit of metal pillar insertion; when using a tight fit of metal pillar insertion, a metal covering layer is formed on the upper surface of the first encapsulation colloid and the inner sidewalls and bottom of the first limiting hole and the second limiting hole, and the drain layer of the chip body is electrically interconnected with the drain island of the first heat sink carrier in advance before installing the second heat sink carrier; After forming the first encapsulation colloid, the gate island is located at the corner notch of the source island, and the drain island is located on the side of the source island away from the corner notch; After flipping and bonding the second heat sink carrier, it further includes: forming a second encapsulation colloid on the first encapsulation colloid to surround and fix the periphery of the second heat sink carrier; Before the second encapsulation colloid is formed and solidified, the second heat sink carrier is detachable and separable relative to the first encapsulation colloid; After forming the second encapsulation colloid, it further includes: planarizing and grinding the second encapsulation colloid and the second heat sink carrier to jointly provide a flush encapsulation top surface by the second encapsulation colloid and the second heat sink carrier, which is parallel to the encapsulation bottom surface provided by the first heat sink carrier; After forming the second encapsulation colloid, it further includes: encapsulation singulation cutting to make the encapsulation structure into a flip chip chip scale package (FC-CSP), and the second heat dissipation surface of the second heat sink carrier is both larger than and covers either the drain layer of the chip body or the source island of the first heat sink carrier.

10. An electronic device, characterized in that, Including: A printed circuit board and a double-sided heat dissipation MOSFET encapsulation structure as described in any one of claims 1-7 bonded to the printed circuit board, wherein the source island, the gate island and the drain island located on the encapsulation bottom surface of the double-sided heat dissipation MOSFET encapsulation structure are bonded to the printed circuit board with solder, and the second heat sink carrier is exposed on the encapsulation top surface of the double-sided heat dissipation MOSFET encapsulation structure.

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