An implementation method and system for L1 cache load miss

Abstract

This invention relates to the field of program control technology, specifically to an implementation method and system for L1 cache load miss, including a load queue module, a pipeline module, a miss queue module, and a refill module. This invention reduces the number of times a load instruction occupies the pipeline; specifically, it reduces the amount of pipeline resources occupied by invalid pipelines, allocating limited pipeline resources to more needed instructions, effectively improving the overall performance of L1 cache while also reducing power consumption. After the reloaded data from a load miss returns, it is not immediately put into the pipeline, but rather given a time window for the load miss instruction to refill the bypass data in the buffer. This ensures that the load miss instruction can return the loaded data as quickly as possible, and also ensures that the reloaded data is written to L1 cache at a relatively fast speed, greatly improving the overall performance of the CPU and reducing operations on D_cache, further reducing power consumption.

Description

Technical Field

[0001] This invention relates to the field of program control technology, specifically to a method and system for implementing L1cache load miss. Background Technology

[0002] (1) Load miss occurs when the required data cannot be loaded on the pipeline many times, but the pipeline is still put on repeatedly. This results in many invalid pipelines being put on, while some valid pipelines do not get pipeline resources. At the same time, too many invalid pipelines lead to high power consumption.

[0003] (2) Since many invalid pipelines will inevitably read D_cache, resulting in wasted power consumption.

[0004] (3) Due to too many invalid pipelines, after the refill data is returned, the load instruction that was just missed may not be able to be loaded onto the pipeline, resulting in the data not being loaded back immediately. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses an implementation method and system for L1 cache load miss, which reduces the number of times a certain load instruction occupies the pipeline. Specifically, it reduces the number of invalid pipelines occupying pipeline resources, allocates limited pipeline resources to instructions that need them more, effectively improves the overall performance of L1 cache, and also reduces power consumption; it also reduces operations on D cache, and load data is written to the target register as quickly as possible, which greatly improves the overall performance of the CPU.

[0006] This invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention discloses a method for implementing L1cache load miss, comprising the following steps:

[0008] S1 receives the upstream LOAD instruction and saves it to the load queue; then selects a request to participate in the arbiter arbitration.

[0009] If S2 determines that it has won the arbitration, then the pipeline checks if there is forward data that satisfies the load condition.

[0010] S3 checks if the condition is met and returns the load data; otherwise, it checks D_cache. If D_cache is hit, it returns the load data.

[0011] If S4 detects that there is no loaded data in forward and D_cache, it will request an entry from the miss queue.

[0012] S5 sends a reload request to L2 through the miss queue entry. L2 returns the reload data and wakes up the load miss instruction in the load queue at the same time.

[0013] S6 obtains the data required by the load in the refill buf forwrad, and outputs the target and deallocated load queue at the same time.

[0014] S7 then pipelines refilled data, writing the reloaded data into D_cache.

[0015] Furthermore, in the method, when L2 returns the reload data, it wakes up the load miss instruction in the load queue. Since the load instruction that is woken up by the reload has a relatively high priority in both the load queue and the arbitration, it has a higher probability of being selected.

[0016] Furthermore, in the method, when the selected load instruction is loaded onto the pipeline, since the previously missed data has already been reloaded and returned, when this instruction is loaded onto the pipeline again, the data required for the load can be obtained from the refill buffer, and the target and deallocated load queue are output.

[0017] Furthermore, in the method, after a load instruction is loaded onto the pipeline, a miss is determined and a miss queue is allocated. Then, the instruction is no longer loaded onto the pipeline. After the reload data returns, the refill module wakes up the load queue and loads the instruction onto the pipeline again, bypassing the required load result directly from the refill data.

[0018] Furthermore, in the method, the loads awakened by refill are selected with higher priority from the load queue, so that the loads awakened by refill can be put into the pipeline as soon as possible.

[0019] Furthermore, in the method, after receiving the reload data, the Refill buffer sends a load miss instruction back to the pipeline for a time window to refill the bypass data in the buffer, and then back to the pipeline.

[0020] In a second aspect, the present invention discloses an implementation system for L1cache load miss, the system being used to execute the L1cache load miss implementation method described in the first aspect, characterized in that it includes a load queue module, a pipeline module, a miss queue module, and a refill module.

[0021] Furthermore, the load queue module is used to select a load instruction from the load queue to be put on the pipeline; when a load miss occurs during the first pipeline entry, the pipeline allocates an entry to the missq queue and blocks the load instruction, preventing it from being put on the pipeline again, until the reload data returns, at which point the refil module wakes up the load instruction to be put on the pipeline again.

[0022] Furthermore, the pipeline module is responsible for data access after the instruction pipeline. If a new missq requests the allocation of an entry item, and if the loaded data is obtained, the data is returned to the target.

[0023] The miss queue module is responsible for sending a reload request to l2 after a D_cache miss;

[0024] The refill module is responsible for receiving data returned from L2, waking up the instruction that just failed to load and reloading it onto the pipeline, and then forwarding the data from the refill buffer to the pipeline.

[0025] The beneficial effects of this invention are as follows:

[0026] This invention reduces the number of times a load instruction occupies the pipeline. Specifically, it reduces the number of invalid pipelines occupying pipeline resources, allowing limited pipeline resources to be allocated to more needed instructions, effectively improving the overall performance of L1 cache and reducing power consumption. After a load miss, the reloaded data is not immediately put into the pipeline, but is given a time window for the load miss instruction to refill the bypass data in the buffer. This ensures that the load miss instruction can return the loaded data as quickly as possible, and also ensures that the reloaded data is written to L1 cache at a relatively fast speed, which greatly improves the overall performance of the CPU and reduces operations on D cache, further reducing power consumption. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a block diagram illustrating the implementation principle of an L1 cache load miss system.

[0029] Figure 2 This is a flowchart illustrating an implementation method for L1 cache load misses;

[0030] Figure 3 It is a timing diagram of the pipeline being restarted after the load miss instruction is woken up in the refill buffer. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Example 1

[0033] This embodiment discloses as follows: Figure 1The system shown is an implementation system for L1cache load miss, used to execute the implementation method of L1cache load miss, including a load queue module, a pipeline module, a miss queue module, and a refill module.

[0034] In this embodiment, the load queue module works as follows: (1) A load instruction is selected from the load queue and put on the pipeline. (2) When it is put on the pipeline for the first time, a load miss occurs. The pipeline allocates an entry to the missq queue and blocks the load instruction, preventing it from being put on the pipeline again. After the reload data is returned, the refil module wakes up the load instruction and puts it on the pipeline again.

[0035] In this embodiment, the pipeline module is responsible for accessing data after the instruction is piped. If a new missq requests the allocation of an entry item, and if the loaded data is obtained, the data is returned to the target.

[0036] In this embodiment, the miss queue module is responsible for sending a reload request to l2 after a D_cache miss.

[0037] In this embodiment, the refill module is responsible for receiving data returned from L2, waking up the instruction that just failed to load the miss and reloading it onto the pipeline, and then forwarding the data from the refill buffer to the pipeline.

[0038] Example 2

[0039] This embodiment discloses a method for implementing L1cache load miss, including the following steps:

[0040] S1 receives the upstream LOAD instruction and saves it to the load queue; then selects a request to participate in the arbiter arbitration.

[0041] If S2 determines that it has won the arbitration, then the pipeline checks if there is forward data that satisfies the load condition.

[0042] S3 checks if the condition is met and returns the load data; otherwise, it checks D_cache. If D_cache is hit, it returns the load data.

[0043] If S4 detects that there is no loaded data in forward and D_cache, it will request an entry from the miss queue.

[0044] S5 sends a reload request to L2 through the miss queue entry. L2 returns the reload data and wakes up the load miss instruction in the load queue at the same time.

[0045] S6 obtains the data required by the load in the refill buf forwrad, and outputs the target and deallocated load queue at the same time.

[0046] S7 then pipelines refilled data, writing the reloaded data into D_cache.

[0047] In this embodiment, if a load instruction is found to be missing after being uploaded to the pipeline, a miss queue is allocated, and it will not be uploaded to the pipeline again. Instead, it will wait for the reload data to return, at which point the refill module will wake up the load queue and re-upload the instruction to the pipeline, bypassing the required results from the refill data.

[0048] In this embodiment, since the load is woken up and re-enters the pipeline, it does not need to read D_cache and tag information, thus effectively reducing power consumption.

[0049] In this embodiment, the loads that are awakened by refill are selected from the load queue with a higher priority, so that the loads awakened by refill can be put into the pipeline as soon as possible.

[0050] In this embodiment, after receiving reload data, the refill buffer does not immediately put the refill on the pipeline. Instead, it puts the load miss instruction on the pipeline again to refill the bypass data in the buffer for a time window before putting it on the pipeline.

[0051] Example 3

[0052] This embodiment discloses as follows: Figure 2 The flowchart shown for the load instruction includes a detailed process:

[0053] (1) The LOAD instruction sent from upstream will first be saved to the load queue.

[0054] (2) Select a request from the load queue to participate in the arbiter arbitration. If the arbiter wins the arbitration, the request will be added to the pipeline.

[0055] (3) After uploading the pipeline

[0056] Check if there is forward data that satisfies the load condition. If so, return the load data directly. The load queue entry item is then deallocated.

[0057] If no forward data matching the load condition is detected, the D_cache will be checked. If the D_cache hits, the load data will be returned directly, and the load queue entry will be deallocated.

[0058] (4) If the loaded data cannot be obtained from either forward or D_cache, an entry will be requested from the miss queue.

[0059] (5) The missing queue entry sends a reload request to L2.

[0060] (6) When L2 returns reload data, it wakes up the load miss instruction in the load queue. Since the load instruction woken up by reload has a relatively high priority in the load queue and arbitration, it is highly likely to be selected.

[0061] (7) When the selected load instruction is added to the pipeline, since the previously missed data has already been reloaded, when this instruction is added to the pipeline again, the data required for the load can be forwarded in the refill buffer. At the same time, the target and deallocated load queue are output.

[0062] (8) The refill data is then piped up and written into D_cache.

[0063] Example 4

[0064] This embodiment discloses as follows: Figure 3 The refill buffer shown provides the timing for re-entering the pipeline after a load miss instruction is triggered.

[0065] Cycle 2: L2 receives reloaded data, l2_c_vld = 1 l2_c_data

[0066] cycle3: Load miss instruction is activated

[0067] cycle4: Load miss instruction onto pipeline, DC0 stage

[0068] Cycle 6: In DC2 stage load instructions, the data is forwarded from refill.

[0069] As long as we ensure that the load can forward data from the refill buffer in cycle 6, and that the refill does not start on the pipeline simultaneously with the load, then the pipeline can start in the next cycle after a load miss instruction. That is, the refill can start on the pipeline in cycle 5.

[0070] cycle 5: Refill the pipeline

[0071] cycle8: Write the refill data to D_cache and deallocate the entry items in the refill.

[0072] The alternative to the present invention is:

[0073] (1) After a load miss, the pipeline is repeatedly loaded, resulting in many invalid pipelines.

[0074] (2) Refills are loaded onto the pipeline first, while load misses are loaded onto the pipeline later, resulting in an extra read of D_cache / tag.

[0075] In summary, this invention reduces the number of times a load instruction occupies the pipeline. Specifically, it reduces the amount of pipeline resources wasted by invalid pipelines, allowing limited pipeline resources to be allocated to more needed instructions, effectively improving the overall performance of the L1 cache while also reducing power consumption.

[0076] Invalid pipeline of this invention: If a pipeline is added, it is certain that no result will be obtained.

[0077] In this invention, after the reloaded data from a load miss returns, it is not immediately put into the pipeline. Instead, a time window is provided for the load miss instruction to refill the bypass data in the buffer. This ensures that the load miss instruction can return the loaded data as quickly as possible, while also ensuring that the reloaded data is written to the L1 cache at a relatively fast speed. This greatly improves the overall performance of the CPU and reduces the operation on the D cache, further reducing power consumption.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing an Ll cache load miss, comprising: The method comprises the following steps: S1 receiving an upstream load instruction and saving it into a load queue; and selecting a load instruction to participate in arbiter arbitration; S2 judging whether the arbitration is won, and then the load instruction is sent to the pipeline to detect whether there is forward data meeting the load instruction; S3 if the data meeting the load instruction is found, the load data is returned; otherwise, the D_cache is checked, and if the D_cache is hit, the load data is returned; S4 detecting the forward and D_cache data without the load data, and requesting to allocate an entry in the miss queue; S5 sending a reload request to the L2 through the miss queue entry, and returning the reload data by the L2 to wake up the load miss instruction in the load queue; S6 obtaining the load data in the refill buf, and outputting the target and the deallocated load queue; S7 sending the subsequent refill data to the pipeline, and writing the reload data into the D_cache.

2. The method of claim 1, wherein the L1 cache load miss is implemented by: In the method, the load miss instruction in the load queue is woken up by the reload data returned by the L2, and the load instruction woken up by the reload has a relatively high priority in the load queue and the arbitration, so that the load instruction has a relatively high probability of being selected.

3. The method of claim 1, wherein the Ll cache load miss is implemented by: In the method, the selected load instruction is sent to the pipeline, and the data required by the load instruction is obtained in the refill buf, and the target and the deallocated load queue are outputted.

4. The method of claim 1, wherein the L1 cache load miss is implemented by: In the method, after a load instruction is sent to the pipeline, the load instruction is determined to be missed, and the miss queue is allocated, and the load instruction is not sent to the pipeline again, and the load queue is woken up by the refill module after the reload data is returned, and the load instruction is sent to the pipeline again, and the result required by the load instruction is directly bypassed from the refill data.

5. The method of claim 1, wherein the L1 cache load miss is implemented by: In the method, the priority of the load instruction woken up by the refill in the load queue is relatively high, so that the load instruction woken up by the refill can be sent to the pipeline in the first time.

6. The method of claim 1, wherein the L1 cache load miss is implemented by: In the method, the refill buf receives the reload data, and the load miss instruction is sent to the pipeline again In the method, the refill buf receives the reload data, and the load miss instruction is sent to the pipeline again In the method, the refill buf receives the reload data, and the load miss instruction is sent to the pipeline again 7. A system for implementing an Ll cache load miss, the system being configured to perform the method for implementing an Ll cache load miss according to any one of claims 1-6, wherein, The load queue module, the pipeline module, the miss queue module and the refill module are included.

8. The system for implementing Ll cache load miss according to claim 7, wherein, The load queue module is used for a load instruction to be selected in the load queue to be pipelined for the first time, a load miss to occur, an entry item of the miss queue to be allocated by the pipeline, the load instruction to be blocked and unable to be pipelined again until data of the load instruction is returned, and the load instruction to be awakened by the refill module to be re-pipelined.

9. The system for implementing Ll cache load miss according to claim 7, wherein, The pipeline module is responsible for data access after instruction pipelining, and if a miss occurs, an entry item of the miss queue is requested to be allocated, and if data of the load is obtained, the data is returned to a target; the miss queue module is responsible for completing a reload request to L2 after D_cache miss; and the refill module is responsible for receiving data returned by L2, awakening an instruction just load missed, re-pipelining, and forwarding data of a refill buf to the pipeline.

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