Apparatus and method for self-test mode suspend circuit

Abstract

The present invention relates to apparatus, systems and methods for a self-test mode abort circuit. A memory device may enter a self-test mode and perform a test operation on the memory array. During the self-test mode, the memory device may ignore external communications. The memory includes an abort circuit that may terminate the self-test mode if the self-test mode cannot be properly terminated. For example, the abort circuit may count the amount of time since the start of the self-test mode and terminate the self-test mode if the amount of time reaches or exceeds a threshold, which may be based on an expected amount of time required to complete the test operation.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, such as semiconductor memory devices. Background Art

[0002] Semiconductor devices may include various circuits and may generally receive instructions loaded from outside the semiconductor device. These instructions may be loaded into a self-test circuit, which may execute the instructions to execute a command sequence on the semiconductor device.

[0003] The self-test circuitry may execute instructions to perform one or more test operations while the device is in the self-test mode. During the self-test mode, to prevent interference, the device may ignore other data and / or commands received by the device. It may be useful to ensure that the self-test mode terminates correctly in order to prevent the device from ignoring external communications indefinitely. Summary of the invention

[0004] In one aspect, the present invention relates to an apparatus comprising: a command / address circuit configured to provide a self-test enable signal at an active level during a self-test mode; a clock circuit configured to provide a self-test clock signal; a self-test circuit configured to perform a test operation on a memory array in response to the self-test enable signal at an active level; and an abort circuit configured to change a count value in response to the self-test clock and to provide an abort signal when the count value matches or exceeds a threshold, wherein the command / address circuit is configured to stop providing the self-test enable signal at the active level in response to the abort signal.

[0005] On the other hand, the present invention relates to a method comprising: entering a self-test mode of a memory device and activating a self-test enable signal; counting the number of times a test clock is provided during the self-test mode; and ending the first test mode in response to the count value reaching or exceeding a threshold.

[0006] In another aspect, the present invention relates to an apparatus comprising: a memory array; and an interface die configured to enter a self-test mode and perform at least one test operation on the memory array, wherein the interface die is configured to exit the self-test mode after entering the self-test mode for a first amount of time, provided that the self-test mode has not ended before the first amount of time has elapsed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-section of a system-in-package (SiP) device according to some embodiments of the present invention.

[0008] Figure 2 is a block diagram of a memory device according to an embodiment of the present invention.

[0009] Figure 3 is a block diagram of a test and abort circuit according to some embodiments of the present invention.

[0010] Figure 4 is a timing diagram of signals during a test operation in which a test end signal is properly provided according to some embodiments of the present invention.

[0011] Figure 5 is a timing diagram of signals during a test operation in which a test end signal is not properly provided according to some embodiments of the present invention.

[0012] Figure 6 is a flow chart of a method of aborting a test operation according to some embodiments of the present invention. DETAILED DESCRIPTION

[0013] The following description of certain embodiments is essentially only exemplary, and it is not intended to limit the scope of the invention or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are shown by means of illustrative specific embodiments in which the description system and method can be practiced therein. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments can be utilized and structural and logical changes can be made without departing from the spirit and scope of the present invention. In addition, for the purpose of clarity, the detailed description of certain features will not be discussed when it is obvious to those skilled in the art, so as not to obscure the description of the embodiments of the present invention. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present invention is limited only by the appended claims.

[0014] A memory device includes a number (usually a large number) of memory cells arranged at the intersection of word lines (rows) and bit lines (columns) in a memory array. The memory device may also include a built-in self-test (BIST) circuit that can be used to check the operation of one or more of the memory cells in the memory array. The BIST circuit may be preloaded with instructions for test operations, which may be executed as part of a self-test mode. In an example test operation, the BIST may write test data to one or more memory cells, and then read the test data back from the memory cells. The BIST may compare the read test data with the original data written to the cell, and generate a result based on the comparison (e.g., reporting an error if the read test data does not match the written test data).

[0015] During the self-test mode, the BIST circuit may typically perform a large number of individual test operations (e.g., a large number of sequential read and write operations). To prevent interference with the test operations, the memory may ignore external communications during the self-test mode. For example, when the internal self-test enable signal is valid, the memory device may ignore commands and / or data received at the external terminals of the memory device. During the normal self-test mode, the BIST may perform test operations based on instructions loaded in the BIST circuit, and once the final instruction is completed, a self-test end signal indicating that the test operation has been completed may be provided. The self-test end signal may cause the BIST enable signal to be deactivated, thereby indicating that the self-test mode has ended and external communications are allowed again. However, some errors may cause one or more failures in the normal operation of the self-test mode, which may cause the memory device to 'hang' or 'lock', which may prevent the memory device from completing the final test operation or providing a self-test end signal. Since the device will continue to ignore external commands in this state, it may be useful to have an independent method for terminating the self-test mode in an error situation.

[0016] The present invention relates to an apparatus, system and method for a self-test mode abort circuit. When a memory device enters a self-test mode, it may generate an internal BIST enable signal. When the BIST enable signal is valid, the BIST circuit may start a test operation. The memory may also include an abort circuit independent of the BIST circuit. The abort circuit may determine whether the self-test mode has failed to terminate correctly, and may provide an abort signal, which may cause the device to deactivate the BIST enable signal, thereby ending the self-test mode and allowing external communications. For example, the abort circuit may count the amount of time (e.g., the number of clock cycles) since the start of the self-test, and once the amount of time reaches a threshold (which is longer than the expected test operation length during the normal self-test mode), the abort signal may be sent.

[0017] Figure 1 1 is a cross-section of a system-in-package (SiP) device according to some embodiments of the present invention. SiP device 100 includes a memory device 102 and a processor 110, which are packaged on a package substrate 114 together with an interposer 112. Memory device 102 may include a self-test circuit, such as a BIST circuit, for performing a test of memory device 102.

[0018] Figure 1 The memory device 102 shown in the example of can be a high bandwidth memory (HBM) device, which includes an interface die (or logic die) 104 and one or more memory core dies 106 stacked on the interface die 104. The memory device 102 includes one or more through silicon vias (TSVs) 108 for coupling the interface die 104 and the core die 106. The processor 110 can serve as a host device of the SiP 100.

[0019] Both the processor 110 and the memory device 102 are coupled to the interposer 112 through a number of microbumps 111. Channels 105 through the interposer 112 may couple some of the microbumps 111 coupled to the processor 110 to corresponding ones of the microbumps 111 coupled to the memory device 102 to form an interface between the memory device 102 and the processor 110. The interposer 112 may be coupled to the package substrate through one or more bumps, such as C4 bumps 113. The package substrate 114 includes bumps 115, some of which are coupled to the processor 110 and some of which are coupled to the memory device 102. Direct access (DA) bumps 116 are coupled to the interface die 104 through the package substrate 114 and the interposer 112.

[0020] Direct access bumps 116 (e.g., portions of bumps 115 coupled to interface die 104) may be organized into probe pads. In some embodiments, an external device such as a tester may be coupled to the probe pads to send and receive signals related to test operations to and from memory device 102 without the need to pass to processor 110. The tester may provide one or more instructions to the self-test circuitry of memory device 102. In some embodiments, the tester may be coupled to processor 110, which may pass the instructions to the self-test circuitry. In some embodiments, processor 110 may generate the instructions and load them into memory device 102.

[0021] Although a particular layout of memory device 102 is described herein (e.g., with interface die 104 and multiple stacked die 106), it should be understood that any layout of a memory device may be used as part of the present invention. For example, in some embodiments, the memory device may be a single die that includes components of interface die 104 and memory die 106. In some embodiments, a memory array may be located on an interface die. In some embodiments, the memory device may not be stacked. In some embodiments, components such as interposer 112 and package substrate 114 may be omitted, and the memory device may not be a SiP device.

[0022] Figure 2 2 is a block diagram of a memory device according to an embodiment of the present invention. In some embodiments, the memory device 200 may include Figure 1 in the memory device 102.

[0023] Similar to Figure 1 The memory device shown, memory device 200, may be an HBM device having an interface die 204 and one or more core dies 206. For clarity, the memory device 200 may be an HBM device having an interface die 204 and one or more core dies 206. Figure 2Only a single core die 206 is shown in FIG. 1 , however, it should be understood that multiple core dies 206 may be coupled to the interface die 204 (e.g., there may be 3 or 7 core dies 206). Each core die may include a memory array including a number of memory cells. The interface die 204 may generally serve as an interface to write data to or retrieve data from the memory array of the core die 206. The interface die 204 may also be used to perform various other operations, such as refreshing memory cells in the core die 206 and / or performing test operations as part of a self-test mode.

[0024] To highlight the operation of the self-test procedure, only certain components of the interface die 204 that are involved in the test process are shown. It should be understood that other components of the interface die 204 that are not shown may be involved in various operations. For example, various components that are coupled via multiplexers to represent that signals can be routed along different signaling paths are shown. For clarity, the signals that control these multiplexers and the logic circuits that control this routing are not shown. Similarly, for clarity, certain connections may be omitted (e.g., P1500 pad 220 and / or direct access pad 216 may access C / A circuit 207).

[0025] The memory device 200 includes three different interface terminals for accessing a core die 206 and / or one or more circuits of the memory, namely, local microbumps (uBumps) 205, direct access (DA) uBumps 216, and test interface uBumps 220. The test interface uBumps 220 may be part of a particular interface protocol, such as an IEEE 1500 interface (also referred to as a P1500 interface). In general, the test interface uBumps 220 may be referred to as P1500 uBumps 220 (and related P1500 operating modes, P1500 circuits, etc.), however, it should be understood that other test interface protocols may be used in other example embodiments.

[0026] The device may have multiple operating modes, which may determine which, if any, of the external terminals 205, 216, and / or 220 the memory device 200 is communicating through. For example, after a reset, the memory may enter a 'local operating mode', where communications are sent and received through the local interface 205. The memory 200 may receive a command that may place the memory 200 in a direct access (DA) mode, where the memory 200 may typically communicate through the DA terminals 216. During the direct access mode, the circuitry of the interface die 204 may typically be bypassed so that signals may be sent directly to the one or more core dies 206. The memory may receive a command that places it in a P1500 mode, where communications may be sent and received through the P1500 terminals 220. The P1500 mode may be used to program the BIST sequencer 228 and / or retrieve data from the BIST logic 225.

[0027] In native operating mode, the logic die can send and receive information via native uBumps 205. In some embodiments, these native uBumps 205 may be included in Figure 1 The local uBumps 205 can be transmitted via one or more channels (e.g., Figure 1 105) is coupled to a processor (e.g., Figure 1 The processor 110 of the memory device 200 may also use the local uBumps 205 to perform one or more other operations of the memory device 200, such as activating a refresh mode or a self-test mode of the memory device 200.

[0028] In an example access operation as part of the local mode, a signal may be received at the local uBumps 205 requesting an access operation, such as a read operation of a memory cell of one or more of the core dies 206. Based on the received signal, the C / A logic may provide a command instruction indicating the read operation and the address of the memory cell to be read, and may be received at the local uBumps 205 as part of a data packet called an 'AWORD'. The AWORD may contain address information, which may indicate which memory cells are to be read. For example, each of the core dies 206 may contain a memory array, which may include memory cells arranged at the intersection of rows (word lines) and columns (bit lines). The AWORD may contain address information, such as a row address and a column address, which specifies the memory cell at the intersection of one or more rows and columns. The AWORD may also contain additional address information, such as a bank address, the address of a particular core die 206, etc. The AWORD may also include command information, such as a clock signal for the timing of the operation and a command indicating whether a read or write operation is being performed. In response to the address information during a read command, the core chip 206 may respond by reading data from the memory cell specified by the address information and then providing the data as part of a DWORD, which may be provided to the local uBumps 205.

[0029] In another example operation of the local mode, information may be received at the local uBumps 205 requesting an access operation, such as a write operation, to certain memory cells of one or more of the core die 206. The C / A circuit 207 may provide an AWORD specifying the write operation and including address information of the memory cells to be written, and a DWORD containing the data to be written. The AWORD and DWORD may be provided to the core die 206, which may write the information contained in the DWORD to the memory cells specified by the address information in the AWORD.

[0030] In some embodiments, the interface die 204 may include a serializer circuit 233 along a path that couples a DWORD leaving one of the core dies 206 to the local uBumps 205. In such embodiments, the number of connections between the interface die 204 and the core die 206 may be much greater than the local uBumps 205. The serializer circuit 233 may receive information in parallel along a first number of data lines (e.g., from the core 206), and then provide the information in serial fashion along a second number of data lines that is less than the first number (e.g., to the local uBumps 205).

[0031] In some cases, it may be desirable to place the memory device 200 in a self-test mode in order to determine one or more characteristics of the memory device 200. The device 200 may include a BIST circuit 225 that may be used to perform test operations as part of the self-test mode. The memory 200 may also include a direct test mode in which test operations are generated by an external device (e.g., a tester) and performed directly on the core die 206 through the DA terminal 216.

[0032] The P1500 uBumps 220 are coupled to a test interface circuit (e.g., a P1500 circuit) 224, which can interpret signals sent and received using the P1500 signal protocol. For example, the P1500 circuit 224 can translate signals received at the P1500 uBumps into signals that can be used by other circuits of the memory device 200, and vice versa. In the P1500 operating mode, the memory device 200 can receive signals through the P1500 uBumps 220 and provide the signals to the P1500 circuit 224. Similarly, signals from the memory device 200 can be provided to the P1500 circuit 224, which can then send the signals out of the memory device via the P1500 uBumps 220.

[0033] The BIST circuit 225 may include a BIST sequencer 228 that may be programmed with one or more test instructions. For example, the BIST sequencer 228 may include an algorithmic pattern generator (APG) that may generate test commands from the test instructions during the self-test mode. For example, the BIST sequencer 228 may be loaded with instructions that cause the BIST sequencer 228 to generate a write command to a first address, wait a set amount of time, then increment the address by 1, and continue in that manner until a maximum value for the address has been reached. As part of the P1500 operating mode, the test instructions may be programmed into the BIST sequencer 228 via the P1500 terminal 220.

[0034] The BIST sequencer 228 may also generate a test data sequence (e.g., a string of logic bits) to write to the memory cells of the core die 206. The BIST sequencer 228 may include several registers that can be used to store the addresses of the memory cells to be tested and the test sequence. Since the space in the BIST sequencer 228 may be limited, the test sequence and / or address may be generated within the BIST sequencer 228 based on instructions. For example, the BIST sequencer 228 may perform a test on a certain address value, increment the address value by 1, and then perform the test again. In some embodiments, to save space in the BIST sequencer 228, the BIST sequencer 228 may load the test sequence into a lookup table, such as a data topology (DTOPO) circuit 230. Each entry in the DTOPO circuit 230 may be associated with a pointer value (e.g., an index value), and the BIST sequencer 228 may generate a sequence of pointer values ​​in a manner similar to an address.

[0035] The memory device 200 may enter a self-test mode during which the BIST circuit 225 may perform test operations (e.g., read and write test operations) on the core chip 206 based on previously loaded instructions. For example, the memory may receive an external command (e.g., via the local terminal 205 and / or the P1500 terminal) that causes the memory to enter the self-test mode. The memory device 200 may provide a self-test enable signal BISTEn at an effective level when in the self-test mode. In some embodiments, the memory 200 may be placed in the self-test mode by a command received via the local terminal 205. In some embodiments, the memory 200 may be placed in the self-test mode by a command received via the P1500 terminal 220. When in the self-test mode, the BIST circuit 225 may perform test operations based on instructions in the BIST sequencer 228.

[0036] During an example write test operation, the BIST sequencer 228 may provide address information (e.g., one or more row and column addresses) and a test sequence (e.g., data to be written to the memory cells specified by the address information) to the input buffer 234. In some embodiments, the BIST sequencer 228 may provide the address information to the input buffer 234, and may provide the index information to the DTOPO circuit 230, which may provide the test sequence to the input buffer 234.

[0037] The input buffer circuit 234 may be a register that may store a value and then write it to the core die 206. The input buffer circuit 234 may operate as a first-in, first-out (FIFO) circuit and may be referred to as a write FIFO (WFIFO) circuit 234. Based on the address information provided from the WFIFO 234, a test sequence may be written to a memory cell specified by the address information.

[0038] During an example read test operation, the BIST sequencer 228 may provide address information to retrieve a test sequence previously stored in the core die 206. Information may be read out from the memory cells specified by the address information to the output buffer circuit 235. The output buffer circuit 235 may be generally similar to the input buffer 234, except that the output buffer 235 receives information from the core chip 206 and then provides it to other circuits of the interface chip 204. The output buffer 235 may be a read FIFO (RFIFO) circuit 235.

[0039] Error capture memory (ECM) circuit 232 may be used to generate result information based on the read test sequence. ECM circuit 232 may be coupled to the address information and test sequence provided to input buffer 234, and further include one or more registers for storing a write test sequence and address information about which memory cell the test sequence is written to. When performing a read operation, ECM circuit 232 may compare the read test sequence from output buffer 235 with the test sequence written to the memory cell as part of an earlier write operation, and may generate result information based on the comparison. ECM circuit 232 may then provide the result information (e.g., which memory cells failed, as part of what test, etc.) to P1500 circuit 224, which may then provide the result information from memory via P1500 uBumps.

[0040] When the device is in self-test mode (e.g., when the BISTEn signal is valid), to prevent interference with the test operation, the memory 200 can ignore the communication along the input terminals 205, 216 and 220. When the BIST circuit 225 completes the execution of the test operation and is ready to provide the result from the ECM circuit 232, the BIST circuit 225 can send a signal indicating that it has been completed. Then, the memory 200 can exit the self-test mode (e.g., by returning the signal BISTEn to an invalid level). As described in more detail herein, the memory 200 can also include an abort circuit 226, which can be used independently to cause the memory 200 to exit from the self-test mode. For example, the abort circuit 226 can track the amount of time that the memory 200 has been in the self-test mode, and can provide a signal ABORT when the time exceeds a threshold. In response to the signal ABORT, the memory 200 can exit the self-test mode. In some embodiments, if the signal ABORT is used, an error report can be generated.

[0041] In addition to the native mode and the P1500 mode, the memory device 200 can also enter the DA mode. In some scenarios, it may be desirable to bypass other components of the SiP package (e.g., Figure 110) to send and receive signals directly from the memory device 200. When the device is in one of the DA modes, signals may be sent and received along the DA uBumps 216, which may bypass other components of the SiP to allow external devices (e.g., tester circuits, probes) to send and receive signals directly from the memory device 200. This may involve activating a DA enable signal. For example, one of the DA uBumps 216 may serve as a DA enable pin, and when a DA enable signal, such as a logic high, is received at the DA enable pin, the memory may transition to DA1500 mode. In DA direct mode, the memory device 200 may operate in a manner similar to the native mode, except that information is provided along the DA uBumps 216 instead of the native uBumps 205.

[0042] For example, in DA direct mode, DA uBumps 216 may receive (and / or provide) AWORD and DWORD in a manner similar to native mode. In some embodiments, there may be fewer DA uBumps 216 than native uBumps 205. To emulate the operation of signals along native uBumps 205, deserializer circuit 222 may be used. Deserializer circuit 222 may receive AWORD and DWORD from DA uBumps 216 and then split the received serial data into a number of parallel lanes. In some embodiments, deserializer circuit 222 may split AWORD and DWORD into a number of parallel lanes to emulate the number of lanes of AWORD and DWORD along which native uBumps 205 receive.

[0043] In DA direct mode, AWORD and DWORD may be received at DA uBumps 216, provided to deserializer circuit 222, and then provided to core die 206. Similarly, in DA direct mode, AWORD and DWORD may be provided to DA uBumps from core die 206. In this manner, while in DA direct mode, memory device 200 may operate through DAuBumps in a manner similar to how memory 200 would operate through native uBumps 205 in native mode.

[0044] Figure 3 is a block diagram of a test and abort circuit according to some embodiments of the present invention. Figure 3 A portion 300 of a memory device is shown, which in some embodiments may be included in Figure 1 Interface chip 104 and / or Figure 2300 is a simplified diagram of circuits and signals that may be used to activate and deactivate the self-test mode. Figure 3 omitted in Figures 1 to 2 Certain components and operations described in .

[0045] Portion 300 includes BIST logic circuit 304. BIST logic circuit 304 may include various components for performing test operations. In some embodiments, BIST logic circuit 304 may include Figure 2 225. When the BIST logic circuit 304 receives the enable signal BISTEn at an effective level (e.g., a high logic level), the BIST logic circuit 304 may perform a test operation. For example, the BIST logic circuit 304 may be programmed to write one or more data patterns to various memory cells, read data from the memory cells, and compare the written information with the read information. This process may be relatively time consuming. For example, the test operation may take about 10 seconds. In other examples, test operations of other lengths may be used.

[0046] Portion 300 includes C / A logic circuit 302. C / A logic circuit 302 may represent various circuits of the memory involved in the timing and operation of the memory. For example, C / A logic circuit 302 may include input / output circuits, control logic, refresh circuitry, etc. C / A logic circuit 302 receives external commands, such as through one or more external terminals (e.g., through Figure 2 Terminal 205 and / or Figure 2 The C / A logic circuit 302 may receive an external command or otherwise determine that the memory 300 should enter the self-test mode. To indicate the start of the self-test mode, the C / A logic circuit 302 may begin to provide a BIST enable signal BISTEn at an active level.

[0047] To prevent interference with the test operation, the C / A logic circuit 302 may ignore external commands when the enable signal BISTEn is valid. For example, the C / A logic circuit 302 may receive a first external command instructing it to start a self-test mode. The C / A logic circuit 302 may begin to provide the signal BISTEn at an effective level. When BISTEn is at an effective level, the C / A logic circuit 302 may receive a second external command (e.g., to read data from one or more memory cells). However, since the signal BISTEn is valid, the C / A logic circuit 302 may ignore the second external command.

[0048] Portion 300 may also include a clock circuit 308. Clock circuit 308 may provide a BIST clock signal BIST_CLK. In some embodiments, clock signal BIST_CLK may be based on a system clock, such as a clock CLK of a memory device. Clock signal BIST_CLK may be a periodic signal with predictable timing (e.g., alternating between a high logic level and a low logic level). Clock signal BIST_CLK may be used to control the timing of a test operation. In some embodiments, clock circuit 308 may also receive an enable signal BISTEn, and may provide clock signal BIST_CLK only when enable signal BISTEn is valid.

[0049] BIST logic 304 can be activated by BIST enable signal BISTEn at an effective level, and once activated, a test operation can be performed. BIST circuit 304 can be loaded with one or more test instructions. Using the timing based on BIST clock BIST_CLK, BIST logic 304 can start executing the instructions when BIST enable signal BISTEn is at an effective level. For example, the instruction can cause BIST circuit 304 to perform a test operation such as reading or writing information to the memory core die along the command / address C / A bus. Once BIST logic circuit 304 completes execution of the stored instruction, BIST logic circuit 304 can provide a BIST end signal BIST_End at an effective level (e.g., a high logic level). C / A logic 302 can receive signal BIST_End, and in response to the signal BIST_End at an effective level, the BIST enable signal can be deactivated (e.g., by providing a signal BISTEn at a low logic level).

[0050] There may be some situations where the BIST circuit 304 cannot correctly provide the end signal BIST_End. For example, the BIST circuit 304 may encounter an internal error that causes it to 'hang up' or 'freeze' when executing one or more of the instruction lines. Since the BIST circuit 304 can provide the end signal BIST_End at an effective level when it reaches the end of the instruction, if the BIST circuit 304 does not reach the end of the instruction, it may not correctly provide the BIST_End signal. In other examples, there may be other reasons that cause the BIST circuit 304 to correctly provide the end signal BIST_End.

[0051] To prevent the test condition from continuing indefinitely when the BIST circuit 304 cannot correctly provide the end signal BIST_End, the memory may also include an abort logic circuit 306. The abort logic circuit 306 may represent an independent path that can be used to stop the test operation when the BIST logic circuit 304 cannot correctly provide the end signal BIST_End. The abort logic circuit 306 may use one or more conditions to determine whether the BIST logic circuit 304 fails to correctly provide the end signal BIST_End, and if so, provide a signal ABORT at an effective level. In response to the signal ABORT being at an effective level, the C / A logic 302 may deactivate the enable signal BISTEn, which may stop the test operation and may cause the C / A logic 302 to start receiving commands from the external terminal again.

[0052] In some embodiments, the abort logic circuit 306 may use the expected completion time of the test operation to determine when to provide the ABORT signal at an active level. For example, the abort logic circuit 306 may count the time that has passed since the start of the test operation and provide the signal ABORT at an active level once the elapsed time exceeds a threshold. The threshold may be based on the expected amount of time to perform the test operation, plus some amount of buffer time to allow for variations in the run time of the test operation.

[0053] To track the time that has passed, the abort logic circuit 306 may include a counter circuit 310 that can count time based on the BIST clock BIST_CLK. For example, each time a rising edge of BIST_CLK is received, the counter circuit 310 can change (e.g., increment) the count value ABORT_CNT. The abort logic circuit 306 may include a comparator circuit 312 that compares the count value ABORT_CNT with a threshold value Threshold. The threshold value may be stored on the memory 300 (e.g., in a register of the abort logic 306, in a mode register of the memory 300), or may be 'hardwired' into the abort logic 306. In some embodiments, the threshold value may be determined based on instructions loaded into the BIST logic circuit 304 for self-testing (e.g., based on a number of test operations). In some embodiments, the threshold value may be loaded into the memory together with the test instructions.

[0054] When the count value ABORT_CNT matches or exceeds the threshold, a signal ABORT at an active level may be provided by the comparator circuit 312. In response to the ABORT signal being at an active level (or, in some embodiments, in response to the signal BISTEn falling to an inactive level), the count value may be reset (e.g., to 0). In some embodiments, the counter may start counting when the signal BISTEn becomes active. In some embodiments, the clock signal BIST_CLK may only be provided when BISTEn is active, and the counter may count all rising edges of BIST_CLK.

[0055] Figure 4 is a timing diagram of signals during a test operation to properly provide a test end signal according to some embodiments of the present invention. Figure 4 Show for example Figure 3 4 is a timing diagram 400 of operations in a memory device of portion 300 of the memory device of FIG. 4. In particular, timing diagram 400 shows the operation of the memory if the BIST circuit correctly sends an end signal.

[0056] At the initial time t0, the signal BISTEn rises to an active level to indicate that the test operation should start. Figure 4 In the embodiment of , the clock signal BIST_CLK is related to the enable signal, so shortly after t0, the clock signal BIST_CLK begins to oscillate. In response to the rising edge of the clock signal BIST_CLK, a counter in the abort circuit can be incremented. When the enable signal BISTEn is valid, the counter can be incremented for each rising edge of the clock signal BIST_CLK. Whenever the counter is incremented, it can be compared with a threshold value (which is the number 'N' in this case) to determine whether an ABORT signal at an effective level should be provided.

[0057] At the first time t1, the test operation may end (e.g., because the BIST circuit reaches the end of its instruction), and the BIST circuit may provide a signal BIST_End at an active level. At this point, the abort counter value is a number L that is less than the threshold count N. Therefore, the signal ABORT remains at an inactive level. The signal BIST_End being at an active level may cause the signal BISTEn to be provided at an inactive level, which in turn may reset the value of the abort counter.

[0058] Figure 5 is a timing diagram of signals during a test operation in which a test end signal is not properly provided according to some embodiments of the present invention. Figure 5 The timing diagram 500 may generally be similar to Figure 4 The timing diagram is Figure 5For the sake of brevity, we will not discuss this in detail. Figure 5 Description and already about Figure 4 Features and signals similar to those described herein.

[0059] At the first time t1 (which can be Figure 4 In the timing diagram 500, the test operation should be completed at the same first time t1 as the timing diagram 400 of FIG. 500. However, in the timing diagram 500, the signal BIST_End remains invalid at the time t1. Therefore, the enable signal BISTEn can remain valid after t1, and the clock signal BIST_CLK can continue to be provided. At the second time t2, the stop counter can reach a value N, which is a threshold value for stopping the logic circuit. Since the count value N matches the threshold value, the stop circuit can begin to provide the signal ABORT under the effective level at the time t3. In response to the signal ABORT under the effective level, the signal BISTEn can be provided under the invalid level. This can reset the stop counter, and also cause the signal ABORT to drop to the invalid level. This can end the self-test mode and reset the self-test circuit, which allows to continue normal operation, even if the BIST circuit does not indicate that the test operation has been completed.

[0060] Figure 6 is a flow chart of a method for terminating a test operation according to some embodiments of the present invention. In some embodiments, method 600 may be used Figures 1 to 3 It may be implemented by one or more of the circuits described in .

[0061] Method 600 may generally begin at block 610, which depicts entering a self-test mode and activating a self-test enable signal. For example, a memory device may include one or more self-test circuits, such as a built-in self-test (BIST) circuit (e.g., Figure 2 225 and / or Figure 3 304). In some embodiments, the memory device may receive an external command to place the device in a self-test mode. In some embodiments, the memory device may include internal logic that instructs the memory device to begin a self-test operation by entering a self-test mode. The BIST circuit may be loaded with one or more instructions that may contain instructions for one or more test operations. During the self-test mode, the BIST circuit may perform one or more test operations based on the instructions. For example, the BIST circuit may write test data to a memory cell of a memory array, read data from the memory cell, and then compare the written data with the read data. The BIST circuit may generate a result file based on the test results.

[0062] Block 610 may generally be followed by block 620, which depicts counting the number of times a test clock is provided during the self-test mode. The test clock may be used to control the timing of test operations performed as part of the self-test mode. In some embodiments, the test clock may be activated by a self-test enable signal, and the test clock may only be provided when the self-test enable signal is valid. In some embodiments, the test clock may be provided regardless of the self-test enable signal. A suspend circuit (e.g., Figure 3 The abort circuit 306 of the test clock may include a counter that counts the test clock. For example, the counter may increment the count value in response to each rising edge of the clock signal. Whenever the count value is updated, the comparator circuit may compare the count value with the threshold value.

[0063] Frame 620 may be followed by frame 630, which describes the end of the self-test mode in response to the count value exceeding the threshold. In some embodiments, the self-test mode may be ended in response to the count value reaching or exceeding the threshold. When the comparator in the abort circuit determines that the count value reaches / exceeds the threshold, an ABORT signal at an effective level may be provided. In response to the ABORT signal at an effective level, the self-test enable signal may be returned to an invalid level. In some cases, the BIST circuit may reach the end of the test operation and may provide a self-test end signal at an effective level. In response to the self-test end signal at an effective level, the self-test enable signal may be returned to an invalid level. In response to the self-test enable signal falling to an invalid level, the counter may be reset (e.g., to 0). When the self-test enable signal is effective, the memory device may ignore external signals. In response to the self-test enable signal becoming invalid, the memory device may start responding to external signals again. In some embodiments, if an ABORT signal is provided at an effective level (e.g., because the self-test end signal is provided at the right time), the BIST circuit may generate an error report, such as an error code or an error flag.

[0064] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in separate devices or device portions according to the present systems, devices, and methods.

[0065] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in detail with reference to exemplary embodiments, it should also be understood that numerous modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as subsequently set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A memory device, comprising: a command / address C / A circuit configured to provide internal command signals and addresses during a local operation mode and to provide a self-test enable signal at an active level during a self-test mode; a clock circuit configured to provide a self-test clock signal in response to the self-test enable signal at an active level provided by the C / A circuit; a self-test circuit configured to perform the test operation on a memory array in response to the self-test enable signal at an active level provided by the C / A circuit and based on address information and a test sequence for the test operation provided by a self-test sequencer; and A suspend circuit configured to: changing a count value in response to the self-test clock signal; and providing a halt signal when the count value matches or exceeds a threshold, the threshold being longer than an expected length of the test operation, wherein the C / A circuit is further configured to stop providing the self-test enable signal at the active level in response to the halt signal, and The pause circuit includes a counter configured to change the count value in response to each rising edge of the self-test clock signal.

2. The memory device of claim 1, wherein the C / A circuit is further configured to ignore external commands when the self-test enable signal is at the active level. 3 . The memory device of claim 1 , wherein the threshold is based on an expected completion time of the self-test mode.

4. The memory device of claim 1, wherein the counter is further configured to increment the count value in response to each rising edge of the self-test clock signal.

5. The memory device of claim 4, wherein the counter is configured to reset the count value in response to the self-test enable signal becoming deasserted.

6. The memory device of claim 1 , wherein the self-test circuit is further configured to provide a self-test end signal at a valid level when one or more of the test operations are completed, and the C / A circuit is further configured to provide the self-test enable signal at an invalid level in response to the self-test end signal at the valid level.

7. A method of operating a memory device, comprising: Internal command signals and addresses are provided by the command / address C / A circuit during the local mode of operation; providing a self-test enable signal by the C / A circuit during a self-test mode; entering a self-test mode of the memory device and activating the self-test enable signal; providing a self-test clock signal by a clock circuit in response to the self-test enable signal provided by the C / A circuit at an active level; performing one or more test operations on a memory array of the memory device during the self-test mode in response to the self-test enable signal at an active level provided by the C / A circuit and based on address information and a test sequence for the test operations provided by a self-test sequencer; counting, by a pause circuit, the number of times the self-test clock signal is provided during the self-test mode; changing a count value by a counter of the abort circuit in response to each rising edge of the self-test clock signal; and The abort circuit provides an abort signal to end the self-test mode in response to the count value reaching or exceeding a threshold value, the threshold value being longer than an expected length of the test operation.

8. The method according to claim 7, further comprising: The self-test mode is terminated when the one or more test operations are completed.

9. The method according to claim 8, further comprising: Instructions are loaded into self-test circuitry of the memory device, wherein the one or more test operations are performed based on the loaded instructions.

10. The method of claim 7, further comprising determining a value for the threshold based on an expected duration of one or more test operations during the self-test mode.

11. The method of claim 7, further comprising ignoring external commands to the memory device when the self-test enable signal is active.

12. A memory device comprising: Memory array; and An interface die configured to: entering a self-test mode in response to a self-test enable signal at an active level and performing at least one of said test operations on said memory array based on address information and a test sequence for the test operations; and exiting the self-test mode after entering the self-test mode for a first amount of time, provided that the self-test mode does not end before the first amount of time has elapsed, wherein the interface die comprises: a self-test sequencer configured to provide the address information and the test sequence for the test operation; a command / address C / A circuit configured to provide an internal command signal and an address during a local operation mode and to provide the self-test enable signal at an active level during the self-test mode; a clock circuit configured to provide a self-test clock signal in response to the self-test enable signal at an active level provided by the C / A circuit; and A pause counter configured to: counting the self-test clock signal during the self-test mode; changing a count value by a counter of the pause counter in response to each rising edge of the self-test clock signal; and A halt signal is provided to terminate the self-test mode when the count value matches or exceeds a threshold value, the threshold value being longer than an expected length of the test operation.

13. The memory device of claim 12, wherein the self-test mode is expected to end after a second amount of time that is shorter than the first amount of time. The memory device of claim 13 , wherein the first amount of time is based on the second amount of time.

15. The memory device of claim 12, wherein the interface die is configured to ignore external commands during the self-test mode.

16. A memory device comprising: a command / address C / A circuit configured to provide a self-test enable signal at an active level during a self-test mode; a clock circuit configured to provide a self-test clock signal; a self-test circuit configured to perform a test operation on a memory array in response to the self-test enable signal at an active level; and an abort circuit configured to change a count value in response to the self-test clock signal and to provide an abort signal when the count value matches or exceeds a threshold value, wherein the C / A circuit is configured to stop providing the self-test enable signal at the active level in response to the suspend signal, and Wherein the suspend circuit includes a counter configured to increment the count value in response to each rising edge of the self-test clock signal.

17. A memory device comprising: Memory array; and an interface die configured to enter a self-test mode and perform at least one test operation on the memory array, wherein the interface die is configured to exit the self-test mode after entering the self-test mode for a first amount of time, provided that the self-test mode does not end before the first amount of time has elapsed, and wherein the interface die includes an abort counter configured to count a self-test clock during the self-test mode, increment a value of the abort counter in response to each rising edge of the self-test clock, and provide an abort signal to end the self-test mode when the value of the abort counter matches or exceeds a threshold value, the threshold value being longer than an expected length of the test operation.

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