Voltage fluctuation detection circuit

Abstract

The present application provides a voltage fluctuation detection circuit, comprising: an upper edge trigger circuit, comprising an input end and an output end, the upper edge trigger circuit detecting an operating voltage received by the input end with a preset clock cycle, and when a change in the operating voltage is greater than a preset bias voltage within one of the clock cycles, an output signal of the output end realizes at least one target flip between a high level and a low level; and a detection and output circuit connected to the output end of the upper edge trigger circuit, detecting a change in the operating voltage and the target flip and outputting a control signal according to the detection result, wherein the target flip occurs in the output signal of the upper edge trigger circuit in N consecutive clock cycles, and when each of all the target flips occurring in the N consecutive clock cycles occurs, the operating voltage is not less than the start threshold, and the detection and output circuit generates a first signal, wherein N is a natural number not less than 2.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a voltage fluctuation detection circuit. Background Art

[0002] Switching power supplies are everywhere. We use them every day to charge our smartphones, tablets, laptops, cameras, and even some cars. Switching power supplies can also power clocks, radios, home audio amplifiers, and other small appliances.

[0003] A switching power supply controller is an integrated circuit chip (IC) used to control a switching power supply. It regulates and / or controls the output of the switching power supply through a specially designed circuit.

[0004] An AC-DC flyback controller is a switching power supply controller. An AC-DC flyback controller needs to detect the AC line voltage to determine when the AC line voltage is high enough to start the operation of the IC. When the AC line voltage is too low, the AC-DC flyback controller must stop the switching operation to protect the system from excessive stress during operation. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a voltage fluctuation detection circuit. The voltage fluctuation detection circuit provided by the present application can detect the voltage of the AC line to determine whether a switch operation can be started or stopped.

[0006] The voltage fluctuation detection circuit includes: an upper edge trigger circuit, including an input end and an output end, the upper edge trigger circuit detects the working voltage received by the input end with a preset clock cycle, and when the change of the working voltage is greater than the preset bias voltage within one clock cycle, the output signal of the output end realizes at least one target flip between a high level and a low level; and a detection and output circuit, connected to the output end of the upper edge trigger circuit, detecting the change of the working voltage and the target flip, and outputting a control signal according to the detection result, wherein, when the detection result of the detection and output circuit shows that within N consecutive clock cycles, the output signal of the upper edge trigger circuit has the target flip, and when each target flip of all the target flips occurring within the N consecutive clock cycles occurs, the working voltage is not less than the start threshold, and the detection and output circuit generates a first signal, wherein N is a natural number not less than 2.

[0007] In some embodiments, the first signal is configured to control the startup of a first target circuit.

[0008] In some embodiments, when the comparator does not experience the target flip within n consecutive clock cycles, the detection and output circuit generates a second signal to indicate that the operating voltage has been converted from a rising edge to a falling edge, where n is a natural number not less than 2.

[0009] In some embodiments, the detection and output circuit includes a second target circuit, and when the comparator does not show the target flip within n consecutive clock cycles, the second target circuit is triggered to indicate that the operating voltage has been converted from a rising edge to a falling edge.

[0010] In some embodiments, the rising edge trigger circuit includes: an adjustment circuit, including an adjustment circuit input terminal, receiving an operating voltage, wherein the operating voltage is an AC voltage, a first adjustment circuit output terminal, outputting a first voltage, and a second adjustment circuit output terminal, outputting a step second voltage; a comparator, including a first comparator input terminal, receiving the first voltage, a second comparator input terminal, receiving the second voltage, and a comparator output terminal, outputting a comparison result of the first voltage and the second voltage, wherein the second voltage differs from the first voltage by the bias voltage at the beginning of a preset clock cycle, and the second voltage does not drop by more than a first amplitude within the clock cycle.

[0011] In some embodiments, the magnitude of the bias voltage is positively correlated with the amplitude of the first voltage.

[0012] In some embodiments, the target flip includes flipping from a low level to a high level, wherein: at the beginning of the clock cycle, the first voltage is lower than the second voltage, and the comparator outputs a low level; and within one of the clock cycles, when the rising amplitude of the first voltage exceeds the bias voltage value, the output of the comparator flips from a low level to a high level.

[0013] In some embodiments, the target flip includes flipping from a high level to a low level, wherein: at the beginning of the clock cycle, the first voltage is higher than the second voltage, and the comparator outputs a high level; and within one of the clock cycles, when the drop in the first voltage exceeds the bias voltage value, the output of the comparator flips from a high level to a low level.

[0014] In some embodiments, the adjustment circuit includes: a voltage bias circuit that adds the bias voltage to the input voltage of the voltage bias circuit; and a step voltage generating circuit that converts the voltage input to the step voltage generating circuit into a step voltage.

[0015] In some embodiments, the step voltage generating circuit includes: a switching circuit; a clock circuit, connected to the switching circuit and controlling the switching circuit to open and close according to the clock cycle to generate the second voltage; and a voltage holding circuit, connected to the switching circuit and maintaining the second voltage after the switching circuit is disconnected so that the second voltage does not drop by more than the first amplitude within the clock cycle.

[0016] In some embodiments, wherein: the voltage bias circuit includes at least one of a voltage-controlled voltage source and a voltage-controlled current source; the switching circuit includes at least one field effect transistor; and the voltage holding circuit includes at least one capacitor.

[0017] In some embodiments, the output terminal of the first adjustment circuit is electrically connected to the input terminal of the adjustment circuit; and the voltage bias circuit is connected in series with the step voltage generating circuit, and the series circuit connects the input terminal of the adjustment circuit and the output terminal of the second adjustment circuit.

[0018] In some embodiments, the first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a positive voltage; or the first comparator input terminal is the negative electrode of the comparator, the second comparator input terminal is the positive electrode of the comparator, and the bias voltage is a positive voltage.

[0019] In some embodiments, the voltage bias circuit is connected in series with the output terminal of the first adjustment circuit and the input terminal of the adjustment circuit; and the step voltage generating circuit is connected in series with the input terminal of the adjustment circuit and the output terminal of the second adjustment circuit.

[0020] In some embodiments, the first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a negative voltage; or the first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a negative voltage.

[0021] In some embodiments, the voltage fluctuation detection circuit further includes a voltage divider circuit, one end of the voltage divider circuit is connected to the input voltage, and the other end is connected to the ground line, and the voltage divider circuit divides the input voltage into the working voltage output. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present disclosure will be further described according to exemplary embodiments. The foregoing and other aspects of the embodiments of the present disclosure will become more apparent in the following detailed description when read in conjunction with the accompanying drawings.

[0023] Figure 1A circuit structure diagram of a voltage fluctuation detection circuit provided according to an embodiment of the present application is shown;

[0024] Figure 2A A timing diagram of various signals when a voltage rising edge detection circuit provided in an embodiment of the present application works is shown;

[0025] Figure 2B A timing diagram of V1 and V2 provided according to an embodiment of the present application is shown;

[0026] Figure 2C Shows Figure 2B The enlarged diagram of the curves of V1 and V2 in the clock cycle T1;

[0027] Figure 2D Shows Figure 2B An enlarged view of the curves of V1 and V2 in the clock cycle T2;

[0028] Figure 2E According to this application Figure 2A Detailed view of area A in the middle;

[0029] Figure 2F A timing diagram of various signals when another voltage rising edge detection circuit provided in an embodiment of the present application works is shown;

[0030] Figure 2G A circuit structure diagram of a detection and output circuit provided according to an embodiment of the present application is shown;

[0031] Figure 3A A comparison diagram of input voltage and output voltage of a voltage bias circuit provided according to an embodiment of the present application is shown;

[0032] Figure 3B A comparison diagram of a voltage at an output terminal of a voltage bias circuit provided according to an embodiment of the present application and a second voltage loaded onto a voltage input terminal of a second comparator is shown;

[0033] Figure 4A A method for providing two different input groups according to an embodiment of the present application is shown. and Comparison of the outputs corresponding to the two sets of inputs when a constant ΔV is used;

[0034] Figure 4B FIG. 4 shows a method of ΔV and V according to an embodiment of the present application. in Schematic diagram of the relationship between peak values;

[0035] Figure 4C Another schematic diagram showing the relationship between ΔV and Vin peak value provided according to an embodiment of the present application is shown;

[0036] Figure 5 A circuit structure schematic diagram of another voltage fluctuation detection circuit provided according to an embodiment of the present application is shown;

[0037] Figure 6 Shows Figure 5 A comparison diagram of the operating voltage, the first voltage and the second voltage in the circuit structure;

[0038] Figure 7 A circuit structure diagram of another voltage fluctuation detection circuit provided according to an embodiment of the present application is shown; and

[0039] Figure 8 A circuit structure schematic diagram of another voltage fluctuation detection circuit provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The terms used herein are only used for the purpose of describing specific example embodiments and are not restrictive. For example, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" used herein may also include plural forms. When used in this specification, the terms "include", "comprise" and / or "contain" mean the existence of the associated integers, steps, operations, element components and / or groups, but do not exclude the existence of one or more other features, integers, steps, operations, elements, components and / or groups or other features, integers, steps, operations, elements, components and / or groups may be added to the system / method. When used in this specification, the term "A on B" may mean that A is directly adjacent to B (above or below), or it may mean that A is indirectly adjacent to B (i.e., there is some material between A and B); the term "A in B" may mean that A is all inside B, or it may mean that A is partially inside B.

[0041] In view of the following description, these and other features of the present disclosure, as well as the operation and function of the related elements of the structure, and the economy of the combination and manufacture of the parts can be significantly improved. Reference is made to the accompanying drawings, all of which form a part of the present disclosure. However, it should be clearly understood that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present disclosure.

[0042] In some cases, ICs require specially designed circuits to detect fluctuations in electrical signals. For example, ICs are usually only allowed to operate on the rising edge of the alternating current (AC) line. In this case, the premise for starting the IC is that the AC must be on the rising edge. Therefore, in the design of switching power supply circuits, special circuits need to be designed to detect the voltage of the AC line.

[0043] In some embodiments, in the design of the switching power supply circuit, a digital circuit can be used to sample and detect the AC line voltage. Since the switching power supply controller is usually an analog IC, adding a digital design to the analog IC will increase the cost of the switching power supply controller.

[0044] The present application provides a voltage fluctuation detection circuit. The voltage fluctuation detection circuit can detect the fluctuation of an electrical signal. The voltage fluctuation detection circuit provided by the present application can strike a balance between circuit complexity, detection accuracy, and sufficiently fast detection speed, achieving a balance between optimal performance and IC cost. The voltage fluctuation detection circuit provided by the present application can be applied to all ICs that need to detect electrical signal characteristics.

[0045] As an example, Figure 1 FIG. 1 is a schematic diagram showing a circuit structure of a voltage fluctuation detection circuit 001 provided according to an embodiment of the present application. As an example, Figure 2A The timing diagram of each signal when a voltage rising edge detection circuit provided according to an embodiment of the present application works is shown. Specifically, the voltage fluctuation detection circuit 001 may include an rising edge trigger circuit 600 and a detection and output circuit 700. As an example, the rising edge trigger circuit 600 may include a voltage adjustment circuit 100 and a comparator 200. In some embodiments, the voltage fluctuation detection circuit 001 may also include a voltage divider circuit 400 and / or a latch circuit 800.

[0046] The voltage divider circuit 400 may include a circuit for dividing the signal V HV Any circuit that divides the voltage into the working voltage signal V0. For example Figure 1 As shown, the voltage divider circuit 400 may include a first resistor R1 and a second resistor R2 connected in series. The output terminal 420 of the voltage divider circuit 400 is connected between the first resistor R1 and the second resistor R2. One end of the voltage divider circuit 400 may be connected to the input voltage pin HV, and the other end may be connected to the ground line GND. In this way, by reasonably designing the resistance values ​​of the first resistor R1 and the second resistor R2, the voltage divider circuit 400 can convert the input voltage signal V HV The divided voltage is the working voltage signal V0 at the output terminal 420 .

[0047] The working voltage signal V0 can be an AC signal or a DC signal. For the convenience of description, in the following description of this application, the working principle of the voltage rising edge detection circuit 001 is first described by taking the working voltage signal as an AC voltage signal as an example. Figure 2A , the working voltage signal V0 includes several cycles, wherein the working voltage signal in each cycle includes at least one rising edge and at least one falling edge. For ease of understanding, in the following description of this application, the input signal V HVTaking the AC power without frequency modulation as an example, the working principle of the circuit provided by the present application is introduced. HV The frequency f HV The frequency of the AC power is the same as that of the mains power, which is 50HZ. That is, the input signal V HV The period is T HV =20ms. Input signal V HV One cycle T HV There are 2 rising edges and 2 falling edges. The duration of a rising edge and a falling edge is 1 / 4T. HV .

[0048] The comparator 200 includes a first comparator input terminal 210, a second comparator input terminal 220, and a comparator output terminal 230. One of the first comparator input terminal 210 and the second comparator input terminal 220 can be the positive pole of the comparator 200 (the input terminal marked with "+"), and the other can be the negative pole of the comparator 200 (the input terminal marked with "-"). When the positive pole voltage is higher than the negative pole voltage, the output terminal 230 of the comparator 200 outputs a high level; when the negative pole voltage is higher than the positive pole, the output terminal 230 of the comparator 200 outputs a low level. Figure 1 For example, the first comparator input terminal 210 can be electrically connected to the first adjustment circuit output terminal 102 to receive the first voltage V1; the second comparator input terminal 220 can be electrically connected to the second adjustment circuit output terminal 103 to receive the second voltage V2. The comparator 200 can compare the first voltage signal V1 and the second voltage signal V2, and output a high level or a low level through the comparator output terminal 230 according to the comparison result, that is, output the comparison result of the first voltage V1 and the second voltage V2. When the first voltage signal V1 is greater than the second voltage signal V2, the comparator outputs a high level; when the first voltage signal V1 is less than the second voltage signal V2, the comparator outputs a low level.

[0049] The detection and output circuit 700 is connected to the comparator output terminal 230. The detection and output circuit 700 can detect the comparison result output by the comparator output terminal 230, and output a signal for controlling the start of the IC or the stop of the IC according to the comparison result. The detection and output circuit 700 can also output the characteristics of the input signal according to the comparison result, such as whether the type of the input signal is AC or DC. As an example, the detection and output circuit 700 may include at least one counting circuit. As an example, the counting circuit may include one or more counters, and determine whether the type of the input signal is AC or DC by counting the number of transitions between the high and low levels of the output of the comparator.

[0050] One end of the latch circuit 800 is connected to the output terminal 230 of the comparator 200, and the other end is connected to the voltage bias circuit 110. The latch circuit 800 can record and latch the output signal of the output terminal 230 of the comparator. HV The peak data is obtained and the peak data is transmitted to the voltage bias circuit 110. The voltage bias circuit 110 can automatically adjust the magnitude of the bias voltage according to the peak data.

[0051] The voltage adjustment circuit 100 includes an adjustment circuit input terminal 101, a first adjustment circuit output terminal 102, and a second adjustment circuit output terminal 103. The adjustment circuit input terminal 101 receives an operating voltage V0. The first adjustment circuit output terminal 102 outputs a first voltage V1. The second adjustment circuit output terminal 103 outputs a stepped second voltage V2. As an example, the second voltage V2 is equal to the first voltage V1 in a preset clock period T sample At the beginning, the phase difference is ΔV and in the clock cycle T sample The decrease in the bias voltage ΔV does not exceed the first amplitude. For example, the first amplitude can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV or an interval between any two numbers. The magnitude of the bias voltage ΔV is related to the first voltage V1.

[0052] Specifically, the voltage adjustment circuit 100 may include a voltage bias circuit 110 and a step voltage generation circuit 500 .

[0053] The voltage bias circuit 110 can add the bias voltage ΔV to the input voltage V of the voltage bias circuit 110. in On, and the output voltage V out As an example, the voltage bias circuit 110 may include at least one of a voltage-controlled voltage source and a voltage-controlled current source. For example, the voltage bias circuit 110 may be a voltage-controlled current source.

[0054] As an example, the bias may be a positive bias (the bias voltage ΔV is a positive voltage), for example, the output voltage V out Ratio input voltage V in Large ΔV, that is, V out =V in +ΔV; the bias may also be a negative bias (the bias voltage ΔV is a negative voltage), for example, the output voltage V out Ratio input voltage V in Small ΔV, that is, V out =V in -ΔV. For the convenience of description, in the following description of this application, V out =V in +ΔV is used as an example to illustrate the working principle of the rising edge detection circuit. As an example, Figure 3A shows an input voltage V of a voltage bias circuit 110 provided according to an embodiment of the present application in and output voltage V out Reference Figure 3A , input voltage V in As the voltage rises, the voltage bias circuit 110 adds a bias voltage ΔV to V in Generate V out .

[0055] It should be noted that Figure 3A The working process of the voltage bias circuit 110 is described by taking the rising edge as an example. For the falling edge, the principle is the same.

[0056] Continue to refer Figure 1 , the step voltage generating circuit 500 can convert the voltage input to the step voltage generating circuit into a step voltage. For example, the step voltage generating circuit 500 may include a switch circuit 120, a clock circuit 300 and a voltage holding circuit 130. As an example, the switch circuit 120 may include at least one field effect transistor. As an example, the field effect transistor may include, but is not limited to, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), a MOS controlled thyristor (MCT) or a static induction transistor (SIT). The clock circuit 300 is connected to the switch circuit 120 and operates according to the clock period T sample The switch circuit 120 is controlled to open and close to generate the second voltage V2. The voltage holding circuit 130 is connected to the switch circuit 120 and holds the second voltage V2 after the switch circuit 120 is turned off, so that the voltage V2 is sample The second voltage V2 loaded on the second comparator input terminal 220 decreases within the clock period T sample As an example, the voltage holding circuit 130 may include at least one capacitor circuit.

[0057] According to the above description, the first voltage V1 and the second voltage V2 are in a preset clock cycle T sample At the beginning, the phase difference is ΔV and in the clock cycle T sample The internal drop does not exceed the first amplitude.

[0058] The working principle of the voltage fluctuation detection circuit 001 is introduced below.

[0059] For ease of description, in the following description of the present application, the “first circuit S1” refers to a circuit connecting the adjustment circuit input terminal 101 and the first adjustment circuit output terminal 102, and the “second circuit S2” refers to a circuit connecting the adjustment circuit input terminal 101 and the second adjustment circuit output terminal 103. The working voltage signal V0 can be transmitted to the first comparator input terminal 210 and the second comparator input terminal 220 via the first circuit S1 and the second circuit S2, respectively. Figure 1 The input end of the first circuit S1 is electrically connected to the working voltage V0, and the output end is the first adjustment circuit output end 102. The first circuit S1 can convert the working voltage V0 into the first voltage V1. The input end of the second circuit S2 is electrically connected to the working voltage V0, and the output end is the second adjustment circuit output end 103. The second circuit S2 can convert the working voltage V0 into the second voltage V2.

[0060] refer to Figure 1 , the voltage divider circuit 400 converts the input signal V HV The voltage is divided into the working voltage V0. The working voltage V0 is input into the adjustment circuit 100 from the adjustment circuit input terminal 101. The adjustment circuit 100 adjusts the working voltage V0 into the first voltage V1 and the second voltage V2 and outputs them from the first adjustment circuit output terminal 102 and the second adjustment circuit output terminal 103 respectively. The first comparator input terminal 210 is the positive electrode of the comparator; the second comparator input terminal 220 is the negative electrode of the comparator. The first comparator input terminal 210 is connected to the first adjustment circuit output terminal 102 and receives the first voltage V1, and the second comparator input terminal 220 is connected to the second adjustment circuit output terminal 103 and receives the second voltage V2.

[0061] The output terminal 102 of the first adjustment circuit is electrically connected to the input terminal 101 of the voltage adjustment circuit 100. Figure 1 As shown, both ends of the first circuit S1 can be directly connected to the output terminal 420 of the voltage divider circuit 400 and the first comparator input terminal 210. Therefore, the first voltage V1 transmitted to the first comparator input terminal 210 via the first circuit S1 is the same as the working voltage V0 outputted from the output terminal of the voltage divider circuit 400, that is, V1=V0.

[0062] The voltage bias circuit 110 is connected in series with the step voltage generating circuit 500, and the series circuit is connected to the input terminal 101 of the voltage regulating circuit and the output terminal 103 of the second regulating circuit. Figure 1As shown, the voltage bias circuit 110 and the step voltage generating circuit 500 can be connected in series and arranged on the second circuit S2. The input end of the voltage bias circuit 110 can be electrically connected to the output end 420 of the voltage divider circuit 400. The voltage bias circuit 110 can add a bias voltage to the working voltage V0. The voltage bias circuit 110 is configured to bias the working voltage V0 by ΔV. In other words, the voltage bias circuit 110 can add a bias voltage ΔV to the working voltage V0. Figure 1 The bias voltages shown in are positive voltages.

[0063] The clock circuit 300 is connected to the switch circuit 120. The clock circuit 300 is connected to the switch circuit 120 at a preset clock period T sample The clock pulse is sent to control the on and off of the switch circuit 120 .

[0064] One end of the switch circuit 120 is connected to the output end of the voltage bias circuit 110, and the other end is connected to the second comparator input end 220 as the output end of the voltage adjustment circuit 100. When the switch circuit 120 is turned on, the second voltage V2 outputted from the output end of the voltage bias circuit 110 can be connected to the second comparator input end 220. When the switch circuit 120 is turned off, the second voltage V2 cannot be connected to the second comparator input end 220. As an example, the switch circuit 120 may include at least one field effect transistor or other circuit that can be controlled to turn on and off the power supply.

[0065] One end of the voltage holding circuit 130 is grounded (GND), and the other end is connected to the second circuit S2 between the switch circuit 120 and the second comparator input terminal 220. The voltage holding circuit 130 is used to stabilize the second voltage V2 loaded on the second comparator input terminal 220 when the switch circuit 120 is closed within a preset range within the preset clock cycle after the switch circuit 120 is disconnected. As an example, the voltage holding circuit 130 includes at least one capacitor circuit. For example, Figure 1 In the embodiment, the voltage holding circuit 130 includes a capacitor C hold When the switch circuit 120 is in the closed state, the second circuit S2 is connected to load the second voltage V2 to the second comparator input terminal 220, and the capacitor C hold When the switch is in the off state, the capacitor C hold The voltage V2 is loaded on the second comparator input terminal 220 as the input signal of the second comparator input terminal 220, so that the input signal of the second comparator input terminal 220 is stabilized at the second voltage V2.

[0066] As an example, Figure 3B The voltage V at the output end of a voltage bias circuit provided in an embodiment of the present application is shown. outA comparison diagram of the second voltage V2 loaded onto the second comparator voltage input terminal 220 (ΔV>0). Figure 3B The voltage V at the input of the voltage bias circuit is also shown as a dotted line. in Timing diagram of .

[0067] The pulse signal m1 occurs at time t1. At this time, the voltage of the first comparator input terminal 210 is V1(t1). At the same time, when the pulse signal m1 arrives, the switch circuit 120 is connected, and the voltage of the second comparator input terminal 220 is V2(t1)=V1(t1)+ΔV. At the same time, when the switch circuit 120 is connected, the capacitor C hold Charge the capacitor C hold The voltage across the positive and negative electrodes becomes V2(t1). After the pulse signal m1 ends, the switch circuit 120 is disconnected, and the capacitor C hold The voltage stabilization effect makes the second voltage of the second comparator input terminal 220 basically stable at V2(t1), and the stabilization time is one clock cycle T of the pulse signal. sample , such as the horizontal line L1 in FIG4. As mentioned above, the substantially stable capacitance C hold The voltage stabilization effect can allow the second voltage of the second comparator input terminal 220 to slightly decrease based on V2(t1). The decrease does not exceed the first amplitude. For example, the first amplitude can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t1) or an interval between any two of these numbers.

[0068] The pulse signal m2 occurs at time t2. When the pulse signal m2 arrives, the voltage at the first comparator input terminal 210 is V1(t2), the switch circuit 120 is connected again, and the voltage at the second comparator input terminal 220 increases instantaneously from V2(t1) to the same voltage as the output terminal of the voltage bias circuit, that is, increases to V2(t2)=V1(t2)+ΔV(t2). At the same time, when the switch circuit 120 is connected, the capacitor C hold Charge the capacitor C hold The voltage across the positive and negative electrodes becomes V2 (t2). After the pulse signal m2 ends, the switch circuit 120 is disconnected, and the capacitor C hold The voltage stabilization effect makes the second voltage of the second comparator input terminal 220 basically stable at V2(t2), and the stabilization time is one clock cycle T of the pulse signal. sample , such as the horizontal line L2 in FIG4. As mentioned above, the substantially stable capacitance C holdThe voltage stabilization effect can allow the second voltage of the second comparator input terminal 220 to slightly decrease based on V2(t2). The decrease does not exceed the first amplitude. For example, the first amplitude can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t2) or an interval between any two of them.

[0069] It can be seen from this that the timing diagram of the voltage V2 acting on the second comparator input terminal 220 is as follows: Figure 3B As shown. Since the magnitude of the first voltage V1 is the same as V in The same. Therefore, we can also get the relationship between the first voltage V1 and the second voltage V2. As an example, Figure 3B Also shown in FIG. 1 is a timing diagram of a first voltage V1 loaded on a first comparator input terminal 220 and a second voltage V2 loaded on a second comparator input terminal 220 provided in accordance with an embodiment of the present application.

[0070] refer to Figure 3B At time t2, the switch circuit 120 receives the pulse signal m2 from the clock circuit 300. The pulse signal m2 causes the second voltage to increase from V2(t1) to V2(t2). Figure 3B As shown by the vertical line L3 in . V2 and V1 intersect, and the intersection point is X1. The time corresponding to X1 is t2. Before the moment t2, the first voltage is above the second voltage, that is, the first voltage is greater than the second voltage. After the moment t2, the first voltage is below the second voltage, that is, the first voltage is less than the second voltage. Since the first voltage V1 is loaded on the first comparator input terminal and the second voltage V2 is loaded on the second comparator input terminal, before the pulse signal m2 arrives, the first voltage is greater than the second voltage, and the output 230 of the comparator 200 is a high level; after the pulse signal m2 ends, the first voltage is less than the second voltage, so the output 230 of the comparator 200 is a low level. That is, when the pulse signal m2 arrives, the comparator changes from a high level to a low level. Therefore, the pulse signal m2 can cause the comparator to flip once.

[0071] Continuing to refer to 3B, according to the previous description, the time between the end of the pulse signal m2 and the arrival of the pulse signal m3 (i.e. Figure 3B During this period, the first voltage V1 continues to rise from the intersection point X1. At point X2, the first voltage and the second voltage intersect again. The time corresponding to the intersection point X2 is t x2 That is, at t x2At the moment t3, the comparator flips again. Combined with the previous description, at the moment corresponding to the intersection X1, the output of the comparator flips from a high level to a low level (i.e., a falling edge appears), at the moment corresponding to the intersection X2, the output of the comparator flips from a low level to a high level (i.e., a rising edge appears), and at the moment t3 when the next pulse signal m3 arrives, the output of the comparator flips from a high level to a low level again (i.e., a falling edge appears again).

[0072] In the clock cycle T sample At the beginning of the second voltage V2 is lower than the first voltage V1; in one clock cycle T sample When the rising amplitude of the working voltage V0 exceeds the bias voltage value, the output of the comparator 200 undergoes at least one high-low level flip.

[0073] Note that the above flip is based on the premise that in a clock cycle T sample At the beginning, ΔV makes the step voltage V2 greater than the voltage V1 that floats naturally with V0, and in a clock cycle T sample Within , the variation range of the floating voltage V1 is greater than ΔV, so that V1 and V2 intersect. Under this condition, every time a pulse signal arrives, the output of the comparator flips from high level to low level (i.e., a falling edge appears); between two pulse signals, the output of the comparator flips from low level to high level (i.e., a rising edge appears); when the next pulse signal arrives, the output of the comparator flips from high level to low level again (i.e., a falling edge appears again).

[0074] Combined with the previous description, when Figure 2A The input signal V HV is an AC signal. HV When at the falling edge, the first voltage V1 decreases with time and is less than the second voltage V2 at the beginning of the V1 clock cycle. Therefore, the second voltage V2 is always greater than the first voltage V1, and the output of the comparator 200 always outputs a low level without flipping.

[0075] In summary, when V HV When V is at the rising edge, the output of the comparator can be reversed, that is, the comparator can output a pulse; HV When at the falling edge, the output of the comparator does not flip, that is, the comparator does not output a pulse.

[0076] Therefore, the detection and output circuit 700 detects whether the comparator can output a pulse to obtain V HV Whether the current is at the rising edge or the falling edge.

[0077] In summary, the voltage fluctuation detection circuit provided in the present application uses the voltage bias circuit 110 in the voltage adjustment circuit 100 to add an offset to the working voltage V0. When the switch is closed, the offset will be stored in the capacitor C hold Using the switch, clock signal and capacitor C downstream of the voltage bias circuit 110 hold The offset signal is sampled and held. This makes the slopes of the first voltage signal (direct sample) loaded on the first comparator input terminal and the second voltage loaded on the second comparator input terminal different, so that a crossover occurs within the clock cycle. Each time a crossover occurs, the output of the comparator will flip. The fluctuation of the electrical signal can be determined based on whether the comparator can output a pulse signal, such as whether the electrical signal fluctuates, whether it is a rising edge, or a falling edge.

[0078] In some embodiments, the IC is only allowed to operate at the rising edge of AC. At the falling edge of AC, the IC is not operated. To determine the timing of stopping the IC, the detection circuit needs to detect when the input signal changes from the rising edge to the falling edge. For the input signal V HV For example, it is the transition from the rising edge to the falling edge at the position of the peak 901. Therefore, if the position of the peak 901 can be accurately detected, the transition timing from the rising edge to the falling edge can be known.

[0079] The detection circuit 001 provided in the present application can determine the transition from the rising edge to the falling edge according to the last intersection point of V1 and V2.

[0080] refer to Figure 2A , when V1 approaches the peak value 901, the slope of V1 gradually decreases. As the clock continues, the slope of V1 gradually decreases to zero and continues to decrease to a negative slope. At the end of the rising edge, as the slope of V1 gradually decreases, the first voltage and the second voltage no longer cross, and the output of the comparator no longer flips. That is, the comparator no longer continuously outputs pulses.

[0081] As an example, Figure 2B shows a timing diagram of V1 and V2 provided according to an embodiment of the present application, Figure 2C Shows Figure 2B The enlarged graph of the curves of V1 and V2 in the clock cycle T1, Figure 2D Shows Figure 2B The enlarged diagram of the curves of V1 and V2 in the clock cycle T2. In the clock cycle T1, V1 and V2 intersect, and their intersection point X1 is the last intersection point of V1 and V2 in the rising edge. In the clock cycle T2 immediately following the clock cycle T1 and the rising edge thereafter, V1 and V2 no longer intersect.

[0082] refer to Figure 2C and Figure 2DIt can be seen that: within the clock cycle T1, the change ΔV1 of V1 is greater than the bias voltage ΔV, so V1 and V2 intersect; while within the clock cycle T2, the change ΔV1 of V1 is less than the bias voltage ΔV, so V1 and V2 do not intersect.

[0083] That is, in one clock cycle T sample When the change of the operating voltage is greater than the bias voltage, V1 and V2 will cross, and the output signal of the output terminal will achieve at least one target flip between a high level and a low level.

[0084] As the input signal climbs along the rising edge, the slope of the input signal gradually decreases, so within a clock cycle, the change of the input signal becomes smaller and smaller until it becomes zero. At the position of the peak 901, the slope of the input signal is zero.

[0085] According to the above description, when the change of the working voltage is greater than the bias voltage, V1 and V2 will cross, and when the change of the working voltage is less than the bias voltage, V1 and V2 will not cross. In the process of the input signal climbing along the rising edge, the change of the input signal becomes smaller and smaller until it reaches zero. Since the magnitude of the bias voltage is not zero, before reaching the peak 901, V1 and V2 gradually change from "crossing" to "not crossing". Therefore, there must be a last intersection.

[0086] The position of the peak 901 can be determined according to the position of the last intersection point, that is, the position of the peak 901 can be determined according to the last target flip event that occurs in the comparator.

[0087] Within the duration of a rising edge, the last pulse output by the comparator corresponds to the last crossing of V1 and V2. In other words, the timing when the comparator stops outputting pulses corresponds to the last crossing.

[0088] In summary, the circuit provided by the present application can judge the transition from rising edge to falling edge according to the timing when the comparator stops outputting pulses. The closer the timing of stopping outputting pulses (i.e. the timing when the last intersection occurs) is to the peak, the higher the accuracy of the judgment.

[0089] As an example, Figure 2E According to this application Figure 2A Detailed view of area A in the middle. Reference Figure 2E When the comparator no longer outputs pulses, the second target circuit can be triggered to monitor the output of the comparator. When the comparator starts to output continuous pulses again, the second target circuit can be reset to indicate that it has entered the rising edge again. In this way, the input signal V can be obtained through the output of the second target circuit. HVThe current state of the second target circuit (at a rising edge or a falling edge). As an example, the second target circuit may be a monitoring circuit. As an example, the monitoring circuit may include a power-on inhibit unit or a switch signal inhibit unit. In some embodiments, the switch inhibit unit may include a hardware power-on inhibit circuit, and the switch signal inhibit unit may include a switch signal inhibit circuit on hardware. In some embodiments, the monitoring circuit may also be implemented by controlling a general circuit through software, such as controlling a general circuit through a power-on inhibit program or a switch signal inhibit program to complete the function of the above-mentioned power-on inhibit circuit or switch signal inhibit circuit.

[0090] Based on the analysis above, the position of the last intersection of V1 and V2 in the rising edge is related to the detection accuracy of the detection circuit. The closer the last intersection is to the real peak, the higher the detection accuracy. By selecting the appropriate bias voltage and clock cycle, the last intersection can be made close to the real peak. In practice, the last intersection will more or less deviate from the real peak, so the circuit sampling will more or less miss the actual peak.

[0091] In some embodiments, it can be set that “once it is detected that the comparator has no output pulse, the power-on prohibition unit or the switch signal prohibition unit is started”.

[0092] refer to Figure 2E , the rising edge and the falling edge are switched at the peak 901. Before the switch, it is a rising edge, and after the switch, it is a falling edge. Assume that the clock time corresponding to the peak 901 is t f At time t f In the previous one or more clock cycles, the first voltage and the second voltage no longer cross each other, and the comparator does not output a pulse.

[0093] In order to improve the detection accuracy and ensure that the second target circuit is started at the falling edge, the detection and output circuit 700 can be configured as follows: when the detection result of the detection circuit shows that the comparator is in n consecutive clock cycles T sample When the target flip does not occur in n consecutive clock cycles, the detection circuit outputs a second signal to trigger the second target circuit, wherein n is a natural number not less than 2. That is, when the comparator does not have the target flip in n consecutive clock cycles, the detection and output circuit generates a second signal to indicate that the operating voltage has been converted from a rising edge to a falling edge, wherein n is a natural number not less than 2. For example, the value of n can be 2, 3, 4, 5, 6, 7, 8, 9, 10, and so on.

[0094] Based on the foregoing description, it can be known that the position of the last intersection of V1 and V2 is related to many factors. As an example, factors affecting the position of the last intersection of V1 and V2 include, but are not limited to, the magnitude of the bias voltage, the sampling frequency of the clock pulse, the frequency and peak value of the input signal, and so on. Therefore, the value of n is also related to the above factors. In practical applications, the value of n can be determined based on the magnitude of the bias voltage, the sampling frequency of the clock pulse, the frequency and peak value of the input signal, and the detection accuracy. In practice, the value of n in the range of 1 to 3 can enable the circuit to maintain a high detection accuracy. In other words, in practice, in order to improve the detection accuracy, the timing of the second target circuit being triggered can be delayed by 1-3 sampling periods T compared to the timing of the last pulse output by the comparator. sample .

[0095] refer to Figure 2A The timing of triggering the second target circuit is delayed by 3 clock cycles T compared to the timing of the comparator stopping outputting pulses. sample , it can be ensured that the second target circuit is triggered on the falling edge, increasing the accuracy of the second target circuit being triggered on the falling edge. If the second target circuit is triggered corresponding to the timing of stopping the IC, then it can be ensured that the timing of stopping the IC is on the falling edge and not far from the actual peak position, thereby improving the detection accuracy of the circuit.

[0096] In addition to the timing of stopping the IC, the detection and output circuit 700 can also determine the timing of starting the IC based on the output of the comparator. Taking the switching power supply controller as an example, the switching power supply controller needs to detect the AC line voltage to determine when the AC line voltage is high enough to start the operation of the IC. When the AC line voltage is too low, the switching power supply controller must stop the switching operation to protect the system from excessive stress during operation.

[0097] Start threshold V HV (start) refers to the pre-set conditions that must be met to start the IC operation. When the input voltage V HV Greater than the start threshold V HV (start) will start the IC operation.

[0098] In some embodiments, V HV A spike may appear on the rising edge. Some of the spikes may cause the input voltage V HV Exceeds the start threshold V for a short time HV (start), and when the spike passes, the input voltage V HV may recover to the start threshold V HV (start) is below (i.e., below the start threshold). In this case, if the setting “once the input voltage V is detected” isHV Exceeding the start threshold V HV (start), the IC is immediately started, which will cause an erroneous start. Therefore, in some embodiments of the present application, the detection and output circuit 700 can be configured as follows: when the detection result of the detection and output circuit 700 is displayed in N consecutive clock cycles T sample The target flip occurs in the comparison results, and the operating voltage V HV are not less than the start threshold V HV (start), the detection and output circuit 700 outputs a first signal to start the IC, wherein N is a natural number not less than 2. For example, the value of N can be 2, 3, 4, 5, 6, 7, 8, 9, 10, etc. As an example, the first signal can be configured to control the start of a first target circuit. As an example, the first target circuit can include an IC. As an example, the IC can include a flyback converter.

[0099] That is, according to the circuit provided by the present application, the IC can be started only when the following two conditions are met at the same time.

[0100] Condition 1: In N consecutive clock cycles T sample In the embodiment, the comparison results output by the comparator 200 all show the target flip.

[0101] Condition 2: When each target flip occurs in all target flips that occur in the N consecutive clock cycles, the operating voltage V HV are not less than the start threshold V HV (start).

[0102] For ease of understanding, in the following description of this application, the circuit is introduced by taking N=2 as an example.

[0103] As an example, Figure 2F FIG. 2 shows a timing diagram of various signals when another voltage rising edge detection circuit provided in an embodiment of the present application is working. Figure 2F , V HV The peak J in V HV In t J When the time exceeds V HV (start), after the peak J passes, V HV Back to V HV (start). If the input voltage V HV Exceeding the start threshold V HV (start), the IC is started immediately, that is, at t JIf the IC is started at the same time, it will cause false start.

[0104] According to the above discussion, according to the circuit provided by the present application, the IC can be started only when both condition 1 and condition 2 are satisfied. Taking N=2 as an example, it can be understood that, to avoid false start, the IC must sample 2 consecutive AC line voltages > the start threshold before enabling the operation.

[0105] Specifically, in Figure 2F In the figure, the peak J makes V HV In t J When the startup threshold V HV (start). HV Exceeding the start threshold V HV In the two consecutive clock cycles from (start) (i.e., in clock cycles T1 and T2), the output results of the comparator both have target flips. Based on the previous description, it can be seen that the target flip in clock cycle T1 corresponds to the timing of the intersection X1, and the target flip in clock cycle T2 corresponds to the timing of the intersection X2. Figure 2F , at the time t when the intersection X1 appears X1 , V HV Less than V HV (start), at the time t when the intersection X2 appears X2 , V HV Greater than V HV (start).

[0106] That is, although V HV Exceeding the start threshold V HV Within the two clock cycles from (start) (i.e., clock cycles T1 and T2), the comparator output results all show a target flip (i.e., satisfying condition 1); however, the corresponding V HV Less than V HV (start) (i.e. condition 2 is not satisfied), therefore, the IC cannot be started. In this way, false start is avoided.

[0107] For two consecutive clock cycles T2 and T3, the comparator output results both have target flips in these two consecutive clock cycles. According to the previous discussion, in the two consecutive clock cycles T2 and T3, the first target flip corresponds to the time when the intersection X2 appears, and the second target flip corresponds to the time when the intersection X3 appears. At the time when the intersection X2 appears, t X2 and the time t at which the intersection X2 appears X3 , V HV Both are greater than V HVThat is, for two consecutive clock cycles T2 and T3, the input signal V HV Conditions 1 and 2 are satisfied at the same time, so the IC can be started. This improves the accuracy of the circuit.

[0108] As an example, Figure 2G FIG. 1 shows a circuit structure diagram of a detection and output circuit 700 provided according to an embodiment of the present application. Figure 2G The detection and output circuit 700 may include a comparator 710 , an AND gate circuit 720 , and a counting circuit 730 .

[0109] Comparator 710 is used to compare V HV and V HV(start) When V HV Greater than V HV(start) When the comparator 710 outputs a high level, when V HV Less than V HV(start) When , the comparator 710 outputs a low level.

[0110] The output terminal of the rising edge trigger circuit 600 is connected to the first input terminal of the AND gate circuit 720. Figure 1 The output of the comparator 200 is the output of the rising edge trigger circuit 600. Based on the above description, when the input signal V HV When the current is AC and the voltage is at a rising edge, the comparator 200 can output a pulse including a target flip (eg Figure 2F shown).

[0111] Continue to refer Figure 2G , the output terminal of the comparator 710 is connected to the second input terminal of the AND gate circuit 720.

[0112] Combination Figure 2G The circuit structure and Figure 2F From the timing diagram of and the principle of AND gate circuit 720, it can be understood that: the pulse output by comparator 200 is used as a sampling pulse to perform a target sampling on the comparison result of comparator 710. The time when each sampling pulse in the target sampling occurs corresponds to the time when the target flip occurs, that is, Figure 2F The moment when the intersection points X1, X2, and X3 occur. When the sampling result corresponding to a sampling pulse is high level, it means that the input signal V HV Greater than V HV(start) , that is, when the intersection occurs, V HV Greater than V HV(start) The output signal of the AND gate circuit 720 represents the result of the sampling. That is, when the output of the AND gate circuit 720 is high, it means that the corresponding intersection occurs when V HV Greater than VHV(start) On the contrary, when the output of AND gate circuit 720 is low, it means that the corresponding cross point appears. HV Less than V HV(start) .

[0113] The input terminal of the counting circuit 730 is connected to the output terminal of the AND gate circuit 720, and the output terminal of the counting circuit 730 is connected to the first target circuit 790. As an example, the first target circuit 790 is a flyback converter. The counting circuit 730 is configured to count the number of pulses output by the AND gate circuit 720. If the counting result of the counting circuit 730 shows that there are two consecutive clock cycles T sample If the AND gate circuit 720 outputs a pulse in both clock cycles, it means that the output of the comparator 200 has a target flip in both clock cycles, and the corresponding V HV Both are greater than V HV(start) Therefore, the IC can be started. In summary, sampling 2 consecutive AC line voltages > the start threshold before starting the IC can cleverly avoid false starts.

[0114] It should be noted that the above only lists two conditions that must be met to start the IC. In actual applications, there may be other conditions to start the IC without affecting the core spirit of this application. Figure 2G In the circuit structure shown, the input end of the AND gate circuit 720 can also be connected to signals corresponding to other conditions.

[0115] In some embodiments, the magnitude of ΔV is constant, with the input voltage V in The characteristics are irrelevant.

[0116] As an example, Figure 4A A method for providing two different input groups according to an embodiment of the present application is shown. and Comparison of the outputs corresponding to the two sets of inputs when a constant ΔV is used.

[0117] exist Figure 4A In FIG. 3 , three graphs are shown from left to right. The sampling clock periods in the three graphs are all T sample . Figure 4A The corresponding input signal of the figure on the left is The corresponding bias voltage is ΔV. Figure 4A The middle figure corresponds to the input signal The corresponding bias voltage is ΔV. Figure 4A The corresponding input signal of the figure on the right is The corresponding bias voltage is ΔV'. Figure 4A in,signal The peak value is greater than the signal The peak value, ΔV' is equal to ΔV.

[0118] refer to Figure 4A In the figure on the left, when the input signal is When: in clock cycle T(1), V1 and V2 cross (crossing point X1), and the comparator outputs a pulse; in clock cycle T(2), V1 and V2 cross (crossing point X2), and the comparator outputs a pulse; in clock cycle T(3), V1 and V2 do not cross, and the comparator stops outputting pulses. According to the above description, the detection and output circuit 700 determines the input signal V according to whether the comparator can output a pulse. HV Is the current rising edge or falling edge? If the comparator stops outputting pulses, the next clock pulse (corresponding to Figure 4A When the pulse m4 at time t4 in the left figure arrives, the detection and output circuit 700 outputs a signal indicating that it is at a falling edge. Figure 4A For example, the detection and output circuit 700 will output a signal indicating V at time t4. HV As an example, if the second target circuit is used to monitor the output of the comparator, when the pulse m4 arrives at time t4, the output of the second target circuit will be reversed.

[0119] refer to Figure 4A In the middle figure, when the input signal is When: In clock cycle T(1), V1 and V2 intersect (intersection point Y1), and the comparator outputs a pulse; starting from clock cycle T(2), V1 and V2 no longer intersect, and the comparator stops outputting pulses. According to the above description, the detection and output circuit 700 determines the input signal V according to whether the comparator can output a pulse. HV The current edge is rising or falling. Similarly, if the next clock pulse (corresponding to Figure 4A When the pulse m3 at time t3 in the middle figure arrives, the detection and output circuit 700 outputs a signal indicating that it is at a falling edge. Figure 4A For example, the detection and output circuit 700 will output a signal indicating V at time t3. HV As an example, if the second target circuit is used to monitor the output of the comparator, when the pulse m3 arrives at time t3, the output of the second target circuit will be reversed.

[0120] contrast Figure 4A The left picture and Figure 4A The middle figure shows that when the input signal has a smaller peak value When the same bias voltage ΔV is used, compared with Figure 4A The left figure is composed of Figure 4A The middle figure shows that the time distance of the second target circuit flipping The peak 901 of has a longer band, that is, when the second target circuit flips, In fact, there is a longer band before the rising edge is converted to the falling edge. When the peak value is small, the initial slope is also small. At this time, if the rising edge has ended and the falling edge has begun according to the output result of the comparator, the detection accuracy of the circuit is not very high.

[0121] In some embodiments, the magnitude of ΔV can be the same as V in Related.

[0122] As an example, ΔV can be the same as V in That is, if The peak value is less than The peak value of ΔV2 is also smaller than the value of ΔV1. As an example, Figure 4B FIG. 4 shows a method of ΔV and V according to an embodiment of the present application. in Schematic diagram of the relationship between the peak values. Figure 4B In the embodiment shown, ΔV=K·(V in The peak value of V is shown in Figure 2, where K is a constant value, that is, ΔV is the same as V HV The peak value is linearly positively correlated. It should be noted that Figure 4B The comparison of ΔV and V is only given as an example. HV The positive correlation between the peak values ​​is described in an example line. HV The peak value can also be a nonlinear positive correlation without affecting the core spirit of this application. For example, Figure 4C Another embodiment of the present invention provides another method of ΔV and V in Schematic diagram of the relationship between the peak values. Figure 4C In the example, ΔV is the same as V HV The peak value is positively correlated, but not linearly. Of course, in some embodiments, the size of ΔV can also vary with V in For example, ΔV(t) = K·V in (t).

[0123] Continue to refer Figure 4A ,for Figure 4A The right side of the figure shows that when the input signal has a smaller peak When a smaller bias voltage ΔV' is used: in clock cycle T(1), V1 and V2 cross (crossing point Z1), and the comparator outputs a pulse; in clock cycle T(2), V1 and V2 cross (crossing point Z2), and the comparator outputs a pulse; starting from clock cycle T(3), V1 and V2 no longer cross, and the comparator stops outputting pulses. According to the above description, the detection and output circuit 700 determines the input signal V according to whether the comparator can output a pulse. HV The current edge is rising or falling. Similarly, if the next clock pulse (corresponding to Figure 4A When the pulse m4 at time t4 in the right figure arrives, the detection and output circuit 700 outputs a signal indicating that it is at a falling edge. Figure 4A For example, the detection and output circuit 700 outputs a signal indicating V at time t4. HV As an example, if the second target circuit is used to monitor the output of the comparator, when the pulse m4 arrives at time t4, the output of the second target circuit will be reversed.

[0124] contrast Figure 4A The middle picture and Figure 4A The figure on the right shows that when the input signal has a smaller peak value When a smaller bias voltage ΔV' is used, compared with Figure 4A The middle picture, Figure 4A In the figure on the right, the moment when the output signal of the second target circuit flips is delayed by one clock cycle T sample , the input signal V corresponding to the moment when the output signal of the second target circuit flips HV Compared to Figure 4A The middle graph is closer to the peak 901, which improves the detection accuracy of the circuit.

[0125] In summary, the present application provides a voltage fluctuation detection circuit that can detect the voltage of an AC line.

[0126] First, the circuit has a simple structure and a small number of components, which can reduce IC cost and volume.

[0127] Secondly, the circuit has high accuracy and can strike a balance between circuit complexity, detection accuracy, sufficiently fast detection speed, and low cost to achieve the best performance and IC cost balance. For example, as long as a reasonable ΔV value and sampling clock T are set sample The frequency of the pulse output by the comparator can be controlled.

[0128] Furthermore, for analog ICs (including, but not limited to, switching power supply controllers, audio and video amplifiers, signal converters, etc.), if digital circuits are used to sample and detect the characteristics of electrical signals, adding digital design to the analog IC will increase the cost of the IC. The detection circuit provided by the present application has an input signal V HV It can be an analog signal. When applied to an analog IC, it can greatly reduce the complexity of the analog IC, thereby achieving a balance between circuit complexity, detection accuracy, sufficiently fast detection speed, and low cost, and achieving the best performance and IC cost balance.

[0129] It should be noted that the above only introduces the principle of the voltage detection circuit provided by the present application by taking the rising edge as an example. The voltage detection circuit provided by the present application can also detect the falling edge to realize the detection of the input signal. If the input signal is at the falling edge, if the circuit is constructed so that in the clock period T sample At the beginning, the first voltage is higher than the second voltage, and within one clock cycle, when the drop amplitude of the first voltage V1 exceeds the bias voltage value, the output of the comparator flips between high and low levels at least once.

[0130] For example, you can Figure 1 The bias voltage in is set to -ΔV. At this time, at the start time of the clock cycle Tsample, the first voltage is higher than the second voltage, and within one clock cycle, when the drop amplitude of the first voltage V1 exceeds the bias voltage value amplitude ΔV, the output of the comparator 200 flips between high and low levels at least once. Figure 5 A circuit structure schematic diagram of another voltage fluctuation detection circuit 002 provided according to an embodiment of the present application is shown.

[0131] refer to Figure 5 The voltage bias circuit 110 is arranged on the first circuit S1. At this time, the voltage bias circuit 110 is connected in series with the first adjustment circuit output terminal 102 and the adjustment circuit input terminal 101. That is, the two ends of the voltage bias circuit 110 are connected to the adjustment circuit input terminal 101 and the first adjustment circuit output terminal 102 respectively.

[0132] The step voltage generating circuit 500 is arranged on the second circuit S2. At this time, the step voltage generating circuit 500 is connected in series with the adjusting circuit input terminal 101 and the second adjusting circuit output terminal 103. That is, the two ends of the step voltage generating circuit 500 are connected to the adjusting circuit input terminal 101 and the second adjusting circuit output terminal 103 respectively. Figure 5 , the first comparator input terminal 210 is the positive electrode of the comparator, the second comparator input terminal 220 is the negative electrode of the comparator, and the bias voltage is a negative voltage -ΔV.

[0133] As an example, Figure 6 Shows Figure 5 A comparison diagram of the operating voltage V0, the first voltage V1 and the second voltage V2 in the circuit structure in FIG.

[0134] The voltage bias circuit 110 adds the bias voltage to the working voltage V0 to generate the first voltage V1. The bias voltage is a negative value, and its absolute value is equal to ΔV, that is, the bias voltage is -ΔV. Then, V1 = V0-ΔV. The timing diagram of the first voltage V1 is as follows: Figure 6 As shown in V1.

[0135] The step voltage generating circuit 500 acts on the working voltage signal V0 to generate a stepped second voltage V2 by causing the working voltage signal V0 to generate a stepped second voltage V2.

[0136] refer to Figure 5 and Figure 6 When the clock pulse m1 arrives, the switch Q1 is connected, the second voltage V2 is the same as the working voltage V0 and is V2(t1). When the switch Q1 is connected, the capacitor C hold is charged to V2(t1); after the clock pulse m1 ends, switch Q1 is disconnected, and capacitor C hold The voltage of the negative electrode of the comparator is basically maintained at V2(t1) (i.e. Figure 6 The holding time is one clock cycle T of the clock pulse. sample The basic stability represents the capacitance C hold The voltage stabilization effect can allow the second voltage of the second comparator input terminal 220 to drop slightly on the basis of V2(t1). The drop does not exceed the first amplitude. For example, the first amplitude can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10% of ΔV(t1) or the interval between any two numbers. Figure 6 It can be seen that the clock cycle T corresponding to the horizontal line L1 sample At the beginning, the first voltage V1 is lower than the second voltage V2. sample During the period, the working voltage V0 rises along the rising edge, and the first voltage V1 also rises along the rising edge. During this period, the second voltage V2 is on the capacitor C hold As the first voltage V1 rises, the first voltage V1 crosses the second voltage V2 (the crossing point is X1) in the clock cycle, and the comparator flips.

[0137] When the clock pulse m2 arrives, the switch Q1 is connected, and the second voltage V2 increases instantaneously to the same as the working voltage V0, that is, increases to V2(t2). Before the clock pulse m2 arrives, the second voltage V2 is V2(t1). The arrival of the clock pulse m2 causes the second voltage V2 to increase instantaneously from V2(t1) to V2(t2). Before the increase, the value of the second voltage V2(t1) is less than the first voltage V1, that is, the positive voltage of the comparator is greater than the negative voltage, and the comparator outputs a high level; after the increase, the value of the second voltage V2(t2) is greater than V1, that is, the positive voltage of the comparator is less than the negative voltage, and the comparator outputs a low level. In other words, the arrival of the clock pulse m2 causes the first voltage V1 and the second voltage V2 to cross once (the intersection point is X2), and the comparator flips once.

[0138] At the same time, the clock pulse m2 reaches the capacitor C when the switch Q1 is turned on. hold is charged, so that the capacitor C hold The voltage across the positive and negative electrodes becomes V2(t2); after the clock pulse m2 ends, switch Q2 is disconnected, and capacitor C hold The second voltage V2 loaded on the negative electrode of the comparator is maintained at V2(t2) (i.e. Figure 6 The holding time is one clock cycle T of the clock pulse. sample .

[0139] In summary, by using a negative bias voltage, the first voltage and the second voltage can also cross within the clock cycle, causing the comparator to flip, so that the input signal can be judged as a DC signal or an AC signal based on the output of the comparator (such as whether the comparator can output pulses and the number of output pulses).

[0140] It should be noted that, for the sake of convenience of description, the above text uses "the first comparator input terminal is the positive electrode of the comparator; the second comparator input terminal is the negative electrode of the comparator" as an example to illustrate the principle of the voltage rising edge detection circuit. The first comparator input terminal can be the negative electrode of the comparator, and the second comparator input terminal can be the positive electrode of the comparator without affecting the core spirit of this application.

[0141] In addition, you can Figure 5 The bias voltage in is set to +ΔV to detect the falling edge of the working voltage V0. sample At the beginning, the first voltage is higher than the second voltage, and within one clock cycle, when the drop amplitude of the first voltage V1 exceeds the bias voltage amplitude ΔV, the output of the comparator 200 flips between high and low levels at least once.

[0142] Figure 7A circuit structure schematic diagram of another voltage fluctuation detection circuit 003 provided according to an embodiment of the present application is shown. Figure 7 The circuit structure shown is the same as Figure 1 The circuit structures shown are similar, except that: Figure 7 The output terminal of the first voltage regulating circuit is connected to the input terminal of the first comparator, wherein the input terminal of the first comparator is the negative electrode of the comparator; Figure 7 The output terminal of the second voltage adjustment circuit in the circuit is connected to the input terminal of the second comparator, wherein the input terminal of the second comparator is the positive electrode of the comparator. That is, the voltage bias circuit 110 is connected in series with the step voltage generating circuit 500 and is arranged on the first circuit S1. Therefore, the first voltage is loaded to the negative electrode of the comparator, and the second voltage is loaded to the positive electrode of the comparator.

[0143] Figure 3B The comparison diagram of the first voltage and the second voltage shown is applicable to Figure 7 Circuit structure. Figure 3B It can be seen that the use of Figure 7 In the circuit structure, every time a clock cycle arrives, the comparator flips once when the clock cycle arrives, and the comparator flips again within the clock cycle. Figure 7 In the circuit shown, taking the pulse signal m2 as an example, before the pulse signal m2 arrives, the second voltage V2(t1) is less than the first voltage V1, that is, the positive voltage of the comparator is less than the negative voltage, and the comparator outputs a low level; the arrival of the pulse signal m2 causes the second voltage to increase from V2(t1) to V2(t2) instantaneously, and the increased second voltage V2(t2) is greater than the first voltage V1, that is, the positive voltage of the comparator is greater than the negative voltage of the comparator, and the comparator outputs a high level. In other words, the arrival of the pulse signal m2 causes the comparator to flip from a low level to a high level. After the pulse signal m2 ends, the second voltage is at the capacitor C hold Under the action of , the second voltage remains at V2(t2). As the first voltage climbs along the rising edge, the second voltage and the first voltage cross again (crossing point X2). Before the crossing point X2, the second voltage is greater than the first voltage, that is, the positive voltage of the comparator is greater than the negative voltage of the comparator, and the comparator outputs a high level; after the crossing point X2, the second voltage is less than the first voltage, that is, the positive voltage of the comparator is less than the negative voltage of the comparator, and the comparator outputs a low level. That is, in the clock cycle T sample The comparator flips from high level to low level.

[0144] That is, when the clock pulse arrives, the comparator flips from low level to high level, and before the next clock pulse arrives, the comparator flips from high level to low level. Therefore, it is also possible to determine whether the input signal is a DC signal or an AC signal based on the output of the comparator (such as whether the comparator can output pulses and the number of pulses output).

[0145] In addition, you can Figure 7 The bias voltage in is set to -ΔV to detect the falling edge of the working voltage V0. sample At the beginning, the first voltage is higher than the second voltage, and within one clock cycle, when the drop amplitude of the first voltage V1 exceeds the bias voltage amplitude ΔV, the output of the comparator 200 flips between high and low levels at least once.

[0146] Figure 8 A circuit structure schematic diagram of another voltage fluctuation detection circuit 004 provided according to an embodiment of the present application is shown. Figure 8 The circuit structure shown is the same as Figure 5 The circuit structures shown are similar, except that: Figure 8 The output terminal of the first voltage regulating circuit is connected to the input terminal of the first comparator, wherein the input terminal of the first comparator is the negative electrode of the comparator; Figure 8 The output terminal of the second voltage adjustment circuit is connected to the input terminal of the second comparator, wherein the second comparator input terminal is the positive electrode of the comparator. In other words, the first voltage is loaded to the negative electrode of the comparator, and the second voltage is loaded to the positive electrode of the comparator. Figure 8 The analysis can refer to Figure 5 For the sake of brevity, the analysis will not be repeated.

[0147] In summary, the voltage fluctuation detection circuit provided in the present application uses the voltage bias circuit 110 in the voltage adjustment circuit 100 to add an offset to the working voltage V0. When the switch is closed, the offset will be stored in the capacitor C hold Using the switch, clock signal and capacitor C downstream of the voltage bias circuit 110 hold The offset signal is sampled and held. This makes the slopes of the first voltage signal (direct sample) loaded on the first comparator input terminal and the second voltage loaded on the second comparator input terminal different, so that a crossover occurs within the clock cycle. Each time a crossover occurs, the output of the comparator will flip. The fluctuation of the electrical signal can be determined based on whether the comparator can output a pulse signal, such as whether the electrical signal fluctuates, whether it is a rising edge, or a falling edge.

[0148] The present application provides a voltage fluctuation detection circuit that can detect the voltage of an AC line. The circuit has a simple structure and a small number of components, which can reduce IC cost and volume. The circuit has high accuracy and can strike a balance between circuit complexity, detection accuracy, sufficiently fast detection speed, and low cost to achieve optimal performance and IC cost balance. For example, as long as a reasonable ΔV value and sampling clock T are set sample The frequency of the pulse output by the comparator can be controlled.

[0149] For analog ICs (including, but not limited to, switching power supply controllers, audio and video amplifiers, signal converters, etc.), if digital circuits are used to sample and detect the characteristics of electrical signals, adding digital design to the analog IC will increase the cost of the IC. The detection circuit provided by the present application has an input signal V HV It can be an analog signal. When applied to an analog IC, it can greatly reduce the complexity of the analog IC, thereby achieving a balance between circuit complexity, detection accuracy, sufficiently fast detection speed, and low cost, and achieving the best performance and IC cost balance.

[0150] The voltage fluctuation rising edge detection circuit provided in the present application can be used in an AC-DC controller. The voltage fluctuation rising edge detection circuit can detect whether the working current of the AC-DC controller is AC or DC, thereby expanding the working current of the AC-DC controller from DC to DC and AC.

[0151] The basic concepts have been described so far, and it may be more apparent to those skilled in the art after reading this detailed disclosure that the above detailed disclosure is intended to be presented only by way of example and not by way of limitation. Although not explicitly stated herein, various changes, improvements and modifications are desired and may be made by those skilled in the art. For example, the steps in the method of the present disclosure may not necessarily be operated in the order described. These steps may also be partially operated and / or operated in other combinations reasonably expected by those of ordinary skill in the art. These changes, improvements and modifications are intended to be proposed by the present disclosure and fall within the spirit and scope of the exemplary embodiments of the present disclosure.

[0152] In addition, certain terms have been used to describe embodiments of the present disclosure. For example, the terms "an embodiment," "an embodiment," and / or "some embodiments" indicate that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Therefore, it should be emphasized and understood that two or more references to "an embodiment," "an embodiment," or "an alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. In addition, particular features, structures, or characteristics may be appropriately combined in one or more embodiments of the present disclosure.

[0153] In addition, those skilled in the art will recognize that aspects of the disclosure may be illustrated and described herein in any of a number of patentable categories or contexts, including any new and useful process, machine, manufacturing or composition problem, or any new and useful improvement thereof. Accordingly, aspects of the disclosure may be implemented entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or software and hardware implementations may be combined, all of which are generally referred to herein as "blocks," "modules," "engines," "units," "components," or "systems." In addition, aspects of the disclosure may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0154] Furthermore, the order of the processing elements or sequences recited, or the numbers, letters, or other designations used therefor, are not intended to limit the claimed processes and methods to any order except as may be specified in the claims. Although the above disclosure discusses various useful embodiments of what are currently considered to be the present disclosure through various examples, it should be understood that such detail is for that purpose only and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover modifications and equivalent arrangements within the spirit and scope of the disclosed embodiments. For example, although the implementation of the various components described above may be embodied in a hardware device, it may also be implemented as a software-only solution, for example, installation on an existing server or mobile device.

[0155] Similarly, it should be understood that in the foregoing description of the embodiments of the present disclosure, various features are sometimes combined in a single embodiment, figure, or description thereof to simplify the present disclosure to aid in understanding one or more of the various inventive embodiments. However, the disclosed approach should not be interpreted as reflecting an intention that the claimed subject matter requires more features than those explicitly recited in each claim. Rather, an inventive embodiment has less than all of the features of a single foregoing disclosed embodiment.

Claims

1. A voltage fluctuation detection circuit, characterized in that: include: An upper edge trigger circuit comprises an input terminal and an output terminal, wherein the upper edge trigger circuit detects an operating voltage received by the input terminal in a preset clock cycle, and when a change of the operating voltage is greater than a preset bias voltage within one of the clock cycles, an output signal of the output terminal realizes at least one target flip between a high level and a low level; as well as A detection and output circuit is connected to the output end of the rising edge trigger circuit, detects the change of the working voltage and the target flip, and outputs a control signal according to the detection result, wherein when the detection result of the detection and output circuit shows In N consecutive clock cycles, the output signal of the rising edge trigger circuit shows the target flip, and When each of the target flips in all the target flips occurring in the N consecutive clock cycles occurs, the operating voltage is not less than the start threshold, The detection and output circuit generates a first signal, wherein N is a natural number not less than 2; When the comparator does not experience the target flip within n consecutive clock cycles, the detection and output circuit generates a second signal to indicate that the operating voltage has switched from a rising edge to a falling edge, wherein n is a natural number not less than 2.

2. The voltage fluctuation detection circuit according to claim 1, characterized in that: The first signal is configured to control the startup of a first target circuit.

3. The voltage fluctuation detection circuit according to claim 1, characterized in that: in, The detection and output circuit includes a second target circuit. When the comparator does not have the target flip within n consecutive clock cycles, the second target circuit is triggered to indicate that the operating voltage has been converted from a rising edge to a falling edge.

4. The voltage fluctuation detection circuit according to claim 1, characterized in that: The rising edge trigger circuit comprises: Adjustment circuit, including The input end of the adjustment circuit receives a working voltage, wherein the working voltage is an AC voltage. The first adjustment circuit output terminal outputs a first voltage, and The output terminal of the second adjustment circuit outputs a stepped second voltage; Comparators, including A first comparator input terminal receives the first voltage, a second comparator input terminal receiving the second voltage, and The comparator output terminal outputs a comparison result of the first voltage and the second voltage, wherein the second voltage differs from the first voltage by the bias voltage at the beginning of a preset clock cycle and the second voltage does not drop by more than a first amplitude within the clock cycle.

5. The voltage fluctuation detection circuit according to claim 4, characterized in that: The magnitude of the bias voltage is positively correlated with the amplitude of the first voltage.

6. The voltage fluctuation detection circuit according to claim 4, characterized in that: The target flipping includes flipping from a low level to a high level, wherein: At the moment when the clock cycle starts, the first voltage is lower than the second voltage, and the comparator outputs a low level; and In one of the clock cycles, when the rising amplitude of the first voltage exceeds the bias voltage value, the output of the comparator flips from a low level to a high level.

7. The voltage fluctuation detection circuit according to claim 4, characterized in that: The target flipping includes flipping from a high level to a low level, wherein: At the moment when the clock cycle starts, the first voltage is higher than the second voltage, and the comparator outputs a high level; and In one of the clock cycles, when the drop amplitude of the first voltage exceeds the bias voltage value, the output of the comparator flips from a high level to a low level.

8. The voltage fluctuation detection circuit according to claim 4, characterized in that: The adjustment circuit comprises: a voltage bias circuit that adds the bias voltage to an input voltage of the voltage bias circuit; and The step voltage generating circuit converts a voltage input to the step voltage generating circuit into a step voltage.

9. The voltage fluctuation detection circuit according to claim 8, characterized in that: The step voltage generating circuit comprises: a switch circuit; a clock circuit connected to the switch circuit and controlling the switch circuit to open and close according to the clock cycle to generate the second voltage; and A voltage holding circuit is connected to the switch circuit and maintains the second voltage after the switch circuit is disconnected so that the second voltage does not drop by more than the first amplitude within the clock cycle.

10. The voltage fluctuation detection circuit according to claim 9, characterized in that: in: The voltage bias circuit includes at least one of a voltage-controlled voltage source and a voltage-controlled current source; The switch circuit includes at least one field effect transistor; and The voltage holding circuit includes at least one capacitor.

11. The voltage fluctuation detection circuit according to claim 8, wherein: The output terminal of the first adjustment circuit is electrically connected to the input terminal of the adjustment circuit; and The voltage bias circuit is connected in series with the step voltage generating circuit, and the series circuit is connected to the input end of the regulating circuit and the output end of the second regulating circuit.

12. The voltage fluctuation detection circuit according to claim 11, characterized in that: The first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a positive voltage; or The first comparator input terminal is a negative electrode of the comparator, the second comparator input terminal is a positive electrode of the comparator, and the bias voltage is a positive voltage.

13. The voltage fluctuation detection circuit according to claim 8, wherein: The voltage bias circuit is connected in series with the output terminal of the first adjustment circuit and the input terminal of the adjustment circuit; and The step voltage generating circuit is connected in series with the input end of the regulating circuit and the output end of the second regulating circuit.

14. The voltage fluctuation detection circuit according to claim 13, wherein: The first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a negative voltage; or The first comparator input terminal is the positive electrode of the comparator, the second comparator input terminal is the negative electrode of the comparator, and the bias voltage is a negative voltage.

15. The voltage fluctuation detection circuit according to claim 1, characterized in that: It also includes a voltage divider circuit, one end of which is connected to the input voltage, and the other end is connected to the ground line. The voltage divider circuit divides the input voltage into the working voltage output.

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