Memory operation condition checking method

Abstract

A method for checking memory operation conditions, implemented by a memory operation condition checking device, enables the central processing unit (CPU) on the motherboard to more precisely adjust the correct supply voltage provided to each device under test (DUT) memory module through the voltage measurement values feedback by the measurement unit disposed at the input voltage (VDD, VDDQ, and VPP) supply terminals of several DUT memory modules, enabling the central processing unit to achieve the highest efficiency. By using the three operating voltages VDD, VDDQ, and VPP to solve the problem of memory power supply voltage deviation, it is possible to precisely adjust the correct supply voltage input to each DUT memory module during mass production testing, so as to achieve consistent calibration.

Description

Technical Field

[0001] The present invention relates to a method for checking memory operation conditions, and particularly to a method for solving the problem of memory power supply voltage deviation with three operating voltages of VDD, VDDQ, and VPP, which can more precisely adjust the correct supply voltage provided to each memory module under test, enabling the central processing unit to achieve the highest efficiency. In particular, it refers to a method that can precisely adjust the correct supply voltage input to each memory module under test during mass production testing to achieve consistent calibration. Background Art

[0002] In a semiconductor device such as a dynamic random access memory (DRAM), the memory die can be mounted on a motherboard and receive power supply from a central processing unit (CPU). The externally supplied power can be transmitted to a power management circuit (PMC), which manages the power supplied to the components of the memory system. Power can be supplied to different components operating at different voltages and having different current requirements. Among them, the power supply terminals VDD and VDDQ on the motherboard are usually equal values (1.2V), and in general use, VDDQ and VDD are combined into one power supply for use. However, due to the influence of factors such as program changes and terminal load voltage, the voltage of the power supply may deviate from the value set by the pulse width modulation (PWM) unit in the power management circuit.

[0003] In view of the inevitable voltage deviation that occurs in the path from the power output of the power management circuit to the memory input, making the actual value reaching the memory end unknown, and the prior art does not measure this. Even though the PWM itself generates a feedback voltage, only the set value just output can be known, but the value received at the end memory has been affected and deviated by the terminal load voltage during operation. Therefore, the power consumption of each memory itself cannot be correctly known.

[0004] Regarding the lack that the prior art does not measure the voltage value from the output of the power management circuit to the memory input to compensate for the power supply voltage deviation, generally, it cannot meet the requirement of precisely adjusting the correct voltage value input to each memory end by the user to achieve consistent calibration during actual use. Summary of the Invention

[0005] The main object of the present invention is to overcome the above problems encountered in the known art and provide a method for checking memory operation conditions, which can more precisely adjust the correct supply voltage provided to each memory module under test, enabling the central processing unit to achieve the highest efficiency. By using three operating voltages, namely VDD, VDDQ, and VPP, to solve the problem of memory power supply voltage deviation, it is possible to accurately adjust the correct supply voltage input to each memory module under test during mass production testing, so as to achieve consistent calibration.

[0006] Another object of the present invention is to provide a method for checking memory operation conditions, which can accurately monitor the reference voltage (V REF ) and other parameters during operation. By quickly changing the operation conditions, it is possible to quickly change the frequency of the Basic Input and Output System (BIOS) and the setting of the latency time (CAS latency, CL), thereby effectively testing the operation capabilities under various conditions.

[0007] To achieve the above objects, the technical solution adopted by the present invention is: a method for checking memory operation conditions, which is implemented by a memory operation condition checking device. The method includes the following steps:

[0008] Step 1: Provide several original supply voltages to several memory modules under test (device under test, DUT) installed on the motherboard via a power management integrated circuit (PMIC). Each memory module under test includes a first input voltage (VDD) supply terminal, a second input voltage (VDDQ) supply terminal, and a third input voltage (VPP) supply terminal. Each of the original supply voltages is input to the first to third input voltage supply terminals of each memory module under test, and each of the original supply voltages includes VDD, VDDQ, and VPP.

[0009] Step 2: Enable each measurement unit coupled to the first to third input voltage supply terminals of each memory module under test. Each measurement unit includes a first measurement component coupled to the first input voltage supply terminal, a second measurement component coupled to the second input voltage supply terminal, and a third measurement component coupled to the third input voltage supply terminal.

[0010] Step 3: Use each measurement unit to measure the input voltage and current of the first to third input voltage supply terminals of each memory module under test to generate corresponding current supply voltages and feedback them to the central processing unit (CPU).

[0011] Step 4: The central processing unit receives the current supply voltages feedback from each measurement unit, compares these current supply voltages with the corresponding original supply voltages, and generates corresponding compensation voltages according to the comparison results.

[0012] Step 5: For the memory module under test related to the compensation voltage, the central processing unit controls the power management chip to provide the compensation voltage to the corresponding memory module under test for compensation, so as to accurately adjust the correct supply voltage input to each memory module under test.

[0013] In the above embodiments of the present invention, the central processing unit is respectively connected to each memory module under test, the power management chip and each measurement unit, and the power management chip is connected to each memory module under test.

[0014] In the above embodiments of the present invention, a storage component is built in the central processing unit, and the original supply voltages provided by the power management chip to each memory module under test and the compensation voltages provided to the corresponding memory modules under test can be managed by software.

[0015] In the above embodiments of the present invention, the measurement unit is a digital multimeter (DMM).

[0016] In the above embodiments of the present invention, the first to third measurement components respectively apply a resistance value to measure the input voltages and currents of the first to third input voltage supply terminals connected correspondingly, and generate corresponding current supply voltages according to the change of the intermediate bias voltage of the resistance value.

[0017] In the above embodiments of the present invention, the resistance value is 8 to 12 milliohms. Brief Description of the Drawings

[0018] Figure 1 is a flowchart of the present invention.

[0019] Figure 2 is a schematic diagram of the architecture of the present invention.

[0020] Label Correspondence:

[0021] Memory module under test 1

[0022] First input voltage supply terminal 11

[0023] Second input voltage supply terminal 12

[0024] Third input voltage supply terminal 13

[0025] Power management chip 2

[0026] Measurement unit 3

[0027] The first measurement component 31

[0028] The second measurement component 32

[0029] The third measurement component 33

[0030] Central processing unit 4

[0031] Storage component 41. Detailed implementation manner

[0032] Please refer to Figure 1 and Figure 2 shown, which are respectively the flow schematic diagram of the present invention and the block schematic diagram of the present invention. As shown in the figure: The present invention is a method for checking memory operation conditions, which is implemented by a memory operation condition checking device, and includes several devices under test (DUT) 1, a power management integrated circuit (PMIC) 2, several measurement units 3, and a central processing unit 4 (central processing unit, CPU). This memory operation condition checking method includes the following steps:

[0033] Step s1: The power management chip 2 supplies several original supply voltages to several devices under test 1, where each device under test 1 is installed on the main board and connected to the power management chip 2. Each device under test 1 includes a first input voltage (VDD) supply terminal 11, a second input voltage (VDDQ) supply terminal 12, and a third input voltage (VPP) supply terminal 13. Each original supply voltage is input to the first to third input voltage supply terminals 11-13 of each device under test 1, and each original supply voltage includes VDD, VDDQ, and VPP.

[0034] Step s2: Enable each measurement unit 3 coupled to the first to third input voltage supply terminals 11-13 of each device under test 1, where each measurement unit 3 includes a first measurement component 31 coupled to the first input voltage supply terminal 11, a second measurement component 32 coupled to the second input voltage supply terminal 12, and a third measurement component 33 coupled to the third input voltage supply terminal 13.

[0035] Step Three S3: Use each measurement unit 3 to measure the input voltages and currents of the first to third input voltage supply terminals 11-13 of each memory module 1 to be tested, so as to generate corresponding current supply voltages and feedback them to the central processing unit 4 (central processing unit, CPU), where the central processing unit 4 is respectively connected to the memory module 1 to be tested, the power management chip 2 and the measurement unit 3. There is a storage component 41 built therein, and the original supply voltage provided to each memory module 1 to be tested can be managed by the power management chip 2 through software control.

[0036] Step Four S4: The central processing unit 4 receives the current supply voltages sent by each measurement unit 3, compares these current supply voltages with the original supply voltages corresponding to the first to third input voltage supply terminals 11-13 of each memory module 1 to be tested, and generates corresponding compensation voltages according to the comparison results.

[0037] Step Five S5: For the memory module 1 to be tested related to the compensation voltage, the central processing unit 4 manages the power management chip 2 through the storage component 41 to control the power management chip 2 to compensate the memory module 1 to be tested corresponding to the compensation voltage, so as to accurately adjust the correct supply voltage input to each memory module 1 to be tested. Thus, a new memory operation condition inspection method is formed by the above disclosed process.

[0038] When in use, in order to more accurately measure the power consumption of each memory module 1 to be tested, the present invention separates the operating voltages VDD and VDDQ that are usually combined on a traditional motherboard, and measures the input voltages and currents according to the three separate first to third input voltage supply terminals 11-13 of VDD, VDDQ and VPP of each memory module 1 to be tested. In a preferred embodiment, the present invention sets several measurement units 3, for example: digital multimeters (digital multimeter, DMM). Each measurement unit 3 is correspondingly coupled with three first to third measurement components 31-33 for measurement on the first to third input voltage supply terminals 11-13 closest to each memory module 1 to be tested on the motherboard, so as to measure the input voltages and currents of the first to third input voltage supply terminals 11-13 of each memory module 1 to be tested at the end, so as to generate corresponding current supply voltages. In this embodiment, although a digital multimeter is used as the description of the measurement unit 3, however, the types of the above measurement units 3 are only examples of listing the current mainstream current measurement components, and other components not mentioned but having the same or similar functions should also be regarded as within the scope covered by the present invention.

[0039] The above measurement unit 3 applies a resistance value of 8 to 12 milliohms (mΩ) to the first to third measurement components 31 to 33 respectively to measure the input voltage and current of the corresponding coupled first to third input voltage supply terminals 11 to 13, and generates a corresponding current supply voltage according to the change of the intermediate bias of the resistance value. Each measurement unit 3 then feeds back the measured current supply voltage to the central processing unit 4. The central processing unit 4 compares the current supply voltage of each memory module 1 to be measured fed back by each measurement unit 3 (for example: 1.19 V) with the original supply voltage (for example: 1.2 V) previously set by the power management chip 2 supplied to each memory module 1 to be measured. After obtaining the voltage deviation value (ΔV = 1.2 - 1.19 = 0.01) generated between the output terminal of the power management chip 2 and the input terminal of each memory module 1 to be measured, a corresponding compensation voltage (for example: 0.01 V) is generated. The central processing unit 4 then controls the power management chip 2 to compensate for the memory module 1 to be measured corresponding to the compensation voltage through the storage component 41, and makes corrections according to whether the voltage needs to be increased or decreased. There is no such technology in the traditional method. Through the feedback of the above measurement values, the motherboard of the present invention can more accurately adjust the correct supply voltage provided to each memory module 1 to be measured, enabling the central processing unit 4 to achieve the highest efficiency, and solving the problem of memory power supply voltage deviation with these three operating voltages VDD, VDDQ, and VPP. Thus, during mass production testing, the correct supply voltage input to each memory module 1 to be measured can be accurately adjusted to achieve consistent calibration.

[0040] Thereby, the present invention can accurately monitor the reference voltage (V REF ) and other parameters during operation. By quickly changing the operating conditions, the frequency and latency time (CAS latency, CL) settings of the Basic Input and Output System (BIOS) can be quickly changed, thereby enabling effective testing of the operating capabilities under various conditions.

[0041] In summary, a method for checking memory operating conditions according to the present invention can effectively improve various shortcomings of the prior art. The central processing unit on the motherboard can more accurately adjust the correct supply voltage provided to each memory module to be measured through the voltage measurement values fed back by the measurement components arranged at the input voltage (VDD, VDDQ, and VPP) supply terminals of each memory module to be measured, enabling the central processing unit to achieve the highest efficiency, and solving the problem of memory power supply voltage deviation with the three operating voltages VDD, VDDQ, and VPP. Thus, during mass production testing, the correct supply voltage input to each memory module to be measured can be accurately adjusted to achieve consistent calibration, and further making the present invention more advanced, more practical, and more in line with the needs of users. It indeed meets the requirements for patent application for invention patents, and a patent application is filed according to law.

[0042] However, the above are only the preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited thereby. Therefore, all simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the invention specification shall still fall within the scope covered by the patent of the present invention.

Claims

1. A method for checking memory operation conditions, which is implemented by a memory operation condition checking device, characterized in that The method comprises the following steps: Step 1: A power management chip provides several original supply voltages to several memory modules under test mounted on a main board. Each memory module under test includes a first input voltage supply terminal, a second input voltage supply terminal, and a third input voltage supply terminal. Each of the original supply voltages is input to the first to third input voltage supply terminals of each memory module under test, and each of the original supply voltages includes VDD, VDDQ, and VPP. The first input voltage supply terminal is the VDD supply terminal, the second input voltage supply terminal is the VDDQ supply terminal, and the third input voltage supply terminal is the VPP supply terminal; Step 2: Enable each measurement unit coupled to the first to third input voltage supply terminals of each memory module under test. Each measurement unit includes a first measurement component coupled to the first input voltage supply terminal, a second measurement component coupled to the second input voltage supply terminal, and a third measurement component coupled to the third input voltage supply terminal; Step 3: Use each measurement unit to apply a resistance value measurement to the input voltage and current of the first to third input voltage supply terminals of each corresponding memory module under test with the first to third measurement components, and generate a corresponding current supply voltage according to the change of the middle bias of the resistance value and feedback it to the central processing unit; Step 4: The central processing unit receives the current supply voltages of each memory module under test sent by each measurement unit, compares these current supply voltages with the original supply voltages corresponding to the first to third input voltage supply terminals of each memory module under test, and generates a corresponding compensation voltage according to the comparison result; Step 5: For the memory module under test related to the compensation voltage, the central processing unit controls the power management chip to provide the compensation voltage to the corresponding memory module under test for compensation, so as to accurately adjust the correct supply voltage input to each memory module under test.

2. The memory operation condition checking method according to claim 1, wherein The central processing unit is respectively connected to each memory module under test, the power management chip, and each measurement unit, and the power management chip is connected to each memory module under test.

3. The memory operation condition checking method according to claim 1, wherein The central processing unit is built with a storage component, and can manage the original supply voltages provided by the power management chip to each memory module under test and provide the compensation voltage to the corresponding memory module under test in a software manner.

4. The memory operation condition checking method according to claim 1, wherein The measurement unit is a digital multimeter.

5. The memory operation condition checking method according to claim 1, wherein The resistance value is 8 to 12 milliohms.

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