Nonvolatile memory device including three-dimensional structure of resistive switching element

Abstract

A nonvolatile memory device according to an embodiment includes a substrate and a gate structure disposed on the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer alternately stacked. In addition, the nonvolatile memory device includes: a hole pattern that penetrates the gate structure on the substrate; and a gate insulating layer, a first ion retaining layer, a second ion retaining layer, and a channel layer that sequentially cover the sidewall surface of the gate electrode layer in the hole pattern. The first ion retaining layer and the second ion retaining layer contain ions that can be exchanged with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2020-0033925, filed on Mar. 19, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a three-dimensional structure including a resistive switching element. Background Art

[0004] With the trend of design scale reduction and integration increase, memory device structures with three-dimensional structures have emerged. Currently, non-volatile memory devices such as flash memory have been manufactured as three-dimensional structures using a three-layer stacked structure of a charge tunneling layer, a charge trap layer and a charge blocking layer as a charge storage structure.

[0005] Recently, various nonvolatile memory devices having structures different from those of conventional flash memory devices have been proposed. An example of a nonvolatile memory device is a resistive memory device. While a flash memory device implements a storage function by storing charge, a resistive memory device causes the resistance state of a storage layer in a memory cell to variably change between a high resistance state and a low resistance state, and stores the changed resistance state in a nonvolatile manner. In this way, the resistive memory device can write the resistance state into the memory cell as predetermined signal information. Summary of the invention

[0006] A nonvolatile memory device according to an embodiment of the present disclosure may include a substrate and a gate structure disposed on the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer alternately stacked. In addition, the nonvolatile memory device includes: a hole pattern that penetrates the gate structure on the substrate; and a gate insulating layer, a first ion retention layer, a second ion retention layer, and a channel layer, which sequentially cover the sidewall surface of the gate electrode layer. The first ion retention layer and the second ion retention layer contain ions that can be exchanged with each other.

[0007] A nonvolatile memory device according to another embodiment of the present disclosure may include a substrate and a gate structure disposed on the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked along a first direction perpendicular to the upper surface of the substrate, and the gate structure extends in a second direction perpendicular to the first direction. In addition, the nonvolatile memory device may include a gate insulating layer, a first ion retaining layer, a second ion retaining layer, and a channel layer, which sequentially cover the sidewall surface of the gate electrode layer on the substrate. The first ion retaining layer and the second ion retaining layer contain ions that can be exchanged with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a perspective view schematically showing a nonvolatile memory device according to an embodiment of the present disclosure.

[0009] Figure 2 yes Figure 1 A plan view of a nonvolatile memory device.

[0010] Figure 3 is along Figure 1 A cross-sectional view of a nonvolatile memory device taken along line II'.

[0011] Figure 4 is a circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure.

[0012] FIG. 5A to FIG. 5F is a diagram schematically illustrating an operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0013] Figure 6 is a perspective view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure.

[0014] Figure 7 yes Figure 6 A plan view of a nonvolatile memory device.

[0015] Figure 8 is along Figure 6 A cross-sectional view of a nonvolatile memory device taken along line II-II'.

[0016] Fig. 9 is a perspective view schematically showing a nonvolatile memory device according to yet another embodiment of the present disclosure.

[0017] Fig.10 yes Fig. 9 A plan view of a nonvolatile memory device.

[0018] Fig.11 is along Fig. 91 is a cross-sectional view of a nonvolatile memory device taken along line III-III'.

[0019] Fig.12 is along Fig. 9 A cross-sectional view of a nonvolatile memory device taken along line IV-IV'.

[0020] Fig.13 is a perspective view schematically showing a nonvolatile memory device according to yet another embodiment of the present disclosure.

[0021] Fig.14 yes Fig.13 A plan view of a nonvolatile memory device.

[0022] Fig.15 is along Fig.13 A cross-sectional view of a nonvolatile memory device taken along line V-V'.

[0023] Fig.16 is along Fig.13 A cross-sectional view of a nonvolatile memory device taken along line VI-VI'. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, in order to clearly represent the components of each device, the size of the components such as the width and thickness of the components are magnified. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of these terms may be interpreted differently according to the ordinary technicians in the field to which the embodiments belong. If clearly defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meaning as the meanings commonly understood by ordinary technicians in the field to which the embodiments belong.

[0025] In addition, unless the context clearly does not use this, the expression of the singular form of the word should be understood to include the plural form of the word. It will be understood that the terms "include", "comprise" or "have" are intended to specify the existence of a feature, number, step, operation, component, element, part or combination thereof, and are not used to exclude the possibility of the existence or addition of one or more other features, numbers, steps, operations, components, elements, parts or combinations thereof.

[0026] In addition, when performing a method or manufacturing method, each process constituting the method may be performed in a different order than that specified, unless a specific order is clearly described in the context. In other words, each process may be performed in the same manner as the described order and may be performed substantially simultaneously. In addition, at least a portion of each of the above processes may be performed in a reverse order.

[0027] In this specification, the term "predetermined direction" may refer to a direction including a direction determined in a coordinate system and a direction opposite to the direction. As an example, in an xyz coordinate system, the x direction may include a direction parallel to the x direction. That is, the x direction may refer to a direction in which the absolute value of the x-axis increases in a positive direction along the x-axis from the origin 0 and a direction in which the absolute value of the x-axis increases in a negative direction along the x-axis from the origin 0. In the xyz coordinate system, the y direction and the z direction may be interpreted in the same manner, respectively.

[0028] Figure 1 is a perspective view schematically showing a nonvolatile memory device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A plan view of a nonvolatile memory device. Figure 3 is along Figure 1 A cross-sectional view of a nonvolatile memory device taken along line II'.

[0029] refer to Figures 1 to 3 , the nonvolatile memory device 1 may include a substrate 101 and a gate structure 110 disposed on the substrate 101. In addition, the nonvolatile memory device 1 may include a first hole pattern 11 and a second hole pattern 12, which penetrate the gate structure 110 on the substrate 101. The nonvolatile memory device 1 may include a gate insulating layer 120, a first ion retaining layer 130, a second ion retaining layer 140, and a channel layer 150, which sequentially cover the gate structure 110 inside the first hole pattern 11 and the second hole pattern 12.

[0030] Meanwhile, the nonvolatile memory device 1 may further include a channel lower contact layer 105, which is on or above the substrate 101 and in contact with one end of the channel layer 150. The channel lower contact layer 105 may be electrically connected to a source electrode (not shown). In addition, the nonvolatile memory device 1 may include a channel upper contact layer 170, which is in contact with the other end of the channel layer 150. Along a direction perpendicular to the upper or lower surface of the substrate 101 (i.e., the z direction), the other end of the channel layer 150 may be arranged opposite to one end of the channel layer 150. The channel upper contact layer 170 may be electrically connected to a drain electrode (not shown). The source electrode and the drain electrode may apply a source-drain voltage to the channel layer 150.

[0031] refer to Figures 1 to 3 The substrate 101 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or a combination of two or more thereof. The semiconductor material may be doped with a dopant. The semiconductor material may, for example, be doped with an n-type dopant or a p-type dopant.

[0032] The base insulating layer 102 may be disposed on or above the substrate 101. The base insulating layer 102 may electrically insulate the under-channel contact layer 105 from the substrate 101. The base insulating layer 102 may include an insulating material. The insulating material may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0033] The channel lower contact layer 105 may be disposed on or above the base insulating layer 102. The channel lower contact layer 105 may be electrically connected to the channel layer 150. The channel lower contact layer 105 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0034] The gate structure 110 may be disposed on the lower channel contact layer 105. The gate structure 110 may include first to fourth gate electrode layers 112a, 112b, 112c, and 112d and first to fifth interlayer insulating layers 113a, 113b, 113c, 113d, and 113e alternately stacked along a first direction (i.e., z direction). The first interlayer insulating layer 113a may be disposed in contact with the lower channel contact layer 105. The fifth interlayer insulating layer 113e may be disposed as the uppermost layer of the gate structure 110.

[0035] Each of the first to fourth gate electrode layers 112a, 112b, 112c and 112d may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide or a combination of two or more thereof. Each of the first to fifth interlayer insulating layers 113a, 113b, 113c, 113d and 113e may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride or a combination of two or more thereof.

[0036] In some embodiments, the number of gate electrode layers of the gate structure 110 may not necessarily be limited to four. The gate electrode layers may be provided in various numbers, and the interlayer insulating layer may insulate the respective gate electrode layers from each other along the first direction (ie, the z direction).

[0037] refer to Figures 1 to 3 , the first hole pattern 11 and the second hole pattern 12 may penetrate the gate structure 110 in a direction perpendicular to the contact layer 105 under the channel. For example, the first hole pattern 11 and the second hole pattern 12 may be formed on the contact layer 105 under the channel along a first direction (i.e., the z-direction). In one embodiment, the first hole pattern 11 and the second hole pattern 12 may be spaced apart from each other in a second direction (i.e., the y-axis direction). The first hole pattern 11 and the second hole pattern 12 may be formed, for example, by known photolithography and etching processes. As described later, the nonvolatile memory device 1 may include a first storage operation unit U11 and a second storage operation unit U12 spaced apart from each other relative to the first hole pattern 11 and the second hole pattern 12.

[0038] A gate insulating layer 120 covering the sidewall surface of the gate structure 110 may be provided in each of the first hole pattern 11 and the second hole pattern 12. The gate insulating layer 120 may serve as a barrier layer to prevent material diffusion between the first to fourth gate electrode layers 112a, 112b, 112c, and 112d and the first ion retaining layer 130.

[0039] In addition, as described below, the gate voltage applied to the first to fourth gate electrode layers 112a, 112b, 112c, and 112d may be provided to the first ion retaining layer 130 and the second ion retaining layer 140 through the gate insulating layer 120. The gate insulating layer 120 may have a sufficiently small thickness so that the gate voltage can be transmitted to the first ion retaining layer 130 and the second ion retaining layer 140 with a sufficient operating amplitude. Moreover, the first ion retaining layer 130 and the second ion retaining layer 140 may require a current driving force of sufficient magnitude for ion exchange. For example, the gate voltage may pass through the gate insulating layer 120 to provide a tunneling current of sufficient magnitude from the first to fourth gate electrode layers 112a, 112b, 112c, and 112d to the first ion retaining layer 130.

[0040] The gate insulating layer 120 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like.

[0041] The first ion retaining layer 130 may be disposed on the gate insulating layer 120 disposed along the sidewall surface of the gate structure 110 inside the first hole pattern 11 and the second hole pattern 12. Similarly, the second ion retaining layer 140 may be disposed on the first ion retaining layer 130 inside the first hole pattern 11 and the second hole pattern 12. As an example, the gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 may be disposed as continuous concentric layers in the first hole pattern 11 and the second hole pattern 12.

[0042] The first ion retaining layer 130 and the second ion retaining layer 140 may include ions that are exchangeable with each other. In one embodiment, the first ion retaining layer 130 and the second ion retaining layer 140 may include metal cations that are exchangeable with each other. When an external electric field is applied, the metal cations may move between the first ion retaining layer 130 and the second ion retaining layer 140.

[0043] In one embodiment, when the metal cation is a lithium (Li) ion, each of the first ion retaining layer 130 and the second ion retaining layer 140 may include, for example, a lithium-based oxide, a transition metal oxide, a perovskite-based material, or a combination of two or more thereof. The lithium-based oxide may include LiPON, LiCoO 2 、LiFePO 4 and LiMn 2 O 4 Etc. Transition metal oxides may include, for example, WO 3 and MoO 3 The perovskite-based materials may include, for example, SrTiO 3 wait.

[0044] In one embodiment, one of the first ion retaining layer 130 and the second ion retaining layer 140 may be used as a supply layer of metal cations. The other of the first ion retaining layer 130 and the second ion retaining layer 140 may be used as a receiving layer of metal cations. In one embodiment, one of the first ion retaining layer 130 and the second ion retaining layer 140 used as a metal cation supply layer may include LiPON, LiCoO 2 、LiFePO 4 and LiMn 2 O 4 etc., while another layer used as a metal cation receiving layer may include, for example, WO 3 、MoO 3 and SrTiO 3 wait.

[0045] Depending on the concentration of ions, the first ion retaining layer 130 and the second ion retaining layer 140 may have different resistances. As an example, the first ion retaining layer 130 may be a metal cation supply layer retaining lithium (Li) ions, and the second ion retaining layer 140 may be a metal cation receiving layer. For example, the first ion retaining layer 130 may include LiCoO 2 , and the second ion retaining layer 140 may include WO 3 .

[0046] When a voltage having a positive polarity is applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d, lithium (Li) ions of the first ion retaining layer 130 may move into the second ion retaining layer 140. Inside the second ion retaining layer 140, the lithium (Li) ions may react with WO 3 Materials combine to form Li x WO 3-x In this process, the WO 3 Oxygen vacancies are formed inside the material. As the concentration of lithium (Li) ions moving from the first ion retaining layer 130 to the second ion retaining layer 140 increases, the concentration of oxygen vacancies distributed in the second ion retaining layer 140 can increase accordingly. Because oxygen vacancies have positive charges and can move along the electric field, oxygen vacancies can reduce the resistance inside the second ion retaining layer 140. Even after the positive voltage applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c and 112d is removed, the second ion retaining layer 140 can maintain the reduced resistance. That is, the second ion retaining layer 140 can store the reduced resistance in the layer as signal information in a non-volatile manner.

[0047] Also, as the magnitude of the positive voltage applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d increases, the concentration of lithium (Li) cations moving to the second ion retaining layer 140 may also increase. As the concentration of lithium (Li) cations increases, the resistance inside the second ion retaining layer 140 may decrease. That is, the second ion retaining layer 140 may have a multi-level resistance based on the amount of retained lithium (Li) cations. The multi-level resistance may be stored in the second ion retaining layer 140 as multi-level signal information in a non-volatile manner.

[0048] On the contrary, when a voltage having a negative polarity is applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d, lithium (Li) cations distributed in the second ion retaining layer 140 may move to the first ion retaining layer 130. In the second ion retaining layer 140, as the amount of lithium (Li) cations decreases, WO3 The concentration of oxygen vacancies in the material may also be reduced. As a result, the resistance of the second ion retaining layer 140 may be increased. Even after the negative voltage applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d is removed, the second ion retaining layer 140 can maintain the increased resistance. That is, the second ion retaining layer 140 can store the increased resistance in the layer as signal information in a non-volatile manner.

[0049] Meanwhile, as the magnitude of the negative voltage applied to at least one of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d increases, the concentration of lithium (Li) cations moving from the second ion retaining layer 140 to the first ion retaining layer 130 may also increase. As the concentration of lithium (Li) cations moving to the first ion retaining layer 130 increases, the resistance of the second ion retaining layer 140 may increase. A plurality of different resistance levels may also be used as multi-level signal information.

[0050] refer to Figures 1 to 3 , the channel layer 150 may be disposed on the channel contact layer 105 inside the first hole pattern 11 and the second hole pattern 12 to cover the second ion retaining layer 140. The channel layer 150 may include a semiconductor material. For example, the semiconductor material may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs), etc. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include a transition metal dichalcogenide (TMDC) or black phosphorus, etc. The transition metal dichalcogenide (TMDC) may include, for example, molybdenum selenide (MoSe 2 ), Hafnium Selenide (HfSe 2 ), indium selenide (InSe), gallium selenide (GaSe), etc. The semiconductor material may include, for example, a metal oxide such as indium gallium zinc oxide (IGZO).

[0051] Meanwhile, a filling insulating layer 160 may be disposed inside the first and second hole patterns 11 and 12 in which the gate insulating layer 120, the first and second ion retaining layers 130 and 140, and the channel layer 150 are disposed. The filling insulating layer 160 may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0052] The channel upper contact layer 170 may be disposed on the filling insulating layer 160 in the first hole pattern 11 and the second hole pattern 12. The channel upper contact layer 170 may contact the upper end of the channel layer 150. Each channel upper contact layer 170 may be electrically connected to a drain electrode (not shown). In some embodiments, the channel upper contact layer 170 may be disposed outside the first hole pattern 11 and the second hole pattern 12. As an example, the channel upper contact layer 170 may be disposed on the channel layer 150 to be electrically connected to the channel layer 150.

[0053] The contact layer 170 on the channel may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof, doped with an n-type dopant or a p-type dopant.

[0054] As described above, in the nonvolatile memory device 1 according to the embodiment of the present disclosure, the first hole pattern 11 and the second hole pattern 12 may penetrate the gate structure 100 disposed on the lower channel contact layer 105. The gate insulating layer 120, the first and second ion retaining layers 130 and 140, and the channel layer 150 may be disposed inside the first and second hole patterns 11 and 12. In addition, the upper channel contact layer 170 may be disposed in contact with a portion of the channel layer 150 in the upper region of the first and second hole patterns 11 and 12.

[0055] In other words, the first to fourth gate electrode layers 112a, 112b, 112c and 112d and the first to fifth interlayer insulating layers 113a, 113b, 113c, 113d, 113e can be arranged to surround the gate insulating layer 120, the first and second ion retaining layers 130 and 140 and the channel layer 150 inside the first and second hole patterns 11 and 12 above the channel contact layer 105.

[0056] In some embodiments, the number of hole patterns passing through the gate structure 110 is not necessarily limited to two. The hole patterns may be formed in various numbers, and each of the gate insulating layer, the first and second ion retaining layers, the channel layer, the filling insulating layer, and the contact layer on the channel may be disposed inside the hole patterns.

[0057] Return to reference Figure 1 and Figure 2, the nonvolatile memory device 1 may include a first memory element unit U11 and a second memory element unit U12, which respectively perform independent operations with respect to each of the first hole pattern 11 and the second hole pattern 12. The first memory element unit U11 and the second memory element unit U12 may share the lower channel contact layer 105. In addition, each of the first memory element unit U11 and the second memory element unit U12 may include an upper channel contact layer 170.

[0058] Figure 4 is a circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 4 The circuit diagram can correspond to the above reference Figures 1 to 3 The nonvolatile memory device 1 described herein may be one of the first memory element unit U11 and the second memory element unit U12. That is, the circuit diagrams of the first memory element U11 and the second memory element U12 may be substantially the same. Hereinafter, as an example, the circuit diagram of the first memory element unit U11 will be described. Specifically, Figure 4 The circuit diagram may include Figures 1 to 3 The gate insulating layer 120, the first ion retaining layer 130 and the second ion retaining layer 140, the channel layer 150, and the first to fourth gate electrode layers 112a, 112b, 112c and 112d in the nonvolatile memory device 1. Figure 4 , the first storage element unit U11 may include first to fourth storage cells MC1, MC2, MC3, and MC4, each of which has a transistor form.

[0059] refer to Figure 4 , the first to fourth memory cells MC1, MC2, MC3 and MC4 may be connected in series with each other between the source electrode SL and the drain electrode DL in the form of a string. Each of the first to fourth memory cells MC1, MC2, MC3 and MC4 may include a transistor-type non-volatile memory element. The first to fourth memory cells MC1, MC2, MC3 and MC4 may include first to fourth resistance element layers VR1, VR2, VR3 and VR4, respectively, and the first to fourth resistance element layers are arranged between the gate insulating layer and the conductive channel of the transistor.

[0060] exist Figures 1 to 3 In the embodiment, the channel lower contact layer 105 and the channel upper contact layer 170 may be electrically connected to a source electrode (not shown) and a drain electrode (not shown), respectively. Here, the source electrode and the drain electrode may correspond to Figure 4 The source electrode SL and the drain electrode DL. Figures 1 to 3 The first to fourth gate electrode layers 112a, 112b, 112c, and 112d may correspond to Figure 4 The first to fourth gate electrodes GL1, GL2, GL3 and GL4 are provided. Figures 1 to 3 In the embodiment, regions of the first ion retaining layer 130 and the second ion retaining layer 140 controlled by the first to fourth gate electrode layers 112a, 112b, 112c, and 112d may correspond to the first to fourth resistance element layers VR1, VR2, VR3, and VR4, respectively.

[0061] FIG. 5A to FIG. 5F FIG. 1 is a diagram schematically illustrating the operation of a nonvolatile memory device according to an embodiment of the present disclosure. Figures 1 to 3 The nonvolatile memory device 1 described here will be described with reference to FIG. 5A to FIG. 5F In addition, for the convenience of explanation, for example, the method of operating the non-volatile memory device will be described. Figure 4 The operation of the nonvolatile memory device will be described with reference to the circuit diagram of the nonvolatile memory device 1 corresponding to the third memory cell MC3 having the third resistance element layer VR3.

[0062] Specifically, Figure 5A It has a first storage operation unit U11 Figure 3 2 is a cross-sectional view of a nonvolatile memory device 1 shown in FIG. Figure 5B It shows that for Figure 5A FIG. 1 is a diagram of a first write operation of the third memory cell MC3 in the region 'A'. Figure 5C is a diagram schematically showing the shape of the gate voltage for the first writing operation. Figure 5D It shows that for Figure 5A FIG. 1 is a diagram of a second write operation of the third memory cell MC3 in the region 'A'. Figure 5E is a diagram schematically showing the shape of the gate voltage for the second writing operation. Fig. 5F 5. The third resistance element layer VR3 may correspond to the first ion retaining layer 130 and the second ion retaining layer 140. Figure 5A The portion controlled by the third gate electrode layer 112c.

[0063] In one embodiment, the first ion retaining layer 130 may be a layer supplying metal cations. The second ion retaining layer 140 may be a receiving layer receiving metal cations. The third memory cell MC3 of the nonvolatile memory device 1 may store different resistance states in a nonvolatile manner, the different resistance states depending on the concentration of the metal cations in the second ion retaining layer 140. As an example, referring to FIG. Figure 5C 140 has a relatively low resistance state. The first write operation may be referred to as a programming operation. As another example, reference will be made to Figure 5A , Figure 5D and Figure 5EThe second write operation in which the second ion retaining layer 140 has a relatively high resistance state is described. The second write operation may be referred to as an erase operation. As another example, reference is made to Figure 5A and Fig. 5F A read operation for reading out the resistance state stored in the second ion retaining layer 140 of the third memory cell MC3 will be described.

[0064] refer to Figure 5A and Figure 5B For the first write operation for the third memory cell MC3, a predetermined first gate voltage including a bias voltage of a positive polarity may be applied to the third gate electrode layer 112c. At this time, the channel layer 150 may be grounded. Figure 5B The first electric field E1 formed by the first gate voltage may act on the first ion retaining layer 130 and the second ion retaining layer 140 of the third memory cell MC3. The first electric field E1 may act on the memory function parts 130m and 140m of the first ion retaining layer 130 and the second ion retaining layer 140.

[0065] The metal cation Pi can move from the first ion retaining layer 130 to the second ion retaining layer 140 through the first electric field E1. Figure 5B , the movement of the metal cation Pi is shown as 'F1'. Therefore, the concentration of the metal cation Pi of the first ion retaining layer 130 may be reduced, and the concentration of the metal cation Pi of the second ion retaining layer 140 may be increased. As described above, as the concentration of the metal cation Pi of the second ion retaining layer 140 increases, the concentration of oxygen vacancies in the second ion retaining layer 140 may increase. As a result, the resistance inside the second ion retaining layer 140 may be reduced.

[0066] Subsequently, the first gate voltage may be removed from the third gate electrode layer 112c. After the first gate voltage is removed, the changed concentration of the metal cation Pi in the storage function parts 130m and 140m of the first ion retaining layer 130 and the second ion retaining layer 140 corresponding to the third memory cell MC3 may be maintained. Therefore, the storage function part 140m of the second ion retaining layer 140 may store the reduced resistance in a nonvolatile manner.

[0067] In one embodiment, Figure 5CAs shown, the first gate voltage may be removed after the first gate voltage is applied within a unit time width Δt1 using a positive pulse voltage P1 having a unit amplitude V1. The magnitude of the first gate voltage may be determined according to the number of times the pulse voltage P1 is applied. That is, a reduction in resistance inside the second ion retaining layer 140 may be obtained by applying one pulse voltage P1. Therefore, in consideration of the reduction in resistance, the magnitude of the first gate voltage may be controlled by the number of times the pulse voltage P1 is applied. As a result, by controlling the magnitude of the first gate voltage using the pulse voltage P1, different resistances may be written into the second ion retaining layer 140, and a plurality of different resistances may be stored in the second ion retaining layer 140 as different signal information. In other words, according to the magnitude of the first gate voltage, the second ion retaining layer 140 may have a plurality of different resistances as signal information based on the amount of increase in the metal cation Pi.

[0068] At the same time, reference Figure 5A and Figure 5D For the second write operation for the third memory cell MC3, a predetermined second gate voltage having a negative polarity bias may be applied to the third gate electrode layer 112c. At this time, the channel layer 150 may be grounded. Figure 5D The second electric field E2 formed by the second gate voltage may act on the first ion retaining layer 130 and the second ion retaining layer 140. The second electric field E2 may act on the memory function parts 130m and 140m of the first ion retaining layer 130 and the second ion retaining layer 140 corresponding to the third memory cell MC3.

[0069] The metal cation Pi can move from the second ion retaining layer 140 to the first ion retaining layer 130 through the second electric field E2. Figure 5D , the movement of the metal cation Pi is shown as 'F2'. Therefore, the concentration of the metal cation Pi of the second ion retaining layer 140 may decrease, and the concentration of the metal cation Pi of the first ion retaining layer 130 may increase. As described above, as the concentration of the metal cation Pi of the second ion retaining layer 140 decreases, the concentration of oxygen vacancies in the second ion retaining layer 140 may decrease. As a result, the resistance inside the second ion retaining layer 140 may increase.

[0070] Subsequently, the second gate voltage may be removed from the third gate electrode layer 112c. After the second gate voltage is removed, the changed concentration of the metal cation Pi in the storage function parts 130m and 140m of the first ion retaining layer 130 and the second ion retaining layer 140 corresponding to the third memory cell MC3 may be maintained. Therefore, the storage function part 140m of the second ion retaining layer 140 may store the increased resistance in a nonvolatile manner.

[0071] In one embodiment, Figure 5E As shown, the second gate voltage may be removed after the second gate voltage is applied within a unit time width Δt2 using a negative pulse voltage P2 having a unit amplitude V2. The magnitude of the second gate voltage may be determined according to the number of times the pulse voltage P2 is applied. That is, an increase in resistance inside the second ion retaining layer 140 may be obtained by applying one pulse voltage P2. Therefore, in consideration of the increase in resistance, the magnitude of the second gate voltage may be controlled by the number of times the pulse voltage P2 is applied. As a result, by controlling the magnitude of the second gate voltage using the pulse voltage P2, the magnitude of resistance inside the second ion retaining layer 140 may be effectively controlled, and different levels of resistance may be stored as multi-level signal information.

[0072] At the same time, reference Figure 5A and Fig. 5F , for a read operation for the third memory cell MC3, a read voltage of a predetermined threshold voltage or higher may be applied to the first gate electrode layer 112a, the second gate electrode layer 112b, and the fourth gate electrode layer 112d. However, the voltage may not be applied to the third gate electrode layer 112c. The read voltage may have a smaller amplitude than the absolute values ​​of the first write voltage and the second write voltage. Therefore, by applying the read voltage, the exchange of metal cations may not occur between the first ion retaining layer 130 and the second ion retaining layer 140 of the third memory cell MC3.

[0073] When a read voltage is applied, a conductive channel 1000c may be formed in the channel layer 150 in a region at or near the interface with the second ion retaining layer 140, but the conductive channel 1000c may be electrically disconnected in a portion of the channel layer 150 electrically controlled by the third gate electrode layer 112c. That is, in the channel layer 150, except for the disconnected portion of the conductive channel 1000c, the conductive channel 1000c may be continuously formed between the channel lower contact layer 105 and the channel upper contact layer 170. This portion may be electrically controlled by the third gate electrode layer. Fig. 5F The disconnected ends of the conductive pathway 1000c are illustrated as a first disconnect portion 150E1 and a second disconnect portion 150E2.

[0074] Subsequently, a source-drain voltage may be applied between the channel lower contact layer 105 and the channel upper contact layer 170. Thus, current may flow along the conductive channel 1000c. However, current may flow through the second ion retaining layer 140 between the first disconnected portion 150E1 and the second disconnected portion 150E2 of the conductive channel 1000c. That is, the internal resistance of the second ion retaining layer 140 may be less than the internal resistance of the channel layer 150 in which the conductive channel 1000c is not formed. As described above, the concentration of oxygen vacancies in the second ion retaining layer 140 may be determined according to the concentration of the metal cation Pi inside the second ion retaining layer 140. And, the concentration of oxygen vacancies may determine the internal resistance of the second ion retaining layer 140.

[0075] As a result, when a read voltage is applied to the first gate electrode layer 112a, the second gate electrode layer 112b, and the fourth gate electrode layer 112d but not to the third gate electrode layer 112c, the source-drain voltage is used to measure a current flowing between the channel lower contact layer 105 and the channel upper contact layer 170. The current flows through the oxygen vacancies in the second ion retaining layer 140 of the third memory cell MC3, so that the current includes or reflects the resistance information stored in the storage function portion 140m of the second ion retaining layer 140. Fig. 5F The current flow is shown as 'Fe', and is shown to flow through the oxygen vacancies Vo inside the second ion retaining layer 140 .

[0076] Figure 6 is a perspective view schematically showing a nonvolatile memory device 2 according to another embodiment of the present disclosure. Figure 7 yes Figure 6 A plan view of a nonvolatile memory device 2 is shown. Figure 8 is along Figure 6 FIG. 1 is a cross-sectional view of the nonvolatile memory device 2 taken along line II-II′.

[0077] refer to Figures 6 to 8 The nonvolatile memory device 2 may be different from the above reference in terms of the configuration of the gate structure 210. Figures 1 to 3 The nonvolatile memory device 1 is described. Configurations of the nonvolatile memory device 2 may be substantially the same as those of the nonvolatile memory device 1 except for the gate structure 210 .

[0078] The gate structure 210 may be disposed on the lower channel contact layer 105. The gate structure 210 may include first to fourth gate electrode layers 212a, 212b, 212c, and 212d and first to fifth interlayer insulating layers 213a, 213b, 213c, 213d, and 213e alternately stacked along a first direction (i.e., z direction) perpendicular to the substrate 101. The first interlayer insulating layer 213a may be disposed in contact with the lower channel contact layer 105. The fifth interlayer insulating layer 213e may be disposed as the uppermost layer of the gate structure 210.

[0079] The gate structure 210 may include hole patterns 21 and 22. The gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 may be disposed to sequentially cover the sidewall surfaces of the first to fourth gate electrode layers 212a, 212b, 212c, and 212d in each of the hole patterns 21 and 22. As an example, the gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 may be disposed as continuous concentric layers in the first hole pattern 21 and the second hole pattern 22. The second ion retaining layer 140 may contact the channel layer 150 in a direction perpendicular to the first direction (i.e., in the x-direction and the y-direction) or in a radial direction starting from the center CT.

[0080] refer to Figures 6 to 8 , and the above reference Figures 1 to 3 Compared with the first to fifth interlayer insulating layers 113a, 113b, 113c, 113d, and 113e of the nonvolatile memory device 1 described above, the first to fifth interlayer insulating layers 213a, 213b, 213c, 213d, and 213e of the present embodiment may be further extended toward the center CT of each of the hole patterns 21 and 22. Specifically, the first to fifth interlayer insulating layers 213a, 213b, 213c, 213d, and 213e may be disposed in contact with the channel layer 150. The center CT of each of the hole patterns 21 and 22 may refer to Figure 7 The center point of each circular hole pattern 21 and 22 in the plan view and can be referred to as Figure 8 The cross-sectional view shows a central axis extending in a direction perpendicular to the upper surface or the lower surface of the substrate 101 and passing through the inside of the hole pattern 21 of the nonvolatile memory device 2.

[0081] The first to fifth interlayer insulating layers 213a, 213b, 213c, 213d, and 213e of the present embodiment can divide the gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 in the z direction. As a result, the region of the gate insulating layer 120, the region of the first ion retaining layer 130, and the region of the second ion retaining layer 140 controlled by one gate electrode layer can be separated from the region controlled by a different gate electrode layer. Therefore, the first to fourth gate electrode layers 212a, 212b, 212c, and 212d and the corresponding regions of the gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 for each gate electrode layer can be separated from each other in the z direction. In other words, the regions of the gate insulating layer 120, the first ion retaining layer 130, and the second ion retaining layer 140 can be prevented from being interfered with or controlled by adjacent gate electrode layers among the first to fourth gate electrode layers 212a, 212b, 212c, and 212d, thereby preventing redundancy or double control. Therefore, with the extension of the first to fifth interlayer insulating layers 213 a , 213 b , 213 c , 213 d , and 213 e toward the center CT, electrical interference occurring between adjacent memory cells along the z direction may be effectively eliminated.

[0082] Fig. 9 is a perspective view schematically showing a nonvolatile memory device 3 according to yet another embodiment of the present disclosure. Fig.10 yes Fig. 9 A plan view of the nonvolatile memory device 3. Fig.11 is along Fig. 9 FIG. 1 is a cross-sectional view of the nonvolatile memory device 3 taken along line III-III′. Fig.12 is along Fig. 9 FIG. 1 is a cross-sectional view of the nonvolatile memory device 3 taken along line IV-IV′.

[0083] refer to Figures 9 to 12 The nonvolatile memory device 3 may include a substrate 101 and a first gate structure 310 and a second gate structure 410 disposed on the substrate 101. The nonvolatile memory device 3 may include gate insulating layers 320a, 320b, and 320c, first ion retaining layers 330a, 330b, and 330c, second ion retaining layers 340a, 340b, and 340c, and channel layers 350a, 350b, and 350c disposed on the substrate 101. The gate insulating layers 320a, 320b, and 320c, the first ion retaining layers 330a, 330b, and 330c, the second ion retaining layers 340a, 340b, and 340c, and the channel layers 350a, 350b, and 350c sequentially cover the sidewall surfaces of the first gate structure 310.

[0084] In addition, the nonvolatile memory device 3 may include gate insulating layers 420a, 420b, and 420c, first ion retaining layers 430a, 430b, and 430c, second ion retaining layers 440a, 440b, and 440c, and channel layers 450a, 450b, and 450c disposed on the substrate 101. The gate insulating layers 420a, 420b, and 420c, the first ion retaining layers 430a, 430b, and 430c, the second ion retaining layers 440a, 440b, and 440c, and the channel layers 450a, 450b, and 450c sequentially cover the sidewall surfaces of the second gate structure 410 on the substrate 101.

[0085] refer to Figures 9 to 12 , a substrate 101 may be provided. A base insulating layer 102 and a lower channel contact layer 105 may be sequentially disposed on the substrate 101. A first gate structure 310 may be disposed on the lower channel contact layer 105. The first gate structure 310 may include first to fourth gate electrode layers 312a, 312b, 312c, and 312d and first to fifth interlayer insulating layers 313a, 313b, 313c, 313d, and 313e alternately stacked along a first direction (i.e., z direction). The first gate structure 310 may extend in a second direction (i.e., y direction) perpendicular to the first direction (i.e., z direction).

[0086] Each of the first to fourth gate electrode layers 312a, 312b, 312c, and 312d may include a conductive material. The conductive material of each of the first to fourth gate electrode layers 312a, 312b, 312c, and 312d may be the same as that of the above reference Figures 1 to 3 The conductive materials of the first to fourth gate electrode layers 112a, 112b, 112c, and 112d of the nonvolatile memory device 1 described above are substantially the same. Each of the first to fifth interlayer insulating layers 313a, 313b, 313c, 313d, and 313e may include an insulating material. The insulating material of each of the first to fifth interlayer insulating layers 313a, 313b, 313c, 313d, and 313e may be the same as that of the above reference 1. Figures 1 to 3 The insulating materials of the first to fifth interlayer insulating layers 113 a , 113 b , 113 c , 113 d , and 113 e of the described nonvolatile memory device 1 are substantially the same.

[0087] In some embodiments, the number of gate electrode layers of the first gate structure 310 may not necessarily be limited to four. The gate electrode layers may be arranged in various numbers, and the interlayer insulating layer may insulate the various numbers of gate electrode layers from each other along the first direction (ie, z direction).

[0088] refer to Figures 9 to 12, gate insulating layers 320a, 320b, and 320c may be disposed on the lower channel contact layer 105 to cover the sidewall surface S1 of the first gate structure 310. The gate insulating layers 320a, 320b, and 320c may be isolated from each other relative to the second direction (i.e., the y direction) by the first unit insulating structure 380a and the second unit insulating structure 380b. That is, the gate insulating layers 320a, 320b, and 320c may be disposed to be spaced apart from each other relative to the second direction (i.e., the y direction). Each of the gate insulating layers 320a, 320b, and 320c may include an insulating material. The insulating material of the gate insulating layers 320a, 320b, and 320c may be the same as that described above with reference to Figures 1 to 3 The insulating material of the gate insulating layer 120 of the described nonvolatile memory device 1 is substantially the same.

[0089] First ion retaining layers 330a, 330b, and 330c, second ion retaining layers 340a, 340b, and 340c, and channel layers 350a, 350b, and 350c may be disposed on the lower channel contact layer 105, respectively, to sequentially cover the gate insulating layers 320a, 320b, and 320c. The first ion retaining layers 330a, 330b, and 330c, the second ion retaining layers 340a, 340b, and 340c, and the channel layers 350a, 350b, and 350c may be isolated from each other with respect to the second direction (i.e., the y direction) by the first unit insulating structure 380a and the second unit insulating structure 380b.

[0090] The second ion retaining layers 340a, 340b, and 340c may include ions that may be exchanged with the corresponding first ion retaining layers 330a, 330b, and 330c. The materials constituting the first ion retaining layers 330a, 330b, and 330c and the second ion retaining layers 340a, 340b, and 340c may be the same as those described above. Figures 1 to 3 The materials constituting the first ion retaining layer 130 and the second ion retaining layer 140 of the nonvolatile memory device 1 are described to be substantially the same.

[0091] Each of the channel layers 350a, 350b, and 350c may include a semiconductor material. The semiconductor material of the channel layers 350a, 350b, and 350c may be the same as that described above. Figures 1 to 3 The semiconductor material of the channel layer 150 of the described nonvolatile memory device 1 is substantially the same.

[0092] Meanwhile, the second gate structure 410 may be disposed on the under-channel contact layer 105 and spaced apart from the first gate structure 310 in the third direction (i.e., the x-direction). The second gate structure 410 may include first to fourth gate electrode layers 412a, 412b, 412c, and 412d and first to fifth interlayer insulating layers 413a, 413b, 413c, 413d, and 413e alternately stacked along the first direction (i.e., the z-direction). The configuration of the first to fourth gate electrode layers 412a, 412b, 412c and 412d and the first to fifth interlayer insulating layers 413a, 413b, 413c, 413d and 413e may be substantially the same as the configuration of the first to fourth gate electrode layers 312a, 312b, 312c and 312d and the first to fifth interlayer insulating layers 313a, 313b, 313c, 313d and 313e of the first gate structure 310.

[0093] refer to Figures 9 to 12 , gate insulating layers 420a, 420b, and 420c may be disposed on the lower channel contact layer 105 to cover the sidewall surface S2 of the second gate structure 410. The gate insulating layers 420a, 420b, and 420c may be isolated from each other relative to the second direction (i.e., the y direction) by the first unit insulating structure 380a and the second unit insulating structure 380b. That is, the gate insulating layers 420a, 420b, and 420c may be disposed to be spaced apart from each other relative to the second direction (i.e., the y direction). Each of the gate insulating layers 420a, 420b, and 420c may include an insulating material. The insulating material of the gate insulating layers 420a, 420b, and 420c may be the same as that of the above reference. Figures 1 to 3 The insulating material of the gate insulating layer 120 of the described nonvolatile memory device 1 is substantially the same.

[0094] The first ion retaining layers 430a, 430b and 430c, the second ion retaining layers 440a, 440b and 440c, and the channel layers 450a, 450b and 450c may be disposed on the lower channel contact layer 105 to sequentially cover the corresponding gate insulating layers 420a, 420b and 420c. The first ion retaining layers 430a, 430b and 430c, the second ion retaining layers 440a, 440b and 440c, and the channel layers 450a, 450b and 450c may be isolated from each other with respect to the second direction (i.e., the y direction) by the first unit insulating structure 380a and the second unit insulating structure 380b.

[0095] The second ion retaining layers 440a, 440b, and 440c may include ions that can be exchanged with the corresponding first ion retaining layers 430a, 430b, and 430c. The materials constituting the first ion retaining layers 430a, 430b, and 430c and the second ion retaining layers 440a, 440b, and 440c may be the same as those described above. Figures 1 to 3 The materials constituting the first ion retaining layer 130 and the second ion retaining layer 140 of the nonvolatile memory device 1 are described to be substantially the same.

[0096] Each of the channel layers 450a, 450b, and 450c may include a semiconductor material. The semiconductor material of the channel layers 450a, 450b, and 450c may be the same as that described above. Figures 1 to 3 The semiconductor material of the channel layer 150 of the described nonvolatile memory device 1 is substantially the same.

[0097] On the lower channel contact layer 105, filling structures 360a, 360b, and 360c may be provided between the channel layers 350a, 350b, and 350c of the first gate structure 310 and the channel layers 450a, 450b, and 450c of the second gate structure 410, respectively. The filling structures 360a, 360b, and 360c may be separated from each other by unit insulating structures 380a and 380b. Each of the filling structures 360a, 360b, and 360c may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0098] Channel contact layers 370a, 370b, and 370c may be disposed on the filling structures 360a, 360b, and 360c. Channel contact layers 370a, 370b, and 370c may be separated from each other by cell insulating structures 380a and 380b. Channel contact layers 370a, 370b, and 370c may be disposed in contact with corresponding channel layers 350a, 350b, and 350c of the first gate structure 310 and channel layers 450a, 450b, and 450c of the second gate structure 410, respectively.

[0099] The unit insulating structures 380a and 380b may be disposed on the lower channel contact layer 105 and extend in the first direction (i.e., the z direction). The unit insulating structures 380a and 380b may be disposed in contact with the first gate structure 310 and the second gate structure 410 in the third direction (i.e., the x direction). The unit insulating structures 380a and 380b may be disposed to be spaced apart from each other in the second direction (i.e., the y direction). Each of the unit insulating structures 380a and 380b may include an insulating material. The insulating material may, for example, include an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0100] Reference again Fig. 9 and Fig.10 , the nonvolatile memory device 3 may include first to sixth storage element units U31, U32, U33, U34, U35, and U36 that perform operations independently of each other. The first storage element unit U31 may include a first gate structure 310, a first gate insulating layer 320a, a first ion retaining layer 330a, a second ion retaining layer 340a, a channel layer 350a, and a channel upper contact layer 370a. In the same manner, as Fig. 9 As shown in, each of the second to sixth storage element units U32, U33, U34, U35 and U36 may include a gate structure and a corresponding first gate insulating layer, a first ion retaining layer, a second ion retaining layer, a channel layer and a channel upper contact layer. The first to sixth storage element units U31, U32, U33, U34, U35 and U36 may share a channel lower contact layer 105.

[0101] The circuit diagram of any one of the first to sixth storage element units U31, U32, U33, U34, U35 and U36 may be the same as Figure 4 The operation methods of the first to sixth storage element units U31, U32, U33, U34, U35 and U36 can be combined with the above FIG. 5A to FIG. 5F The operation method of the nonvolatile memory device 1 described above is basically the same. That is, the write operation and the read operation of any one of the first to sixth storage element units U31, U32, U33, U34, U35 and U36 can be combined with the above FIG. 5A to FIG. 5F The write operation and the read operation of the described nonvolatile memory device 1 are substantially the same.

[0102] Fig.13 is a perspective view schematically showing a nonvolatile memory device 4 according to yet another embodiment of the present disclosure. Fig.14 yes Fig.13 A plan view of the nonvolatile memory device 4 is shown. Fig.15 is along Fig.13 FIG. 4 is a cross-sectional view of the nonvolatile memory device 4 taken along line VV′. Fig.16 is along Fig.13 4 is a cross-sectional view taken along line VI-VI′ of the nonvolatile memory device 4.

[0103] refer to Figures 13 to 16 The nonvolatile memory device 4 may be similar to the above reference in terms of the configuration of the first gate structure 510 and the second gate structure 610. Figures 9 to 12 The nonvolatile memory device 3 described is different. Except for the first gate structure 510 and the second gate structure 610 , the remaining configuration of the nonvolatile memory device 4 may be substantially the same as the nonvolatile memory device 3 .

[0104] The first gate structure 510 may include first to fourth gate electrode layers 512a, 512b, 512c, and 512d and first to fifth interlayer insulating layers 513a, 513b, 513c, 513d, and 513e alternately stacked on the lower channel contact layer 105 along the first direction (i.e., the z direction). The first interlayer insulating layer 513a may be disposed in contact with the lower channel contact layer 105. The fifth interlayer insulating layer 513e may be disposed as the uppermost layer of the first gate structure 510. Similarly, the second gate structure 610 may include first to fourth gate electrode layers 612a, 612b, 612c, and 612d and first to fifth interlayer insulating layers 613a, 613b, 613c, 613d, and 613e alternately stacked on the lower channel contact layer 105 along the first direction (i.e., the z direction). The first interlayer insulating layer 613a may be disposed in contact with the lower channel contact layer 105. A fifth interlayer insulating layer 613 e may be provided as an uppermost layer of the second gate structure 610 .

[0105] refer to Figures 13 to 16 , and the above reference Figures 9 to 12 Compared to the first to fifth interlayer insulating layers 313a, 313b, 313c, 313d and 313e of the first gate structure 310 described above, the first to fifth interlayer insulating layers 513a, 513b, 513c, 513d and 513e of the first gate structure 510 may be further extended toward the third direction (i.e., the x direction). Specifically, the first to fifth interlayer insulating layers 513a, 513b, 513c, 513d and 513e of the first gate structure 510 may be disposed in contact with the channel layers 350a, 350b and 350c. Similarly, in the present embodiment, the first to fifth interlayer insulating layers 613a, 613b, 613c, 613d and 613e of the second gate structure 610 may be compared to the above reference Figures 9 to 12 The first to fifth interlayer insulating layers 413a, 413b, 413c, 413d and 413e of the described second gate structure 410 further extend toward the third direction (i.e., the x direction). Specifically, the first to fifth interlayer insulating layers 613a, 613b, 613c, 613d and 613e of the second gate structure 610 may be disposed in contact with the channel layers 450a, 450b and 450c.

[0106] The first to fifth interlayer insulating layers 513a, 513b, 513c, 513d and 513e of the first gate structure 510 can separate the gate insulating layers 320a, 320b and 320c, the first ion retaining layers 330a, 330b and 330c and the second ion retaining layers 340a, 340b and 340c in the z direction. Figures 9 to 12Compared with the nonvolatile memory device 3 described above, the gate insulating layer, the first ion retaining layer, and the second ion retaining layer are divided into segments or portions spaced apart in the z direction. As a result, regions of the gate insulating layers 320a, 320b, and 320c, regions of the first ion retaining layers 330a, 330b, and 330c, and regions of the second ion retaining layers 340a, 340b, and 340c, which are electrically controlled by the first to fourth gate electrode layers 512a, 512b, 512c, and 512d, respectively, can be separated from each other in the z direction by the interlayer insulating layers 513a, 513b, 513c, 513d, and 513e. In other words, the region of the gate insulating layers 320a, 320b, and 320c, the region of the first ion retaining layers 330a, 330b, and 330c, and the region of the second ion retaining layers 340a, 340b, and 340c can be prevented from being interfered with or controlled by adjacent gate electrode layers among the first to fourth gate electrode layers 512a, 512b, 512c, and 512d, thereby preventing redundant or double control. Therefore, by extending the first to fifth interlayer insulating layers 513a, 513b, 513c, 513d, and 513e, electrical interference occurring between adjacent memory cells along the z direction can be effectively reduced or prevented.

[0107] Likewise, the first to fifth interlayer insulating layers 613a, 613b, 613c, 613d, and 613e of the second gate structure 610 extend in the x-direction to contact the channel layers 450a, 450b, and 450c. The gate insulating layers 420a, 420b, and 420c, the first ion retaining layers 430a, 430b, and 430c, and the second ion retaining layers 440a, 440b, and 440c may be separated or divided in the z-direction. As a result, the regions of the gate insulating layers 420a, 420b, and 420c, the regions of the first ion retaining layers 430a, 430b, and 430c, and the regions of the second ion retaining layers 440a, 440b, and 440c, which are electrically controlled by the first to fourth gate electrode layers 612a, 612b, 612c, and 612d, respectively, can be separated from each other in the z direction by the interlayer insulating layers 613a, 613b, 613c, 613d, and 613e. In other words, the regions of the gate insulating layers 420a, 420b, and 420c, the regions of the first ion retaining layers 430a, 430b, and 430c, and the regions of the second ion retaining layers 440a, 440b, and 440c can be prevented from being interfered with or controlled by adjacent gate electrode layers among the first to fourth gate electrode layers 612a, 612b, 612c, and 612d, thereby preventing redundant control or double control. Therefore, by extending the first to fifth interlayer insulating layers 613a, 613b, 613c, 613d, and 613e, electrical interference occurring between adjacent memory cells along the z-direction may be effectively reduced or prevented.

[0108] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the appended claims.

Claims

1. A nonvolatile memory device, comprising: substrate; A gate structure, which is arranged on the substrate, and includes at least one gate electrode layer and at least one interlayer insulating layer alternately stacked; a hole pattern penetrating the gate structure on the substrate; and a gate insulating layer, a first ion retaining layer, a second ion retaining layer and a channel layer, which sequentially cover the side wall surface of the gate electrode layer in the hole pattern, wherein the first ion retaining layer and the second ion retaining layer contain ions that can exchange with each other, The first ion retaining layer and the second ion retaining layer contain metal cations that can be exchanged with each other.

2. The nonvolatile memory device according to claim 1, further comprising: a lower channel contact layer, which is disposed on the substrate and contacts the first end of the channel layer; and an upper channel contact layer in contact with a second, opposite end of the channel layer; The channel lower contact layer and the channel upper contact layer are electrically connected to the source electrode and the drain electrode, respectively.

3. The nonvolatile memory device according to claim 1, wherein: When a predetermined positive voltage is applied to the gate electrode layer, the first ion retaining layer provides metal cations to the second ion retaining layer.

4. The nonvolatile memory device according to claim 3, wherein: The second ion retaining layer stores the resistance decreased based on the increased amount of the metal cations in a nonvolatile manner after the positive voltage applied to the gate electrode layer is removed.

5. The nonvolatile memory device according to claim 1, wherein: When a predetermined negative voltage is applied to the gate electrode layer, the second ion retaining layer provides metal cations to the first ion retaining layer.

6. The nonvolatile memory device according to claim 5, wherein: The second ion retaining layer stores the increased resistance based on the reduced amount of the metal cations in a nonvolatile manner after the negative voltage applied to the gate electrode layer is removed.

7. The nonvolatile memory device according to claim 1, wherein: Each of the first ion retaining layer and the second ion retaining layer includes at least one selected from a lithium-based oxide, a transition metal oxide, and a perovskite-based material.

8. The nonvolatile memory device according to claim 1, wherein: The second ion retaining layer has a multi-level resistance based on the amount of retained ions.

9. The nonvolatile memory device according to claim 1, wherein: The interlayer insulating layer extends toward a center of the hole pattern to be disposed in contact with the channel layer.

10. The nonvolatile memory device according to claim 1, wherein: The second ion retaining layer is disposed in contact with the channel layer.

11. A nonvolatile memory device comprising: substrate; a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulating layer alternately stacked along a first direction perpendicular to an upper surface of the substrate, wherein the gate structure extends in a second direction perpendicular to the first direction; and a gate insulating layer, a first ion retaining layer, a second ion retaining layer and a channel layer, which sequentially cover the side wall surface of the gate electrode layer on the substrate, wherein the first ion retaining layer and the second ion retaining layer contain ions that can exchange with each other, The first ion retaining layer and the second ion retaining layer contain metal cations that can be exchanged with each other.

12. The nonvolatile memory device according to claim 11, wherein: Each of the first ion retaining layer and the second ion retaining layer includes at least one selected from a lithium-based oxide, a transition metal oxide, and a perovskite-based material.

13. The nonvolatile memory device according to claim 11, further comprising: a lower channel contact layer, which is disposed on the substrate and contacts the first end of the channel layer; and an upper channel contact layer in contact with a second, opposite end of the channel layer; The channel lower contact layer and the channel upper contact layer are electrically connected to the source electrode and the drain electrode, respectively.

14. The nonvolatile memory device according to claim 11, wherein: The second ion retaining layer has a multi-level resistance based on the amount of retained ions.

15. The nonvolatile memory device according to claim 14, wherein: The amount of the retained ions is controlled by a voltage applied to the gate electrode layer.

16. The nonvolatile memory device according to claim 11, further comprising: a plurality of unit insulating structures disposed on the substrate and spaced apart from each other in the second direction, The plurality of unit insulating structures extend in the first direction and in a third direction perpendicular to the first direction and the second direction on the substrate, and separate the first ion retaining layer, the second ion retaining layer and the channel layer relative to the second direction.

17. The nonvolatile memory device according to claim 11, wherein: The interlayer insulating layer extends in a third direction perpendicular to the first direction and the second direction to be disposed in contact with the channel layer.

18. The nonvolatile memory device according to claim 11, wherein: The second ion retaining layer is disposed in contact with the channel layer.

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