An Ultra-Low Drift Quasi-Static Charge Amplifier

Abstract

A quasi-static charge amplifier with ultra-low drift. The invention relates to an improvement of a quasi-static charge amplifier. The invention comprises a first quasi-static charge amplifier and a second quasi-static charge amplifier, wherein the first quasi-static charge amplifier and the quasi-static charge amplifier are respectively connected to an output push-pull circuit. A dual quasi-static charge amplifier is used, one quasi-static charge amplifier is used for charge measurement, and the other quasi-static charge amplifier is used for generating a drift voltage Vb. The output voltage drift rate is reduced by one order of magnitude, and the measurement accuracy is improved, thereby making it possible to calibrate the sensitivity of a small-range force and pressure sensor.

Description

Technical Field

[0001] The invention relates to a charge amplifier, and in particular to an improvement of a quasi-static charge amplifier. Background Art

[0002] In the prior art, force and pressure sensors need to be calibrated for sensitivity before use, and then connected to a charge amplifier for measurement. Especially when calibrating the sensitivity of small-range force and pressure sensors, due to the existence of the RC time constant and the influence of the bias current of the pre-operational amplifier, the zero point drifts, which becomes larger and larger over time, affecting the measurement accuracy and even making it impossible to measure. When calibrating the sensitivity of small-range force and pressure sensors, the output voltage drift rate of the traditional quasi-static charge amplifier is too large, affecting the measurement accuracy. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention provides a quasi-static charge amplifier with high measurement accuracy and ultra-low drift.

[0004] The present invention is implemented by the following technical solution: an ultra-low drift quasi-static charge amplifier, comprising a first quasi-static charge amplifier and a second quasi-static charge amplifier, wherein the first quasi-static charge amplifier and the second quasi-static charge amplifier are respectively connected to an output push-pull circuit.

[0005] The charge signal in the first quasi-static charge amplifier is introduced from one pin of the socket XS1, the second pin of the socket XS1 is grounded, the charge signal is connected to the gate of the MOS tube V1 through the resistor R12, and is connected to one pin of the charge amplifier output voltage socket XS2 through the first RC network.

[0006] The first RC network is formed by a resistor R11, a resistor R10, a capacitor C2, a capacitor C3, and a capacitor C4 connected in parallel, wherein the resistor R11 is connected in series with the switch SW3, the resistor R10 is connected in series with the switch SW4, the capacitor C3 is connected in series with the switch SW1, and the capacitor C4 is connected in series with the switch SW2.

[0007] The drain of the MOS pair tube V1 is connected to one end of the potentiometer RP1 through the resistor R2, and is also connected to the inverting end of the operational amplifier N1. The drain of the MOS pair tube V2 is connected to the other end of the potentiometer RP1 through the resistor R3, and is also connected to the non-inverting end of the operational amplifier N1. The center tap of the potentiometer RP1 is connected to the negative power supply voltage. The potentiometer RP1 is used to adjust the output zero point when the charge amplifier is in the reset state.

[0008] A diode V3 and a diode V4 are connected in parallel between the inverting terminal of the operational amplifier N1 and the non-inverting terminal of the operational amplifier N1, the positive terminal of the diode V3 is connected to the negative terminal of the diode V4, and the negative terminal of the diode V3 is connected to the positive terminal of the diode V4;

[0009] The resistor R1 and the capacitor C1 are connected in series and between the inverting terminal of the operational amplifier N1 and the non-inverting terminal of the operational amplifier N1 to prevent the operational amplifier from oscillating;

[0010] The source of the MOS pair tube V1 and the source of the MOS pair tube V2 are short-circuited together and connected to the positive power supply voltage through the resistor R4. The output end of the operational amplifier N1 is sent to the diode V5 and the diode V6 through the resistor R5 to connect to the output push-pull circuit.

[0011] The negative end of the diode V5 in the output push-pull circuit is connected to the positive end of the diode V6, and is connected to the output end of the operational amplifier N1 via the resistor R5;

[0012] The positive end of the diode V5 is connected to one end of the resistor R6 and is also connected to the base of the second transistor. The other end of the resistor R6 is short-circuited with the collector of the second transistor and is connected to the positive power supply voltage. The negative end of the diode V6 is connected to one end of the resistor R7 and is also connected to the base of the third transistor. The other end of the resistor R7 is short-circuited with the collector of the third transistor and is connected to the negative power supply voltage.

[0013] The emitter of the second transistor is connected to one end of the resistor R8, the emitter of the third transistor is connected to one end of the resistor R9, the resistors R8 and R9 are connected to one pin of the socket XS2, and the two pins of the socket XS2 are grounded.

[0014] The drain of the MOS tube V7 is connected to one end of the potentiometer RP2 through the resistor R14, and is also connected to the inverting end of the operational amplifier N2;

[0015] The drain of the MOS tube V8 is connected to the other end of the potentiometer RP2 through the resistor R15, and is also connected to the in-phase end of the operational amplifier N2. The center tap of the potentiometer RP2 is connected to the negative power supply voltage. The potentiometer is used to adjust the output zero point when the operational amplifier N2 is in the reset state.

[0016] A diode V9 and a diode V10 are connected in parallel between the inverting terminal of the operational amplifier N2 and the non-inverting terminal of the operational amplifier N2, the positive terminal of the diode V9 is connected to the negative terminal of the diode V10, the negative terminal of the diode V9 is connected to the positive terminal of the diode V10, and the resistor R13 and the capacitor C5 are connected in series and connected between the inverting terminal of the operational amplifier N2 and the non-inverting terminal of the operational amplifier N2 to prevent the operational amplifier from oscillating;

[0017] The source of the MOS pair tube V7 and the source of the MOS pair tube V8 are short-circuited together and connected to the positive power supply voltage via the resistor R16;

[0018] The charge signal is introduced from one pin of the socket XS3, and the second pin of the socket XS3 is grounded. The charge signal is connected to the gate of the MOS tube V7 through the resistor R18, and is connected to the charge amplifier output voltage OUT1 through the second RC network. The output end of the operational amplifier N2 is connected to the output voltage OUT1 through the resistor R17.

[0019] The second RC network is formed by a resistor R19 and a capacitor C6 connected in parallel, and the resistor R19 is connected in series with the switch SW5;

[0020] The output voltage OUT1 is sent to one foot of the resistor R20, the other foot of the resistor R20 is connected to one foot of the resistor R21, and is connected to the inverting end of the operational amplifier N3, and the non-inverting end of the operational amplifier N3 is grounded; the output end of the operational amplifier N3 is connected to the other end of the resistor R21 to obtain the output voltage OUT2, and the gate of the MOS tube V2 is connected to the switch SW6 via the resistor R22.

[0021] MOS pair of tubes V1, MOS pair of tubes V2, MOS pair of tubes V7 and MOS pair of tubes V8 are all 3N165 MOS pair of tubes.

[0022] Compared with the prior art, the present invention adopts dual quasi-static charge amplifiers, one quasi-static charge amplifier is used for charge measurement, and the other quasi-static charge amplifier is used to generate a drift voltage Vb, and Vb is introduced into the quasi-static charge amplifier circuit for measuring charge, and the potentiometer is adjusted so that the voltage drift rate of the quasi-static charge amplifier for generating the drift voltage Vb is equal to the voltage drift rate of the quasi-static charge amplifier for measuring charge, thereby offsetting most of the voltage drift of the quasi-static charge amplifier for measuring charge, so that the output voltage drift rate of the patent application can be ±0.2mV / minute at the capacitance C=1NF level, and the output voltage drift rate is reduced by one order of magnitude, thereby improving the measurement accuracy, thereby making it possible to calibrate the sensitivity of small-range force and pressure sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0025] like Figure 1As shown, the charge signal is introduced from one pin of the socket XS1, and the two pins of the socket XS1 are grounded. V1 and V2 are 3N165MOS pairs, and V7 and V8 are also 3N165MOS pairs. The charge signal is connected to the gate of the MOS pair labeled V1 through the resistor R12, and is connected to one pin of the charge amplifier output voltage socket XS2 through the RC network. The RC network is formed by a resistor R11, a resistor R10, a capacitor C2, a capacitor C3, and a capacitor C4 in parallel, wherein the resistor R11 is connected in series with the switch SW3, the resistor R10 is connected in series with the switch SW4, the capacitor C3 is connected in series with the switch SW1, and the capacitor C4 is connected in series with the switch SW2.

[0026] The relationship between the RC network and the output gain of the charge amplifier is shown in Table 1.

[0027] Output gain mV / Unit Capacitor switch status 10 SW1 and SW2 are both disconnected 1 SW1 is on 0.1 SW2 is on

[0028] Table 1

[0029] The relationship between the RC network and the working mode of the charge amplifier is shown in Table 2.

[0030] Working Mode Resistor switch status Reset SW3 is on dynamic SW4 is on Quasi-static SW3 and SW4 are both disconnected

[0031] Table 2

[0032] When the charge amplifier output gain is 10mV / Unit, the feedback capacitance C is the smallest, that is, the output voltage drift rate is the largest. Therefore, when discussing the output voltage drift rate, only the charge amplifier output gain of 10mV / Unit is considered.

[0033] When the charge amplifier output gain is 10mV / Unit, when switch SW3 is turned on, the charge amplifier is in reset mode; when switch SW4 is turned on, the charge amplifier is in dynamic mode, which is used to measure dynamic charge signals; when switches SW3 and SW4 are both turned off, the charge amplifier is in quasi-static mode, which is used to statically calibrate the sensitivity of force and pressure sensors. In reset mode, the zero point of the charge amplifier output voltage can be adjusted, and it is used to protect the 3N165 tube when not in the measurement state.

[0034] The drain of the MOS pair tube labeled V1 is connected to one end of the potentiometer RP1 through the resistor R2, and is also connected to the inverting end (pin 3) of the operational amplifier labeled N1; the drain of the MOS pair tube labeled V2 is connected to the other end of the potentiometer RP1 through the resistor R3, and is also connected to the non-inverting end (pin 2) of the operational amplifier labeled N1. The center tap of the potentiometer RP1 is connected to the negative power supply voltage. The potentiometer RP1 is used to adjust the output zero point when the charge amplifier is in the reset state.

[0035] Diodes V3 and V4 are connected in parallel between the inverting terminal (pin 2) of the operational amplifier labeled N1 and the non-inverting terminal (pin 3) of the operational amplifier labeled N1 to prevent the MOS pair from being damaged by excessive drain voltage. The positive terminal of diode V3 is connected to the negative terminal of diode V4, and the negative terminal of diode V3 is connected to the positive terminal of diode V4. At the same time, resistor R1 and capacitor C1 are connected in series and connected between the inverting terminal (pin 2) and the non-inverting terminal (pin 3) of the operational amplifier labeled N1 to prevent the operational amplifier from oscillating. The source of the MOS pair labeled V1 and the source of the MOS pair labeled V2 are short-circuited together and connected to the positive power supply voltage through resistor R4.

[0036] The output end (pin 6) of the operational amplifier labeled N1 is sent to the diodes V5 and V6 through the resistor R5 to output the push-pull circuit. In this way, when the capacitance of the charge amplifier feedback capacitor C (100NF) is high, it can provide a larger current to meet the needs of dynamic measurement of the charge amplifier.

[0037] The output push-pull circuit is designed as follows: the negative end of the diode V5 is connected to the positive end of the diode V6, and is connected to the output end (pin 6) of the operational amplifier labeled N1 through the resistor R5. The positive end of the diode V5 is connected to one end of the resistor R6, and is also connected to the base of the second triode (the triode labeled V7 in the figure). The other end of the resistor R6 is short-circuited with the collector of the second triode and connected to the positive power supply voltage. The negative end of the diode V6 is connected to one end of the resistor R7, and is also connected to the base of the third triode (the triode labeled V8 in the figure). The other end of the resistor R7 is short-circuited with the collector of the third triode and connected to the negative power supply voltage.

[0038] The emitter of the second transistor is connected to one end of the resistor R8, the emitter of the third transistor is connected to one end of the resistor R9, the resistors R8 and R9 are connected to one pin of the socket XS2 (the output voltage end of the charge amplifier), and the second pin of the socket XS2 is grounded.

[0039] The drain of the MOS pair tube V7 is connected to one end of the potentiometer RP2 through the resistor R14, and is also connected to the inverting end (pin 2) of the operational amplifier labeled N2; the drain of the MOS pair tube V8 is connected to the other end of the potentiometer RP2 through the resistor R15, and is also connected to the non-inverting end (pin 2) of the operational amplifier labeled N2. The center tap of the potentiometer RP2 is connected to the negative power supply voltage. The potentiometer is used to adjust the output zero point when the operational amplifier N2 is in the reset state.

[0040] Diodes V9 and V10 are connected in parallel between the inverting terminal (pin 2) of the operational amplifier labeled N2 and the non-inverting terminal (pin 3) of the operational amplifier labeled N2 to prevent the MOS pair from being damaged by excessive drain voltage. The positive end of diode V9 is connected to the negative end of diode V10, and the negative end of diode V9 is connected to the positive end of diode V10. At the same time, resistor R13 and capacitor C5 are connected in series and connected between the inverting terminal (pin 2) and the non-inverting terminal (pin 3) of the operational amplifier labeled N2 to prevent the operational amplifier from oscillating. The source of the MOS pair labeled V17 and the source of the MOS pair V8 are short-circuited together and connected to the positive power supply voltage through resistor R16.

[0041] The charge signal is introduced from one pin of the socket XS3, and the second pin of the socket XS3 is grounded. The charge signal is connected to the gate of the MOS pair tube V7 through the resistor R18, and is connected to the charge amplifier output voltage OUT1 through the RC network. The output end (pin 6) of the operational amplifier labeled N2 is connected to OUT1 through the resistor R17. The RC network is formed by the resistor R19 and the capacitor C6 connected in parallel, and the resistor R19 is connected in series with the switch SW5. When the switch SW5 is turned on, the operational amplifier N2 is in the reset state, and the potentiometer RP2 is adjusted to make the OUT1 voltage zero; when the switch SW5 is turned off, the operational amplifier N2 is in a quasi-static state, and the drift voltage OUT1 is generated.

[0042] The drift voltage OUT1 is sent to one foot of the resistor R20, the other foot of the resistor R20 is connected to one foot of the resistor R21, and is connected to the inverting end (3rd foot) of the OP07 operational amplifier labeled N3, and the non-inverting end (2nd foot) of the OP07 operational amplifier labeled N3 is grounded. The output end (6th foot) of the OP07 operational amplifier labeled N3 is connected to the other end of the resistor R21 to obtain the output voltage OUT2, the voltage of OUT2 is equal to the voltage of OUT1, and the polarity is opposite.

[0043] The OUT1 voltage signal and the OUT2 voltage signal are respectively added to the two ends of the potentiometer RP3. The center tap of the potentiometer RP3 is the voltage OUT3. The voltage range of OUT3 is -OUT1~+OUT1, which is adjusted by the potentiometer RP3.

[0044] The gate of the 3N165MOS pair tube labeled V2 is connected to the switch SW6 through the resistor R22. The switch SW6 is a single-pole double-throw switch with two positions, one connected to the ground and the other connected to the voltage OUT3. When the output voltage of the quasi-static charge amplifier needs to compensate for drift, the voltage OUT3 is sent to the gate of the 3N165MOS pair tube labeled V2. The potentiometer RP3 is carefully adjusted to make the drift rate of the output voltage of the quasi-static charge amplifier less than 0.2mV / minute, which greatly reduces the drift rate of the output voltage of the quasi-static charge amplifier, making it possible to calibrate the sensitivity of small-range force and pressure sensors.

[0045] The present invention adopts dual quasi-static charge amplifiers, one quasi-static charge amplifier is used for charge measurement, and the other quasi-static charge amplifier is used for generating a drift voltage Vb, and Vb is introduced into the quasi-static charge amplifier circuit for measuring charge, and the potentiometer is adjusted so that the voltage drift rate of the quasi-static charge amplifier for generating the drift voltage Vb is equal to the voltage drift rate of the quasi-static charge amplifier for measuring charge, thereby offsetting most of the voltage drift of the quasi-static charge amplifier for measuring charge, so that the output voltage drift rate of the patent application can be ±0.2mV / minute at the capacitance C=1NF level, and the output voltage drift rate is reduced by one order of magnitude, thereby improving the measurement accuracy, thereby making it possible to calibrate the sensitivity of small-range force and pressure sensors.

[0046] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. An ultra-low drift quasi-static charge amplifier, comprising a first quasi-static charge amplifier and a second quasi-static charge amplifier, characterized in that: The first quasi-static charge amplifier and the second quasi-static charge amplifier are respectively connected to output push-pull circuits; The charge signal in the first quasi-static charge amplifier is introduced from one pin of the socket XS1, the second pin of the socket XS1 is grounded, the charge signal is connected to the gate of the MOS pair tube V1 through the resistor R12, and is connected to one pin of the charge amplifier output voltage socket XS2 through the first RC network; The output of the operational amplifier N1 is sent to the diode V5 and the diode V6 through the resistor R5 to connect to the output push-pull circuit; The positive end of the diode V5 is connected to one end of the resistor R6 and is also connected to the base of the second transistor. The other end of the resistor R6 is short-circuited with the collector of the second transistor and is connected to the positive power supply voltage. The negative end of the diode V6 is connected to one end of the resistor R7 and is also connected to the base of the third transistor. The other end of the resistor R7 is short-circuited with the collector of the third transistor and is connected to the negative power supply voltage. The emitter of the second transistor is connected to one end of the resistor R8, the emitter of the third transistor is connected to one end of the resistor R9, the resistor R8 is connected to the resistor R9 and connected to one pin of the socket XS2, and the two pins of the socket XS2 are grounded; The charge signal is introduced from one pin of the socket XS3, the second pin of the socket XS3 is grounded, the charge signal is connected to the gate of the MOS tube V7 through the resistor R18, and is connected to the charge amplifier output voltage OUT1 through the second RC network, and the output end of the operational amplifier N2 is connected to the output voltage OUT1 through the resistor R17; The second RC network is formed by a resistor R19 and a capacitor C6 connected in parallel, and the resistor R19 is connected in series with the switch SW5; The output voltage OUT1 is sent to one foot of the resistor R20, the other foot of the resistor R20 is connected to one foot of the resistor R21, and is connected to the inverting end of the operational amplifier N3, and the non-inverting end of the operational amplifier N3 is grounded; the output end of the operational amplifier N3 is connected to the other end of the resistor R21 to obtain the output voltage OUT2, and the gate of the MOS tube V2 is connected to the switch SW6 via the resistor R22; When the switch SW5 is turned off, the operational amplifier N2 is in a quasi-static state, and a drift voltage OUT1 is generated; The OUT1 voltage signal and the OUT2 voltage signal are respectively added to the two ends of the potentiometer RP3, and the center tap of the potentiometer RP3 is the voltage OUT3; Switch SW6 is a single-pole double-throw switch with two positions, one connected to ground and the other connected to voltage OUT3; when the output voltage of the quasi-static charge amplifier needs to compensate for drift, voltage OUT3 is sent to the gate of the 3N165MOS pair tube labeled V2, and the potentiometer RP3 is adjusted so that the drift rate of the output voltage of the quasi-static charge amplifier is less than 0.2mV / minute, thereby reducing the drift rate of the output voltage of the quasi-static charge amplifier.

2. The ultra-low drift quasi-static charge amplifier according to claim 1, characterized in that: The first RC network is formed by a resistor R11, a resistor R10, a capacitor C2, a capacitor C3, and a capacitor C4 connected in parallel, wherein the resistor R11 is connected in series with the switch SW3, the resistor R10 is connected in series with the switch SW4, the capacitor C3 is connected in series with the switch SW1, and the capacitor C4 is connected in series with the switch SW2.

3. The ultra-low drift quasi-static charge amplifier according to claim 2, characterized in that: The drain of the MOS pair tube V1 is connected to one end of the potentiometer RP1 through the resistor R2, and is also connected to the inverting end of the operational amplifier N1. The drain of the MOS pair tube V2 is connected to the other end of the potentiometer RP1 through the resistor R3, and is also connected to the non-inverting end of the operational amplifier N1. The center tap of the potentiometer RP1 is connected to the negative power supply voltage. The potentiometer RP1 is used to adjust the output zero point when the charge amplifier is in the reset state.

4. The ultra-low drift quasi-static charge amplifier according to claim 3, characterized in that: A diode V3 and a diode V4 are connected in parallel between the inverting terminal of the operational amplifier N1 and the non-inverting terminal of the operational amplifier N1, the positive terminal of the diode V3 is connected to the negative terminal of the diode V4, and the negative terminal of the diode V3 is connected to the positive terminal of the diode V4; The resistor R1 and the capacitor C1 are connected in series and between the inverting terminal of the operational amplifier N1 and the non-inverting terminal of the operational amplifier N1 to prevent the operational amplifier from oscillating; The source of the MOS pair tube V1 and the source of the MOS pair tube V2 are short-circuited together and connected to the positive power supply voltage via the resistor R4.

5. The ultra-low drift quasi-static charge amplifier according to claim 4, characterized in that: The negative end of the diode V5 in the output push-pull circuit is connected to the positive end of the diode V6 and is connected to the output end of the operational amplifier N1 via the resistor R5.

6. The ultra-low drift quasi-static charge amplifier according to claim 1, characterized in that: The drain of the MOS tube V7 is connected to one end of the potentiometer RP2 through the resistor R14, and is also connected to the inverting end of the operational amplifier N2; The drain of the MOS tube V8 is connected to the other end of the potentiometer RP2 through the resistor R15, and is also connected to the in-phase end of the operational amplifier N2. The center tap of the potentiometer RP2 is connected to the negative power supply voltage. The potentiometer is used to adjust the output zero point when the operational amplifier N2 is in the reset state. A diode V9 and a diode V10 are connected in parallel between the inverting terminal of the operational amplifier N2 and the non-inverting terminal of the operational amplifier N2, the positive terminal of the diode V9 is connected to the negative terminal of the diode V10, the negative terminal of the diode V9 is connected to the positive terminal of the diode V10, and the resistor R13 and the capacitor C5 are connected in series and connected between the inverting terminal of the operational amplifier N2 and the non-inverting terminal of the operational amplifier N2 to prevent the operational amplifier from oscillating; The source of the MOS pair tube V7 and the source of the MOS pair tube V8 are short-circuited together and connected to the positive power supply voltage via the resistor R16.

7. The ultra-low drift quasi-static charge amplifier according to claim 1, characterized in that: MOS pair of tubes V1, MOS pair of tubes V2, MOS pair of tubes V7 and MOS pair of tubes V8 are all 3N165 MOS pair of tubes.

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