Method and apparatus for a phase-locked loop circuit

Abstract

A phase-locked loop (PLL) circuit [200] includes a voltage-controlled oscillator (VCO) [208], a first loop circuit [220], and a second loop circuit [222]. The first loop circuit includes a first loop filter [206] configured to receive a first signal [224] based on a feedback signal [218] from the VCO and provide a first VCO frequency control signal [226] to the VCO. The second loop circuit includes a compensation circuit [210] configured to receive a reference signal [218] and the first signal and provide a second VCO frequency control signal [228] to the VCO.

Description

Technical Field

[0001] Examples of the present disclosure relate generally to integrated circuits ("ICs"), and in particular, to embodiments related to temperature variation compensation for phase-locked loop (PLL) circuits. Background Art

[0002] Temperature changes often have a significant impact on the locking process of a PLL circuit. During the operation of the PLL circuit, temperature changes (e.g., from -40°C to 125°C or vice versa) may cause the frequency of the voltage-controlled oscillator (VCO) of the PLL circuit to drift. Typically, to compensate for those frequency drifts, the PLL circuit can shift the VCO frequency control signal to bring the VCO output frequency Fout back to the desired frequency (e.g., the reference frequency Fref×N). However, such a VCO frequency control signal may exceed the operating range of the charge pump of the PLL circuit, which may cause the PLL to fail to lock.

[0003] Therefore, it would be desirable and useful to provide an improved method and system for compensating for temperature variations in a PLL. Summary of the Invention

[0004] In some embodiments, a phase-locked loop (PLL) circuit may include a voltage-controlled oscillator (VCO), a first loop circuit including a first loop filter, and a second loop circuit including a compensation circuit. The first loop filter may be configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The compensation circuit may be configured to receive a reference signal and the first signal and provide a second VCO frequency control signal to the VCO.

[0005] In some embodiments, the first bandwidth of the first loop circuit may be greater than the second bandwidth of the second loop circuit.

[0006] In some embodiments, the first bandwidth may be at least 10 times greater than the second bandwidth.

[0007] In some embodiments, the compensation circuit may include an operational amplifier configured to generate a second signal based on the first signal and a reference signal. The compensation circuit may also include a second loop filter configured to generate a second VCO frequency control signal based on the second signal.

[0008] In some embodiments, the second loop filter may be a low-pass filter configured such that a first bandwidth of the first loop circuit is greater than a second bandwidth of the second loop circuit.

[0009] In some embodiments, the second VCO frequency control signal may have a minimum voltage that is the same as the ground voltage.

[0010] In some embodiments, the VCO may include a ring oscillator.

[0011] In some embodiments, the second VCO frequency control signal may be configured to control at least one of a variable capacitor of the VCO and a current source of the VCO to control an output frequency of the VCO.

[0012] In some embodiments, the VCO may be configured to receive a third VCO frequency control signal from an open-loop temperature-dependent voltage circuit.

[0013] In some embodiments, the PLL circuit may further include a compensation mode selection circuit configured to select a compensation mode to control the output frequency of the VCO. The compensation mode may be selected from a first compensation mode, a second compensation mode, a third compensation mode, and a fourth compensation mode. In the first compensation mode, the second VCO frequency control signal may be configured to control one of a variable capacitor of the VCO and a current source of the VCO. In the second compensation mode, the second VCO frequency control signal may be configured to control the other of the variable capacitor of the VCO and the current source of the VCO. In the third compensation mode, the second VCO frequency control signal may be configured to control both the variable capacitor of the VCO and the current source of the VCO. In the fourth compensation mode, the third VCO frequency control signal may be configured to control both the variable capacitor of the VCO and the current source of the VCO.

[0014] In some embodiments, a method includes receiving, by a first loop filter of a first loop circuit, a first signal based on a feedback signal from a voltage-controlled oscillator (VCO), and providing, by the first loop filter, a first VCO frequency control signal to the VCO. The method may also include receiving, by a compensation circuit of a second loop circuit, a reference signal and the first signal, and providing, by the compensation circuit, a second VCO frequency control signal to the VCO based on a difference between the reference signal and the first signal.

[0015] In some embodiments, the first bandwidth of the first loop circuit may be greater than the second bandwidth of the second loop circuit.

[0016] In some embodiments, the first bandwidth may be at least 10 times greater than the second bandwidth.

[0017] In some embodiments, the method may include generating, by the compensation circuit, a second signal based on a difference between the first signal and a reference signal, and generating a second VCO frequency control signal based on the second signal by using a second loop filter of the compensation circuit.

[0018] In some embodiments, the second loop filter may be a low-pass filter configured such that a first bandwidth of the first loop circuit is greater than a second bandwidth of the second loop circuit.

[0019] In some embodiments, the second VCO frequency control signal may have a minimum voltage that is the same as the ground voltage.

[0020] In some embodiments, the VCO may include a ring oscillator.

[0021] In some embodiments, the method may include controlling at least one of a variable capacitor of the VCO and a current source of the VCO by a second VCO frequency control signal to control an output frequency of the VCO.

[0022] In some embodiments, the method may include receiving, by the VCO, a third VCO frequency control signal from an open-loop temperature-dependent voltage circuit.

[0023] In some embodiments, the method may include controlling the output frequency of the VCO in a compensation mode selected from a first compensation mode, a second compensation mode, a third compensation mode, and a fourth compensation mode. In the first compensation mode, the second VCO frequency control signal may be configured to control one of a variable capacitor of the VCO and a current source of the VCO. In the second compensation mode, the second VCO frequency control signal may be configured to control the other of the variable capacitor of the VCO and the current source of the VCO. In the third compensation mode, the second VCO frequency control signal may be configured to control both the variable capacitor of the VCO and the current source of the VCO. In the fourth compensation mode, the third VCO frequency control signal may be configured to control both the variable capacitor of the VCO and the current source of the VCO.

[0024] Other aspects and features will become apparent from a review of the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram illustrating an exemplary architecture for an IC according to some embodiments of the present disclosure.

[0026] Figure 2 is a block diagram illustrating an exemplary phase-locked loop (PLL) circuit including a primary loop circuit and a secondary loop circuit according to some embodiments of the present disclosure.

[0027] Figure 3 is a block diagram illustrating an exemplary compensation circuit for a secondary loop circuit of a PLL circuit according to some embodiments of the present disclosure.

[0028] Figure 4A shows an amplitude curve of a PLL circuit according to some embodiments of the present disclosure; Figure 4B A phase curve of a PLL circuit according to some embodiments of the present disclosure is shown.

[0029] Figure 5A shows a voltage comparison of signal 224 when the PLL operates in different modes according to some embodiments of the present disclosure; Figure 5B According to some embodiments of the present disclosure, Figure 5A The temperature change at the corresponding time; Figure 5C The frequency of the output signal of the VCO according to some embodiments of the present disclosure is shown.

[0030] Figure 6A An exemplary ring voltage controlled oscillator (VCO) circuit according to some embodiments of the present disclosure is shown; Figure 6B shows a VCO power supply control circuit according to some embodiments of the present disclosure; Figure 6C shows a VCO grounding control circuit according to some embodiments of the present disclosure; and Figure 6D A VCO current source control circuit according to some embodiments of the present disclosure is shown.

[0031] Figure 7 A compensation mode selection circuit according to some embodiments of the present disclosure is shown.

[0032] Figure 8 Included is a table illustrating various compensation modes according to some embodiments of the present disclosure.

[0033] Figure 9 is a block diagram illustrating an exemplary PLL circuit including a primary loop circuit, a secondary loop circuit, and an open-loop circuit for temperature compensation according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] Various embodiments are described below with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the claimed invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. The same reference numerals always refer to the same elements. Therefore, the same elements will not be described in detail for the description of each figure. It should also be noted that the accompanying drawings are only for the convenience of describing the embodiments. They are not intended to be an exhaustive description of the claimed invention or a limitation on the scope of the claimed invention. In addition, the illustrated embodiments do not need to have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular embodiment are not necessarily limited to that embodiment and may be practiced in any other embodiment, even if not so stated, or even if not so explicitly described. These features, functions, and advantages can be implemented independently in various embodiments or can be combined in other embodiments.

[0035] Before describing the exemplary embodiments schematically depicted in several figures, a general introduction is provided to further understand. As described above, in a typical PLL circuit, to compensate for frequency drift caused by temperature changes, the PLL circuit can shift the VCO frequency control signal to bring the VCO output frequency Fout back to the desired frequency (e.g., reference frequency Fref×N). However, such a VCO frequency control signal may exceed the operating range of the PLL circuit's charge pump, which may cause the PLL to fail to lock. An open-loop temperature-dependent voltage circuit can be used to generate a temperature-dependent voltage to control Fout and reduce its sensitivity to temperature. However, this open-loop compensation technique relies on models and simulations to predict that the temperature changes of the VCO and the temperature-dependent voltage circuit are synchronized. In addition, this open-loop compensation technique does not maximize the calibration potential of the temperature compensation because the temperature-dependent voltage may not rail from the VCO's ground-to-power supply range, which may not be sufficient to compensate for highly temperature-dependent oscillators, such as 7nm ring oscillators.

[0036] For an integrated circuit (IC) solution, it has been discovered that by using a closed secondary compensation loop in a phase-locked loop circuit, a closed temperature tracking loop is provided to continuously monitor the VCO control signal changes caused by temperature and provide an appropriate control signal to compensate for such changes.

[0037] Various advantages may exist in various applications of the present disclosure. No particular advantage is required of all embodiments, and different embodiments may provide different advantages. One advantage of some embodiments is that by using a closed secondary loop having a bandwidth less than the bandwidth of the primary loop of the PLL circuit, temperature compensation is improved while maintaining the stability of the PLL circuit without requiring knowledge of the exact temperature characteristics of the VCO. Another advantage of some embodiments is that the secondary loop may provide a VCO control signal that is connected from the ground voltage of the VCO to the power supply voltage, which improves the temperature compensation capability of the PLL circuit. Another advantage of some embodiments is that by providing a compensation mode selection circuit for selecting from various programmable compensation modes using the primary loop control signal, the secondary loop control signal, and / or the open-loop temperature-dependent voltage control signal, greater flexibility is achieved in providing temperature compensation to the VCO.

[0038] Because one or more of the above embodiments are illustrated using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

[0039] A programmable logic device ("PLD") is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD, a field programmable gate array ("FPGA"), typically includes an array of programmable tiles. These programmable tiles may include, for example, input / output blocks ("IOBs"), configurable logic blocks ("CLBs"), application specific random access memory ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), and the like. As used herein, the terms "include" and "including" mean including, but not limited to, these.

[0040] Each programmable cell block typically includes programmable interconnects and programmable logic. The programmable interconnects typically include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). Programmable logic implements user-designed logic using programmable elements, which may include, for example, function generators, registers, arithmetic logic, and so on.

[0041] Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. Configuration data can be read from or written to the FPGA by an external device from memory (e.g., from an external PROM). The collective state of the individual memory cells then determines the functionality of the FPGA.

[0042] Another type of PLD is a complex programmable logic device (CPLD). A CPLD consists of two or more "function blocks" that are connected together and to input / output ("I / O") resources through an interconnect switch matrix. Each function block of a CPLD consists of a two-level AND / OR structure similar to those used in programmable logic arrays ("PLAs") and programmable array logic ("PAL") devices. In a CPLD, configuration data is typically stored in on-chip nonvolatile memory. In some CPLDs, configuration data is stored in on-chip nonvolatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

[0043] Generally speaking, in each of these programmable logic devices ("PLDs"), the functionality of the device is controlled by configuration data provided to the device for this purpose. The configuration data can be stored in volatile memory (e.g., static memory cells commonly found in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory in some CPLDs), or any other type of memory cell.

[0044] Other PLDs are programmed by applying a processing layer (e.g., a metal layer) that programmably interconnects the various components on the device. These PLDs are known as mask-programmable devices. PLDs can also be implemented in other ways, such as using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switching fabric that programmably interconnects the hard-coded transistor logic.

[0045] As mentioned above, advanced FPGAs can include many different types of programmable logic blocks in an array. For example, Figure 1 An exemplary FPGA architecture 100 is shown. FPGA architecture 100 includes a number of different programmable blocks, including multi-gigabit transceivers ("MGTs") 101, configurable logic blocks ("CLBs") 102, random access memory blocks ("BRAMs") 103, input / output blocks ("IOBs") 104, configuration and clock logic ("CONFIG / CLOCKS") 105, digital signal processing blocks ("DSPs") 106, specialized input / output blocks ("I / Os") 107 (e.g., configuration ports and clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic, etc.). Some FPGAs also include specialized processor blocks ("PROCs") 110.

[0046] In some FPGAs, each programmable cell block may include at least one programmable interconnect element ("INT") 111 having connections to input and output terminals 120 of programmable logic elements within the same cell block, such as Figure 1 As shown in the example included at the top. Each programmable interconnect element 111 may also include a connection to an interconnect segment 122 of an adjacent programmable interconnect element in the same cell block or other cell blocks. Each programmable interconnect element 111 may also include a connection to an interconnect segment 124 of a general wiring resource between logic blocks (not shown). The general wiring resources may include wiring channels between logic blocks (not shown) including tracks of interconnect segments (such as interconnect segments 124) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of the general wiring resources (such as interconnect segments 124) may span one or more logic blocks. The programmable interconnect elements 111, together with the general wiring resources, implement a programmable interconnect structure ("programmable interconnect") for the FPGA shown.

[0047] In an example implementation, CLB 102 may include a configurable logic element ("CLE") 112 that can be programmed to implement user logic, plus a single programmable interconnect element ("INT") 111. BRAM 103, in addition to including one or more programmable interconnect elements, may also include a BRAM logic element ("BRL") 113. Typically, the number of interconnect elements included in a cell block depends on the height of the cell block. In the illustrated example, the BRAM cell block has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, DSP cell block 106 may also include a DSP logic element ("DSPL") 114. In addition to one instance of programmable interconnect element 111, IOB 104 may include, for example, two instances of input / output logic element ("IOL") 115. It will be apparent to those skilled in the art that, for example, the actual I / O pads connected to I / O logic element 115 are generally not limited to the area of ​​input / output logic element 115.

[0048] exist Figure 1 In the example of Figure 1 Areas 105, 107, and 108 shown in FIG. 1 and 2 may be used for configuration, clock, and other control logic. Columns 109 (depicted vertically) extending from this horizontal area or other columns may be used to distribute clock and configuration signals across the width of the FPGA.

[0049] use Figure 1 Some FPGAs of the illustrated architecture include additional logic blocks that disrupt the conventional columnar structure that makes up a large portion of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic. For example, PROC 110 spans multiple columns of CLBs and BRAMs. PROC 110 can include a variety of components, from a single microprocessor to a complete programmable processing system with a microprocessor, memory controller, peripherals, etc.

[0050] In one aspect, PROC 110 is implemented as a dedicated circuit, e.g., as a hard-wired processor that is fabricated as part of a die that implements programmable circuitry of an IC. PROC 110 may represent any of a variety of different processor types and / or systems, ranging in complexity from a single processor (e.g., a single core capable of executing program code) to an entire processor system having one or more cores, modules, coprocessors, interfaces, etc.

[0051] Alternatively, PROC 110 may be omitted from architecture 100 and replaced by one or more of the other types of programmable blocks described. Furthermore, such blocks may be used to form a "soft processor," where various blocks of programmable circuitry may be used to form a processor that executes program code, as in the case of PROC 110.

[0052] The phrase "programmable circuitry" may refer to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or cells described herein, as well as interconnect circuitry that selectively couples the various circuit blocks, cells, and / or elements according to configuration data loaded into the IC. For example, Figure 1 Portions shown external to PROC 110, such as CLB 102 and BRAM 103, may be considered programmable circuitry of the IC.

[0053] In some embodiments, the functionality and connectivity of the programmable circuits are not established until configuration data is loaded into the IC. A set of configuration data can be used to program the programmable circuits of an IC, such as an FPGA. In some cases, the configuration data is referred to as a "configuration bitstream." Typically, the programmable circuits will not operate or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a specific circuit design within the programmable circuits. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

[0054] In some embodiments, "hardwired" or "hardened" (i.e., non-programmable) circuits are manufactured as part of an IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented by loading a configuration bitstream after the IC is manufactured. Hardwired circuits are generally considered to have dedicated circuit blocks and interconnects, e.g., they can operate without first loading a configuration bitstream into the IC (e.g., PROC 110).

[0055] In some cases, hardwired circuits can have one or more operating modes that can be set or selected based on register settings or values ​​stored in one or more memory elements within the IC. For example, the operating mode can be set by loading a configuration bitstream into the IC. Despite this capability, hardwired circuits are not considered programmable circuits because they are operational and have a specific function when they are manufactured as part of the IC.

[0056] Figure 1 The present invention is intended to illustrate exemplary architectures that can be used to implement an IC that includes programmable circuitry (e.g., programmable fabric). For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the order of the logic blocks in the rows. Figure 1The interconnect / logic implementation schemes included at the top of the FIGURE are purely exemplary. For example, in a real IC, more than one adjacent CLB row is typically included wherever a CLB appears to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. In addition, Figure 1 An FPGA is shown as one example of a programmable IC that can employ examples of the interconnect circuits described herein. The interconnect circuits described herein can be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements.

[0057] It should be noted that the IC that can implement one or more embodiments described herein is not limited to Figure 1 The example ICs depicted in FIG. 1 are not limited to the example ICs depicted in FIG. 1 , and ICs having other configurations or other types of ICs may also implement those embodiments.

[0058] refer to Figure 2 As an example, the figure shows a temperature compensated PLL circuit 200, also referred to as a PLL circuit 200. The PLL circuit 200 receives a reference frequency F ref The reference signal 214 (also referred to as the reference clock signal 214) is used to generate the output signal 216 (also referred to as the output clock signal 216). When the PLL circuit 200 operates in the lock mode, the output signal 216 has a phase and frequency relationship with the reference signal 214. In one example, in the lock mode, the frequency F of the output signal 216 is out is the reference frequency F ref N times, where N is a programmable positive integer.

[0059] The PLL circuit 200 includes a primary loop 220 (also referred to as the PLL loop 220) and a secondary loop 222 (also referred to as an auxiliary loop 222 or a temperature compensation loop 222). The primary loop 220 includes a phase frequency detector (PFD) circuit 202, a charge pump circuit 204, a filter circuit 206 (also referred to as a loop filter circuit 206), a voltage controlled oscillator (VCO) 208, and a frequency divider circuit 212 (also referred to as a feedback frequency divider circuit 212). The secondary loop 222 includes the PFD circuit 202, the charge pump circuit 204, the compensation circuit 210, the VCO 208, and the frequency divider circuit 212.

[0060] like Figure 2 As shown in the example of FIG, the reference signal 214 is coupled to the PFD circuit 202. The PFD circuit 202 also receives a feedback signal 217 having a frequency F of the output signal 216. out1 / N of the reference signal 214, where N is a programmable positive integer. PFD circuit 202 generates an output signal 219 indicating the frequency and / or phase difference between reference signal 214 and feedback signal 217. Feedback signal 217 is generated by divider circuit 212 based on output signal 216. When PLL circuit 200 operates in locked mode, feedback signal 217 may have the same frequency and / or phase as reference signal 214.

[0061] The PFD circuit 202 is coupled to a charge pump circuit 204. The charge pump circuit 204 receives a signal 219 from the PFD circuit 202 and generates an output signal 224. The output signal 224 may include a bias voltage in response to the signal 219 from the PFD circuit 202. The output signal 224 of the charge pump circuit 204 may be coupled to the loop filter circuit 206.

[0062] The loop filter circuit 206 may include any suitable filter circuit, including, for example, a low-pass filter. Examples of low-pass filters include resistor-capacitor (RC) filters, resistor-inductor (RL) filters, and resistor-inductor-capacitor (RLC) filters. The loop filter circuit 206 generates a VCO control signal 226 (also referred to as Vctrl1) and provides the VCO control signal 226 to the voltage-controlled oscillator (VCO) 208. In various embodiments, the loop filter circuit 206 may determine the loop dynamics of the main loop 220, also referred to as the stability of the main loop, which indicates how the main loop responds to disturbances (e.g., the reference frequency F ref , changes in divider circuit 212, etc.). Loop filter circuit 206 can be used to suppress voltage ripple or noise in signal 224. Some design tradeoffs for loop filter circuit 206 in PLL circuit 200 include, for example, increasing loop bandwidth may reduce stability, and heavy damping for better stability may reduce speed and increase settling time. In some examples, loop filter circuit 206 is programmable and includes programmable resistors and / or programmable capacitors.

[0063] The VCO circuit 208 can generate an oscillating output signal 216, wherein the output signal 216 has a higher frequency or a lower frequency in response to the VCO control signal 226 (e.g., its bias voltage). The output signal 216 can be provided to a circuit that requires a clock signal with a frequency that is different from the F of the reference signal 214. ref With the relationship (for example, N*F ref ).

[0064] exist Figure 2In the example of FIG, the secondary loop 222 includes a compensation circuit 210. The compensation circuit receives the output signal 224 from the charge pump 204, receives the reference voltage signal 218 having the reference voltage Vref, generates a VCO control signal 228 (also referred to as Vctrl2), and provides the VCO control signal 228 to the VCO circuit 208 for controlling the frequency F of the output signal 216. out In some embodiments, the reference voltage Vref is determined based on the operating range of the charge pump 204 . In one example, the reference voltage Vref is determined to ensure that the signal 224 is within the operating range of the charge pump 204 .

[0065] refer to Figure 3 , an example compensation circuit 300 in the secondary loop 222 is shown (eg, Figure 2 Compensation circuit 300 includes an operational amplifier 304 and a filter circuit 306 (also referred to as loop filter circuit 306). Signal 224 having voltage V1 from charge pump 204 is provided to operational amplifier 304 (e.g., at the non-inverting input of operational amplifier 304). Operational amplifier 304 also receives reference voltage Vref 218 (e.g., at the inverting input of operational amplifier 304). In one example, Vref 218 can be provided based on a predetermined reference voltage value or externally set by an operator. Vref 218 can be determined based on the phase noise performance of the VCO circuit. The gain A of operational amplifier 304 can be determined based on the performance requirements of PLL circuit 200. For example, a higher gain A can be selected so that operational amplifier 304 forces the voltage V1 of signal 224 to be closer to reference voltage Vref 218 within the voltage variation range of voltage V1.

[0066] In various embodiments, a voltage divider may be used to scale signal 224 to the input voltage at the non-inverting input of operational amplifier 304 based on parameters of operational amplifier 304. In those embodiments, reference voltage Vref 218 may be scaled accordingly.

[0067] Operational amplifier 304 amplifies the differential input voltage, ie, the voltage difference between V1 of signal 224 and Vref 218, and generates output signal 310. The output voltage of signal 310 may be provided as A*(V1-Vref).

[0068] Loop filter 306 receives signal 310 from operational amplifier 304 and generates output signal 228. In some embodiments, loop filter 306 is a low-pass filter and is designed to make the loop response of secondary loop 222 slower than the loop response of primary loop 220, which improves the stability of PLL circuit 200.

[0069] refer to Figure 4A and 4B , which shows an example without the secondary loop 222 ( Figure 4A Curves 402 and 452) and the temperature compensation loop with secondary loop 222 ( Figure 4B 4 and 404). As discussed in detail below, in various embodiments, the secondary loop 222 is designed so that it does not affect the stability of the PLL circuit 200. Specifically, the secondary loop 222 can be designed (e.g., using design parameters of the Vref 218, the operational amplifier 304, and / or the loop filter 306) so that the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled meets various design requirements, including, for example, phase margin requirements to ensure the stability of the PLL circuit 200.

[0070] exist Figure 4A , are magnitude curves 402 and 404 of the PLL circuit 200. Specifically, the magnitude curve 402 corresponds to the PLL circuit 200 operating with the secondary loop 222 disabled. In other words, the magnitude curve 402 corresponds to the PLL circuit 200 operating with only the primary loop 220 enabled. The magnitude curve 404 corresponds to the PLL circuit 200 operating with the secondary loop 222 enabled. In other words, the magnitude curve 404 corresponds to the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled.

[0071] exist Figure 4B 4 are phase curves 452 and 454 of the PLL circuit 200. Specifically, the phase curve 452 corresponds to the PLL circuit 200 operating with the primary loop 220 enabled and the secondary loop 222 disabled. As shown by the magnitude curve 402 and the phase curve 452, the phase margin Pm1 456 of the primary loop 220 (e.g., approximately 60°) is the difference between the phase of the response 452 and −180° at the frequency 406 when the loop gain of the primary loop 220 is 1.0 (e.g., where the magnitude of the response is 0 dB). The phase curve 454 corresponds to the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled.

[0072] As in Figure 4A and 4BAs shown in the example of FIG, the secondary loop 222 is designed so that the phase margin Pm2 of the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled meets the phase margin requirement. The phase margin requirement can be based on the phase margin Pm1 456 of the primary loop 220. In one example, the secondary loop 222 is designed so that the difference between the phase margins Pm1 and Pm2 is less than 10% of the phase margin Pm1. In another example, the secondary loop 222 is designed so that the difference between the phase margins Pm1 and Pm2 is less than 1% of the phase margin Pm1.

[0073] In various embodiments, the design parameters (e.g., cutoff frequency) of the loop filter 306 (e.g., a low-pass filter) can be determined to meet the design requirements of the PLL circuit 200 operating with the primary loop 220 and the secondary loop 222 enabled. In some embodiments, the loop filter 306 is designed so that the loop bandwidth of the secondary loop 222 is less than the loop bandwidth of the primary loop 220. In one example, the loop bandwidth of the primary loop 220 (e.g., approximately 1 MHz) is equal to or greater than 10 times the loop bandwidth of the secondary loop 222 (e.g., approximately 10 kHz). In this particular example, the difference between the phase margins Pm1 and Pm2 is less than 1% of the phase margin Pm1.

[0074] As in Figure 5A 、 5B As shown in the examples of FIG5C , by using the secondary loop 222 and the primary loop 220 together in the PLL circuit 200, the effects of temperature changes on the PLL circuit 200 (e.g., the frequency drift of the VCO) are compensated. Specifically, the secondary loop 222 includes a closed-loop temperature tracking loop that continuously monitors temperature changes and provides an appropriate control signal 228 to the VCO 208 to compensate for the temperature changes. Figure 5A In the example of FIG. 2 , voltage curves 224 - 1 and 224 - 2 of the PLL circuit 200 are shown. Specifically, the voltage curve 224 - 1 shows a voltage versus time curve of the signal 224 when the PLL circuit 200 operates with the secondary loop 222 disabled. In other words, the voltage curve 224 - 1 corresponds to the PLL circuit 200 operating with only the primary loop 220 enabled. The voltage curve 224 - 2 shows a voltage versus time curve of the signal 224 when the PLL circuit 200 operates with the secondary loop 222 enabled. In other words, the voltage curve 224 - 2 corresponds to the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled.

[0075] exist Figure 5B In the example of FIG. 5 , a temperature difference curve 506 is shown, which indicates the temperature difference at corresponding time. Figure 5BAs shown, the temperature changes from temperature Temp1 to temperature Temp2 between time 502 and time 504. In one example, this temperature increase results in a voltage change in voltage curves 224-1 and / or 224-2.

[0076] Review Reference Figure 5A As shown by voltage curve 224-2, by using secondary loop 222 in PLL circuit 200, the voltage of signal 224-2 is more stable during time 502 and 504 (e.g., compared to signal 224-1). This is achieved by using secondary loop 222 to compensate for temperature changes. Figure 5C As an example, the frequency curve of the output signal 216 of the VCO 208 is shown in the figure. Figure 5C As shown, due to the use of the secondary loop 222 , the effect of temperature variations on the frequency of the signal 216 is reduced, thereby providing a more stable frequency of the output signal 216 of the VCO 208 .

[0077] refer to Figure 6A 、 6B , 6C and 6D, the figures show a ring VCO 600 (e.g., Figure 2 VCO 208). In various embodiments, a PLL circuit using a ring VCO has a significant area advantage over a corresponding PLL circuit using an LC-tank VCO, but may be susceptible to temperature variations, especially in highly scaled processes such as 7nm processes. By using secondary loop 222 as a closed-loop temperature tracking loop that continuously monitors voltage variations caused by temperature and provides appropriate control signals to cancel the voltage variations, temperature variations in the PLL circuit using a ring VCO are compensated, and PLL performance is improved by providing a more stable output frequency.

[0078] like Figure 6A As shown, the ring VCO 600 is a pseudo differential three-stage VCO. Figure 6B and 6C As shown, in the ring VCO 600, coarse frequency control can be implemented by using a pMOS transistor and a control signal 622 (e.g., coarse_b<5:0>) in the power path 620 and an nMOS transistor and a control signal 642 (e.g., coarse_b<5:0>) in the ground path 640, respectively. Figure 6A and 6DAs shown, fine frequency tuning of the ring VCO 600 is achieved by using various control paths. For example, the control path may include a Kvco1 path that uses a control signal 606 (also referred to as a Kvco1 signal 606) to control variable capacitors 602-1, 602-2, and 602-3 of the three-stage delay cells of the ring VCO 600. For further example, the control path may include a Kvco2 path that uses a control signal 608 (also referred to as a Kvco2 signal 608) that closes the secondary loop 222 to control variable capacitors 604-1, 604-2, and 604-3 of the three-stage delay cells of the ring VCO 600. For further example, Figure 6D As shown, the control path may include a Kvco3 path that uses an nMOS current source control circuit 660 having a control signal 662 (also referred to as Kvco3 signal 662 ) (eg, by controlling avss_reg).

[0079] refer to Figure 7 and 8 For example, a PLL circuit including its Kvco1, Kvco2 and Kvco3 paths (e.g., having Figure 2 The PLL circuit 200 (including the primary loop 220 and the secondary loop 222) can be programmed to operate in various compensation modes. Figure 7 A compensation mode control circuit 700 is shown, wherein compensation mode control signals Ctrl1 702 and Ctrl2 706 can be programmed (e.g., using switches 704 and 708, respectively) to generate a Kvco1 signal 606, a Kvco2 signal 608, and a Kvco3 signal 662 using Vctrl1 226, Vctrl2 228, and a temperature-dependent voltage Vte 710, wherein the temperature-dependent voltage Vte 710 is generated by an open loop having a temperature-dependent voltage circuit 712. For example, the Kvco1 path can be used for the primary loop 220 (e.g., signal 226 of the primary loop 220 is used as the Kvco1 signal 606). Further, for example, the Kvco2 path can be programmed for use in the primary loop 220 (e.g., signal 226 of the primary loop 220 is used as the Kvco2 signal 608) or in the secondary loop 222 (e.g., signal 228 of the secondary loop 222 is used as the Kvco2 signal 608). As another example, the Kvco3 path may be programmed for the secondary loop 222 (eg, the signal 228 of the secondary loop 222 is used as the Kvco3 signal 662 ) or for an open loop with the temperature dependent voltage circuit 712 .

[0080] refer to Figure 8, various compensation modes 802 are illustrated. For example, in the "fully open loop" mode, the signal 226 of the primary loop 220 is provided as the Kvco1 signal 606 and the Kvco2 signal 608, and the open loop Vte 710 is provided as the Kvco3 signal 662 for temperature compensation. In other words, in the "fully open loop" mode, the signal 228 of the secondary loop 222 is not used for temperature compensation.

[0081] By further example, in the “closed loop through variable capacitors, open loop through current sources” mode, signal 226 of primary loop 220 is provided as Kvco1 signal 606, signal 228 of secondary loop 222 is provided as Kvco2 signal 608 (e.g., providing a closed loop for compensation through variable capacitors 604-1, 604-2, and 604-3), and open loop Vte 710 is provided as Kvco3 signal 662 (e.g., providing an open loop for compensation through current source control circuit 660).

[0082] Further for example, in the “closed loop via current source” mode, the signal 226 of the primary loop 220 is provided as the Kvco1 signal 606 and the Kvco2 signal 608, and the signal 228 of the secondary loop 222 is provided as the Kvco3 signal 662 for temperature compensation (e.g., a closed loop for compensation is provided via the current source control circuit 660).

[0083] By further example, in the “closed loop through variable capacitors and current sources” mode, the signal 226 of the primary loop 220 is provided as the Kvco1 signal 606, and the signal 228 of the secondary loop 222 is provided as the Kvco2 signal 608 (e.g., providing a closed loop for compensation through the variable capacitors 604-1, 604-2, and 604-3) and the Kvco3 signal 662 (e.g., providing a closed loop for compensation through the current source control circuit 660).

[0084] refer to Figure 9 The figure shows an example that is basically similar to Figure 2 The PLL circuit 900 is similar to the PLL circuit 200, except for the differences described below. The PLL circuit 900 includes a primary loop 220, a secondary loop 222, and an open loop using a temperature-dependent voltage Vte 710 generated by a temperature-dependent voltage circuit 712. The temperature-dependent voltage Vte 710 is provided to the VCO 208 for use in outputting the frequency of the signal 216 (e.g., as described above with reference to FIG. 1 ). Figure 7 and 8 Frequency tuning in the discussed "fully open loop mode" or "closed loop through variable capacitor, open loop through current source" mode).

[0085] It should be pointed out that Figure 1-9 The various structures shown are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow. Those skilled in the art will appreciate that other configurations may be used. One or more elements in various embodiments may be implemented using software, hardware (e.g., an application-specific integrated circuit (ASIC), an application-specific standard component (ASSP), logic on a programmable logic IC (e.g., an FPGA)), firmware, and / or a combination thereof. Embodiments may be implemented using various hardware resources, such as DSP chips, BRAM, and programmable resources of an FPGA; however, in other embodiments, digital signal processors, microprocessors, multi-core processors, memory, and / or other hardware may be used. When implemented in software, the elements of an embodiment of the present invention are essentially code segments that perform the necessary tasks. Programs or code segments may be stored in a processor-readable storage medium or device, which may be downloaded via a computer data signal embodied in a carrier wave on a transmission medium or communication link. Processor-readable storage devices may include any medium that can store information, including optical, semiconductor, and magnetic media. Examples of processor-readable storage devices include electronic circuits; semiconductor devices, semiconductor memory devices, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM); floppy disks, CD-ROMs, optical disks, hard disks, or other storage devices. The code segments may be downloaded via a computer network such as the Internet, an intranet, or the like.

[0086] Although specific embodiments have been shown and described, it should be understood that it is not intended to limit the claimed invention to the preferred embodiments, and that various changes and modifications are apparent to those skilled in the art without departing from the spirit and scope of the claimed invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive. The claimed invention is intended to cover alternatives, modifications, and equivalents.

Claims

1. A phase-locked loop (PLL) circuit, characterized in that: The PLL circuit comprises: Voltage controlled oscillator VCO; A first loop circuit comprising a first loop filter, wherein the first loop filter is configured to: receiving a first signal based on a feedback signal from the VCO; and providing a first VCO frequency control signal to the VCO; a second loop circuit comprising a compensation circuit, wherein the compensation circuit is configured to: receiving a reference signal and the first signal; and providing a second VCO frequency control signal to the VCO; and A compensation mode selection circuit is configured to selectively provide the second VCO frequency control signal to an input terminal of the VCO.

2. The PLL circuit according to claim 1, wherein: A first bandwidth of the first loop circuit is greater than a second bandwidth of the second loop circuit.

3. The PLL circuit according to claim 2, wherein: The first bandwidth is greater than the second bandwidth by at least 10 times.

4. The PLL circuit according to any one of claims 1 to 3, wherein: The compensation circuit comprises: an operational amplifier configured to generate a second signal based on the first signal and the reference signal; and A second loop filter is configured to generate the second VCO frequency control signal based on the second signal.

5. The PLL circuit according to claim 4, wherein: The second loop filter is a low-pass filter configured to make a first bandwidth of the first loop circuit greater than a second bandwidth of the second loop circuit.

6. The PLL circuit according to any one of claims 1 to 3 and 5, characterized in that: The second VCO frequency control signal has a minimum voltage that is the same as a ground voltage.

7. The PLL circuit according to any one of claims 1 to 3 and 5, characterized in that: The VCO includes a ring oscillator.

8. The PLL circuit according to any one of claims 1 to 3 and 5, characterized in that: The second VCO frequency control signal is configured to control at least one of a variable capacitor of the VCO and a current source of the VCO to control an output frequency of the VCO.

9. The PLL circuit according to any one of claims 1 to 3 and 5, characterized in that: The VCO is configured as: A third VCO frequency control signal is received from an open-loop temperature dependent voltage circuit.

10. The PLL circuit according to claim 9, wherein: The compensation mode selection circuit is configured to select a compensation mode from the following to control the output frequency of the VCO: a first compensation mode, wherein the second VCO frequency control signal is configured to control one of a variable capacitor of the VCO and a current source of the VCO; a second compensation mode, wherein the second VCO frequency control signal is configured to control the other of a variable capacitor of the VCO and a current source of the VCO; a third compensation mode, wherein the second VCO frequency control signal is configured to control both a variable capacitor of the VCO and a current source of the VCO; and A fourth compensation mode, wherein the third VCO frequency control signal is configured to control both a variable capacitor of the VCO and a current source of the VCO.

11. A method for a phase-locked loop circuit, characterized in that: The method comprises: receiving a first signal based on a feedback signal from a voltage controlled oscillator (VCO) through a first loop filter of a first loop circuit; providing a first VCO frequency control signal to the VCO through the first loop filter; receiving a reference signal and the first signal through a compensation circuit of a second loop circuit; providing, by the compensation circuit, a second VCO frequency control signal to the VCO based on a difference between the reference signal and the first signal; and The second VCO frequency control signal is selectively provided to the input terminal of the VCO through the compensation mode selection circuit.

12. The method according to claim 11, characterized in that The method further comprises: generating, by the compensation circuit, a second signal based on a difference between the first signal and the reference signal; and The second VCO frequency control signal is generated based on the second signal by using a second loop filter of the compensation circuit.

13. The method according to claim 11 or 12, characterized in that The method further comprises: At least one of a variable capacitor of the VCO and a current source of the VCO is controlled by the second VCO frequency control signal to control an output frequency of the VCO.

14. The method according to any one of claims 11 or 12, characterized in that The method further comprises: A third VCO frequency control signal from an open-loop temperature-dependent voltage circuit is received through the VCO.

15. The method according to claim 14, characterized in that The method further comprises: Select a compensation mode to control the VCO output frequency from the following: a first compensation mode, wherein the second VCO frequency control signal is configured to control one of a variable capacitor of the VCO and a current source of the VCO; a second compensation mode, wherein the second VCO frequency control signal is configured to control the other of a variable capacitor of the VCO and a current source of the VCO; a third compensation mode, wherein the second VCO frequency control signal is configured to control both a variable capacitor of the VCO and a current source of the VCO; and A fourth compensation mode, wherein the third VCO frequency control signal is configured to control both a variable capacitor of the VCO and a current source of the VCO.

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