Method for multiple analog-to-digital conversion

Abstract

A method for multi-analog-to-digital conversion, comprising: one ADC among a plurality of analog-to-digital converters (ADCs) receives a ramp reference signal from a ramp generator; a control circuit in the ADC generates a local ramp signal according to the received ramp reference signal; a comparator in the ADC compares an analog signal input to the ADC with the local ramp signal; and the ADC generates a digital signal according to the output of the comparator. The local ramp signal is generated by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator. Within a predetermined period after a reset is performed in at least one of the plurality of ADCs, the signal level of the ramp reference signal output from the ramp generator remains unchanged, and the process of the ADC generating a digital signal is suspended.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter (ADC), and more particularly to a multi-conversion ADC. More specifically, the present invention relates to a single-slope ADC (SSADC) with a multi-conversion function. The present invention also relates to an image sensor for generating a digital image such as a static image (still image) or a moving image (video image). In addition, the present invention relates to a device including an image sensor, such as a mobile device, a digital camera, etc. Background Art

[0002] Digital cameras, digital video cameras and devices with camera functions (for example, mobile phones, smart phones, wireless communication terminals, tablet devices, personal computers, etc.) all include image sensors of complementary metal-oxide-semiconductor (CMOS) or charge coupled device (CCD) type.

[0003] The image sensor includes a plurality of pixel units, the pixel units outputting analog signals of signal levels corresponding to the intensity of incident light, and a plurality of ADCs for converting those analog signals output from the pixel units into digital signals.

[0004] Single slope ADC (SS ADC) is a type of ADC. SS ADC enables a comparator to compare a reference signal with a ramp waveform (ramp reference signal) with the analog signal output by the pixel unit, and outputs a digital signal according to the output of the comparator. SS ADC can reduce time noise such as quantization and input noise, and has the advantages of low power consumption and small silicon area.

[0005] Regarding SS ADC, the specification of US Pat. No. 8,816,893 proposes an SS ADC with a multi-conversion function (multi-conversion ADC). The multi-conversion ADC performs the conversion of an analog signal to a digital signal multiple times and outputs an average value of the conversion results in each cycle of a ramp reference signal. The average conversion result reduces quantization noise and noise in the analog signal and the ramp reference signal.

[0006] The multi-conversion ADC (ADC 90) is further described below with reference to Figures 6 and 7. Figure 6 is a schematic circuit diagram of an AD converter provided in the related art. Figure 7 is a timing diagram of a modification of a ramp reference signal provided in the related art.

[0007] As shown in FIG6 , in ADC 90, the analog signal is input to the negative (-) input terminal of the comparator through capacitor C0. The ramp reference signal is input to the positive (+) input terminal of the comparator through capacitors C1 and C2. The signal level of the ramp reference signal is reset by the on / off switching of switch SW1. In FIG6 , the ramp reference signal after reset is represented as a “modified ramp reference signal”.

[0008] The on / off switching of the switch SW1 is controlled by the ramp control signal output by the control circuit. The control circuit performs the on / off switching of the switch SW1 according to the output of the comparator. For example, when the reset ramp reference signal is equal to or less than the input pixel signal, the control circuit performs the on / off switching in response to the Hi level signal output from the comparator.

[0009] For example, as shown in FIG7 , the signal level of the ramp reference signal is reset once in the LARGE SIGNALSAMPLING section, and its waveform is modified to include two tooth waves. In this section, one AD conversion is performed. In the SMALL SIGNAL SAMPLING section, the signal level of the ramp reference signal is reset five times, and its waveform is modified to include six tooth waves. In this section, six AD conversions are performed.

[0010] The conversion counter counts the number of AD conversions in each cycle of the ramp reference signal according to the output of the comparator. When the output of the comparator is at the HI level, the summing counter counts the number of pulses of the master clock. The arithmetic operator divides the counting result performed by the summing counter by the counting result of the conversion counter to calculate the average value. This averaging method reduces quantization noise and input noise. The image sensor includes a plurality of ADCs, each of which has the same structure as ADC 90, and these ADCs are electrically connected to each other through a common ramp reference line for transmitting the ramp reference signal.

[0011] In the above-mentioned ADC 90, the on / off switching of the switch SW1 generates an instantaneous current, so that the switching noise voltage can appear in the common ramp reference line due to its parasitic resistance. The switching noise voltage causes interference of the ramp reference signal waveform, and the interference causes other comparators to output wrong comparison results. In addition, the error in the comparator output generates noise (switching noise) in the digital signal. The interference of the ramp reference signal waveform is propagated to other ADCs through the common ramp reference line. Therefore, the switching noise (i.e., crosstalk noise) propagated by the common reference line causes the quality of the digital image finally output from the image sensor to be reduced. Summary of the invention

[0012] The embodiments provide an AD converter, an image sensor, a mobile device or a digital camera, a method for converting an analog signal into a digital signal, and a method for generating a digital image. For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, etc., and may capture images and / or videos.

[0013] To achieve the above purpose, the embodiment adopts the following technical solutions:

[0014] A first aspect of an embodiment provides a method for performing multi-analog-to-digital conversion. The method according to the first aspect includes:

[0015] An ADC among a plurality of analog-to-digital converters (ADCs) receives a ramp reference signal from a ramp generator;

[0016] The control circuit in the ADC generates a local ramp signal according to the received ramp reference signal;

[0017] The comparator in the ADC compares the analog signal input to the ADC with the local ramp signal;

[0018] The ADC generates a digital signal according to the output of the comparator,

[0019] wherein the local ramp signal is generated by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator,

[0020] Within a predetermined period after the at least one ADC among the plurality of ADCs is reset, the signal level of the ramp reference signal output from the ramp generator remains unchanged, and the process of the ADC generating a digital signal is suspended.

[0021] According to the first aspect, within a predetermined period after a reset is performed in at least one of the multiple ADCs, the process of the ADC generating a digital signal is suspended, so that noise caused by the reset in at least one of the multiple ADCs can be prevented from interfering with the digital signal.

[0022] Specifically, even if the noise generated in a certain ADC is propagated to other ADCs through the common ramp reference line, the interference caused by the noise will not occur on the digital signal in any of these ADCs, thereby avoiding the interference of crosstalk noise on the digital signal. During the period when the process of generating the digital signal is suspended, AD conversion is not performed, so that the number of AD conversions can be reduced, thereby reducing the power consumption of the ADC. In addition, the multi-AD conversion can also reduce time noise such as quantization noise and input noise.

[0023] According to the first aspect, in a first possible implementation manner of the method, generating a digital signal includes:

[0024] Calculating the number of transitions in each cycle of the ramp reference signal;

[0025] counting the number of pulses of the master clock when the output of the comparator is at a predetermined level;

[0026] generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock,

[0027] The counting of the number of conversions and the counting of the number of pulses of the main clock are suspended within a predetermined period after at least one ADC among the plurality of ADCs is reset.

[0028] According to the first possible implementation of the first aspect, within a predetermined period after a reset is performed in at least one of the multiple ADCs, the calculation of the number of conversions in each period of the ramp reference signal and the number of pulses of the calculation master clock are suspended. This makes it possible to avoid the influence of noise generated by the reset of the received ramp reference signal on the counting result, so that even if the noise causes the comparator to output an erroneous comparison result, the noise can be prevented from interfering with the digital signal. In addition, the counting process is stopped within the period in which the calculation of the number of conversions and the number of pulses of the calculation master clock are suspended, so that the processing load can be reduced, thereby reducing the power consumption of the ADC.

[0029] According to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the method, the method further includes:

[0030] The ADC receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein the width of each pulse in the pulse train corresponds to the predetermined period after the reset,

[0031] The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

[0032] According to the second possible implementation of the first aspect, the signal level of the received ramp reference signal is reset according to a pulse train having a shorter period than the ramp reference signal period, and multiple AD conversions are performed in each period of the ramp reference signal. In addition, the width of each pulse in the pulse train corresponds to the predetermined period after the reset, and the signal level of the received ramp reference signal is reset to the predetermined initial level at the rising edge of the pulse in the pulse train, so that the noise can be prevented from interfering with the digital signal by using the pulse train. In particular, providing a pulse train to each ADC allows each ADC to easily implement the above control.

[0033] According to the first aspect or the first possible implementation manner of the first aspect or the second possible implementation manner of the first aspect, in a third possible implementation manner of the method,

[0034] The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed by switching a switch circuit,

[0035] The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

[0036] According to the third possible implementation method of the first aspect, the predetermined period after the reset is set to a period longer than the establishment time of the transient phenomenon caused by the switching of the switching circuit, so that the switching noise caused by the switching of the switching circuit can be avoided from interfering with the digital signal.

[0037] According to the first aspect or the second possible implementation of the first aspect, in a fourth possible implementation of the method, the pulse train is set in such a way that one pulse in the pulse train appears for every N pulses (N≥2) of the master clock. For example, when the resolution of the AD conversion is 10 bits, N is set to 16, 32 or 64.

[0038] According to the fourth possible implementation method of the first aspect, the individual pulses in the pulse train are defined at equal intervals according to the pulses of the master clock, so that the pulse train can be easily set according to the resolution of the AD conversion and the maximum number of AD conversions that can be performed in each cycle of the ramp reference signal.

[0039] According to the first aspect or the second possible implementation manner or the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the method, the ramp reference signal is generated based on a set of pulses extracted from a master clock during the LO level duration of the pulse train.

[0040] According to the fifth possible implementation of the first aspect, each ADC can easily perform control to stop ramping down the ramp reference signal according to the pulse train during the period when the process of generating the digital signal is suspended.

[0041] A second aspect of an embodiment provides a multi-analog-to-digital conversion circuit. The circuit according to the second aspect includes:

[0042] A ramp generator, used for generating a ramp reference signal;

[0043] a plurality of analog-to-digital converters (ADCs) for receiving the ramp reference signal from the ramp generator, wherein one of the plurality of ADCs comprises:

[0044] a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal;

[0045] a comparator for comparing the analog signal input to the ADC with the local ramp signal,

[0046] in,

[0047] the controller generates a digital signal, wherein the digital signal resets the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator,

[0048] The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs,

[0049] The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

[0050] According to the second aspect,

[0051] Within a predetermined period after the at least one ADC among the plurality of ADCs is reset, the process of the ADC generating a digital signal is suspended, so that noise caused by the reset of the at least one ADC among the plurality of ADCs is prevented from interfering with the digital signal.

[0052] Specifically, even if the noise generated in a certain ADC is propagated to other ADCs through the common ramp reference line, the interference caused by the noise will not occur on the digital signal in any of these ADCs, thereby avoiding the interference of crosstalk noise on the digital signal. During the period when the process of generating the digital signal is suspended, AD conversion is not performed, so that the number of AD conversions can be reduced, thereby reducing the power consumption of the ADC. In addition, the multi-AD conversion can also reduce time noise such as quantization noise and input noise.

[0053] According to the second aspect, in a first possible implementation of the circuit,

[0054] The ADC performs the following operations:

[0055] Calculating the number of transitions in each cycle of the ramp reference signal;

[0056] counting the number of pulses of the master clock when the output of the comparator is at a predetermined level;

[0057] generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock,

[0058] The counting of the number of conversions and the counting of the number of pulses of the main clock are suspended within a predetermined period after at least one ADC among the plurality of ADCs is reset.

[0059] According to the first possible implementation manner of the second aspect,

[0060] In a predetermined period after a reset is performed in at least one of the plurality of ADCs, the calculation of the number of conversions per period of the ramp reference signal and the calculation of the number of pulses of the master clock are suspended. This makes it possible to avoid the influence of noise generated by the reset of the received ramp reference signal on the counting result, so that even if the noise causes the comparator to output an erroneous comparison result, the noise can be prevented from interfering with the digital signal. In addition, the counting process is stopped during the period in which the calculation of the number of conversions and the calculation of the number of pulses of the master clock are suspended, so that the processing load can be reduced, thereby reducing the power consumption of the ADC.

[0061] According to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the circuit,

[0062] The ADC also receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the reset,

[0063] The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

[0064] According to the second possible implementation of the second aspect, the signal level of the received ramp reference signal is reset according to a pulse train having a shorter period than the ramp reference signal period, and multiple AD conversions are performed in each period of the ramp reference signal. In addition, the width of each pulse in the pulse train corresponds to the predetermined period after the reset, and the signal level of the received ramp reference signal is reset to the predetermined initial level at the rising edge of the pulse in the pulse train, so that the noise can be prevented from interfering with the digital signal by using the pulse train. In particular, providing a pulse train to each ADC allows each ADC to easily implement the above control.

[0065] According to the second aspect or the first possible implementation manner of the second aspect or the second possible implementation manner of the second aspect, in a third possible implementation manner of the circuit,

[0066] The controller resets the signal level of the received ramp reference signal to a predetermined initial level by switching the switch circuit.

[0067] The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

[0068] According to the third possible implementation method of the second aspect, the predetermined period after the reset is set to a period longer than the establishment time of the transient phenomenon caused by the switching of the switching circuit, so that the switching noise caused by the switching of the switching circuit can be avoided from interfering with the digital signal.

[0069] According to the second aspect or the second possible implementation of the second aspect, in a fourth possible implementation of the circuit, the pulse train is set in such a way that one pulse in the pulse train appears for every N pulses (N≥2) of the master clock. For example, when the resolution of the AD conversion is 10 bits, N is set to 16, 32 or 64.

[0070] According to the fourth possible implementation method of the second aspect, the individual pulses in the pulse train are defined at equal intervals according to the pulses of the master clock, so that the pulse train can be easily set according to the resolution of the AD conversion and the maximum number of AD conversions that can be performed in each cycle of the ramp reference signal.

[0071] According to the second aspect or the second possible implementation manner or the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner of the method, the ramp generator generates the ramp reference signal based on a set of pulses extracted from a master clock during the LO level duration of the pulse train.

[0072] According to the fifth possible implementation of the second aspect, each ADC can easily perform control to stop ramping down the ramp reference signal according to the pulse train during the period when the process of generating the digital signal is suspended.

[0073] A third aspect of the embodiment provides an image sensor. The image sensor according to the third aspect includes:

[0074] A plurality of pixel units for generating an analog signal of a level corresponding to the amount of received light through photoelectric conversion;

[0075] a multi-analog-to-digital conversion circuit, configured to receive the analog signal outputted from at least one pixel unit among the plurality of pixel units as an analog signal,

[0076] The circuit comprises: a ramp generator for generating a ramp reference signal, and a plurality of analog-to-digital converters (ADCs) for receiving the ramp reference signal from the ramp generator, wherein one of the plurality of ADCs comprises:

[0077] a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal;

[0078] a comparator for comparing the analog signal input to the ADC with the local ramp signal,

[0079] in,

[0080] the controller generates a digital signal by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator,

[0081] The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs,

[0082] The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

[0083] According to the third aspect,

[0084] In a predetermined period after the at least one ADC among the plurality of ADCs is reset, the process of the ADC generating a digital signal is suspended, so that the noise caused by the reset of at least one ADC among the plurality of ADCs can be prevented from interfering with the digital signal. As a result, the noise of the digital signal output from the image sensor is reduced, thereby improving the quality of the output image.

[0085] Specifically, even if the noise generated in a certain ADC is propagated to other ADCs through the common ramp reference line, the interference caused by the noise will not occur on the digital signal in any of these ADCs, thereby avoiding the interference of the crosstalk noise on the digital signal. Although the generation of crosstalk noise can reduce the overall quality of the image output from the image sensor, the application of the above configuration avoids the crosstalk noise, which can significantly improve the overall quality of the image output from the image sensor having a large number of pixels.

[0086] In the period when the process of generating the digital signal is suspended, AD conversion is not performed, so that the number of AD conversions can be reduced, thereby reducing the power consumption of the ADC. In addition, the multiple AD conversion can reduce time noise such as quantization noise and input noise, which helps to further improve the quality of the output image.

[0087] According to the third aspect, in a first possible implementation manner of the image sensor, the image sensor may include the circuit according to any one of the first to fifth possible implementation manners of the second aspect.

[0088] A fourth aspect of the embodiment provides a device with a camera function. The device according to the fourth aspect may preferably be a digital camera or a mobile device, which can capture digital images, such as static images (still images) or moving images (video images). For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, etc., which can capture images and / or videos.

[0089] The device according to the fourth aspect comprises:

[0090] The image sensor comprises: a plurality of pixel units for generating an analog signal of a level corresponding to the amount of received light through photoelectric conversion; a multi-analog-to-digital conversion circuit for receiving the analog signal output from at least one analog unit among the plurality of pixel units as an analog signal,

[0091] The circuit comprises: a ramp generator for generating a ramp reference signal, and a plurality of analog-to-digital converters (ADCs) for receiving the ramp reference signal from the ramp generator, wherein one of the plurality of ADCs comprises:

[0092] a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal;

[0093] a comparator for comparing the analog signal input to the ADC with the local ramp signal,

[0094] in,

[0095] the controller generates a digital signal by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator,

[0096] The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs,

[0097] The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

[0098] According to the fourth aspect, within a predetermined period after the at least one ADC among the plurality of ADCs is reset, the process of the ADC generating a digital signal is suspended, so that the noise caused by the reset of at least one ADC among the plurality of ADCs can be prevented from interfering with the digital signal. As a result, the noise of the digital signal output from the image sensor is reduced, thereby improving the quality of the output image.

[0099] Specifically, even if the noise generated in a certain ADC is propagated to other ADCs through the common ramp reference line, the interference caused by the noise will not occur on the digital signal in any of these ADCs, thereby avoiding the interference of the crosstalk noise on the digital signal. Although the generation of crosstalk noise can reduce the overall quality of the image output from the image sensor, the application of the above configuration avoids the crosstalk noise, which can significantly improve the overall quality of the image output from the image sensor having a large number of pixel units.

[0100] In the period when the process of generating the digital signal is suspended, AD conversion is not performed, so that the number of AD conversions can be reduced, thereby reducing the power consumption of the ADC. The reduction in power consumption extends the battery-based operation time in small devices such as digital cameras or mobile devices, which helps to improve usability. In addition, the multi-AD conversion can reduce time noise such as quantization noise and input noise, which helps to further improve the quality of the output image.

[0101] According to the fourth aspect, in a first possible implementation manner of the device, the image sensor in the device may include a circuit according to any one of the first to fifth possible implementation manners of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] Figure 1 A schematic block diagram of a description device provided for an embodiment of the present invention.

[0103] Figure 2 A schematic diagram describing an image sensor provided in accordance with an embodiment of the present invention.

[0104] Figure 3 A schematic circuit diagram describing a multi-AD conversion circuit provided in an embodiment of the present invention.

[0105] Figure 4 A schematic circuit diagram describing a controller in a multi-AD conversion circuit provided in an embodiment of the present invention.

[0106] Figure 5 A timing diagram describing signals and clocks in a readout circuit is provided for an embodiment of the present invention.

[0107] FIG. 6 is a schematic circuit diagram illustrating an AD converter provided in the related art.

[0108] FIG. 7 is a timing diagram illustrating modification of a ramp reference signal provided by the related art. DETAILED DESCRIPTION

[0109] The technical scheme of the embodiment will be described below in conjunction with the accompanying drawings. It is understood that the embodiments described below are not all embodiments, but only some embodiments related to the present invention. It should be noted that other embodiments that can be obtained according to the embodiments described below by those skilled in the art without paying creative labor are within the scope of protection of the present invention.

[0110] refer to Figure 1 , the device 10 having a camera function will be described below. Figure 1 A schematic block diagram of a description device provided for an embodiment of the present invention.

[0111] For example, the apparatus 10 may be a mobile device, a digital camera, etc. For example, the mobile device may be a mobile phone, a smart phone, a wireless communication terminal, a tablet device, a personal computer, etc., and may capture images and / or videos.

[0112] like Figure 1 As shown, the device 10 includes a lens 10a, an image sensor 10b, a processing circuit 10c, and a memory 10d. Hereinafter, the combination of the lens 10a and the image sensor 10b may be referred to as an "imaging unit." The device 10 may include a plurality of imaging units.

[0113] The lens 10a is an optical system that guides incident light to the image sensor 10b. The image sensor 10b converts the light input through the lens 10a into an electrical signal (analog signal) by photoelectric conversion. The image sensor 10b also converts the analog signal into a digital signal. The digital signal output from the image sensor 10b is input to the processing circuit 10c.

[0114] The processing circuit 10c processes the digital signal output from the image sensor 10b to generate image data, and stores the generated image data in the memory 10d. For example, the processing circuit 10c compresses / encodes the digital signal according to a compression / encoding method standardized by a standardization group such as the Joint Photographic Experts Group (JPEG), and generates image data from the digital signal. The processing circuit 10c can store the digital signal as RAW data in the memory 10d.

[0115] Next, we will refer to Figure 2 The image sensor 10b is further described. Figure 2 A schematic diagram describing an image sensor provided in accordance with an embodiment of the present invention.

[0116] like Figure 2 As shown, the image sensor 10 b includes a control circuit 11 , a pixel array 12 , and a multi-AD conversion circuit 13 .

[0117] To simplify the description, the shape of the pixel array 12 is Figure 2 1 is regular, but in other embodiments, pixel array 12 may have a regular or irregular arrangement and include more or fewer pixels, rows, and columns. In addition, pixel array 12 may include red, green, and blue pixels designed to capture images in the visible portion of the spectrum, or may include pixels for capturing images in non-visible portions of the spectrum, such as infrared or ultraviolet.

[0118] To simplify the explanation, Figure 2Only two columns 12a and 12b are shown, each column including 4 pixel units. However, a practical image sensor may include hundreds to thousands of columns, each column may include hundreds to thousands of pixels.

[0119] Each pixel unit in the pixel array 12 outputs an analog signal having a signal level corresponding to the intensity of the received light. The analog signal output from each pixel unit is input to the multi-AD conversion circuit 13. The multi-AD conversion circuit 13 includes a plurality of ADCs for converting analog signals into digital signals. For example, analog signals output from a plurality of pixel units in a column corresponding to each ADC are input to each ADC. The control circuit 11 controls the above operation.

[0120] For example, analog signals (first pixel signals) output from each pixel unit in column 12a are input to ADC 13a in multi AD conversion circuit 13. Analog signals (second pixel signals) output from each pixel unit in column 12b are input to ADC 13b in multi AD conversion circuit 13.

[0121] ADC 13a performs AD conversion on the first pixel signal to generate a first digital signal. The first digital signal output from ADC 13a is input to processing circuit 10c. ADC 13b performs AD conversion on the second pixel signal to generate a second digital signal. The second digital signal output from ADC 13b is input to processing circuit 10c.

[0122] Next, we will refer to Figure 2 The multi AD conversion circuit 13 is further described. Figure 3 A schematic circuit diagram describing a multi-AD conversion circuit provided in an embodiment of the present invention.

[0123] like Figure 3 As shown, the multi-AD conversion circuit 13 includes a ramp generator 13c, an AND circuit 13d, an ADC 13a, an ADC 13b, and other components. Although the multi-AD conversion circuit 13 actually includes three or three ADCs, for the purpose of description, Figure 3 Only the ADCs 13a and 13b are shown in FIG. The multi AD conversion circuit 13 may further include an element for supplying a master clock and an element for supplying a control clock described later.

[0124] The ADC 13 a includes a controller 131 , a comparator 132 , a DFF (D-Flip Flop) circuit 133 , a NOR circuit 134 , AND circuits 135 and 136 , a conversion counter 137 , a counter 138 , and an average calculator 139 .

[0125] The ADC 13b includes a controller 141, a comparator 142, a DFF circuit 143, a NOR circuit 144, AND circuits 145 and 146, a conversion counter 147, a counter 148, and an average calculator 149. The other ADCs included in the multi AD conversion circuit 13 have the same circuit configuration.

[0126] The master clock is input to AND circuits 13d, 136, 136, 146, etc. The output (Gated Clock B) of the AND circuit 13d is input to the ramp generator 13c. The ramp generator 13c generates a ramp reference signal synchronized with the gated clock B. The ramp reference signal output from the ramp generator 13c is input to IN terminals of the controllers 131 and 141. The controllers 131 and 141 generate local ramp signals according to the ramp reference signal.

[0127] refer to Figure 4 , the specific circuit configuration of the controller 131 will be described. Figure 4 A schematic circuit diagram describing a controller in a multi-AD conversion circuit provided in an embodiment of the present invention.

[0128] like Figure 4 As shown, the controller 131 includes an IN terminal, an OUT terminal, a switch SW1, and a capacitor C1. Hereinafter, for the sake of description, the switch SW1 may be referred to as a switch 131a.

[0129] The switch 131 a is switched on / off according to the signal level of the signal (gated clock A1 ) input to the CNT terminal of the controller 131 .

[0130] Specifically, when the gated clock A1 is at the HI level, the switch 131 a is turned on, and on the other hand, when the gated clock A1 is at the LO level, the switch 131 a is turned off.

[0131] The IN terminal of the controller 131 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to one end of the switch 131a and the OUT terminal of the controller 131. The reset voltage V_RESET is supplied to the other end of the switch 131a. The controller 131 operates as a clamp circuit.

[0132] Through the above operation, when the gated clock A1 becomes HI level, the controller 131 resets the signal level of the ramp reference signal input to the IN terminal to the initial level corresponding to the reset voltage V_RESET. During the HI level duration of the gated clock A1, the controller 131 maintains the signal level at the OUT terminal at the initial level. During the LO level duration of the gated clock A1, the controller 131 provides the reset ramp reference signal to the OUT terminal.

[0133] The controller 131 generates the local ramp signal by the above method. Figure 4 The circuit configuration shown in can be applied to the controller 141 and controllers included in other ADCs. When this configuration is applied to the controller 141, for example, the controller 141 performs on / off switching of the switch SW1 according to the signal level of the signal (gated clock A2) input to the CNT terminal of the controller 141.

[0134] Reference again Figure 3 , the local ramp signal (RAMP_1) output from the controller 131 is input to the negative (-) terminal of the comparator 132. The first pixel signal output from the column 12a is input to the positive (+) terminal of the comparator 132. The comparator 132 compares RAMP_1 with the first pixel signal and outputs an enable signal of a signal level corresponding to the comparison result.

[0135] For example, the comparator 132 maintains the HI level unchanged during the period when the signal level of RAMP_1 is equal to or less than the signal level of the first pixel signal, and outputs an enable signal (HI level signal) that maintains the LO level unchanged during another period. Specifically, the comparator 132 outputs the HI level during the period when the signal level of RAMP_1 is equal to or less than the first pixel signal, and changes the output to the LO level synchronized with the rising time of CLK_A, which requires resetting the local ramp signal. The enable signal output from the comparator 132 is input to the CLK terminal of the DFF circuit 133 and the EN terminal of the counter 138, which is LO effective.

[0136] The HI level (fixed) signal is input to the D (input) terminal of the DFF circuit 133. The inverted output of the NOR circuit 134 is input to the R (RESET) terminal of the DFF circuit 133. The output of the comparator 132 and the control clock (CLK_A) generated from the master clock are input to the NOR circuit 134. CLK_A is a pulse signal such that one pulse appears for every N pulses of the master clock.

[0137] When the resolution of AD conversion performed by ADC 13a is 10 bits, CLK_A is set so that one pulse appears every 64 pulses of the main clock as long as the maximum number of multiple AD conversions is set to "16". That is, N is set to 64 (64=1024 / 16). NOR circuit 134 performs a NOR operation of CLK_A and the output of comparator 132. The operation result performed by NOR circuit 134 is input to the R terminal of DFF circuit 133 after inversion.

[0138] The signal output from the Q (output) terminal of the DFF circuit 133 is input to the AND circuit 135. The output of the DFF circuit 133 and CLK_A are input to the AND circuit 135. The AND circuit 135 performs an AND operation of the output of the DFF circuit 133 and CLK_A. The operation result performed by the AND circuit 135 is input to the CNT terminal of the controller 131 and the conversion counter 137 as the gated clock A1.

[0139] The conversion counter 137 counts the number of pulses of the gated clock A1. As described above, when the gated clock A1 is at the HI level, the controller 131 resets the signal level of the ramp reference signal and outputs the reset ramp reference signal as RAMP_1. Since the number of times the conversion counter 137 performs reset corresponds to the number of pulses of RAMP_1, the number of pulses of the gated clock A1 corresponds to the number of AD conversions performed by the ADC 13a.

[0140] The output of the conversion counter 137 is input to the average calculator 139. The output of the counter 138 is also input to the average calculator 139. The counter 138 counts the number of pulses of the signal input to the clock terminal during the HI level duration of the signal input to the EN terminal. As described above, the output of the comparator 132 is input to the EN terminal of the counter 138, which is LO effective. The signal (gated clock B) output from the AND circuit 136 is input to the clock terminal of the counter 138.

[0141] The master clock and the inverted CLK_A are input to the AND circuit 136. The AND circuit 136 performs an AND operation of the master clock and the inverted CLK_A and outputs the operation result as the gated clock B. In other words, the gated clock B is a pulse set in the master clock that is extracted during the LO level duration of CLK_A.

[0142] The gated clock B is also generated by the AND circuit 13d and is also provided to the ramp generator 13c. The ramp generator 13c generates a ramp reference signal according to the gated clock B. Therefore, in a period in which there is no pulse of the gated clock B, the signal level of the ramp reference signal is maintained at the signal level at the start time of the period. That is, during the HI level duration of CLK_A, the signal level of the ramp reference signal becomes constant. In this period, the number of calculations in the counter 138 will not increase.

[0143] Note the gated clock A1 output from the AND circuit 135. As described above, the gated clock A1 is a signal obtained by gating the output of the DFF circuit 133 with the pulse of CLK_A. Then, the gated clock A1 is input to the CNT terminal of the controller 131 and is used for the on / off control of the switch 131a. In other words, the on / off control of the switch 131a is performed at the rising edge of the CLK_A pulse.

[0144] As described above, during the HI level duration of CLK_A, the ramp generator 13c keeps the level of the ramp reference signal constant, and the counter 138 suspends counting. That is, during the HI level duration of CLK_A, the AD conversion in the ADC 13a is suspended. During the HI level duration of CLK_A, the AD conversion in the ADC 13b is also suspended. Therefore, the switching noise generated by the on / off control of the switch 131a does not affect the AD conversion in the ADCs 13a and 13b. That is, the crosstalk noise does not affect the AD conversion in each ADC of the image sensor.

[0145] As described above, the outputs of the conversion counter 137 and the counter 138 are input to the average calculator 139. The average calculator 139 divides the output of the counter 138 by the output of the conversion counter 137 to calculate the average number of pulses of the master clock in a single AD conversion. Then, the average calculator 139 outputs a bit value sequence corresponding to the calculated average number of pulses as a first digital signal.

[0146] The ADC 13 b and other ADCs included in the multi AD conversion circuit 13 have the same configuration as that of the ADC 13 a .

[0147] For example, the controller 141 corresponds to the above-mentioned controller 131. The comparator 142 corresponds to the above-mentioned comparator 132. The DFF circuit 143 corresponds to the above-mentioned DFF circuit 133. The NOR circuit 144 corresponds to the above-mentioned NOR circuit 134. AND circuits 145 and 146 correspond to the above-mentioned AND circuits 135 and 136, respectively. The conversion counter 147 corresponds to the above-mentioned conversion counter 137. The counter 148 corresponds to the above-mentioned counter 138. The average calculator 149 corresponds to the above-mentioned average calculator 139.

[0148] However, it should be noted that the second pixel signal output from the column 12b is input to the + terminal of the comparator 142. As a result, the local ramp signal (RAMP_2) output from the controller 141 is different from the RAMP_1 output from the controller 131. In addition, the signal (gated clock A2) output from the AND circuit 145 and input to the CNT terminal of the controller 141 and input to the conversion counter 147 is different from the gated clock A1 output from the AND circuit 135. In addition, the second digital signal is output from the average calculator 149.

[0149] As described above, ADC 13a and 13b and other ADCs work according to the same master clock, ramp reference signal and CLK_A. Therefore, when the ramp reference signal in any ADC is reset, the switching noise is transmitted through the common line of the ramp reference signal. However, as described above, during the HI level duration of CLK_A, each ADC suspends AD conversion to avoid the influence of switching noise. As a result, crosstalk noise is also avoided in the multi-AD conversion circuit 13.

[0150] Next, we will refer to Figure 5 The specific operations of the ADCs 13a and 13b are further described. Figure 5 A timing diagram describing signals and clocks in a readout circuit is provided for an embodiment of the present invention.

[0151] exist Figure 5 In the example of FIG. 1 , it is assumed that the signal level of the first pixel signal is higher than the signal level of the second pixel signal.

[0152] At timing T0, the ramp generator 13c starts ramping down the output of the ramp generator 13c in synchronization with the gated clock B. The counters 138 and 148 start the operation of counting the number of pulses of the gated clock B.

[0153] At timing T1, the signal level of the ramp reference signal reaches the signal level of the first pixel signal. At this time, the output of the comparator 132 becomes HI level, and the output of the DFF circuit 133 becomes HI level. Then, the counting of the counter 138 is suspended. At the same time, the counter 148 continues the counting operation for AD conversion of the second pixel signal.

[0154] At timing T2, CLK_A becomes HI level. The gated clock A1 becomes HI level, so that the conversion counter 137 performs counting. That is, the counter indicating the number of AD conversions is incremented by "1". The gated clock B becomes LO level. That is, the supply of the main clock to the counters 138 and 148 is suspended. The controller 131 resets the signal level of RAMP_1 to the initial level. The ramp generator 13c suspends the ramp down of its output.

[0155] As described above, at timing T2, RAMP_1 is reset for the next AD conversion. Then, due to the on / off switching of the switch 131a, a charge and discharge current is generated on the common ramp reference line, so that a transient phenomenon may appear on the ramp reference signal (see the part indicated by the reference symbol "FL"). For example, when the interference of the ramp reference signal becomes large, the interference causes RAMP_2 to cross the second pixel signal, so that a signal based on an erroneous comparison result can be output from the comparator 142.

[0156] However, as described above, in the multi AD conversion circuit 13 according to the present embodiment, the supply of the main clock to the counters 138, 148 is suspended. Therefore, even if a signal based on an erroneous comparison result is output from the comparator 142, the counter 148 does not perform counting, so that the result of AD conversion is hardly affected. In order to obtain such an effect, it is better to set the pulse width of CLK_A to be much longer than the setup time of the transient phenomenon.

[0157] At timing T3, CLK_A becomes LO level. Ramp generator 13c restarts the ramp down of its output. Therefore, RAMP_1 ramps down from the initial level for the next AD conversion. RAMP_2 ramps down from the signal level of the ramp reference signal at timing T2. DFF circuit 133 resets the output so that gated clock A1 becomes LO level. Counters 138 and 148 restart counting the number of pulses to be provided as gated clock B.

[0158] At timing T4, the level of RAMP_2 reaches the signal level of the second pixel signal. At this time, the output of the comparator 142 becomes HI level. The output of the DFF circuit 143 becomes HI level, so that the counter 148 suspends the counting operation. At timing T4, CLK_A is at LO level, and the pulse of the main clock is provided to the ramp generator 13c as the gated clock B. As a result, the ramp generator 13c continuously generates a ramp reference signal.

[0159] At timing T5, the level of RAMP_1 reaches the signal level of the first pixel signal again. At this time, the output of the comparator 132 becomes HI level. The output of the DFF circuit 133 becomes HI level, so that the counter 138 suspends the counting operation.

[0160] At timing T6, CLK_A becomes HI level. Gate clocks A1 and A2 become HI level, so that the number of calculations in each conversion counter 137 and 147 increases by "1". The signal levels of RAMP_1 and RAMP_2 are reset to initial levels.

[0161] At the timing T7, CLK_A becomes the LO level. The gated clocks A1 and A2 become the LO level, so that the next AD conversion of the first pixel signal and the second pixel signal starts, and the counters 138 and 148 restart the counting operation.

[0162] At timing T8, the signal level of RAMP_1 reaches the signal level of the first pixel signal. At this time, the output of the comparator 132 becomes HI level, and the counter 138 stops counting. At the same time, since the signal level of RAMP_2 does not reach the signal level of the second pixel signal, the counter 148 continues counting.

[0163] At timing T9, CLK_A becomes HI level. Then, counter 148 suspends counting operation, and ramp generator 13c suspends outputting ramp reference signal. Conversion counter 137 increases the calculation number of AD conversion times representing the first pixel signal by "1" according to gated clock A1. Conversion counter 147 increases the calculation number of AD conversion times representing the first pixel signal by "1" according to gated clock A2.

[0164] Continue to repeat the above AD conversion operation until the number of pulses of CLK_A reaches a predetermined number N (for example, N=16). After the operation is completed, average calculators 139 and 149 average the number of calculations in counters 138 and 148 according to the number of calculations in conversion counters 137 and 147 (the number of AD conversions in one cycle of the ramp reference signal) to calculate the average number of pulses of the main clock in a single AD conversion, respectively. This average calculation reduces time noise such as quantization noise and input noise.

[0165] It should be noted that the circuit configuration and operation of the multi-AD conversion circuit 13 described so far are merely illustrative, and the example can be modified in the form of various other embodiments. For example, the resolution of the AD conversion can be set to a value other than 10 bits, and the number of pulses N of CLK_A can be set to a number other than "16". Although the above description shows a pulse train including pulses arranged at equal intervals as a preferred example with respect to the arrangement of the pulses of CLK_A, the pulses of CLK_A can be arranged at unequal intervals. These modifications are also included in the technical scope of the present invention.

[0166] As described above, the embodiments of the present invention make it possible to avoid the influence of switching noise on the AD conversion results in each ADC. Specifically, the influence of switching noise generated in a specific ADC on the AD conversion results in other ADCs can be avoided, thereby effectively suppressing the generation of crosstalk noise in a large number of ADCs equipped in the image sensor. In addition, multi-AD conversion also reduces temporal noise. These advantages improve the quality of the digital signal output by the image sensor. This enhancement of image quality helps to improve the quality of the output image captured by the device 10.

[0167] The above description only discloses preferred embodiments and is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that the above embodiments and all or part of other embodiments and modifications obtained according to the scope of the claims of the present invention are within the scope of the present invention.

Claims

1. A method for multi-analog-to-digital conversion, characterized in that: include: An ADC among the plurality of analog-to-digital converters ADC receives a ramp reference signal from a ramp generator; The control circuit in the ADC generates a local ramp signal according to the received ramp reference signal; The comparator in the ADC compares the analog signal input to the ADC with the local ramp signal; The ADC generates a digital signal according to the output of the comparator, wherein the local ramp signal is generated by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator, Within a predetermined period after the at least one ADC among the plurality of ADCs is reset, the signal level of the ramp reference signal output from the ramp generator remains unchanged, and the process of the ADC generating a digital signal is suspended.

2. The method according to claim 1, characterized in that Generating a digital signal comprises: Calculating the number of transitions in each cycle of the ramp reference signal; counting the number of pulses of the master clock when the output of the comparator is at a predetermined level; generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock, The calculated number of conversions and the calculated number of pulses of the main clock are suspended within a predetermined period after at least one of the plurality of ADCs is reset.

3. The method according to claim 1 or 2, characterized in that: Also includes: The ADC receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein the width of each pulse in the pulse train corresponds to the predetermined period after the reset, The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

4. The method according to claim 1, characterized in that The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed by switching a switch circuit, The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

5. The method according to claim 3, characterized in that: The pulse train is arranged in such a way that a pulse in the pulse train appears for every N pulses of the master clock, where N is greater than or equal to 2.

6. The method according to claim 3, characterized in that The ramp reference signal is generated from a set of pulses extracted from a master clock during the LO level duration of the pulse train.

7. The method according to claim 5, characterized in that N is set to 16, 32, or 64.

8. A multi-analog-to-digital conversion circuit, characterized in that: include: A ramp generator, used for generating a ramp reference signal; A plurality of analog-to-digital converters ADC, configured to receive the ramp reference signal from the ramp generator, wherein one ADC among the plurality of ADCs comprises: a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal; a comparator for comparing the analog signal input to the ADC with the local ramp signal, in, The controller generates a digital signal, wherein the digital signal resets the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator, The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs, The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

9. The circuit according to claim 8, characterized in that The ADC performs: Calculating the number of transitions in each cycle of the ramp reference signal; counting the number of pulses of the master clock when the output of the comparator is at a predetermined level; generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock, The calculated number of conversions and the calculated number of pulses of the main clock are suspended within a predetermined period after at least one of the plurality of ADCs is reset.

10. The circuit according to claim 8 or 9, characterized in that The ADC also receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the reset, The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising edge of a pulse in the pulse train.

11. The circuit according to claim 8, characterized in that The controller resets the signal level of the received ramp reference signal to a predetermined initial level by switching the switch circuit. The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

12. The circuit according to claim 10, characterized in that The pulse train is arranged in such a way that a pulse in the pulse train appears for every N pulses of the master clock, where N is greater than or equal to 2.

13. The circuit according to claim 10, characterized in that The ramp generator generates the ramp reference signal based on a set of pulses extracted from a master clock during a LO level duration of the pulse train.

14. The circuit according to claim 12, characterized in that N is set to 16, 32, or 64.

15. An image sensor, characterized in that: include: A plurality of pixel units for generating an analog signal of a level corresponding to the amount of received light through photoelectric conversion; a multi-analog-to-digital conversion circuit, configured to receive the analog signal outputted from at least one pixel unit among the plurality of pixel units as an analog signal, The circuit comprises: a ramp generator for generating a ramp reference signal, and a plurality of analog-to-digital converters ADC for receiving the ramp reference signal from the ramp generator, wherein one ADC of the plurality of ADCs comprises: a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal; a comparator for comparing the analog signal input to the ADC with the local ramp signal, in, the controller generates a digital signal by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator, The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs, The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

16. The image sensor according to claim 15, characterized in that The ADC performs the following operations: Calculating the number of transitions in each cycle of the ramp reference signal; counting the number of pulses of the master clock when the output of the comparator is at a predetermined level; generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock, The calculated number of conversions and the calculated number of pulses of the main clock are suspended within a predetermined period after at least one of the plurality of ADCs is reset.

17. The image sensor according to claim 15 or 16, characterized in that: The ADC also receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the reset, The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising time of a pulse in the pulse train.

18. The image sensor according to claim 15, characterized in that The controller resets the signal level of the received ramp reference signal to a predetermined initial level by switching the switch circuit. The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

19. The image sensor according to claim 17, characterized in that: The pulse train is arranged in such a way that a pulse in the pulse train appears for every N pulses of the master clock, where N is greater than or equal to 2.

20. The image sensor according to claim 17, wherein: The ramp generator generates the ramp reference signal based on a set of pulses extracted from a master clock during a LO level duration of the pulse train.

21. The image sensor according to claim 19, characterized in that N is set to 16, 32, or 64.

22. A device with camera function, characterized in that: The device comprises: The image sensor comprises: a plurality of pixel units for generating an analog signal of a level corresponding to the amount of received light through photoelectric conversion; a multi-analog-to-digital conversion circuit for receiving the analog signal output from at least one analog unit among the plurality of pixel units as an analog signal, The circuit comprises: a ramp generator for generating a ramp reference signal, and a plurality of analog-to-digital converters ADC for receiving the ramp reference signal from the ramp generator, wherein one ADC of the plurality of ADCs comprises: a controller, configured to receive the ramp reference signal from the ramp generator and generate a local ramp signal according to the received ramp reference signal; a comparator for comparing the analog signal input to the ADC with the local ramp signal, in, the controller generates a digital signal by resetting the signal level of the received ramp reference signal to a predetermined initial level according to the output of the comparator, The ramp generator keeps the signal level of the ramp reference signal constant for a predetermined period after a reset is performed in at least one of the plurality of ADCs, The ADC generates a digital signal according to the output of the comparator, and suspends the process of generating the digital signal within the predetermined period after the resetting.

23. The device according to claim 22, characterized in that The ADC performs: Calculating the number of transitions in each cycle of the ramp reference signal; counting the number of pulses of the master clock when the output of the comparator is at a predetermined level; generating the digital signal according to the calculated number of conversions and the calculated number of pulses of the master clock, The calculated number of conversions and the calculated number of pulses of the main clock are suspended within a predetermined period after at least one of the plurality of ADCs is reset.

24. The device according to claim 22 or 23, characterized in that The ADC also receives a pulse train having a period shorter than that of the ramp reference signal to reset the signal level of the received ramp reference signal, wherein a width of each pulse in the pulse train corresponds to the predetermined period after the reset, The resetting of the signal level of the received ramp reference signal to a predetermined initial level is performed at a rising time of a pulse in the pulse train.

25. The device according to claim 22, characterized in that The controller resets the signal level of the received ramp reference signal to a predetermined initial level by switching the switch circuit. The predetermined period after the resetting is set to a period longer than a build-up time of a transient phenomenon generated by switching of the switch circuit.

26. The device according to claim 24, characterized in that The pulse train is arranged in such a way that a pulse in the pulse train appears for every N pulses of the master clock, where N is greater than or equal to 2.

27. The device according to claim 24, characterized in that The ramp generator generates the ramp reference signal based on a set of pulses extracted from a master clock during a LO level duration of the pulse train.

28. The device according to claim 26, characterized in that N is set to 16, 32, or 64.

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