Memory device and method for forming the same

Abstract

A memory device and a method for forming the same are provided. The memory device includes a first layer located on a substrate and a second layer located on the first layer. The first layer includes a first layer stack; a first gate electrode passing through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second layer includes a second layer stack; a second gate electrode passing through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

Description

Technical Field

[0001] The present application relates to memory devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of integrated circuits, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while its geometry (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally brings the benefits of increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments are needed in IC processing and manufacturing to realize these advantages. For example, three-dimensional (3D) memory devices, such as 3D NOR type memories, have been introduced to replace planar memory devices. However, 3D memory devices are not completely satisfactory in all aspects, and other issues have arisen that should be addressed. Summary of the invention

[0004] Some embodiments of the present application provide a memory device, comprising: a first layer, arranged on a substrate, wherein the first layer comprises: a first layer stack; a first gate electrode, passing through the first layer stack; a first channel layer, arranged between the first layer stack and the first gate electrode; and a first ferroelectric layer, arranged between the first channel layer and the first gate electrode; and a second layer, arranged on the first layer, wherein the second layer comprises: a second layer stack; a second gate electrode, passing through the second layer stack; a second channel layer, arranged between the second layer stack and the second gate electrode; and a second ferroelectric layer, arranged between the second channel layer and the second gate electrode.

[0005] Some other embodiments of the present application provide a method for forming a memory device, comprising: forming a first layer stack on a substrate, wherein the first layer stack includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence; forming a first opening in the first layer stack to pass through the first layer stack; forming a first gate structure in the first opening; removing a portion of the second conductive layer and a portion of the second dielectric layer to expose a portion of the first conductive layer to form a stepped region; forming a second layer stack on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence; forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer; forming a second opening in the second layer stack to pass through the second layer stack; and forming a second gate structure in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent of each other.

[0006] Some other embodiments of the present application provide a memory device, comprising: a layer stack disposed on a substrate, wherein the layer stack includes a first dielectric layer, a first source / drain (S / D) layer, a second dielectric layer, and a second source / drain layer stacked in sequence; a first conductive pillar passing through the layer stack; a first ferroelectric layer wrapping the first conductive pillar; and a first channel layer disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0008] Figures 1 to 6A is a cross-sectional view of a method of forming a three-dimensional (3D) memory device according to a first embodiment.

[0009] Figure 6B It is along Fig. 6A Plan view of cross section I-I'.

[0010] Fig. 7A is a cross-sectional view of a 3D memory device according to a second embodiment.

[0011] Figure 7B It is along Fig. 7A Plan view of section II-II'.

[0012] Figure 8 is a cross-sectional view of a 3D memory device according to a third embodiment.

[0013] Fig. 9 is a cross-sectional view of a 3D memory device according to a fourth embodiment.

[0014] Figures 10 to 16 is a cross-sectional view of a method of forming a 3D memory device according to a fifth embodiment.

[0015] Fig.17 is a cross-sectional view of a 3D memory device according to a sixth embodiment.

[0016] Fig.18 is a cross-sectional view of a 3D memory device according to a seventh embodiment.

[0017] Fig.19 A flow chart of a method of forming a 3D memory device according to some embodiments is shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different parts of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in a direct contact manner, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly.

[0020] According to some embodiments, a three-dimensional (3D) memory device includes a first layer having a plurality of first memory cells and a second layer having a plurality of second memory cells stacked above the first layer. The second memory cells are stacked on the first memory cells, thereby enabling easy modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. In addition, a dielectric material (e.g., an isolation structure) is disposed between the first and second memory cells to reduce or eliminate leakage current between two vertically adjacent memory cells, thereby improving device performance.

[0021] Figures 1 to 6A is a cross-sectional view of a method of forming the 3D memory device 100 according to the first embodiment. Figure 6B It is along Fig. 6A The 3D memory device 100 is a 3D memory device having a ferroelectric material, and may be, but is not limited to, a 3D or NOR type memory device.

[0022] refer to Figure 1 In the front end of line (FEOL) process of semiconductor manufacturing, a plurality of electronic components 104, such as transistors, resistors, capacitors, inductors, diodes, etc., are formed in a device region of a semiconductor substrate 102. The semiconductor substrate 102 may be a bulk substrate, such as a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The electronic components 104 may be formed in / on the semiconductor substrate 102 using any suitable formation method known or used in semiconductor manufacturing.

[0023] After forming the electronic components 104, an interconnect structure is formed over the semiconductor substrate 102 to connect the electronic components 104 to form a functional circuit. The interconnect structure may include a plurality of dielectric layers (e.g., 106, 108) and conductive features 105 (e.g., vias, metal lines) formed in the dielectric layers. In some embodiments, the interconnect structure is formed in a back-end of line (BEOL) process of semiconductor manufacturing. The formation of the interconnect structure is known in the art, so the details are not repeated here. To avoid confusion and facilitate discussion, in the following discussion, the semiconductor substrate 102, the electronic components 104, and the interconnect structure on the semiconductor substrate 102 are collectively referred to as the substrate 101, and Figure 1 The details of the substrate 101 shown in FIG. 1 may be omitted in subsequent figures.

[0024] Figures 2 to 6A 1 shows further process steps in the BEOL process of forming the 3D memory device 100 according to the first embodiment. Referring now to Figure 2 , a layer stack 110 is formed on a substrate 101. In detail, the layer stack 110 may include a dielectric layer 112, a conductive layer 114, a dielectric layer 116, and a conductive layer 118, which are sequentially formed on the substrate 101.

[0025] In some embodiments, dielectric layer 112 and dielectric layer 116 may include a dielectric material such as an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. The inorganic dielectric material may include: a nitride such as silicon nitride; an oxide such as silicon oxide; a nitride oxide such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or a combination thereof. Dielectric layer 112 may be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, dielectric layer 112 and dielectric layer 116 have the same dielectric material, such as silicon oxide. However, embodiments of the present invention are not limited thereto, and in other embodiments, dielectric layers 112 and 116 have different dielectric materials.

[0026] In some embodiments, the conductive layer 114 and the conductive layer 118 may include a conductive material such as a metal. For example, the conductive layer 114 and the conductive layer 118 may be formed of the same source / drain (S / D) material such as W, Ru, etc. In this case, the conductive layers 114 and 118 may also be referred to as a first source / drain metal layer 114 and a second source / drain metal layer 118, respectively.

[0027] The first source / drain metal layer 114 and the second source / drain metal layer 118 may be formed of an N-type metal or a P-type metal, depending on the type of device being formed (e.g., N-type or P-type). In some embodiments, Sc, Ti, Cr, Ni, Al, etc. are used as N-type metals for forming the first source / drain metal layer 114 and the second source / drain metal layer 118. In some embodiments, Nb, Pd, Pt, Au, etc. are used as P-type metals for forming the first source / drain metal layer 114 and the second source / drain metal layer 118. The N-type or P-type metal layer may be formed by a suitable formation method, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc. In some alternative embodiments, the source / drain metal layer 114 and the source / drain metal layer 118 have different metal materials.

[0028] Next, refer to Figure 3, a plurality of openings 10 are formed in the layer stack 110 to expose the substrate 101. That is, the openings 10 pass through the layer stack 110, and the substrate 101 is exposed at the bottom of the openings 10. In addition, the openings 10 expose the sidewalls of the dielectric layer 112, the dielectric layer 116, and the sidewalls of the conductive layer 114, the conductive layer 118. Note that in the discussion herein, the sidewalls of the layer stack 110 include the corresponding sidewalls of all the constituent layers (e.g., 112, 114, 116, and 118) of the layer stack. For example, the sidewalls of the layer stack 110 exposed by the openings 10 include the sidewalls of the dielectric layer 112, the dielectric layer 116, and the sidewalls of the conductive layer 114, the conductive layer 118 exposed by the openings 10.

[0029] In some embodiments, the opening 10 is formed by an anisotropic etching process such as a plasma etching process. A mask pattern such as a patterned photoresist layer may be formed on the layer stack 110. Then, an anisotropic etching process may be performed by using the mask pattern as an etching mask to form the opening 10. After the anisotropic etching process is completed, the mask pattern (e.g., the patterned photoresist layer) may be removed by a suitable removal process such as ashing or stripping.

[0030] refer to Figure 4 , firstly, a channel layer 120 is formed to cover the sidewalls of the opening 10. In some embodiments, the channel layer 120 is formed by depositing a channel material, which conformally covers the bottom and sidewalls of the opening 10 and further covers the upper surface of the conductive layer 118; then an anisotropic etching process is performed to remove the channel material on the bottom of the opening 10 and the upper surface of the conductive layer 118. In this case, the channel layer 120 may have a rounded or curved top surface adjacent to the conductive layer 118. In some embodiments, the channel layer 120 may have a flat top surface, such as Figure 4 shown.

[0031] In some embodiments, the channel layer 120 may include a metal oxide such as indium gallium zinc oxide (IGZO) formed by a suitable formation method such as PVD, CVD, ALD, etc. Other suitable materials for the channel layer 120 include zinc oxide (ZnO), indium tungsten oxide (IWO), tungsten oxide (WO), tantalum oxide (TaO), and molybdenum oxide (MoO). In an example embodiment, the dielectric layer 112 and the dielectric layer 116 are made of SiO 2 The conductive layer 114 and the conductive layer 118 are formed of tungsten, and the channel layer 120 is formed of IGZO.

[0032] Next, if Figure 4As shown, a ferroelectric layer 122 is formed in the opening 10 to cover the channel layer 120. The ferroelectric layer 122 may include a ferroelectric material such as HZO, HSO, HfSiO, HfLaO, HfO doped with La, Y, Si, or Ge. 2 、HfZrO 2 、ZrO 2 or HfO 2 , and can be formed by PVD, CVD, ALD, etc. In some embodiments, the ferroelectric layer 122 is formed by depositing a ferroelectric material that conformally covers the channel layer 120, the bottom of the opening 10, and further covers the upper surface of the conductive layer 118; and then an anisotropic etching process is performed to remove the ferroelectric material on the bottom of the opening 10 and the upper surface of the conductive layer 118. In this case, the ferroelectric layer 122 can have a rounded or curved top surface.

[0033] Afterwards, if Figure 4 As shown, a conductive material is formed to fill the opening 10. The conductive material may include copper, tungsten, cobalt, aluminum, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, etc., and may be formed by a suitable deposition method, such as CVD, PVD, ALD, electroplating, etc. After the conductive material is formed, a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to remove excess portions of the conductive material from the upper surface of the conductive layer 118. In this case, the remaining portion of the conductive material in the opening 10 forms a conductive pillar 124 (also referred to as a gate electrode 124).

[0034] After forming the conductive pillar 124, as shown in FIG. Figure 4 As shown, a plurality of gate structures 125 are formed in the opening 10. In detail, each gate structure 125 may include a channel layer 120, a ferroelectric layer 122 and a conductive pillar 124. The ferroelectric layer 122 wraps the conductive pillar 124. The ferroelectric layer 122 is sandwiched between the channel layer 120 and the conductive pillar 124 and is in physical contact with them. The channel layer 120 is disposed between the layer stack 110 and the ferroelectric layer 122. That is, the channel layer 120 (or the gate structure 125) is surrounded by the dielectric layer 112, the dielectric layer 116 and the conductive layer 114, the conductive layer 118.

[0035] refer to Figure 5 , portions of the conductive layer 118 and portions of the dielectric layer 116 are removed by one or more etching processes (eg, anisotropic etching processes) using an etching mask, thereby forming a stepped region 150. The etching time of each etching process may be adjusted to achieve different etching amounts (eg, depths).

[0036] like Figure 5 As shown, after forming the stepped region 150, a portion of the upper surface of the conductive layer 114 is exposed. Figure 5 In the example of FIG. 1 , dielectric layer 112 and conductive layer 114 have the same width W1. Dielectric layer 116 and conductive layer 118 have the same width W2 which is smaller than width W1. That is, conductive layer 118 in stepped region 150 has sidewalls aligned along the same line with the corresponding sidewalls of dielectric layer 116. In addition, the widths of conductive layer 114 and conductive layer 118 increase in a direction toward substrate 101, so that the width of upper conductive layer 118 is smaller than the width of lower conductive layer 114. Stepped region 150 facilitates the proximity of subsequently formed contact 128 to conductive layer 114 (see FIG. 1 ). Fig. 6A ).

[0037] refer to Fig. 6A ,exist Figure 5 A dielectric material 126 is formed on the structure. A plurality of contacts 128 (also referred to as contact plugs) are formed in the dielectric material 126 and are electrically coupled to the conductive pillars 124 or the conductive layers 114 and 118. In some embodiments, the contacts 128 electrically coupled to the conductive pillars 124 are also referred to as gate contacts 128G, and the contacts 128 electrically coupled to the conductive layers 114 and 118 are also referred to as source / drain contacts 128SD. In some embodiments, the length of the source / drain contacts 128SD contacting the conductive layer 114 is greater than the length of the source / drain contacts 128SD contacting the conductive layer 118.

[0038] The dielectric material 126 may include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. The inorganic dielectric material may include: a nitride such as silicon nitride; an oxide such as silicon oxide; a nitride oxide such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or a combination thereof. The dielectric material 126 may be formed by spin coating, lamination, CVD, etc. In addition, the contact 128 may be formed by forming an opening in the dielectric material 126 to expose the underlying conductive component (e.g., 124, 114, or 118), and filling the opening with a conductive material (e.g., copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, etc.).

[0039] Next, a plurality of connectors 130 (also referred to as conductive connectors or conductive bumps) are formed over the contacts 128 and electrically coupled to the contacts 128. The connectors 130 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), combinations thereof (e.g., metal pillars with solder balls attached thereto), and the like. The connectors 130 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, and the like, or combinations thereof. In some embodiments, as an example, the connectors 130 include eutectic materials and may include solder bumps or solder balls. The solder may be, for example, lead-based and lead-free solders, such as lead-tin compositions for lead-based solders; lead-free solders including indium antimonide; tin, silver, and copper (SAC) components; and other eutectic materials having a common melting point and forming conductive solder connections in electrical applications. The connectors 130 may form a grid, such as a ball grid array (BGA). In some embodiments, a reflow process may be performed, which in some embodiments, imparts a partially spherical shape to connector 130. Alternatively, connector 130 may include other shapes. Connector 130 may also include a non-spherical conductive connector.

[0040] In some embodiments, connector 130 comprises a metal component (such as a copper pillar or copper wire) formed by sputtering, printing, electroplating, chemical plating, CVD, etc., with or without solder material thereon. The metal pillar may be solder-free and have substantially vertical sidewalls or tapered sidewalls.

[0041] Figure 6B Shows Fig. 6A But along Fig. 6A 3D memory device in section I-I'. Figure 6B In the cross-sectional view of FIG. 1 , the ferroelectric layer 122 wraps (eg, surrounds) the conductive pillar 124, and the channel layer 120 wraps the ferroelectric layer 122. The area to the right of the dashed line 160 corresponds to the stepped region 150 of the 3D memory device 100.

[0042] like Fig. 6A As shown, Fig. 6AThe dotted box in shows a memory cell 140 of the 3D memory device 100. The 3D memory device 100 includes a plurality of such memory cells. The memory cell 140 includes a gate structure 125 passing through the layer stack 110, and a conductive layer 114 and a conductive layer 118 (hereinafter referred to as S / D layer 124). The gate structure 125 may include a conductive pillar 124 (hereinafter referred to as gate electrode 124), a ferroelectric layer 122 wrapping the gate electrode 124, a channel layer 120, and the channel layer 120 between the layer stack 110 and the ferroelectric layer 122. In the illustrated embodiment, since the channel layer 120 is disposed between the S / D layers 114 and 118 of the layer stack 110, each memory cell 140 of the 3D memory device 100 is a transistor having a ferroelectric layer 122. Fig. 6A The dashed arrow 145 in FIG. 1 shows a possible current flow direction in the channel layer 120 when the transistor of the memory cell is turned on.

[0043] exist Fig. 6A In the example of , two memory cells side by side are shown. To avoid confusion, other memory cells are not marked with a dashed box except for memory cell 140. Memory cell 140 can be programmed (e.g., written to and / or read) by connectors 130 (e.g., connectors 130 labeled Vg1, Vs1, and Vd1) electrically coupled to the gate and S / D terminals of the transistor of the memory cell. Similarly, connectors 130 labeled Vg2, Vs1, Vd1 can be used to program another memory cell disposed next to memory cell 140.

[0044] To perform a write operation on a particular memory cell (e.g., memory cell 140), a write voltage is applied to the portion of the ferroelectric layer 122 corresponding to the memory cell 140. For example, the write voltage may be applied by applying a first voltage to the gate electrode 124 of the memory cell 140 (via the connector 130 labeled Vg1) and applying a second voltage to the S / D layer 114 and S / D 118 (via the connector 130 labeled Vs1 or Vd1). The voltage difference between the first voltage and the second voltage sets the polarization direction of the ferroelectric layer 122. Depending on the polarization direction of the ferroelectric layer 122, the V of the corresponding transistor of the memory cell 140 is set to Vd1. T The voltage can be from the low threshold voltage V L Switching to high threshold voltage V H , and vice versa. The threshold voltage of the transistor (V L or V H ) can be used to indicate a bit “0” or “1” stored in a memory cell.

[0045] To perform a read operation on memory cell 140, V L and high threshold voltage V HA read voltage of a voltage between 1 and 2 is applied to the transistor, for example, between the gate electrode 124 and the second S / D layer 118. Depending on the polarization direction of the ferroelectric layer 122 (or the threshold voltage of the transistor), the transistor of the memory cell 140 may or may not be turned on. As a result, when a voltage is applied, for example, at the first S / D layer 114, current may or may not flow between the first S / D layer 114 and the second S / D layer 118 through the channel layer 120. Therefore, the current can be detected to determine the digital bit stored in the memory cell.

[0046] It should be noted that in the present embodiment, the gate structure 125 is vertically arranged on the substrate 101 and passes through the layer stack 110, so that the S / D layer 114 and the S / D layer 118 wrap or surround the gate structure 125, thereby forming a similar all-around gate (GAA) memory device. In this case, the memory cell is surrounded by the S / D layer 114 and the S / D layer 118 arranged on the same layer, so that the memory cell shares the same S / D voltage (Vs1 or Vd1), thereby simplifying the wiring layout of the S / D layer. In addition, compared with the planar memory device, the memory device of the present embodiment can effectively utilize the area of ​​the chip in the horizontal direction and increase the integration density of the memory device, which is conducive to the miniaturization of the chip.

[0047] As another example, although the disclosed embodiments describe the process of forming the S / D layer 114 and the S / D layer 118, these embodiments are illustrative and not restrictive. In an alternative embodiment, the S / D layers 114 and 118 may be formed by a replacement process. Specifically, a layer stack including a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer stacked in sequence is formed on the substrate 101. An opening 10 is formed in the layer stack to expose the substrate 101. The gate structures 125 are respectively formed in the openings 10. One or more slits are formed next to the openings 10 and pass through the layer stack. Then, the first nitride layer and the second nitride layer are replaced by a source / drain (S / D) material (such as W, Ru, etc.). In some embodiments, the replacement process includes the following steps: removing the first nitride layer and the second nitride layer by an etching process such as a wet etching process to form a plurality of gaps between the first oxide layer and the second oxide layer; and filling the S / D material in the gaps between the first oxide layer and the second oxide layer to form the S / D layer 114 and the S / D layer 118. Before the replacement process, portions of the S / D layer 114 and the S / D layer 118 are removed to form the stepped region 150.

[0048] Fig. 7A is a cross-sectional view of a 3D memory device 300 according to a second embodiment. Figure 7B It is along Fig. 7A The 3D memory device 200 is similar to Fig. 6A The 3D memory device 100 is similar to the 3D memory device 100 of claim 1 , but with additional processing to increase (eg, double) the memory cell density.

[0049] In some embodiments, to form the 3D memory device 200, follow Figures 1 to 5 100. Next, a slot-shaped opening is formed in each conductive pillar 124. The slot-shaped opening extends vertically from the upper surface of the conductive pillar 124 away from the substrate 101 to the lower surface of the conductive pillar 124 facing the substrate 101. In a top view, the slot-shaped opening extends along, for example, the diameter of the conductive pillar 124 and divides the conductive pillar 124 into two independent gate pillars 124A and 124B (hereinafter referred to as gate electrodes). Figure 7B In the example shown, the slot-shaped opening also extends into the ferroelectric layer 122 and the channel layer 120, and cuts the ferroelectric layer 122 into two separate segments 122A and 122B, and further cuts the channel layer 120 into two separate segments 120A and 120B. That is, the slot-shaped opening cuts the gate structure 125 into two separate parts 125A and 125B.

[0050] In addition, if Fig. 7A As shown, each gate electrode 124A and gate electrode 124B has a top portion extending along the upper surface of the ferroelectric layer 122, and therefore, the conductive pillar 124A (or conductive pillar 124B) has an L-shaped cross section. The top portions of the gate electrodes 124A and gate electrodes 124B allow for more flexibility in selecting the position of the connector 130 coupled to the gate electrodes. In some alternative embodiments, if the width of the gate electrodes 124A and gate electrodes 124B in the embedded layer stack 110 is large enough to be coupled to the connector 130, the top portions of the gate electrodes 124A and gate electrodes 124B may be omitted.

[0051] Next, if Fig. 7A As shown, a dielectric material 127 such as silicon oxide, silicon nitride, etc. is formed to fill the slot-shaped opening. The dielectric material 127 can be referred to as an isolation structure to electrically isolate the gate electrode 124A from the gate electrode 124B. Thereafter, a dielectric material 126 is formed on the conductive layer 118, and a contact 128 is formed in the dielectric material 126 to electrically couple to the respective underlying conductive components (e.g., the gate electrodes 124A / 124B or the S / D layers 114 / 118). Next, a connector 130 is formed on the corresponding contact 128 and electrically coupled to the corresponding contact 128. Figure 7B Shows Fig. 7A The 3D memory device 200 however follows Fig. 7AIn some embodiments, the filling of the slot-shaped opening and the formation of the dielectric material 126 are performed together in the same deposition process, and therefore, the dielectric material 127 filling the slot-shaped opening is the same as the dielectric material 126 on the conductive layer 118. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the dielectric material 127 and the dielectric material 126 may be formed in different deposition processes and may have different dielectric materials.

[0052] Since the dielectric material 127 separates the conductive pillar 124 into two separate, independently controlled (eg, having different gate voltages) gate electrodes 124A and 124B, the number of memory cells in the 3D memory device 200 is twice that of the 3D memory device 100 . Fig. 7A The dashed boxes 140A and 140B in FIG. 1 show the Fig. 6A Two memory cells are formed in the region of the memory cell 140. Fig. 7A As shown, each memory cell 140A / 140B is Fig. 6A The memory cell 140 is half the size. Fig. 7A In the example of FIG. 1 , there are four connections 130 (labeled Vg1, Vg2, Vg3, and Vg4), each of which is electrically coupled to the gate of the transistor of the memory cell. In addition, there are two connections 130 labeled Vs1 and Vd1, where the two connections 130 are coupled to the S / D layer 114 and the S / D layer 118 of the transistor of the memory cell. Therefore, Fig. 7A The example of shows four memory cells, each of which can be programmed by applying appropriate voltages to the gate and S / D terminals of the transistor of each memory cell.

[0053] Figure 8 is a cross-sectional view of a 3D memory device 300 according to a third embodiment.

[0054] The 3D memory device 300 is similar to Fig. 6A The 3D memory device 100, but in Fig. 6A 1 and 10. The connectors 130 labeled Vg1 and Vg2 in FIG. 1 are replaced by conductive features 136 in the substrate 101. The conductive features 136 may be formed as part of an interconnect structure of the substrate 101. In addition, a conductive region 132 is formed in the substrate 101, located below the gate electrode 124 (e.g., located directly below and in physical contact with the gate electrode 124), and electrically coupled to the gate electrode 124. In some embodiments, the conductive region 132 is an epitaxial region including an epitaxially grown semiconductor material. In some embodiments, the conductive region 132 is a doped region, such as a semiconductor region doped with an N-type or P-type dopant. Figure 8Also shown is an electrical path 134, such as a conductive line in the substrate 101, connecting the conductive features 136 with the corresponding conductive regions 132. The electrical path 134 may be a conductive line in the interconnect structure of the substrate 101. The gate voltage of the 3D memory device 300 is applied to the gate electrode 124 through the conductive feature 136.

[0055] Fig. 9 is a cross-sectional view of a 3D memory device 400 according to a fourth embodiment.

[0056] The 3D memory device 400 is similar to Figure 8 3D memory device 400, but the conductive region 132 is electrically coupled to a connection 138 at the bottom surface of the substrate 101 through another electrical path 135 such as a through substrate via (TSV). Therefore, the gate voltage of the 3D memory device 400 is applied to the connection 138.

[0057] It should be noted that in some embodiments, the gate voltage of the 3D memory device 300 or 400 can be applied from the interconnect structure of the substrate 101, thereby simplifying the wiring layout of the gate electrode. In addition, the disclosed embodiments allow easy modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. The disclosed method of forming the 3D memory device can be easily integrated into the existing BEOL process, thereby enabling the memory device to be integrated into various semiconductor devices at a low production cost.

[0058] Figures 10 to 16 is a cross-sectional view of a method of forming a 3D memory device 500 according to a fifth embodiment. The 3D memory device 500 is similar to Fig. 6A 3D memory device 100 , but with an additional process to increase (eg, double) the memory cell density.

[0059] In some embodiments, to form the 3D memory device 500, follow Figures 1 to 6A Next, refer to the process steps for the 3D memory device 100. Fig.10 ,exist Fig. 6A A dielectric material 226a is formed over the structure. In some embodiments, the dielectric material 226a may include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. The inorganic dielectric material may include: a nitride such as silicon nitride; an oxide such as silicon oxide; a nitride oxide such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or a combination thereof. The dielectric material 226a may be formed by spin coating, lamination, CVD, etc.

[0060] refer to Fig.11, a plurality of contacts 228a (also referred to as contact plugs) are formed in the dielectric material 226a and electrically coupled to the connectors 130 labeled Vs1 and Vd1. In some embodiments, the contacts 228a may be formed by forming openings in the dielectric material 226a to expose the underlying connectors 130 labeled Vs1 and Vd1 and filling the openings with a conductive material such as copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, etc. After forming the conductive material, a planarization process such as a CMP process may be performed to remove excess portions of the conductive material from the upper surface of the dielectric material 226a.

[0061] refer to Fig.12 , a conductive layer 214 and a dielectric layer 212 are sequentially formed on the dielectric material 226a. Then, the conductive layer 214 and the dielectric layer 212 are patterned to expose the top surface of the contact 228a marked as Vd1 in the stepped region 150, while the contact 228a marked as Vs1 is covered by the conductive layer 214 and the dielectric layer 212. The structure, material and function of the conductive layer 214 and / or the dielectric layer 212 are similar to those of the conductive layer 114 and / or the dielectric layer 112, and have been described in the above embodiments, so the details are omitted here.

[0062] refer to Fig.13 , dielectric material 226b is formed beside conductive layer 214 and dielectric layer 212 and covers dielectric material 226a. Contact 228b is formed on contact 228a, and contact 228a is coupled to connector 130 labeled Vd1. That is, contact 228a is extended to reach the height of the top surface of dielectric layer 212. Dielectric material 226b and dielectric material 226a may have the same material such as SiO 2 In other words, dielectric materials 226a and 226b may be referred to as the same dielectric layer or film 226. In addition, contacts 228a and 228b may have the same metal material, such as copper. In other words, contacts 228a and 228b may be considered to be the same contact plug or conductive via 228. In some embodiments, the length of contact 228 of connector 130 labeled Vd1 is greater than the length of contact 228a of connector 130 labeled Vs1.

[0063] refer to Fig.14 , conductive layer 218 and dielectric layer 216 are sequentially formed on dielectric material 226b and conductive layer 214, thereby forming layer stack 210. Specifically, conductive layer 218 is in physical contact with contact plug 228 connected to connection 130 labeled Vd1. On the other hand, conductive layer 214 is in physical contact with contact 228 connected to connection 130 labeled Vs1. Fig.14In the example of FIG. 1 , dielectric layer 212 and conductive layer 214 have the same width W3. Dielectric layer 216 and conductive layer 218 have the same width W4 which is greater than width W3. That is, conductive layer 214 in stepped region 150 has sidewalls aligned along the same line with corresponding sidewalls of dielectric layer 212.

[0064] The structure, material, and function of the conductive layer 218 and / or the dielectric layer 216 are similar to those of the conductive layer 118 and / or the dielectric layer 116 and have been described in the above embodiments, so the details are omitted here.

[0065] refer to Fig.15 , a plurality of gate structures 225 are respectively formed in a plurality of openings 20 passing through the layer stack 210. In detail, each gate structure 225 may include a channel layer 220, a ferroelectric layer 222 and a conductive pillar 224. The ferroelectric layer 222 wraps the conductive pillar 224. The ferroelectric layer 222 is sandwiched between the channel layer 220 and the conductive pillar 224 and is in physical contact with them. The channel layer 220 is disposed between the layer stack 210 and the ferroelectric layer 222. That is, the channel layer 220 (or the gate structure 225) is surrounded by the dielectric layer 212, the dielectric layer 216 and the conductive layer 214, the conductive layer 218. The structure, material and function of the channel layer 220, the ferroelectric layer 222 and the conductive pillar 224 are similar to those of the channel layer 120, the ferroelectric layer 122 and the conductive pillar 124, and have been described in the above-mentioned embodiments, so the details are omitted here.

[0066] refer to Fig.16 ,exist Fig.15 A dielectric material 227 is formed on the structure. Then, a plurality of contacts 229 (also referred to as contact plugs) are formed in the dielectric material 227 and electrically coupled to the conductive pillars 224. In some embodiments, the contacts 229 electrically coupled to the conductive pillars 224 are also referred to as gate contacts 229G. Next, a plurality of connectors 230 (also referred to as conductive connectors or conductive bumps) are formed over the contacts 229 and electrically coupled to the contacts 229. The structures, materials, and functions of the dielectric material 227, the contacts 229, and the connectors 230 are similar to those of the dielectric material 126, the contacts 128, and the connectors 130, and have been described in the above embodiments, so the details are omitted here.

[0067] like Fig.16As shown, after forming the connector 230, the memory device 500 is completed. In detail, the memory device 500 may include a first layer T1 on the substrate 101 and a second layer T2 stacked above the first layer T1. The first layer T1 may include a first layer stack 110 and a first gate structure 125 passing through the first layer stack 110. The second layer T2 may include a second layer stack 210 and a second gate structure 225 passing through the second layer stack 210. The memory device 500 also includes a first electrical path P1 and a second electrical path P2 in the stepped region 150 between the first layer T1 and the second layer T2. The first electrical path P1 is electrically connected to the conductive layer 114 and the conductive layer 218, and has a first S / D voltage from the connector 130 marked as Vd1. The second electrical path P2 is electrically connected to the conductive layer 118 and the conductive layer 214, and has a second S / D voltage from the connector 130 marked as Vs1. That is, conductive layer 114 and conductive layer 218 share a first S / D voltage, while conductive layer 118 and conductive layer 214 share a second S / D voltage different from the first S / D voltage.

[0068] also, Fig.16 The dotted box in FIG. 5 also shows a memory cell 240 of the 3D memory device 500. The 3D memory device 500 includes a plurality of such memory cells. The memory cell 240 includes a second gate structure 225 passing through the second layer stack 210, and conductive layers 214 and 218 (hereinafter referred to as S / D layers 224). The second gate structure 225 may include a conductive pillar 224 (hereinafter referred to as a gate electrode 224), a ferroelectric layer 222 wrapping the gate electrode 224, a channel layer 220, and a channel layer 220 between the second layer stack 210 and the ferroelectric layer 222. Since the channel layer 220 is disposed between the S / D layers 214 and 218 of the second layer stack 210, in the illustrated embodiment, each memory cell 240 of the 3D memory device 500 is a transistor having a ferroelectric layer 222. Fig.16 The dashed arrow 245 in FIG. 2 shows a possible current flow direction in the channel layer 220 when the transistor of the memory cell is turned on.

[0069] Since the second layer T2 having the memory cell 240 is stacked above the first layer T1 having the memory cell 140, the number of memory cells in the 3D memory device 500 is twice that of the 3D memory device 100. Fig.16In the example of , four memory cells are shown. To avoid confusion, other than memory cell 140 and memory cell 240, other memory cells are not marked with dashed boxes. Memory cell 140 can be programmed (e.g., written to and / or read) by connectors 130 (e.g., connectors 130 labeled Vg1, Vs1, and Vd1) electrically coupled to the gate and S / D terminals of the transistor of the memory cell. Similarly, connectors 130 labeled Vg2, Vs1, and Vd1 can be used to program another memory cell disposed next to memory cell 140. Memory cell 240 can be programmed by connectors 230 and connectors 130, wherein connectors 230 are electrically coupled to the gate terminals of the transistors of the memory cell, such as connectors 230 labeled Vg3, and connectors 130 are electrically coupled to the S / D terminals of the transistors of the memory cell, such as connectors 130 labeled Vs1 and Vd1. Similarly, connection 230 labeled Vg2 and connection 130 labeled Vs1, Vd1 can be used to program other memory cells disposed next to memory cell 240. In some embodiments, gate structures 125 and 225 are electrically independent of each other, making wiring layout and operation more flexible.

[0070] It should be noted that in the present embodiment, memory cell 240 is stacked on memory cell 140 to allow easy modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. In addition, dielectric material 226a is provided between memory cell 140 and memory cell 240 to reduce or eliminate leakage current between two vertically adjacent memory cells 140 and 240, thereby improving device performance. As another example, although the disclosed embodiments show two layers T1 and T2 above substrate 101, these embodiments are illustrative and not restrictive. Those skilled in the art will readily appreciate that more than two layers may be formed above substrate 101. This will allow more memory cells to be formed in a 3D memory device.

[0071] Fig.17 is a cross-sectional view of a 3D memory device 600 according to a sixth embodiment.

[0072] The 3D memory device 600 is similar to Fig.16 The structure, material and function of the 3D memory device 500, that is, the 3D memory device 600 are similar to those of the 3D memory device 500 and have been described in the above embodiments, so the details are omitted here. The main difference between the 3D memory devices 500 and 600 is that the gate structure 225 and the gate structure 125 share the same gate voltage (Vg1 or Vg2) through the third electrical path P3 between the memory cells 140 and 240, thereby simplifying the circuit complexity.

[0073] Fig.18 is a cross-sectional view of a 3D memory device 700 according to a seventh embodiment.

[0074] The 3D memory device 700 is similar to Fig.16 The structure, material and function of the 3D memory device 500, that is, the 3D memory device 700 are similar to those of the 3D memory device 500 and have been described in the above embodiments, so the details are omitted here. The main difference between the 3D memory devices 500 and 700 is that the conductive layers 114, 118, 214 and 218 of the memory device 700 are electrically independent of each other.

[0075] Specifically, the memory device 700 includes a second layer T2 stacked on the first layer T1. The second layer T2' may include a second layer stack 210', and the second layer stack 210' includes a dielectric layer 212, a conductive layer 214, a dielectric layer 216, and a conductive layer 218 sequentially formed on a dielectric material 226a. Fig.18 In the example of , the dielectric layer 212 and the conductive layer 214 have the same width W5. The dielectric layer 216 and the conductive layer 218 have the same width W6 which is less than the width W5. That is, the conductive layer 218 in the stepped region 150 has sidewalls that are aligned along the same line with the corresponding sidewalls of the dielectric layer 216. The second gate structure 225 passes through the second layer stack 210'. The dielectric material 227 is formed over the second layer stack 210' and the second gate structure 225. The contact 229 is formed in the dielectric material 227 and is electrically coupled to the conductive pillar 224 or the conductive layer 214 and the conductive layer 218. In some embodiments, the contact 229 electrically coupled to the conductive pillar 224 is also referred to as a gate contact 229G, and the contact 229 electrically coupled to the conductive layer 214 and the conductive layer 218 (hereinafter referred to as the S / D layer) is also referred to as a source / drain contact 229SD. The connector 230 is formed over the contact 229 and is electrically coupled to the contact 229 .

[0076] exist Fig.18 In the example of FIG. 1 , there are four connections 130 and 230 (labeled Vg1, Vg2, Vg3, and Vg4), each of which is electrically coupled to the gate of the transistor of the memory cell. In addition, there are two connections 130 labeled Vs1 and Vd1, where the two connections 130 are coupled to the S / D layer 114 and S / D layer 118 of the transistor of the memory cell. In addition, there are two connections 230 labeled Vs2 and Vd2, where the two connections 230 are coupled to the S / D layers 214 and 218 of the transistor of the memory cell. Therefore, Fig.18The example of shows four memory cells, each of which can be programmed by applying appropriate voltages to the gate and S / D terminals of the transistor of each memory cell.

[0077] Note that although Fig.18 Only two layers T1 and T2' are shown in the figure, but the embodiments of the present invention are not limited thereto. In other embodiments, more than two layers may be formed above the substrate 101. This will allow more memory cells to be formed in the 3D memory device. The disclosed method for forming a 3D memory device can be easily integrated into an existing BEOL process, thereby enabling the memory device to be integrated into various semiconductor devices at a low production cost.

[0078] In addition, the first layer T1 of the 3D memory devices 500, 600, and 700 may be composed of Fig. 9 The illustrated structure 400 is substituted. In this case, another layer or layer stack may be stacked under the bottom surface of the substrate 101, thereby increasing the memory cell density.

[0079] Fig.19 1000 is a flowchart showing a method of forming a memory device according to some embodiments. It should be understood that Fig.19 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will appreciate many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.19 The various steps shown.

[0080] refer to Fig.19 , at box 1010, a first layer stack is formed on a substrate, wherein the first layer stack includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence. At box 1020, a first opening is formed in the first layer stack to pass through the first layer stack. At box 1030, a first gate structure is formed in the first opening. At box 1040, a portion of the second conductive layer and a portion of the second dielectric layer are removed to expose a portion of the first conductive layer, thereby forming a stepped region. At box 1050, a second layer stack is formed on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence. At box 1060, a first electrical path and a second electrical path are respectively formed in a stepped region between the first layer stack and the second layer stack, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer. At box 1070, a second opening is formed in the second layer stack to pass through the second layer stack. At block 1080 , a second gate structure is formed in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent of each other.

[0081] According to one embodiment, a memory device includes a first layer located on a substrate and a second layer located on the first layer. The first layer includes a first layer stack; a first gate electrode passing through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second layer includes a second layer stack; a second gate electrode passing through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

[0082] In some embodiments, the first layer stack includes: a first dielectric layer; a first conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the first conductive layer; and a second conductive layer disposed on the second dielectric layer, wherein the first channel layer contacts the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer. In some embodiments, the first dielectric layer and the first conductive layer have a first width, the second dielectric layer and the second conductive layer have a second width, and the second width is less than the first width. In some embodiments, the second layer stack includes: a third conductive layer disposed above the second conductive layer; a third dielectric layer disposed on the third conductive layer; a fourth conductive layer disposed on the third dielectric layer; and a fourth dielectric layer disposed on the fourth conductive layer, wherein the second channel layer contacts the third conductive layer, the third dielectric layer, the fourth conductive layer, and the fourth dielectric layer. In some embodiments, the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is greater than the third width. In some embodiments, the first conductive layer and the fourth conductive layer are connected to a first connector, and the second conductive layer and the third conductive layer are connected to a second connector different from the first connector. In some embodiments, the first gate electrode and the second gate electrode are connected to a third connector. In some embodiments, the second layer stack includes: a third dielectric layer disposed above the second conductive layer; a third conductive layer disposed on the third dielectric layer; a fourth dielectric layer disposed on the third conductive layer; and a fourth conductive layer disposed on the fourth dielectric layer, wherein the second channel layer contacts the third dielectric layer, the third conductive layer, the fourth dielectric layer, and the fourth conductive layer. In some embodiments, the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is less than the third width. In some embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are electrically independent of each other.

[0083] According to an embodiment, a method for forming a memory device includes: forming a first layer stack on a substrate, wherein the first layer stack includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence; forming a first opening in the first layer stack to pass through the first layer stack; forming a first gate structure in the first opening; removing a portion of the second conductive layer and a portion of the second dielectric layer to expose a portion of the first conductive layer, thereby forming a stepped region; forming a second layer stack on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence; forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer; forming a second opening in the second layer stack to pass through the second layer stack; and forming a second gate structure in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent of each other.

[0084] In some embodiments, the forming of the first gate structure includes: forming a first channel layer on the sidewall of the first opening, wherein the first conductive layer and the second conductive layer surround the first channel layer and are in physical contact with the first channel layer; forming a first ferroelectric layer on the first channel; and filling the first opening with a conductive material to form a first gate electrode. In some embodiments, the forming of the second gate structure includes: forming a second channel layer on the sidewall of the second opening, wherein the third conductive layer and the fourth conductive layer surround the second channel layer and are in physical contact with the second channel layer; forming a second ferroelectric layer on the second channel; and filling the second opening with a conductive material to form a second gate electrode. In some embodiments, the first electrical path includes a first contact plug in physical contact with the first conductive layer, the second electrical path includes a second contact plug in physical contact with the second conductive layer, and the length of the first contact plug is greater than the length of the second contact plug. In some embodiments, the second electrical path includes a third contact plug in physical contact with the third conductive layer, the first electrical path includes a fourth contact plug in physical contact with the fourth conductive layer, and the length of the fourth contact plug is greater than the length of the third contact plug.

[0085] According to an embodiment, a memory device includes: a layer stack disposed on a substrate, wherein the layer stack includes a first dielectric layer, a first source / drain layer, a second dielectric layer, and a second source / drain layer stacked in sequence; a first conductive pillar passing through the layer stack; a first ferroelectric layer wrapping the first conductive pillar; and a first channel layer between the first ferroelectric layers, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar.

[0086] In some embodiments, a portion of the first source / drain layer is exposed by the second dielectric layer and the second source / drain layer to form a stepped region. In some embodiments, the memory device further comprises: a first contact plug disposed on the first source / drain layer in the stepped region; a second contact plug disposed on the second source / drain layer in the stepped region, wherein the length of the first contact plug is greater than the length of the second contact plug; a second conductive pillar disposed beside the first conductive pillar and passing through the layer stack; a second ferroelectric layer wrapping the second conductive pillar; and a second channel layer disposed between the layer stack and the second ferroelectric layer, wherein the second ferroelectric layer contacts the second channel layer and the second conductive pillar, and the first conductive pillar and the second conductive pillar are electrically independent of each other. In some embodiments, the memory device further comprises: an isolation structure embedded in the first conductive pillar to divide the first conductive pillar into two gate pillars. In some embodiments, the memory device further includes: a conductive region disposed in the substrate below the first conductive pillar, wherein the conductive region contacts a bottom surface of the first conductive pillar; a connector disposed in the substrate or on a bottom surface of the substrate; and an electrical path electrically connected to the conductive region and the connector.

[0087] The components of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and various changes, substitutions and modifications may be made thereto without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: A first layer is provided on the substrate, wherein the first layer comprises: A first layer of stacked pieces; a first gate electrode passing through the first layer stack; a first channel layer disposed between the first layer stack and the first gate electrode; and a first ferroelectric layer disposed between the first channel layer and the first gate electrode; and A second layer is provided on the first layer, wherein the second layer comprises: A second layer of stacked pieces; a second gate electrode passing through the second layer stack; a second channel layer disposed between the second layer stack and the second gate electrode; and a second ferroelectric layer disposed between the second channel layer and the second gate electrode; The second gate electrode and the first gate electrode are electrically independent of each other.

2. The memory device according to claim 1, wherein: The first stack comprises: a first dielectric layer; a first conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the first conductive layer; and a second conductive layer disposed on the second dielectric layer, wherein the first channel layer contacts the first dielectric layer, the first conductive layer, the second dielectric layer and the second conductive layer.

3. The memory device according to claim 2, wherein: The first dielectric layer and the first conductive layer have a first width, the second dielectric layer and the second conductive layer have a second width, and the second width is smaller than the first width.

4. The memory device according to claim 2, wherein: The second layer stack comprises: a third conductive layer, disposed above the second conductive layer; a third dielectric layer disposed on the third conductive layer; a fourth conductive layer disposed on the third dielectric layer; and A fourth dielectric layer is disposed on the fourth conductive layer, wherein: The second channel layer contacts the third conductive layer, the third dielectric layer, the fourth conductive layer, and the fourth dielectric layer.

5. The memory device according to claim 4, wherein: The third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is greater than the third width.

6. The memory device according to claim 4, wherein: The first conductive layer and the fourth conductive layer are connected to a first connection member, and the second conductive layer and the third conductive layer are connected to a second connection member different from the first connection member.

7. The memory device according to claim 4, wherein: The first gate electrode and the second gate electrode are connected to a third connection member.

8. The memory device according to claim 2, wherein: The second layer stack comprises: a third dielectric layer, disposed above the second conductive layer; a third conductive layer, disposed on the third dielectric layer; a fourth dielectric layer, disposed on the third conductive layer; and A fourth conductive layer is disposed on the fourth dielectric layer, wherein the second channel layer is in contact with the third dielectric layer, the third conductive layer, the fourth dielectric layer and the fourth conductive layer.

9. The memory device according to claim 8, wherein: The third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is smaller than the third width.

10. The memory device according to claim 7, wherein: The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are electrically independent from each other.

11. A method of forming a memory device, comprising: forming a first layer stack on a substrate, wherein the first layer stack comprises a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence; forming a first opening in the first layer stack to penetrate the first layer stack; forming a first gate structure in the first opening; removing a portion of the second conductive layer and a portion of the second dielectric layer to expose a portion of the first conductive layer, thereby forming a stepped region; forming a second layer stack on the first layer stack, wherein the second layer stack comprises a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence; forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer; forming a second opening in the second layer stack to penetrate the second layer stack; and A second gate structure is formed in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent of each other.

12. The method according to claim 11, wherein: The forming of the first gate structure comprises: forming a first channel layer on a sidewall of the first opening, wherein the first conductive layer and the second conductive layer surround the first channel layer and are in physical contact with the first channel layer; forming a first ferroelectric layer on the first channel layer; and The first opening is filled with a conductive material to form a first gate electrode.

13. The method according to claim 11, wherein: Forming the second gate structure includes: forming a second channel layer on a sidewall of the second opening, wherein the third conductive layer and the fourth conductive layer surround the second channel layer and are in physical contact with the second channel layer; forming a second ferroelectric layer on the second channel layer; and The second opening is filled with a conductive material to form a second gate electrode.

14. The method according to claim 11, wherein: The first electrical path includes a first contact plug in physical contact with the first conductive layer, the second electrical path includes a second contact plug in physical contact with the second conductive layer, and a length of the first contact plug is greater than a length of the second contact plug.

15. The method according to claim 11, wherein: The second electrical path includes a third contact plug in physical contact with the third conductive layer, the first electrical path includes a fourth contact plug in physical contact with the fourth conductive layer, and a length of the fourth contact plug is greater than a length of the third contact plug.

16. A storage device comprising: A layer stack is disposed on a substrate, wherein the layer stack comprises a first dielectric layer, a first source / drain (S / D) layer, a second dielectric layer, and a second source / drain layer stacked in sequence; a first conductive column passing through the layer stack; a first ferroelectric layer, wrapping the first conductive pillar; and a first channel layer disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar; A first dielectric material is disposed on the second source / drain layer and directly contacts the second source / drain layer, and a contact surface between the first dielectric material and the second source / drain layer is coplanar with a top surface of the first channel layer and a top surface of the first ferroelectric layer.

17. The memory device according to claim 16, wherein: Portions of the first source / drain layer are exposed by the second dielectric layer and the second source / drain layer to form a stepped region.

18. The memory device according to claim 17, further comprising: a first contact plug disposed on the first source / drain layer in the stepped region; a second contact plug disposed on the second source / drain layer in the stepped region, wherein the length of the first contact plug is greater than the length of the second contact plug; a second conductive column disposed beside the first conductive column and passing through the layer stack; a second ferroelectric layer, wrapping the second conductive pillar; and A second channel layer is disposed between the layer stack and the second ferroelectric layer, wherein the second ferroelectric layer contacts the second channel layer and the second conductive pillar, and the first conductive pillar and the second conductive pillar are electrically independent of each other.

19. The memory device according to claim 16, further comprising: An isolation structure is embedded in the first conductive pillar to divide the first conductive pillar into two gate pillars.

20. The memory device according to claim 16, further comprising: a conductive region, disposed in the substrate below the first conductive column, wherein the conductive region contacts a bottom surface of the first conductive column; a connector, disposed in the substrate or on the bottom surface of the substrate; and An electrical path is electrically connected to the conductive area and the connection member.

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