Delay Circuit and Phase Interpolator

Abstract

The present disclosure relates to a delay circuit and a phase interpolator. The delay circuit includes a first delay line configured to delay a first clock by a delay value adjusted based on a delay control code; a delay control circuit configured to compare a phase of the first clock delayed by the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having a delay value corresponding to half of the delay value of the first delay line based on the delay control code.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0043459, filed on Apr. 9, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments relate to a delay circuit and a phase interpolator. Background Art

[0004] Generally, a phase interpolator is used to generate clocks having various phases in various integrated circuits. The phase interpolator receives a plurality of clocks having different phases and synthesizes the received clocks, thereby generating an output clock having an intermediate phase between the phases of the received clocks.

[0005] Figure 1 is a diagram illustrating a conventional phase interpolator 100 and its operation.

[0006] Reference Figure 1 , the phase interpolator 100 may include inverters 101 and 102 for transmitting a first input clock CLKA_IN, inverters 106 and 107 for transmitting a second input clock CLKB_IN, and inverters 103 to 105 for synthesizing the first input clock CLKA_IN and the second input clock CLKB_IN.

[0007] Figure 1 shows a first input clock CLKA_IN and a second input clock CLKB_IN having a phase difference “dT” therebetween, and an interpolated output clock CLKAB_OUT output from the phase interpolator 100 having an intermediate phase between a first output clock CLKA_OUT and a second output clock CLKB_OUT. This is because the interpolated output clock CLKAB_OUT is generated by fusing analog components of the periods of the first input clock CLKA_IN and the second input clock CLKB_IN that are transformed.

[0008] When the phase difference “dT” between the first input clock CLKA_IN and the second input clock CLKB_IN is large, the periods of the first input clock CLKA_IN that are transformed and the periods of the second input clock CLKB_IN that are transformed do not overlap with each other. In such a case, it is important to synthesize the analog components of the two clocks CLKA_IN and CLKB_IN. Therefore, when the two clocks CLKA_IN and CLKB_IN to be synthesized are low-frequency clocks, it is impossible to use Figure 1 the conventional phase interpolator 100 to perform phase interpolation. SUMMARY OF THE INVENTION

[0009] Each embodiment is directed to a phase interpolator that can generate an intermediate phase clock between multiple clocks having a phase difference therebetween.

[0010] In one embodiment, a delay circuit may include: a first delay line adapted to delay a first clock by a delay value adjusted based on a delay control code; a delay control circuit adapted to compare the phase of the first clock delayed by the first delay line with the phase of a second clock to generate a delay control code; and a second delay line having a delay value that is half of the delay value of the first delay line based on the delay control code.

[0011] In one embodiment, a phase interpolator may include: a first delay line adapted to delay a first clock by a delay value adjusted based on a delay control code; a delay control circuit adapted to compare the phase of the first clock delayed by the first delay line with the phase of a second clock to generate a delay control code; and a second delay line adapted to delay the first clock based on the delay control code by a delay value that is half of the delay value of the first delay line to generate a phase interpolation clock.

[0012] In one embodiment, a phase interpolator may include: a first delay line adapted to delay a first input clock by a delay value adjusted based on a delay control code; a delay control circuit adapted to compare the phase of the first input clock delayed by the first delay line with the phase of a second input clock to generate a delay control code; a first driver adapted to output the first input clock delayed by the first delay line as a first output clock; a first synthesizer adapted to synthesize the first input clock delayed by the first delay line with the second input clock to drive a first node with the synthesized clock; a second delay line adapted to delay the synthesized clock of the first node based on the delay control code by a delay value that is half of the delay value of the first delay line to output the delayed clock as a second output clock; a second driver adapted to transmit the second input clock to a second node; and a third delay line adapted to delay the clock of the second node by a delay value adjusted based on the delay control code and equal to the delay value of the first delay line to output the delayed clock as a third output clock.

[0013] In one embodiment, a phase interpolation method may include: delaying a first clock by a delay value adjusted based on a delay control code; comparing the phase of the delayed first clock with the phase of a second clock to generate a delay control code configured to make the first and second input clocks in phase; synthesizing the delayed first input clock and the second input clock to output a synthesized clock; delaying the synthesized clock by a delay value corresponding to half of the delay value of the first input clock based on the delay control code to output a delayed synthesized clock; and delaying a second output clock by a delay value equal to the delay value of the first input clock based on the delay control code.

[0014] This embodiment may be capable of generating an intermediate phase clock between clocks having a large phase difference therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram illustrating a conventional phase interpolator and its operation.

[0016] Figure 2 is a diagram illustrating a delay circuit 200 according to an embodiment of the present invention.

[0017] Figure 3 is a diagram illustrating Figure 2 a detailed diagram of a first embodiment of first and second delay lines.

[0018] Figure 4 is a diagram illustrating Figure 2 a detailed diagram of a second embodiment of first and second delay lines.

[0019] Figure 5 is a diagram illustrating Figure 2 a detailed diagram of a third embodiment of first and second delay lines.

[0020] Figure 6 is a diagram illustrating a phase interpolator according to an embodiment of the present invention.

[0021] Figure 7 is a diagram illustrating a phase interpolator according to another embodiment of the present invention. DETAILED DESCRIPTION

[0022] Various embodiments will be described hereinafter with reference to the accompanying drawings in order to describe the present disclosure in detail, such that those skilled in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure. In the description of this embodiment, components irrelevant to the subject matter of this embodiment may be omitted. When reference numerals are assigned to components in the drawings, even if the components are illustrated in different drawings, the same components may be denoted by the same reference numerals.

[0023] Note that references to "an embodiment", "another embodiment", etc. do not necessarily mean only one embodiment, and different references to any such phrase are not necessarily to the same (multiple) embodiments.

[0024] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Thus, the first element described below could also be termed the second or third element without departing from the spirit and scope of the present invention.

[0025] It will further be understood that when the terms "comprises", "comprising", "includes" and "including" are used in this specification, they specify the presence of the stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] As used herein, unless the context clearly dictates otherwise, the singular forms may also include the plural forms and vice versa. Unless otherwise specified or clear from the context that it is directed to the singular form, the articles "a" and "an" used in this application and the appended claims should generally be understood to mean "one or more".

[0027] Figure 2 is a diagram showing a delay circuit 200 according to an embodiment of the present invention.

[0028] Reference Figure 2 , the delay circuit 200 may include a first delay line 210, a delay control circuit 220, and a second delay line 230.

[0029] The first delay line 210 may generate a delayed first clock CLK1D by delaying a first clock CLK1. The first delay line 210 may have a delay control code DLY_CONT <n:1>Adjusted delay value.

[0030] The delay control circuit 220 can generate a delay control code DLY_CONT by comparing the delayed first clock CLK1D and the second clock CLK2. <n:1>The delay control circuit 220 can increase or decrease the delay control code DLY_CONT according to the phase comparison result between the delayed first clock CLK1D and the second clock CLK2 <n:1>The code value. Therefore, the delay control circuit 220 can generate a delay control code DLY_CONT <n:1>, so that the delayed first clock CLK1D and the second clock CLK2 are in phase, that is, the delay value of the first delay line 210 becomes equal to the phase difference between the first clock CLK1 and the second clock CLK2.

[0031] The second delay line 230 may have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value corresponds to half of the delay value of the first delay line 210. Since the second delay line 230 receives the same delay control code DLY_CONT as the first delay line 210 <n:1>, so the second delay line 230 can be designed to have a delay value that is half of the delay value of the first delay line 210. The second delay line 230 can be used to delay the random signal IN that needs to be delayed.

[0032] Reference Figure 2 , the first delay line 210 can have a delay value corresponding to the phase difference between the first clock CLK1 and the second clock CLK2, and the second delay line 230 can have a delay value corresponding to half of the phase difference between the first clock CLK1 and the second clock CLK2. Based on this characteristic, the phase interpolator to be described below can be designed.

[0033] Figure 3 is a diagram Figure 2 detailed view of the first embodiment of the first delay line 210 and the second delay line 230.

[0034] Reference Figure 3 , the first delay line 210 can include two variable delays 311 and 312, and the second delay line 230 can include one variable delay 321.

[0035] The first delay line 210 can include a first variable delay 311 and a second variable delay 312 coupled in series. Each of the first variable delay 311 and the second variable delay 312 can have a delay controlled by the delay control code DLY_CONT <n:1>Adjusted delay values, and the first variable delay 311 and the second variable delay 312 can be designed in the same manner (i.e., can have the same component configuration) and have the same delay values.

[0036] The second delay line 230 may include a third variable delay 321. The third variable delay 321 may have a delay control code DLY_CONT <n:1>Adjusted delay value. The third variable delay 321 can be designed in the same manner as the first variable delay 311 (i.e., can have the same component configuration) and has the same delay value as the first variable delay 311.

[0037] Since the first to third variable delays 311, 312, and 321 are designed in the same manner and receive the same delay control code DLY_CONT <n:1>, so the first to third variable delays 311, 312, and 321 can be equal to each other. Since the first delay line 210 includes two variable delays 311 and 312 coupled in series, and the second delay line 230 includes one variable delay 321, the delay value of the first delay line 210 can be twice as large as the delay value of the second delay line 230.

[0038] Figure 4 is a diagram Figure 2 detailed diagram of a second embodiment of the first delay line 210 and the second delay line 230.

[0039] Reference Figure 4 , the first delay line 210 may include a first variable delay 411. The first variable delay 411 may have a delay control code DLY_CONT <n:1>Adjusted delay value.

[0040] The second delay line 230 may include a code value converter 431 and a second variable delay 432.

[0041] The code value converter 431 may convert the delay control code DLY_CONT <n:1>Halve the code value to generate the half-delay control code DLY_CONT_HALF <n:1>。The half-delay control code DLY_CONT_HALF <n:1>It can be code like this: for controlling the delay value to the delay control code DLY_CONT <n:1>Half of the code value. Delay control code DLY_CONT <n:1>It may have a binary code format or a thermometer code format. In any case, the code value converter 431 can generate a half-delay control code DLY_CONT_HALF <n:1>, such that corresponding to this half-delay control code DLY_CONT_HALF <n:1>The delay value becomes corresponding to the delay control code DLY_CONT <n:1>Half of the code value.

[0042] The second variable delay 432 can be designed in the same manner as the first variable delay 411 (i.e., can have the same element configuration), and can have a half delay control code DLY_CONT_HALF <n:1>Adjusted delay value. Thus, the second variable delay 432 can have a delay value that corresponds to half of the delay value of the first variable delay 411.

[0043] Figure 5 is a diagram Figure 2 detailed illustration of a third embodiment of the first delay line 210 and the second delay line 230. In Figure 5 which, <1> to <n>Can represent the delay control code DLY_CONT <n:1>N bits. In addition, <1>B to <n>B can represent by applying the delay control code DLY_CONT <n:1>Bits obtained by inverting N bits of

[0044] Reference Figure 5 , the first delay line 210 may include NAND gates 511 to 521 and inverters 522 to 527. The first delay line 210 may have a delay control code DLY_CONT <n:1>Adjusted delay value. When the delay control code has the value 000…11, the first clock CLK1 can be delayed by NAND gates 511, 513, 515, 516, 520, 519, and 518. Further, when the delay control code has the value 000…01, the first clock CLK1 can be delayed by NAND gates 511, 513, 514, 519, and 518. Inverters 522 to 527 can act as latches used to form the load. According to the delay control code DLY_CONT <n:1>Value, the path that the first clock CLK1 passes through in the first delay line 210 can be adjusted in the first delay line 210. That is, according to the delay control code DLY_CONT <n:1>For the value, one path among N paths can be selected, and the first clock CLK1 can be delayed by the selected path. For example, NAND gates 512, 514, and 516 can select the path through which the first clock CLK1 passes in the first delay line 210.

[0045] The second delay line 230 can include NAND gates 531 to 541 and inverters 542 to 547. The second delay line 230 has N / 2 paths and can be controlled by the delay control code DLY_CONT <n:1>even code values DLY_CONT<2>, <4>,..., and <n>, to select one path out of N / 2 paths, and this one path is used to delay the input signal IN. Delay control code DLY_CONT <n:1>The odd code values DLY_CONT<1>, <3>,..., and <n-1>, the latch composed of inverters 542 to 547 can be enabled or disabled, thereby adjusting the loading. When the delay control code has the value 000...11, the input signal can be delayed by NAND gates 531, 533, 534, 539, and 538. In this case, inverter 543 can be disabled. Therefore, the latch formed by inverters 544 and 545 can be disabled. When the delay control code has the value 000...01, the input signal IN can be delayed by NAND gates 531, 532, and 538. In this case, inverter 543 can be enabled. Therefore, the latch formed by inverters 542 and 543 can be enabled to increase the loading. For reference, NAND gates 542, 544, and 546 can select the path through which the input signal IN passes in the second delay line 230.

[0046] Since the delay values of the first delay line 210 and the second delay line 230 are determined by the same delay control code DLY_CONT <n:1>Adjust, and select a path in the second delay line 230 having a length corresponding to half of the length of the first delay line 210, so that the second delay line 230 can have a delay value corresponding to half of the delay value of the first delay line 210.

[0047] Figure 6 is a diagram illustrating a phase interpolator 600 according to an embodiment of the present invention.

[0048] Reference Figure 6 , the phase interpolator 600 may include a first delay line 610, a delay control circuit 620, and a second delay line 630.

[0049] The first delay line 610 may generate a delayed first clock CLK1D by delaying the first clock CLK1. The first delay line 610 may have a delay controlled by the delay control code DLY_CONT <n:1>Adjusted delay value. The first delay circuit 610 can be designed in the same manner as the first delay circuit 210 (i.e., can have the same component configuration).

[0050] The delay control circuit 620 can generate a delay control code by comparing the phases of the delayed first clock CLK1D and the second clock CLK2. The delay control circuit 620 can increase or decrease the delay control code DLY_CONT according to the phase comparison result between the delayed first clock CLK1D and the second clock CLK2. <n:1>The code value. Therefore, the delay control circuit 620 can generate a delay control code DLY_CONT <n:1>, such that the delayed first clock CLK1D and the second clock CLK2 are in phase, that is, the delay value of the first delay line 610 becomes equal to the phase difference between the first clock CLK1 and the second clock CLK2.

[0051] The second delay line 630 may have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value corresponds to half of the delay value of the first delay line 610. Since the second delay line 630 receives the same delay control code DLY_CONT as the first delay line 610 <n:1>, so the second delay line 630 can be designed to have a delay value that is half of the delay value of the first delay line 610. The second delay line 630 can be designed in the same manner as the second delay line 230 (i.e., can have the same element configuration).

[0052] The second delay line 630 can generate a phase interpolation clock CLK12 by delaying the first clock CLK1. Since the second delay line 630 has a delay value corresponding to half of the phase difference between the first clock CLK1 and the second clock CLK2, and the phase interpolation clock CLK12 is obtained by delaying the first clock CLK1 via the second delay line 630, the phase interpolation clock CLK12 can have an intermediate phase between the first clock CLK1 and the second clock CLK2.

[0053] Figure 7 is a diagram showing a phase interpolator 700 according to another embodiment of the present invention. Figure 7 The phase interpolator 700 can use four input clocks CLK0_IN, CLK90_IN, CLK180_IN, and CLK270_IN having a 90-degree phase difference therebetween to generate eight output clocks CLK0_OUT, CLK45_OUT, CLK90_OUT, CLK135_OUT, CLK180_OUT, CLK225_OUT, CLK270_OUT, and CLK315_OUT, with a 45-degree phase difference between the above output clocks.

[0054] Reference Figure 7 , the phase interpolator 700 can include a first delay line 711 to an eleventh delay line 721, a delay control circuit 730, first drivers 741 to 744, and first synthesizers 751 to 754.

[0055] The first delay line 711 can have a delay controlled by the delay control code DLY_CONT <n:1>Adjusted delay value and delay the first input clock CLK0_IN.

[0056] The delay control circuit 730 can generate a delay control code DLY_CONT by comparing the phase of the output clock of the first delay line 711 with the second input clock CLK90_IN. <n:1>Therefore, the delay control circuit 730 can generate a delay control code DLY_CONT <n:1>, so that the output clock of the first delay line 711 is in phase with the second input clock CLK90_IN, that is, the delay value of the first delay line 711 becomes equal to the phase difference between the first input clock CLK0_IN and the second input clock CLK90_IN.

[0057] The first driver 741 can output the output clock of the first delay line 711 as the first output clock CLK0_OUT. The first driver 741 can include two inverters coupled in series.

[0058] The first synthesizer 751 can synthesize the output clock of the first delay line 711 and the second input clock CLK90_IN, and transmit the synthesized clock to the second delay line 712. Since the output clock of the first delay line 711 is in phase with the second input clock CLK90_IN, it can be considered that the first synthesizer 751 transmits two clocks to the second delay line 712. The first synthesizer 751 can include three inverters.

[0059] The second delay line 712 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value corresponds to half of the delay value of the first delay line 711. That is, the second delay line 712 may have a delay value corresponding to a 45-degree phase difference between the clocks. The second delay line 712 may delay the output clock of the first synthesizer 751 and output the delayed clock as the second output clock CLK45_OUT.

[0060] The second driver 742 may transmit the second input clock CLK90_IN to the third delay line 713. The second driver 742 may include two inverters coupled in series.

[0061] The third delay line 713 may have a delay control code DLY_CONT <n:1>An adjusted delay value, and this delay value is equal to the delay value of the first delay line 711. That is, the third delay line 713 can have a delay value corresponding to a 90-degree phase difference between the clocks. The third delay line 713 can delay the output clock of the second driver and output the delayed clock as the third output clock CLK90_OUT.

[0062] The fourth delay line 714 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value is equal to the delay value of the first delay line 711. The fourth delay line 714 can delay the second input clock CLK90_IN.

[0063] The second synthesizer 752 can transmit the output clock of the fourth delay line 714 and the third input clock CLK180_IN to the fifth delay line 715. The second synthesizer 752 can include three inverters.

[0064] The fifth delay line 715 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value corresponds to half of the delay value of the first delay line 711. The fifth delay line 715 may delay the output clock of the second synthesizer 752 and output the delayed clock as the fourth output clock CLK135_OUT.

[0065] The third driver 743 may transmit the third input clock CLK180_IN to the sixth delay line 716. The third driver 743 may include two inverters coupled in series.

[0066] The sixth delay line 716 has a delay control code DLY_CONT <n:1>An adjusted delay value, and this delay value is equal to the delay value of the first delay line 711. The sixth delay line can delay the output clock of the third driver 743 and output the delayed clock as the fifth output clock CLK180_OUT.

[0067] The seventh delay line 717 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value is equal to the delay value of the first delay line 711. The seventh delay line 717 can delay the third driving input clock CLK180_IN.

[0068] The third synthesizer 753 can transmit the output clock of the seventh delay line 717 and the fourth input clock CLK270_IN to the eighth delay line 718. The third synthesizer 753 can include three inverters.

[0069] The eighth delay line 718 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the adjusted value corresponds to half of the delay value of the first delay line 711. The eighth delay line 718 can delay the output clock of the third synthesizer 753, and output the delayed clock as the sixth output clock CLK225_OUT.

[0070] The fourth driver 744 can transmit the fourth input clock CLK270_IN to the ninth delay line 719. The fourth driver 744 can include two inverters coupled in series.

[0071] The ninth delay line 719 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and this delay value is equal to the delay value of the first delay line 711. The ninth delay line 719 can delay the output clock of the fourth driver 744, and output the delayed clock as the seventh output clock CLK270_OUT.

[0072] The tenth delay line 720 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and the delay value is equal to the delay value of the first delay line 711. The tenth delay line 720 can delay the fourth drive input clock CLK270_IN.

[0073] The fourth synthesizer 754 can transmit the output clock of the tenth delay line 720 and the first input clock CLK0_IN to the eleventh delay line 721.

[0074] The eleventh delay line 721 can have a delay control code DLY_CONT <n:1>An adjusted delay value, and this delay value corresponds to half of the delay value of the first delay line 711. The eleventh delay line 721 can delay the output clock of the fourth synthesizer 754 and output the delayed clock as the eighth output clock CLK315_OUT.

[0075] According to Figure 7 the embodiments of, delay lines 711, 713, 714, 716, 717, 719, and 720 having delay values corresponding to a 90-degree phase difference between clocks, and delay lines 712, 715, 718, and 721 having delay values corresponding to a 45-degree phase difference between clocks can be combined, such that the phase interpolator can be capable of generating clocks CLK0_OUT, CLK45_OUT, CLK90_OUT, CLK135_OUT, CLK180_OUT, CLK225_OUT, CLK270_OUT, and CLK315_OUT having desired phases.

[0076] According to an embodiment of the present invention, even in a case where two clocks to be synthesized are low-frequency clocks, the two clocks can be synthesized after making the two clocks in phase.

[0077] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope as defined in the following claims. < / n> < / n> < / n>

Claims

1. A delay circuit, comprising: A first delay circuit, adapted to delay a first clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first clock delayed by the first delay circuit with the phase of a second clock to generate the delay control code; And A second delay circuit, having a delay value corresponding to half of the delay value of the first delay circuit based on the delay control code, wherein the first delay circuit includes: A first variable delay component, having a delay value adjusted based on the delay control code; And A second variable delay component, serially coupled to the first variable delay component and having the same element configuration as the first variable delay component, wherein the second delay circuit includes a third variable delay component having the same element configuration as the first variable delay component.

2. The delay circuit according to claim 1, wherein the delay control circuit is adapted to increase or decrease the code value of the delay control code according to the result of phase comparison.

3. A delay circuit, comprising: A first delay circuit, adapted to delay a first clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first clock delayed by the first delay circuit with the phase of a second clock to generate the delay control code; And A second delay circuit, having a delay value corresponding to half of the delay value of the first delay circuit based on the delay control code, wherein the first delay circuit includes a first variable delay component having a delay value adjusted based on the delay control code, wherein the second delay circuit includes: A code value converter, adapted to halve the code value of the delay control code to generate a half-delay control code; And A second variable delay component, having a delay value adjusted based on the half-delay control code and having the same element configuration as the first variable delay.

4. A delay circuit, comprising: A first delay circuit, adapted to delay a first clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first clock delayed by the first delay circuit with the phase of a second clock to generate the delay control code; And A second delay circuit, having a delay value corresponding to half of the delay value of the first delay circuit based on the delay control code, wherein the delay control code includes N delay control signals, wherein the first delay circuit includes N delay paths, and one of the N delay paths is selected by the N delay control signals, wherein the second delay circuit includes N / 2 delay paths, and one of the N / 2 delay paths is selected by half of the N delay control signals, where N is an even number.

5. The delay circuit according to claim 4, wherein the other half of the delay control signal that is not used when the delay path is selected is used to adjust the loading of the variable delay.

6. A phase interpolator, comprising: A first delay circuit, adapted to delay a first clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first clock delayed by the first delay circuit with the phase of a second clock to generate the delay control code; And A second delay line, adapted to delay the first clock by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to generate a phase interpolation clock, wherein the first delay line includes: A first variable delay component having a delay value adjusted based on the delay control code; and A second variable delay component serially coupled to the first variable delay component and having the same element configuration as the first variable delay component, wherein the second delay line includes a third variable delay component having the same element configuration as the first variable delay component.

7. The phase interpolator according to claim 6, wherein the delay control circuit is adapted to increase or decrease the code value of the delay control code according to the result of the phase comparison.

8. A phase interpolator, comprising: A first delay line, adapted to delay a first clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first clock delayed by the first delay line with the phase of a second clock to generate the delay control code; and A second delay line, adapted to delay the first clock by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to generate a phase interpolation clock, wherein the first delay line includes a first variable delay having a delay value adjusted based on the delay control code, wherein the second delay line includes: A code value converter, adapted to halve the code value of the delay control code to generate a half delay control code; and A second variable delay component having a delay value adjusted by the half delay control code.

9. A phase interpolator, comprising: A first delay line, adapted to delay a first input clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first input clock delayed by the first delay line with the phase of a second input clock to generate the delay control code; and A second delay line, adapted to delay the first input clock by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to generate a phase interpolation clock, wherein the delay control code includes N delay control signals, wherein the first delay line includes N delay paths and one of the N delay paths is selected by the N delay control signals, wherein the second delay line includes N / 2 delay paths and one of the N / 2 delay paths is selected by half of the N delay control signals, where N is an even number.

10. The phase interpolator according to claim 9, wherein the other half of the delay control signal that is not used when the delay path is selected is used to adjust the loading of the variable delay.

11. A phase interpolator, comprising: A first delay line, adapted to delay a first input clock by a delay value adjusted based on a delay control code; A delay control circuit, adapted to compare the phase of the first input clock delayed by the first delay line with the phase of a second input clock to generate the delay control code; A first driver, adapted to output the first input clock delayed by the first delay line as a first output clock; A first synthesizer, adapted to synthesize the first input clock delayed by the first delay line and the second input clock to drive a first node with the synthesized clock; A second delay line, adapted to delay the synthesized clock of the first node based on the delay control code by a delay value that is half of the delay value of the first delay line, and output the delayed clock as a second output clock; A second driver, adapted to transmit the second input clock to a second node; And A third delay line, adapted to delay the clock of the second node by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line, and output the delayed clock as a third output clock; 12. The phase interpolator according to claim 11, further comprising: A fourth delay line, adapted to delay the second input clock by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line; A second synthesizer, adapted to synthesize the second input clock delayed by the fourth delay line and a third input clock to drive a third node with the synthesized clock; A fifth delay line, adapted to delay the synthesized clock of the third node based on the delay control code by a delay value that is half of the delay value of the first delay line, and output the delayed clock as a fourth output clock; A third driver, adapted to transmit the third input clock to a fourth node; And A sixth delay line, adapted to delay the clock of the fourth node by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line, and output the delayed clock as a fifth output clock; 13. The phase interpolator according to claim 12, further comprising: A seventh delay line, adapted to delay the third input clock by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line; A third synthesizer, adapted to synthesize the third input clock delayed by the seventh delay line and a fourth input clock to drive a fifth node with the synthesized clock; An eighth delay line, adapted to delay the synthesized clock of the fifth node based on the delay control code by a delay value that is half of the delay value of the first delay line, and output the delayed clock as a sixth output clock; A fourth driver, adapted to transmit the fourth input clock to a sixth node; And A ninth delay line, adapted to delay the clock of the sixth node by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line, and output the delayed clock as a seventh output clock; 14. The phase interpolator according to claim 13, further comprising: A tenth delay line, adapted to delay the fourth input clock by a delay value that is adjusted based on the delay control code and equal to the delay value of the first delay line; A fourth synthesizer, adapted to synthesize the fourth input clock delayed by the tenth delay line and the first input clock to drive a seventh node with the synthesized clock; The eleventh delay circuit is adapted to delay the synthesized clock of the seventh node based on the delay control code by a delay value that is half of the delay value of the first delay circuit, and output the delayed clock as the eighth output clock.

15. The phase interpolator according to claim 11, wherein the delay control circuit is adapted to increase or decrease the code value of the delay control code according to the result of phase comparison.

16. A phase interpolation method, comprising: Delay the first input clock by a delay value adjusted based on the delay control code; Compare the phase of the delayed first input clock with the phase of the second input clock to generate the delay control code, which is configured to make the first input clock and the second input clock in phase; Synthesize the delayed first input clock and the second input clock to output a synthesized clock; Based on the delay control code, delay the synthesized clock by a delay value that is half of the delay value of the first input clock to output a delayed synthesized clock; Based on the delay control code, delay the second input clock by a delay value equal to the delay value of the first input clock.

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