Enhanced data clock operation in memory

Abstract

Methods and apparatuses for improving a data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and synchronize the data clock with the host. The memory includes a clock tree buffer configured to be triggered based on the data clock to capture write data or output read data, and a command decoder configured to detect a data clock pause command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable the triggering based on the data clock in response to the command decoder detecting the data clock pause command. The host includes a memory controller configured to provide the data clock pause command to the memory via the link while the data clock is synchronized between the host and the memory.

Description

[0001] CLAIM

[0002] This patent application claims priority to Non-Provisional Application No. 16 / 803,977, filed February 27, 2020, entitled “Enhanced Data Clock Operations in Memory,” and Provisional Application No. 62 / 812,689, filed March 1, 2019, entitled “Enhanced Data Clock Operations in Memory,” assigned to the assignee of the present application and incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to methods and apparatuses with enhanced data clock operations, and more specifically to methods and apparatuses with a data clock pause mode to reduce power consumption while the data clock is in an always-on mode. BACKGROUND

[0004] Computing devices (e.g., laptops, mobile phones, etc.) can include one or more processors to perform various functions, such as phone applications, wireless data access, and camera / video functions, among others. Memory is an important component of a computing device. One processor can be coupled to the memory to perform the computing functions described above, and / or store temporary data used to process these computing functions within the memory, among other things.

[0005] The memory can be embedded with one processor on a semiconductor die or be part of a different semiconductor die. The memory can perform various functions. For example, the memory can be used as a cache, a register file, or a storage. The memory can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, among others.

[0006] As the demand for computing devices to perform more functions at increased speeds grows, the power issues also grow. While energy conservation can be particularly important for mobile computing devices, non-mobile devices can also benefit from reduced power consumption to reduce waste heat generation. Thus, various kinds of computing devices can benefit from memory systems that have reduced power consumption. Accordingly, schemes to reduce power consumption are desirable. SUMMARY

[0007] This summary identifies some example aspects and is not an exclusive or exhaustive description of the subject matter disclosed. Additional features and aspects are described and will become apparent to those skilled in the art upon consideration of the following detailed description and with reference to the accompanying drawings.

[0008] An apparatus according to at least one embodiment includes a memory configured to receive a data clock from a host via a link and synchronize the data clock with the host, a clock tree buffer configured to be triggered based on the data clock to capture write data or output read data, and a command decoder configured to detect a data clock pause command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable the triggering based on the data clock in response to the command decoder detecting the data clock pause command.

[0009] Another apparatus according to at least one embodiment includes a host coupled to a memory via a link. The host is configured to synchronize a data clock with the memory and output write data or capture read data based on the data clock. The host includes a memory controller configured to provide a data clock pause command to the memory via the link while the data clock is synchronized between the host and the memory. The data clock pause command informs the memory to disable a clock tree buffer configured to be triggered based on the data clock. The memory controller is further configured to trigger the data clock after providing the data clock pause command.

[0010] A method of reducing power of a data clock of a memory coupled to a host via a link includes synchronizing the data clock between the host and the memory via the link, triggering a clock tree buffer of the memory based on the data clock to capture write data or output read data, providing a data clock pause command by the host to the memory via the link while the data clock is synchronized between the host and the memory, disabling the triggering by the clock tree buffer based on the data clock in response to the data clock pause command, and triggering the data clock by the host after providing the data clock pause command.

[0011] Another method of reducing power of a data clock of a memory coupled to a host via a link includes providing a data clock synchronization command by the host to the memory via the link and providing a data clock pause command by the host to the memory via the link after synchronizing the data clock. The data clock pause command informs the memory to disable a data clock buffer that is triggered based on the data clock. The method further includes triggering the data clock by the host after providing the data clock pause command.

[0012] Another method of reducing power of a data clock of a memory coupled to a host via a link includes receiving, by the memory from the host, a data clock via the link; synchronizing, by the memory, the data clock with the host; triggering, by a clock tree buffer of the memory, based on the data clock to capture write data or output read data; detecting, by the memory, a data clock suspend command while the data clock is synchronized between the memory and the host; and in response to detecting the data clock suspend command, disabling triggering the clock tree buffer based on the data clock. BRIEF DESCRIPTION OF DRAWINGS

[0013] Various aspects of apparatuses and methods are now presented in the detailed description with reference to the drawing figures, by way of example, and not limitation, in which like reference numerals refer to similar elements throughout

[0014] CLAIM An apparatus including at least one processor, a memory, and a link coupling the at least one processor and the memory is illustrated in accordance with certain aspects of the present disclosure.

[0015] CLAIM A data clock (WCK) synchronization (WCK2CK) command provided by a host to a memory via a link in accordance with certain aspects of the present disclosure is illustrated. CLAIM

[0016] CLAIM A waveform of a data clock (WCK) synchronization with a data suspend (WCK SUSPEND) mode in accordance with certain aspects of the present disclosure is illustrated.

[0017] CLAIM Operation and communication of a data clock (WCK) suspend mode between a host and a memory via a link in accordance with certain aspects of the present disclosure is illustrated. CLAIM

[0018] CLAIM Operation of a data clock synchronization (WCK2CK) suspend mode of a memory controller including an enhanced data clock module in accordance with certain aspects of the present disclosure is illustrated. CLAIM

[0019] A portion of a memory I / O module 160 operating a data clock (WCK) suspend mode in accordance with certain aspects of the present disclosure is illustrated. CLAIM CLAIM A method of reducing power of a data clock (WCK) of a memory coupled to a host via a link 190 in accordance with certain aspects of the present disclosure is illustrated.

[0020] CLAIM CLAIM

[0021] CLAIM ​​​​​FIG. illustrates a method of reducing power of a data clock (WCK) of a memory coupled to a host via a link in accordance with certain aspects of the present disclosure. CLAIM FIG. illustrates a method of reducing power of a data clock (WCK) of a memory coupled to a host via a link in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form, rather than in detail, in order to avoid obscuring the concepts.

[0023] As used herein, the term "coupled to" in various tenses of the verb "couple" can mean that element A is directly connected to element B, or that other elements can be connected between elements A and B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the case of electrical components, the term "coupled to" can also be used herein to mean that elements A and B are electrically connected (as well as any components electrically connected between them) using wires, traces, or other conductive materials. In some examples, the term "coupled to" means that electrical energy is transferred between elements A and B to operate certain intended functions.

[0024] In some examples, the term "electrically connected" means having a current or being configurable to have a current flowing between elements A and B. For example, elements A and B can be connected via a resistor, transistor, or inductor in addition to wires, traces, or other conductive materials and components. Still further, for radio frequency functions, elements A and B can be "electrically connected" via a capacitor.

[0025] The terms "first," "second," "third," etc. are used to conveniently refer to elements, and do not connote any real or substantive meaning. Likewise, names of components / modules can be used for ease of reference, and are not limiting. For example, such non-limiting names can include "clock tree" buffers, "command" decoders, "memory mode" registers, and / or "memory" controllers. Modules and components presented in the present disclosure can be implemented in hardware, software, or a combination of hardware and software.

[0026] The term "bus system" can provide elements coupled to the "bus system" from which information can be exchanged directly or indirectly. In this manner, the "bus system" can encompass a number of physical connections and intervening stages such as buffers, latches, registers, etc. Modules can be implemented in hardware, software, or a combination of hardware and software.

[0027] Methods and apparatuses are presented that include memory with enhanced data clock operation. A data clock between a host and memory can be synchronized for the host to access (e.g., read or write) the memory. Once synchronized, the data clock can be in a constant-on mode or can be free-running to maintain synchronization. Since the memory can include a clock tree that is driven by the data clock, power is consumed by the clock tree when the data clock is running in the constant-on mode even when the host is not accessing the memory.

[0028] Methods and apparatuses are presented that include memory with enhanced data clock operation to allow the memory to gate the clock tree when the data clock is in a constant-on mode and a trigger. The data clock is kept synchronized between the host and the memory. Advantageously, since the data clock is kept synchronized, power is reduced when the memory gates the clock tree without adding cycles for resynchronization.

[0029] Methods and apparatuses are presented in this disclosure through the non-limiting example of a low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, the LPDDR memory operates in accordance with an LPDDR specification promulgated by the Joint Electron Device Engineering Council (JEDEC). Such an LPDDR specification can be LPDDR5.

[0030] CLAIM An apparatus 100 is illustrated that includes a host 110, a memory 150, and a link 190 coupling the host 110 and the memory 150 in accordance with certain aspects of the present disclosure. The apparatus 100 can be, for example, one of the following: a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop, a phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system or an augmented reality (AR) system, etc. The host 110 can include at least one processor 120 coupled to the memory 150 via the link 190 to perform a computing function, such as one of the following: data processing, data communication, graphics display, camera, AR or VR rendering, image processing, etc. For example, the memory 150 can store instructions or data for the at least one processor 120 to perform the aforementioned computing function. The at least one processor 120 can be a set of processing logic or one or more central processing units. For example, the at least one processor 120 can be a central processing unit (CPU) 122, a graphics processing unit (GPU) 123, or a digital signal processor (DSP) 124 configured to implement the aforementioned computing function.

[0031] CLAIMThe host is illustrated as including at least one processor 120 coupled to a memory controller 130 via a bus system 115, which is coupled to a memory 150 via the memory controller 130 and a link 190. The memory can be a LPDDR DRAM (e.g., LPDDR5). The host 110, memory 150, and / or link 190 can operate according to a LPDDR (e.g., LPDDR5) specification. As presented below, the memory 150 can be configured to receive a data clock (e.g., WCK) from the host 110 via the link 190 and synchronize the data clock WCK with the host 110 (e.g., with command and address clocks from the host 110).

[0032] The memory controller 130 can include an enhanced data clock module 132 and a host I / O module 134. The enhanced data clock module 132 can be configured to determine when an enhanced data clock operation, such as a data clock suspend mode, is beneficial and to issue a data clock suspend command to enter the data clock suspend mode. The host I / O module 134 can be configured to drive and receive signals on the link 190. The host I / O module 134 can be referred to as a PHY layer and configured to control electrical characteristics (e.g., voltage levels, phase, delay, frequency, etc.) or receive signals based on electrical characteristics of signaling on the link 190. In some examples, the host I / O module 134 can be configured to output write data to the memory 150 via the link 190 based on the data clock WCK. For example, the host I / O module 134 can be configured to output write data that is synchronized with the data clock WCK. In some examples, the host I / O module 134 can be configured to capture read data from the memory 150 via the link 190 based on the data clock WCK. For example, the host I / O module 134 can be configured such that a buffer that captures (e.g., samples) the read data is clocked or based on the data clock WCK.

[0033] In some examples, link 190 can be a chip-to-chip link or a die-to-die link between host 110 and memory 150, which are located on different dies. In some examples, link 190 can be an intra-die link, with host 110 and memory 150 located on the same die. For example, link 190 can include a plurality of signal lines including signal lines that transmit unidirectional signals from host 110 to memory 150 (e.g., data clock (WCK), command and address (CA), CA clock (CLK), etc.) and signal lines used to transmit bidirectional directional signals (data (DQ), data strobe (DQS), etc.). For example, CA can include CAS signaling / pins, chip select (CS) signaling / pins, and column address (CA) signaling. Link 190 and signaling between host 110 and memory 150 can be in accordance with JEDEC DRAM specifications (e.g., LPDDR5). In some examples, memory 150 can use data clock WCK to capture or sample write data (e.g., received at DQ) for a write operation and to trigger read data (e.g., output at DQ) for a read operation. Thus, memory 150 can utilize data clock WCK to either capture write data or output read data.

[0034] CLAIM FIG. 1 illustrates memory 150 with memory I / O module 160, memory array 162, mode register 170, and command decoder 173 coupled via bus system 172. Memory I / O module 160 can be configured to drive and receive signals on link 190. Memory I / O module 160 can be referred to as a PHY layer and configured to control electrical characteristics (e.g., voltage levels, phase, delay, frequency, etc.) or receive signals based on electrical characteristics of signaling on link 190. For example, memory I / O module 160 can be configured to capture (e.g., sample) write data from host 110 via link 190 based on data clock WCK. In some examples, memory I / O module 160 can be configured to clock a buffer to capture write data clocked based on data clock WCK. In some examples, memory I / O module 160 can be configured to output read data to host 110 via link 190 based on data clock WCK. For example, host I / O module 134 can be configured to synchronize output read data with data clock WCK.

[0035] The memory array 162 can include a plurality of memory cells (e.g., DRAM memory cells) that store data. The at least one processor can read data stored in the memory array 162 and / or write data into the memory array 162 via the link 190. The memory array 162 can be arranged into a plurality of memory banks 180-1 through 180-M. The memory array 162 can be accessed (e.g., read or written) via a READ command or a WRITE command.

[0036] The mode register 170 can include a register that stores a value regarding an operation, signaling feature, and / or information of the memory 150. The mode register 170 can be accessed (e.g., read or written) via a mode register read (MRR) command or a mode register write (MRW) command, which are different from the READ command and the WRITE command (e.g., the MRR command and the MRW command do not access the memory array 162 CLAIM For example, the memory controller 130 can issue a MRW command via the link 190 to set the memory 150 for a read operation or a write operation. In response to the MRW command, the memory 150 stores an operand or OP provided by the MRW command into the mode register 170.

[0037] In some examples, the MRR command and the MRW command do not access the memory array 162. For example, the operand written to or read from the mode register 170 is not written to or read from the memory array 162. The mode register 170 includes a WCK suspend register 171. The WCK suspend register 171 can be configured to store information of a data clock (WCK) suspend command. For example, the WCK suspend register 171 can be configured to store a value that indicates whether the memory 150 supports or enables an enhanced data clock WCK operation such as a data clock (WCK) suspend command.

[0038] For a write operation, the at least one processor 120 can issue a write request to the memory controller 130 via the bus system 115. The memory controller 130 can issue a WRITE command to the memory 150 via the CA and CLK of the link 190. Write data is provided by the memory controller 130 via the DQ of the link 190, which is clocked by the data clock WCK. In response, the memory 150 stores the write data into the memory array 162 addressed by the WRITE command.

[0039] For a read operation, the at least one processor 120 can issue a read request to the memory controller 130 via the bus system 115. The memory controller 130 can issue a READ command to the memory 150 via the CA (e.g., clock CLK, address, command) of the link 190. In response, the memory 150 outputs data stored in the memory array 162 addressed by the READ command to the at least one processor 120. The data can be output via the DQ of the link 190, which is clocked by the data clock WCK (and / or RDQS). The memory 150 (e.g., memory I / O module 160) can receive the data clock WCK from the host 110 and use an internal clock tree to drive and buffer the internal data clock WCK to clock the DQ.

[0040] The data clock WCK can operate at a different frequency than the CA clock CLK. For example, according to LPDDR5, the data clock WCK can operate at twice or four times the CLK frequency. The memory 150 can use a frequency divider to match the frequency of the WCK clock tree to the CLK. This function can require synchronization of the state of the CA clock CLK with the internal WCK clock tree. This process can be referred to as WCK2CK synchronization (e.g., in the LPDDR5 specification) and can require several synchronization cycles.

[0041] The host 110 (e.g., memory controller 130) can initiate WCK2CK synchronization via the link 190 by issuing a WCK2CK SYNC command. The WCK2CK SYNC command can be a CAS command. For example, a CAS signal that triggers the command and address (CA) prior to a read command or a write command. For example, the read command or the write command can immediately follow the CAS command of the WCK2CK SYNC command. In response, the host 110 and the memory 150 engage in a synchronization cycle of the data clock WCK timing (e.g., triggering).

[0042] Having established synchronization via WCK2CK synchronization, the data clock WCK can be left on (e.g., free running) to maintain synchronization. As long as the data clock WCK is timing (e.g., triggering), the data clock WCK remains synchronized between the host 110 and the memory 150. The WCK2CK synchronization can exit by the memory 150 receiving a command for a power down, self-refresh power down, deep sleep command, or reset. This on mode of the data clock WCK improves performance since subsequent read commands and write commands do not require re-synchronization. However, even when the memory 150 is idle (e.g., not reading or writing), the memory 150 continues to draw current caused by the triggering of the internal WCK clock tree as the data clock WCK triggers.

[0043] Command decoder 173 can be configured to decode various commands provided by host 110 (e.g., memory controller 130) via link 190. For example, command decoder 173 can be configured to decode read commands, write commands, and the various WCK2CK commands introduced above.

[0044] CLAIM FIGS. 210 and 220 illustrate a data clock synchronization (WCK2CK SYNC) command provided by host 110 to memory 150 via link 190 in accordance with certain aspects of the present disclosure. CLAIM FIGS. 210 and 220 illustrate a data clock synchronization (WCK2CK SYNC) command provided by host 110 to memory 150 via link 190 in accordance with certain aspects of the present disclosure. CLAIM FIGS. 210 and 220 include a graph 210 of a WCK2CK SYNC command issued as a CAS command and a graph 220 of a mode of a (WCK2CK SYNC) CAS command. Graph 210 illustrates that a (WCK2CK SYNC) CAS command can operate on any bank configuration. At a clock CK rising edge, CS pin is high, and the operand of the WCK2CK SYNC command is provided at addresses CA0 to CA6. At a clock CK falling edge, additional operands are input. The operands (e.g., variables, fields, or values indicative of certain aspects of the WCK2CK SYNC command) can include DC0 to DC3, WS_WR, WS_RD, WS_FS, WRX, WXS, B3 as provided by the LPDDR5 specification. For example, WS_WR at a logic one can indicate a write command immediately following the WCK2CK SYNC command. A WS_RD at a logic one can indicate a read command immediately following the WCK2CK SYNC command. WS_FS can indicate a fast synchronization. WRX and WXS can indicate a write X function (e.g., WRX and / or WXS can be operands of a write X function). B3 can indicate a read burst start address.

[0045] Figure 220 illustrates that the mode for a (WCK2CK SYNC) CAS command can include WCK2CK SYNC for WRITE (e.g., WS_WR is a logic one), WCK2CK SYNC for READ (e.g., WS_RD is a logic one), FAST WCK2CK SYNC (e.g., WS_FS is a logic one), and WCK2CK SYNC OFF (a command to end WCK synchronization and turn off the internal WCK clock tree in memory 150). The (WCK2CK SYNC) CAS command is also enhanced with a data clock suspend (WCK SUSPEND mode). For example, the (WCK2CK SYNC) CAS command can enter a WCK SUSPEND mode where WS_WR is a logic one, WS_RD is a logic zero, and WS_FS is a logic one. For ease of reference, a WCK2CK SYNC command with this WCK SUSPEND mode can be referred to as a data clock (WCK) suspend command. Even though the data clock WCK continues to clock (e.g., tick), the data clock (WCK) suspend command signals to memory 150 to turn off at least one internal WCK clock tree to memory 150. In this way, the at least one internal WCK clock tree stops ticking and power consumption is saved while maintaining WCK synchronization. After the WCK SUSPEND mode, no new WCK synchronization is needed to perform a read operation or a write operation.

[0046] For LPDDR5 dual bank configurations, memory controller 130 can be configured to use the LPDDR5 WCK2CK SYNC broadcast feature to enable enhanced data clock (WCK) operations. For example, CAS-WCK SUS is broadcast to both banks (bank 0 and 1) to improve command and address (CA) bus efficiency.

[0047] In some examples, mode register 170 CLAIM may include a field to indicate support or enablement of a data suspend (WCK SUSPEND) mode. See, e.g., WCK Suspend register 171 in CLAIM Host 110 (e.g., memory controller 130) can issue a mode register read (MRR) command via link 190 to read WCK Suspend register 171 within mode register 170 and determine whether memory 150 supports a clock data suspend (WCK SUSPEND) mode based on the value or operand stored in WCK Suspend register 171.

[0048] In some examples, the clock data suspend (WCK SUSPEND) mode can be exited by a subsequent read command or write command. In response to the subsequent read command or write command (while in the clock data suspend mode), the memory 150 can restart the at least one internal WCK clock tree trigger. There is no performance penalty since no additional clock cycles are required to exit the clock data suspend (WCK SUSPEND) mode.

[0049] CLAIM waveforms with WCK SUSPEND mode of WCK synchronization are illustrated. In CLAIM In the example of FIG. 6, a read operation is provided as an example. A write operation can be implemented in a similar manner. At TO (and at T 0_f , falling edge of clock CK), the host 110 (e.g., memory controller 130) issues a WCK2CK SYNC command to the memory 150 via the link 190 with WS_RD as a logical one. In the immediately subsequent clock cycle Tl, the host 110 (e.g., memory controller 130) issues a read command to the memory 150 via the link 190. As a result, the host 110 and the memory 150 enter a data clock WCK synchronization (WCK2CK) cycle. At T b1 , the data clock WCK is synchronized between the host 110 and the memory 150. Subsequently, the host 110 continues to clock (e.g., trigger) the data clock WCK to maintain synchronization. The host 110 (e.g., memory controller 130) can issue additional read commands or write commands to the memory 150 via the link 190 without requiring further data clock WCK synchronization.

[0050] At T d0 (plus T 0_f , falling edge of clock CK), the host 110 (e.g., memory controller 130) issues a clock data suspend (WCK SUSPEND) command (which specifies the WCK SUSPEND mode) to the memory 150 via the link 190 to enter the WCK SUSPEND mode. In response, the memory 150 can stop the at least one internal WCK clock tree trigger. In this manner, power consumption within the memory 150 is reduced.

[0051] After entering the WCK SUSPEND mode, at T e0 , the host 110 (via the memory controller 130) issues a read command (or write command). In response to the read command / write command, the memory 150 starts the one or more internal WCK clock tree triggers, and the read operation / write operation proceeds normally. There is no change in the read operation / write operation.

[0052] CLAIMThe diagram illustrates the communication between host 110 and memory 150 according to certain aspects of this disclosure. CLAIM The operation and communication of the data clock (WCK) pause mode are handled via link 190. At 402, host 110 (e.g., memory controller 130) provides a mode register read command to memory 150 via link 190. For example, the mode register read command may be directed to read the WCD pause register 171 of mode register 170. At 404, memory 150 provides host 110 via link 190 with information about a data clock (WCK) pause command stored, for example, in the WCD pause register 171 of mode register 170. The information about the data clock (WCK) pause command may indicate whether memory 150 supports the data clock (WCK) pause command.

[0053] At 410, host 110 (e.g., memory controller 130) provides a data clock synchronization (WCK2CK SYNC) command to memory 150 via link 190. See also CLAIM T0 in the example. For example, refer to CLAIM As shown in Figure 220, the WCK2CK SYNC command can be a WCK2CK SYNC for READ, where the operands WS_WR are logic zero, WS_RD are logic one, and WS_FS are logic zero. Host 110 (e.g., memory controller 130) can be configured to use the data clock WCK to output write data (e.g., synchronize with it) and / or capture (e.g., sample) read data. Memory 150 (e.g., memory I / O module 160) can be configured to receive the data clock WCK and is configured to capture (e.g., sample) write data and / or output (e.g., synchronize with it) read data. Memory 150 can include one or more internal data clock trees containing one or more clock tree buffers. The clock tree buffers are configured to be triggered based on the data clock WCK (e.g., triggered using the data clock WCK) to capture write data or output read data. One or more clock tree buffers are configured to drive the internal data clock WCK within memory 150 to perform, for example, capture write data and / or output read data (e.g., synchronize with it).

[0054] At 420, host 110 and memory 150 synchronize (e.g., in WCK2CK synchronization). See T for example. b0 With T b1The synchronization cycle between them. For example, memory controller 130 can be configured to perform a synchronization cycle according to the LPDDR5 specification to synchronize the data clock WCK with memory 150 (e.g., synchronize the CA clock CLK with the internal data clock of memory 150; for example, both are in the same state). At 430, host 110 (e.g., memory controller 130) provides a data clock (WCK) pause command to memory 150 via link 190, and memory 150 enters a data clock (WCK) pause mode. For example, memory 150 can be configured to receive and decode the data clock (WCK) pause command after the data clock (e.g., WCK) is synchronized between host 110 and memory 150 and / or while the data clock (e.g., WCK) is synchronized between host 110 and memory 150. See also CLAIM T d0 The host 110 (e.g., memory controller 130) can be configured to continue triggering the data clock (WCK) after a data clock (WCK) pause command has been provided. In response to the data clock (WCK) pause command, the memory 150 can enter a data clock (WCK) pause mode. For example, the memory 150 can be configured to disable clock tree triggering based on the data clock (WCK) to reduce power consumption.

[0055] At 440, after providing a data clock (WCK) pause command, host 110 (e.g., memory controller 130) provides read (or write) commands to memory 150 via link 190 without performing synchronization between the synchronous host 110 and memory 150. See also CLAIM T e0 In T d0 After providing the data clock (WCK) pause command, T is provided through host 110. e0 The read command is located at [location]. Host 110 and memory 150 are in T [location]. d0 The data clock (WCK) pause command is provided at 430 and at T d0 No synchronization of the data clock WCK is performed between read or write commands (at 440) (no synchronization cycle). No synchronization cycle is required between 430 and 440 because the data clock WCK remains synchronized in a data clock (WCK) synchronization pause mode as long as the host 110 triggers it. In response to a read (or write) command, memory 150 performs a read (or write) operation. Memory 150 can use a clock powered by one or more clock tree buffers triggered based on the data clock WCK to output read data (e.g., synchronized with it) and / or capture write data.

[0056] CLAIM The illustrations depict certain aspects of this disclosure, including...CLAIM of the memory controller 130 of the enhanced data clock module 132 of the operation data clock synchronization (WCK2CK) suspend mode. CLAIM The memory controller 130 is illustrated as including a memory command module 506, a memory access queue module 508, and an enhanced data clock module 132. The enhanced data clock module 132 can include some or all of a WCK suspend support determination module 502 and a WCK suspend usage determination module 504. The modules are coupled by a bus system 510 via which the modules communicate. The bus system 410 is also coupled to the host I / O module 134.

[0057] The memory command module 506 can be configured to provide various commands to the memory 150 via the link 190 (and via the host I / O module 134). For example, the memory command module 506 can be configured to provide a mode register read command (e.g., to obtain information for a data clock suspend command; see 402 of CLAIM ), a data clock (WCK) synchronization command (see 410 of CLAIM ), a data clock (WCK) suspend command (e.g., based on the information for the data clock suspend command and / or while the data clock WCK is synchronized between the host 110 and the memory 150; see 430 of CLAIM ), and / or a read (or write) command to instruct the memory 150 to perform a read (or write) operation (e.g., after providing the data clock suspend command and / or without needing to perform synchronization between the data clock WCK between providing the data clock suspend command and providing the read or write command; see 440 of CLAIM ). The memory access queue module 508 can be, for example, one or more storage elements and can be configured to store one or more memory access commands or instructions.

[0058] The WCK suspend support determination module 502 can be configured to determine whether the memory 150 supports enhanced data clock operations, such as a data clock (WCK) suspend mode. For example, at 402 of CLAIM , the WCK suspend support determination module 502 can receive information for a data clock (WCK) suspend module stored in the mode register 170 (e.g., the WCK suspend register 171) of the memory 150. The information for the data clock (WCK) suspend module can indicate whether the memory 150 supports a data clock suspend command.

[0059] The WCK suspend use determination module 504 can be configured to determine whether to use the data clock (WCK) suspend mode (e.g., whether to provide the data clock (WCK) suspend command) based on the information of the data clock suspend command. In the case where the information of the data clock suspend command indicates that the memory 150 supports the data clock (WCK) suspend mode, the WCK suspend use determination module 504 can look to the memory access queue module 508 to determine whether the power savings from the data clock (WCK) suspend mode are sufficient to justify entering the data clock (WCK) mode. The WCK suspend use determination module 504 can make this determination based on the type, number, timing (e.g., timing differences) of commands or instructions stored in the memory access queue module 508.

[0060] For example, if it is determined that the memory access commands or instructions occur frequently, the power savings in this case can not justify entering the data clock (WCK) suspend mode. Alternatively, if it is determined from the memory access queue module 508 that a next memory access (read or write) is needed after a first time period, the host 110 (e.g., the WCK suspend use determination module 504) can determine that the power savings will justify entering the data clock (WCK) suspend mode and cause the memory command module 506 to provide the data clock (WCK) suspend command (e.g., operands of WS_WR and WS_FS at logic one, operand of WS_RD at logic zero) to the memory 150 via the link 190 (and via the host I / O module 134). In other words, the (next) read command or write command can be provided after the first time period or after the data clock (WCK) suspend command. For example, the host 110 can be configured to provide the (next) read command or write command after the first time period after providing the data clock (WCK) suspend command.

[0061] Alternatively, if the (next) read command or write command is to be provided after a second time period that is longer than the first time period, the WCK suspend use determination module 504 can be configured to determine that exiting the data clock synchronization (WCK2CK) can save more power. In this case, the host 110 (e.g., the WCK suspend use determination module 504) can choose not to cause the memory command module 506 to provide the data clock (WCK) suspend command. The host 110 (e.g., the WCK suspend use determination module 504) can cause the memory command module 506 to provide an instruction to the memory 150 via the link 190 to exit the data clock synchronization (WCK2CK) (e.g., power down). In this way, the host 110 can be configured to provide the (next) read command or write command to the memory 150 via the link 190 between the first time period and the second time period after providing the data clock (WCK) suspend command.

[0062] CLAIM FIG. illustrates portions of a memory I / O module 160 that operates a data clock (WCK) suspend mode in accordance with certain aspects of the present disclosure. CLAIM CLAIM FIG. illustrates that the memory I / O module 160 includes a WCK buffer 602, a CA buffer 606, and a DQ buffer 608 (the memory I / O module 160 can include multiple instances of these buffers). CLAIM FIG. also illustrates that the memory I / O module 160 includes a clock tree 603 and a WCK suspend control module 605.

[0063] The WCK buffer 602 can be an input buffer / receiver configured to receive a data clock WCK and configured to output to the clock tree 603. The clock tree 603 can be configured to be triggered using the received data clock WCK and to output an internal WCK to the DQ buffer 608. The clock tree 603 includes one or more clock tree buffers 604 configured to be triggered (e.g., triggered using the data clock WCK) based on the data clock WCK to capture write data or to output read data. In some examples, the clock tree buffers 604 can be after (e.g., directly or indirectly receive output from) the WCK buffer 602 (i.e., after the memory I / O module 160). The DQ buffer 608 can be an input / output buffer configured to receive write data from DQs of the link 190 and to output read data to the DQs of the link 190. The DQ buffer 608 can be configured to be clocked by (or based on) the internal WCK. For example, the DQ buffer 608 can be configured to capture (e.g., sample) write data based on the internal WCK (which is in turn based on the data clock WCK) and / or configured to output (e.g., synchronize output with the internal WCK) based on the internal WCK (which is in turn based on the data clock WCK).

[0064] The CA buffer 606 can be an input buffer / receiver configured to receive command inputs and address inputs from the link 190 and configured to output to a command decoder 173. The command decoder 173 can be configured to detect, for example, a mode register read command (e.g., to obtain information for a data clock suspend command; see 402 of FIG. 4), a data clock synchronization (e.g., WCK2CK) command (see 410 of FIG. 4), a data clock (WCK) suspend command (e.g., based on information for a data clock (WCK) suspend command and / or while the data clock WCK is synchronized between the host 110 and the memory 150; see 412 of FIG. 4), and / or a data clock (WCK) resume command (e.g., based on information for a data clock (WCK) resume command and / or while the data clock WCK is synchronized between the host 110 and the memory 150; see 414 of FIG. 4). CLAIM CLAIM CLAIM ​​​read (or write) command to instruct the memory 150 to perform a read (or write) operation (e.g., after detecting a data clock (WCK) pause command without performing a synchronization of the data clock WCK between detecting the data clock (WCK) pause command and detecting the read command or the write command; see CLAIM of 440).

[0065] In some examples, the data clock (WCK) pause command informs the memory 150 to disable triggering the clock tree buffer 604 that is configured to trigger based on the data clock WCK. Accordingly, in response to the command decoder 173 detecting the data clock (WCK) pause command, the WCK pause control module 605 disables the clock tree buffer 604 from triggering. Thus, the clock tree buffer 604 is configured to disable triggering based on the data clock WCK in response to the command decoder 173 detecting the data clock (WCK) pause command. In this way, timing power consumed by the clock tree 603 is conserved.

[0066] In some examples, the read command or the write command after the data clock (WCK) pause command informs the memory 150 to enable triggering the clock tree buffer 604. Accordingly, in response to detecting the read command or the write command after the data clock (WCK) pause command, the command decoder 173, the WCK pause control module 605 enables the clock tree buffer 604 to enable triggering based on the data clock WCK. Thus, the clock tree buffer 604 is configured to enable triggering based on the data clock WCK in response to the command decoder 173 detecting the read command or the write command (after the data clock (WCK) pause command). Further, the memory 150 is configured to perform a read (or write) operation (e.g., from CLAIM the memory array 162) in response to the command decoder 173 detecting the read command or the write command. In this way, performance of the memory 150 is not hindered since no additional synchronization period is needed.

[0067] CLAIM illustrates a method of reducing power of a data clock (WCK) of a memory 150 coupled to a host 110 via a link 190 in accordance with certain aspects of the present disclosure. CLAIM illustrates a method of reducing power of a data clock (WCK) of a memory 150 coupled to a host 110 via a link 190 in accordance with certain aspects of the present disclosure. CLAIM The operations of FIG. 8 are implemented by, for example, the apparatus 100 (e.g., the memory 150) as presented in FIG. 1. The arrows indicate certain relationships between the operations, but not necessarily sequential relationships. CLAIM The operations of FIG. 8 are implemented by, for example, the apparatus 100 (e.g., the memory 150) as presented in FIG. 1. The arrows indicate certain relationships between the operations, but not necessarily sequential relationships.

[0068] At 710, the memory receives a data clock from the host via a link. See, for example, CLAIM and CLAIM, the WCK buffer receives a data clock WCK from the host 110 via the link 190. At 720, the data clock is synchronized between the memory and the host. See, e.g., the synchronization period between Tb0 and T CLAIM b1 CLAIM At 730, clock tree buffers of the memory are triggered based on the data clock to capture write data or output read data. See, e.g., the clock tree buffers 604 are triggered based on the data clock WCK to capture write data or output read data.

[0069] At 740, while the data clock is synchronized between the memory and the host, the memory detects a data clock suspend command. See, e.g., the 430 of CLAIM CLAIM The command decoder 173 detects a data clock (WCK) suspend command (e.g., a WCK2CK command with operands WS_WR and WS_FS at logic one and WS_RD at logic zero). At 750, in response to detecting the data clock suspend command, the triggering of the clock tree buffers is disabled based on the data clock. See, e.g., the 605 of CLAIM In response to the command decoder 173 detecting the data clock (WCK) suspend mode, the WCK suspend control module 605 disables the triggering of the clock tree buffers 604.

[0070] At 760, after detecting the data clock suspend command, the memory detects a read command or a write command. See, e.g., the 440 of CLAIM CLAIM The command decoder 173 detects a read (or write) command after detecting the data clock WCK suspend command. At 770, in response to detecting the read command or the write command, the triggering of the clock tree buffers is enabled based on the data clock. See, e.g., the 604 of CLAIM In response to the command decoder 173 detecting the read command or the write command, the clock tree buffers 604 are triggered based on the data clock WCK (enabled by the WCK suspend control module 605).

[0071] At 780, in response to the read command or the write command, the memory performs a read operation or a write operation without performing synchronization of the data clock between detecting the data clock suspend command and detecting the read command or the write command. See, e.g., the 420 of CLAIM ​​​​of 440. The memory 150 performs read operations or write operations in response to read commands or write commands without performing synchronization of the data clock WCK between detecting a data clock (WCK) suspend command and detecting a read command or a write command. Because the host 110 and the memory 150 remain in the WCK2CK mode (data clock synchronization mode), such synchronization is not needed. At 790, the memory mode register stores information of the data clock suspend command. Reference is made to CLAIM The mode register 170 includes a WCK suspend register 171 that stores information about whether the memory 150 supports enhanced data clock WCK operations, such as a data clock (WCK) suspend command.

[0072] CLAIM FIGURE illustrates a method of reducing power of a data clock (WCK) of a memory 150 coupled to a host 110 via a link 190, in accordance with certain aspects of the present disclosure. CLAIM The operations of FIGURE can be implemented (for example, by the host 110) using the apparatus 100 as presented in the present disclosure. The arrows indicate certain relationships between the operations, but not sequential relationships. CLAIM The operations of FIGURE can be implemented (for example, by the host 110) using the apparatus 100 as presented in the present disclosure. The arrows indicate certain relationships between the operations, but not sequential relationships. CLAIM The operations of FIGURE and FIGURE can be combined as presented in the present disclosure. CLAIM The operations of FIGURE and FIGURE can be combined as presented in the present disclosure. CLAIM At 810, a data clock synchronization command is provided by the host to the memory via the link. Reference is made to of 410. Reference is made to

[0073] The memory command module 506 provides a data clock synchronization command (for example, WCK2CK for READ or WCK2CK for WRITE; see CLAIM ) to the memory 150 via the link 190. At 820, after synchronizing the data clock, a data clock suspend command is provided by the host to the memory via the link. The data clock suspend command informs the memory to disable data clock buffers that are triggered based on the data clock. Reference is made to CLAIM of 430. Reference is made to CLAIM After synchronizing the data clock with the memory 150 (for example, 420 of CLAIM ), the memory command module 506 provides a data clock (WCK) suspend command to the memory 150 via the link 190. Reference is made to CLAIM The command decoder 173 detects the data clock (WCK) suspend command and causes the WCK suspend control module 605 to disable the clock tree buffer 604 from being triggered based on the data clock WCK. CLAIM CLAIM

[0074] ​At 830, the data clock is triggered by the host after the data clock suspend command is provided. See, e.g., 440 of FIG. 4. CLAIM At 830, the data clock is triggered by the host after the data clock suspend command is provided. See, e.g., 440 of FIG. 4. d0 The host 110 continues to trigger the data clock WCK after the data clock suspend command is provided at 830. Thus, the host 110 and the memory 150 are still in the data clock synchronization mode (WCK2CK mode), and a subsequent read operation or write operation requires a synchronization period.

[0075] At 840, the host provides a read command or a write command to the memory via the link after the data clock suspend command, without performing synchronization of the data clock between providing the data clock suspend command and providing the read command or the write command. See, e.g., 440 of FIG. 4. CLAIM At 850, the data clock suspend command is provided in response to the information of the data clock suspend command. See, e.g., 430 of FIG. 4. CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM CLAIM At 850, the data clock suspend command is provided in response to the information of the data clock suspend command. See, e.g., 430 of FIG. 4.

[0076] Appendices I, II, and III are attached hereto and incorporated by reference in their entirety.

[0077] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ include any combination of A, B, and / or C, and can include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combination can contain one or more member(s of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing that has been stated herein is intended to cause a withdrawal of any aspect of the present disclosure from the public domain. The word “module,” “mechanism,” “element,” “device,” and the like does not require that all of these components be implemented in software. Rather, some of these components, such as the controller, can be implemented at least partially in hardware, as claimed. Such hardware can also enforce limitations described throughout the present disclosure for controller or other components or wherein functions are described to be performed by a controller. In other words, one or more components of an aspect can be implemented in a circuit, in one or more ASICs, in a circuit chip, and the like, which can perform one or more of the described functions. Therefore, the foregoing description is provided as an illustration of the principles of the various aspects. Other aspects are within the scope of the following claims.

Claims

1. An apparatus for reducing the power of a data clock transmitted to a host memory via a link, comprising: The memory, configured to receive the data clock from the host via the link and synchronize the data clock with the host, further includes: A clock tree buffer is configured to be triggered based on the data clock to capture written data or output read data; A command decoder is configured to detect a data clock pause command while the data clock is synchronized between the host and the memory, wherein the clock tree buffer is configured to disable triggering based on the data clock in response to the command decoder detecting the data clock pause command; and The command decoder is also configured to detect a read command or a write command after the data clock pause command is detected, without performing data clock synchronization between detecting the data clock pause command and detecting the read command or write command, and the clock tree buffer is also configured to initiate a trigger in response to the command decoder detecting the read command or write command based on the data clock.

2. The apparatus of claim 1, wherein the memory is configured to perform a read operation or a write operation in response to the read command or the write command.

3. The apparatus of claim 1, wherein the memory further comprises a memory mode register configured to store information of the data clock pause command.

4. The apparatus of claim 3, wherein the information of the data clock pause command indicates whether the memory supports the data clock pause command.

5. The apparatus of claim 1, wherein the memory is configured to operate according to a low-power double data rate dynamic random access memory specification.

6. The apparatus of claim 5, wherein the data clock pause command comprises operands WS_WR and WS_FS at logic one and WS_RD at logic zero.

7. The apparatus of claim 5, further comprising one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, the augmented reality system including the host, the memory, and the link, wherein the host further includes at least one processor coupled to the memory to perform computing functions of one of the following: the computing system, the mobile computing system, the Internet of Things device, the virtual reality system, or the augmented reality system.

8. The apparatus of claim 7, wherein the memory comprises LPDDR5 memory.

9. The apparatus of claim 7, wherein the clock tree buffer is configured to receive an output directly or indirectly from a data clock buffer configured to receive the data clock.

10. An apparatus for reducing the power consumption of a memory's data clock, comprising: A host computer, coupled to the memory via a link, is configured to synchronize a data clock with the memory and to output write data or capture read data based on the data clock. The host includes a memory controller, which is configured to: While the data clock is synchronized between the host and the memory, a data clock pause command is provided to the memory via the link. This data clock pause command instructs the memory to disable triggering of the clock tree buffer, which is configured to trigger based on the data clock. After providing the data clock pause command, the data clock is triggered. Following the data clock pause command, a read command or write command is provided to the memory via the link, wherein the read command or write command instructs the memory to activate the trigger data clock buffer. The read or write command is provided to access the memory without performing data clock synchronization between providing the data clock pause command and providing the read or write command.

11. The apparatus of claim 10, wherein the memory controller is configured to provide a mode register read command to the memory via the link to obtain information about the data clock pause command, and is configured to provide the data clock pause command based on the information about the data clock pause command.

12. The apparatus of claim 11, wherein the information of the data clock pause command indicates whether the memory supports the data clock pause command.

13. The apparatus of claim 11, wherein the memory controller is configured to operate according to a low-power double data rate dynamic random access memory specification.

14. The apparatus of claim 13, wherein the data clock pause command comprises operands WS_WR and WS_FS at logic one and WS_RD at logic zero.

15. The apparatus of claim 13, further comprising one of the following: a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, the augmented reality system including the host, the memory, and the link, wherein the host further includes at least one processor coupled to the memory to perform computing functions of one of the following: the computing system, the mobile computing system, the Internet of Things device, the virtual reality system, or the augmented reality system.

16. The apparatus of claim 15, wherein the memory comprises LPDDR5 memory.

17. The apparatus of claim 15, wherein the read command or write command is between a first time period and a second time period following the data clock pause command.

18. A method for reducing the power of a data clock signal coupled to a host memory via a link, comprising: Data clock is received from the host via the memory through the link; The data clock is synchronized with the host through the memory; Based on the data clock, the clock tree buffer of the memory is used to trigger the capture of written data or the output of read data; While the data clock is synchronized between the memory and the host, a data clock pause command is detected through the memory. In response to the detection of the data clock pause command, triggering the clock tree buffer based on the data clock is prohibited; After detecting the data clock pause command, the memory detects a read command or a write command. In response to the detection of the read command or write command, a trigger is initiated based on the data clock via the clock tree buffer; as well as In response to the read command or write command, a read operation or write operation is performed through the memory without needing to synchronize the data clock between detecting the data clock pause command and detecting the read command or write command.

19. The method of claim 18, further comprising: The information of the data clock pause command is stored in the memory mode register.

20. The method of claim 19, wherein the information of the data clock pause command indicates whether the memory supports the data clock pause command.

21. The method of claim 18, wherein the memory operates according to a low-power double data rate dynamic random access memory specification.

22. The method of claim 21, wherein the data clock pause command comprises operands WS_WR and WS_FS at logic one and WS_RD at logic zero.

23. The method of claim 22, wherein the link operates according to the LPDDR5 specification.

24. The method of claim 23, wherein the memory comprises LPDDR5 memory.

25. The method of claim 24, wherein the host operates according to the LPDDR5 specification.

26. A method for reducing data clock power of memory coupled to a host via a link, comprising: Synchronize data clocks between the host and the memory via a link; The data clock is triggered via the clock tree buffer of the memory to capture written data or output read data; While the data clock is synchronized between the host and the memory, a data clock pause command is provided to the memory via the link through the host. In response to the data clock pause command, triggering based on the data clock is disabled via the clock tree buffer; After providing the data clock pause command, the data clock is triggered via the host. And after the data clock pause command, a read command or write command is provided to the memory via the link through the host, without performing data clock synchronization between providing the data clock pause command and providing the read command or write command.

27. The method of claim 26, further comprising: In response to the read or write command, the clock tree buffer is triggered via the memory.

28. The method of claim 27, wherein a read operation or a write operation is performed through the memory in response to the read command or the write command.

29. The method of claim 26, further comprising: The host provides a mode register read command to the memory via the link; as well as In response to the mode register read command, information about the data clock pause command is provided to the host via the link through the memory.

30. The method of claim 29, wherein the information of the data clock pause command indicates whether the memory supports the data clock pause command.

31. The method of claim 30, wherein the data clock pause command is provided in response to the information of the data clock pause command.

32. The method of claim 31, wherein the host, the memory, and the link operate according to a low-power double data rate dynamic random access memory specification.

33. The method of claim 32, wherein the data clock pause command comprises operands WS_WR and WS_FS at logic one and WS_RD at logic zero.

34. The method of claim 33, wherein the host operates according to the LPDDR5 specification.

35. A method for reducing the power of a data clock signal coupled to a host memory via a link, comprising: The host provides data clock synchronization commands to the memory via a link. After synchronizing the data clock, a data clock synchronization command is provided to the memory via the link through the host, wherein the data clock pause command instructs the memory to disable the data clock buffer that is triggered based on the data clock; After providing the data clock pause command, the data clock is triggered via the host. as well as Following the data clock pause command, a read command or write command is provided to the memory via the link through the host, without needing to synchronize the data clock between providing the data clock pause command and providing the read command or write command.

36. The method of claim 35, wherein in response to the read command or write command, the memory initiates the data clock buffer.

37. The method of claim 36, wherein the memory performs a read operation or a write operation in response to the read command or write command.

38. The method of claim 35, further comprising: The host provides a mode register read command to the memory via the link to obtain information about the data clock pause command.

39. The method of claim 38, wherein the information of the data clock pause command indicates whether the memory supports the data clock pause command.

40. The method of claim 39, wherein the data clock pause command is provided in response to the information of the data clock pause command.

41. The method of claim 35, wherein the host, the memory, and the link operate according to a low-power double data rate dynamic random access memory specification.

42. The method of claim 35, wherein the data clock pause command comprises operands WS_WR and WS_FS at logic one and WS_RD at logic zero.

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