Semiconductor devices

Abstract

A semiconductor device is provided, comprising: a drift region of a first conductivity type, which is arranged in a semiconductor substrate; a base region of a second conductivity type, which is arranged above the drift region; an accumulation region of the first conductivity type, which is arranged between the base region and the drift region and has a doping concentration higher than that of the drift region; and an electric field relaxation region, which is arranged between the base region and the accumulation region and has a doping concentration lower than a peak of the doping concentration of the accumulation region, wherein a boundary between the electric field relaxation region and the accumulation region is a half-value position of a peak of the accumulation region, and an integrated concentration of the electric field relaxation region is 5E14cm ‑2 Above and 5E15cm ‑2 the following.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device including a reservoir region in a mesa portion between trench portions (for example, see Patent Documents 1 to 3).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2005-347289

[0004] Patent Document 2: Japanese Patent Application Publication No. 2008-205015

[0005] Patent Document 3: Japanese Patent Application Publication No. 2007-311627 Summary of the invention

[0006] Technical issues

[0007] It is desirable to suppress leakage current of a semiconductor device.

[0008] Technical Solution

[0009] In a first aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a drift region of a first conductivity type, which is provided in a semiconductor substrate; a base region of a second conductivity type, which is provided above the drift region; an accumulation region of the first conductivity type, which is provided between the base region and the drift region and has a doping concentration higher than that of the drift region; and an electric field relaxation region, which is provided between the base region and the accumulation region and has a doping concentration lower than a peak of the doping concentration of the accumulation region, wherein a boundary between the electric field relaxation region and the accumulation region is a half-value position of a peak of the accumulation region, and an integrated concentration of the electric field relaxation region is 5E14cm -2 Above and 5E15cm -2 the following.

[0010] The film thickness of the electric field relaxation region may be 0.4 μm or more and 3.0 μm or less.

[0011] The film thickness of the electric field relaxation region may be 1.0 μm or more and 1.8 μm or less.

[0012] The film thickness of the electric field relaxation region may be 1.5 μm or more and 2.0 μm or less.

[0013] The film thickness of the electric field relaxation region may be greater than the film thickness of the storage region.

[0014] The electric field relaxation region may include a region with the same doping concentration as that of the drift region.

[0015] The electric field relaxation region may have a peak smaller than a half value of a peak of the accumulation region.

[0016] The doping concentration of the accumulation region may be lower than the peak of the doping concentration of the base region.

[0017] The doping concentration of the accumulation region can be 1E16cm -3 Above and 4E16cm -3 the following.

[0018] The film thickness of the reservoir region may be 0.5 μm or more and 1.5 μm or less.

[0019] It should be noted that the above summary of the invention does not list all the features of the present invention, and sub-combinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A An example of a cross section of the semiconductor device 100 according to the embodiment is shown.

[0021] Figure 1B An example of a top view of the semiconductor device 100 according to the embodiment is shown.

[0022] Figure 1C An example of a doping concentration distribution in the depth direction of the semiconductor device 100 according to the embodiment is shown.

[0023] Figure 2A An example of a cross section of a semiconductor device 500 according to a comparative example is shown.

[0024] Figure 2B An example of a doping concentration distribution in the depth direction of a semiconductor device 500 according to a comparative example is shown.

[0025] Figure 2C The actually measured waveform of the current Ices of the semiconductor device 500 of the comparative example is shown.

[0026] Figure 2D A simulation waveform of the current Ices of the semiconductor device 500 according to the comparative example is shown.

[0027] Figure 3A An example of the doping concentration distribution of the electric field relaxation region 17 is shown.

[0028] Figure 3B The change of the current Ices corresponding to the film thickness W of the electric field relaxation region 17 is shown.

[0029] Figure 4A The relationship between the peak concentration of the accumulation region 16 and the film thickness W of the electric field relaxation region 17 is shown.

[0030] Figure 4B The relationship between the peak concentration in the accumulation region 16 and the integrated concentration in the electric field relaxation region 17 is shown.

[0031] Figure 4CThe relationship among the peak concentration in the accumulation region 16 , the film thickness W in the electric field relaxation region 17 , and the integrated concentration in the electric field relaxation region 17 is shown.

[0032] Figure 5 An example of an enlarged cross-sectional view of the semiconductor device 100 according to the embodiment is shown.

[0033] Figure 6 Another example of the doping concentration distribution of the semiconductor device 100 according to the embodiment is shown.

[0034] Explanation of symbols

[0035] 10: semiconductor substrate, 12: emitter region, 14: base region, 15: contact region, 16: storage region, 17: electric field relaxation region, 18: drift region, 20: buffer region, 21: front surface, 22: collector region, 23: back surface, 24: collector electrode, 26: interlayer insulating film, 30: dummy groove portion, 32: dummy insulating film, 34: dummy conductive portion, 40: gate groove portion, 42: gate insulating film, 44: gate conductive portion, 52: emitter electrode, 54: contact hole, 60: mesa portion, 100: semiconductor device, 500: semiconductor device, 512: emitter region, 514: base region, 516: storage region, 518: drift region DETAILED DESCRIPTION

[0036] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0037] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". In addition, one of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity.

[0038] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the upper surface of a semiconductor substrate is referred to as an XY plane, and a depth direction of the semiconductor substrate is referred to as a Z axis.

[0039] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities.

[0040] In this specification, the doping concentration refers to the concentration of the impurity obtained by donorization or acceptorization. In this specification, the concentration difference between the donor and the acceptor is sometimes set as the doping concentration. In addition, sometimes the peak value of the doping concentration distribution in the doping region is set as the doping concentration in the doping region.

[0041] In this specification, in the layer and / or region with the prefix N or P, it means that electrons or holes are the majority carriers, respectively. In addition, + and - marked in N and / or P respectively indicate that the doping concentration is higher and lower than the doping concentration of the layer and / or region not marked with + and -.

[0042] Figure 1A An example of a cross section of the semiconductor device 100 according to the embodiment is shown. Figure 1A The components shown are formed to extend in a direction perpendicular to the paper surface of the drawing. The semiconductor device 100 reduces the on-resistance and the on-voltage by conductivity modulation. As an example, the semiconductor device 100 is a semiconductor chip having an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0043] The interlayer insulating film 26 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 26 is, for example, a silicate glass film (PSG film) to which phosphorus is added or a silicate glass film (BPSG film) to which phosphorus and boron are added.

[0044] The contact hole 54 is an opening provided in the interlayer insulating film 26. The contact hole 54 is provided to expose the front surface 21 of the semiconductor substrate 10 and connect the emitter electrode 52 to the front surface 21. The contact hole 54 of this example is provided at the center of the mesa portion 60, but is not limited thereto.

[0045] The emitter electrode 52 is provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 of this example is formed on the upper surface of the interlayer insulating film 26. The emitter electrode 52 may be in contact with a portion of the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 is also formed in the contact hole 54 and in contact with the emitter region 12. In addition, the interlayer insulating film 26 insulates the emitter electrode 52 from the gate conductive portion 44.

[0046] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as a metal. For example, the emitter electrode 52 and the collector electrode 24 can be formed of a conductive material containing aluminum. In addition, in the emitter electrode 52 and the collector electrode 24, the portion formed in a fine area such as the opening of the insulating film can also be formed of a conductive material containing tungsten.

[0047] The semiconductor substrate 10 may be a silicon substrate or a compound semiconductor substrate. The semiconductor substrate 10 may also be a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0048] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0049] The emitter region 12 is a region of the first conductivity type provided on the front surface 21 side of the semiconductor substrate 10. As an example, the emitter region 12 is of N+ type. The emitter region 12 is provided to contact the dummy groove portion 30 or the gate groove portion 40. The emitter region 12 is provided in the mesa portion 60 between adjacent groove portions, extending from one groove portion to another groove portion.

[0050] The base region 14 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. As an example, the base region 14 is of P-type. The base region 14 is provided below the emitter region 12. In addition, the base region 14 is provided above the drift region 18.

[0051] The accumulation region 16 is a region of the first conductivity type disposed between the base region 14 and the drift region 18. As an example, the accumulation region 16 of this example is of N type. The accumulation region 16 is disposed in contact with the dummy groove portion 30 or the gate groove portion 40. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The accumulation region 16 suppresses holes injected into the drift region 18 from the back side 23 of the semiconductor substrate 10 from crossing to the front side 21 of the semiconductor substrate 10, thereby increasing the carrier density on the upper surface side of the drift region 18. In this way, the accumulation region 16 modulates the conductivity of the semiconductor device 100 through the carrier injection enhancement effect (IE effect). As a result, the on-resistance of the semiconductor device 100 is reduced, and the on-voltage can be reduced.

[0052] The electric field alleviation region 17 is provided between the base region 14 and the accumulation region 16. The upper end of the electric field alleviation region 17 is the junction position between the base region 14 and the electric field alleviation region 17. The lower end of the electric field alleviation region 17 is the half-value position of the peak of the doping concentration with respect to the accumulation region 16. As an example, the electric field alleviation region 17 is N-type.

[0053] The doping concentration of the electric field relaxation region 17 is lower than the peak doping concentration of the accumulation region 16. The doping concentration of the electric field relaxation region 17 may be lower than the peak doping concentration of the base region 14. In the electric field relaxation region 17, the depletion layer easily extends, and the concentration of the electric field can be relaxed.

[0054] In one example, the electric field relaxation region 17 has a region having the same doping concentration as the drift region 18. The electric field relaxation region 17 has a region having the same doping concentration as the drift region 18 with a predetermined film thickness. For example, the electric field relaxation region 17 has a region having the same doping concentration as the drift region 18 with a film thickness of 0.5 μm or more.

[0055] The film thickness W of the electric field relaxation region 17 is set to be able to suppress the leakage current between CE when a high voltage is applied. The leakage current between CE refers to the leakage current of the current Ices flowing between the collector electrode 24 and the emitter electrode 52. In one example, the film thickness W of the electric field relaxation region 17 is set to relax the electric field between the storage region 16 and the base region 14 and suppress the leakage current.

[0056] For example, the film thickness W of the electric field buffering region 17 is greater than the film thickness of the accumulation region 16. By increasing the film thickness of the electric field buffering region 17, it is easy to suppress leakage current. In addition, the film thickness W of the electric field buffering region 17 may be less than the film thickness of the accumulation region 16. The film thickness W of the electric field buffering region 17 may be greater than 0.4 μm and less than 3.0 μm. The film thickness W of the electric field buffering region 17 may be greater than 1.0 μm and less than 1.8 μm. The film thickness W of the electric field buffering region 17 may be greater than 1.5 μm and less than 2.0 μm.

[0057] The buffer zone 20 is a region of the first conductivity type disposed below the drift region 18. As an example, the buffer zone 20 of this example is of N+ type. The doping concentration of the buffer zone 20 is higher than the doping concentration of the drift region 18. The buffer zone 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region of the first conductivity type.

[0058] The dummy groove portions 30 and the gate groove portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy groove portions 30 and the gate groove portions 40 extend along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction. The dummy groove portions 30 and the gate groove portions 40 extend from the front surface 21 side of the semiconductor substrate 10 through the emitter region 12, the base region 14, the electric field relaxation region 17, and the storage region 16 to the drift region 18.

[0059] The gate trench portion 40 is set to a gate potential. The gate trench portion 40 includes a gate trench formed on the front surface 21 , a gate insulating film 42 , and a gate conductive portion 44 .

[0060] The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0061] The gate conductive portion 44 is formed inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate conductive portion 44 is covered by the interlayer insulating film 26 on the front side 21. The gate conductive portion 44 includes at least a region opposite to the adjacent base region 14. If a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface in contact with the gate groove portion 40 in the base region 14. The gate conductive portion 44 of this example has a portion protruding toward the back side 23 of the semiconductor substrate 10 further than the lower surface of the storage region 16.

[0062] The dummy trench portion 30 is set to an emitter potential. The dummy trench portion 30 includes a dummy trench formed on the front surface 21 side, a dummy insulating film 32 , and a dummy conductive portion 34 .

[0063] The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy insulating film 32 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the dummy trench. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10 .

[0064] The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 is covered by the interlayer insulating film 26 on the front surface 21.

[0065] The semiconductor device 100 of this example has a structure in which one gate groove portion 40 and two dummy groove portions 30 are repeatedly arranged in this order. The arrangement structure of the groove portion is not limited to this example. A plurality of gate groove portions 40 may also be arranged continuously. It may also be arranged so that one dummy groove portion 30 is sandwiched between two gate groove portions 40. The semiconductor device 100 may also have only a gate groove portion 40 as a groove portion.

[0066] The mesa portion 60 is a region sandwiched between two trench portions of the semiconductor substrate 10. The emitter region 12, the base region 14, the electric field relaxation region 17, and the accumulation region 16 are provided in the mesa portion 60.

[0067] Figure 1B An example of a top view of the semiconductor device 100 according to the embodiment is shown. Figure 1B The B-B' cross section is equivalent to Figure 1A The cross-sectional view shown in .

[0068] The contact region 15 is a region of the second conductivity type having a higher doping concentration than the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is provided on the front surface 21 of the mesa portion 60. The contact region 15 of this example is in contact with the dummy trench portion 30 and the gate trench portion 40.

[0069] In the mesa portion 60, the emitter region 12 and the contact region 15 are provided on the front surface 21 of the semiconductor substrate 10. The emitter region 12 and the contact region 15 are provided to contact two groove portions, respectively, and the two groove portions are two groove portions adjacent to the mesa portion 60. The emitter region 12 and the contact region 15 are provided alternately in the extension direction. The emitter region 12 and the contact region 15 are provided at the same interval in the extension direction. However, the width of the emitter region 12 in the extension direction may be larger or smaller than the width of the contact region 15.

[0070] The contact hole 54 is provided so as to extend in the extending direction. The contact hole 54 is formed above each region of the emitter region 12 and the contact region 15. It should be noted that the contact hole 54 and the interlayer insulating film 26 are omitted for the sake of simplicity of the drawings.

[0071] Figure 1C FIG. 1 shows an example of a doping concentration distribution in the depth direction of the semiconductor device 100 of the embodiment. The vertical axis shows the doping concentration (cm -3 ), and the horizontal axis represents the depth (μm) from the front surface 21 of the semiconductor substrate 10.

[0072] The doping concentration distribution of this example shows Figure 1A The doping concentration distribution of the A-A' section. That is, Figure 1A The AA′ cross section shows the doping concentration distribution in the emitter region 12 , the base region 14 , the electric field relaxation region 17 , the accumulation region 16 , and the drift region 18 . Depths D1 to D4 show the depths from the front surface 21 of the semiconductor substrate 10 .

[0073] The depth D1 shows the depth of the lower end of the emitter region 12 with respect to the front surface 21 of the semiconductor substrate 10. That is, the depth D1 corresponds to the boundary position between the emitter region 12 and the base region 14. The depth D1 is the depth of the junction of the doping concentration distribution between the N-type emitter region 12 and the P-type base region 14. For example, the depth D1 is set within a range of 0.3 μm or more and 0.8 μm or less from the front surface 21 of the semiconductor substrate 10.

[0074] The doping concentration of the emitter region 12 shows a maximum value near the front surface 21 of the semiconductor substrate 10 (ie, near a depth of 0 μm). The maximum value of the doping concentration of the emitter region 12 may be 1E20 cm -3 It should be noted that E refers to the power of 10, for example 1E20cm -3 It means 1×10 20 cm -3 .

[0075] The depth D2 shows the depth of the lower end of the base region 14 based on the front surface 21 of the semiconductor substrate 10. The depth D2 corresponds to the boundary position between the base region 14 and the electric field relaxation region 17. The depth D2 is the depth of the junction of the doping concentration distribution between the P-type base region 14 and the N-type electric field relaxation region 17. For example, the depth D2 is set within a range of 1.5 μm or more and 2.5 μm or less from the front surface 21 of the semiconductor substrate 10.

[0076] The peak P1 of the doping concentration of the base region 14 is 5E16 cm -3 Above and 5E17cm -3 In the present embodiment, the peak P1 of the doping concentration of the base region 14 is set within a range of 0.8 μm or more and 1.8 μm or less from the front surface 21 of the semiconductor substrate 10 .

[0077] The depth D3 shows the depth of the lower end of the electric field relaxation region 17 with respect to the front surface 21 of the semiconductor substrate 10. The depth D3 corresponds to the boundary position between the electric field relaxation region 17 and the accumulation region 16. The depth D3 of this example is determined as the boundary position between the accumulation region 16 and the electric field relaxation region 17 at the position of the half value Ph of the peak P2 of the accumulation region 16 in the doping concentration distribution.

[0078] Here, the doping concentration of the electric field relaxation region 17 is lower than the peak P1 of the doping concentration of the base region 14. In addition, the doping concentration of the electric field relaxation region 17 is lower than the peak P2 of the doping concentration of the accumulation region 16. The electric field relaxation region 17 may have a region having the same doping concentration as the drift region 18. In this case, the electric field relaxation region 17 can be set as a region where the drift region 18 remains, so there is no need to perform additional ion implantation for the electric field relaxation region 17. Therefore, the manufacturing cost of the semiconductor device 100 is reduced.

[0079] The depth D4 shows the depth of the lower end of the accumulation region 16 with respect to the front surface 21 of the semiconductor substrate 10. The depth D4 corresponds to the depth at which the concentration becomes the same as the concentration of the drift region 18. For example, the depth D4 is configured within a range of 2.5 μm or more and 5.0 μm or less from the front surface 21 of the semiconductor substrate 10. In the present embodiment, the drift region 18 has a substantially constant doping concentration. In the present embodiment, the doping concentration of the drift region 18 is 5E13 cm -3 Above and 5E14cm -3 the following.

[0080] The doping concentration of the accumulation region 16 is lower than the peak P1 of the doping concentration of the base region 14. For example, the peak P2 of the doping concentration of the accumulation region 16 is 1E16 cm -3 Above and 4E16cm -3In the present embodiment, the depth position at which the doping concentration of the accumulation region 16 becomes maximum is arranged within a range of 2.0 μm or more and 4.5 μm or less from the front surface 21 of the semiconductor substrate 10 .

[0081] Figure 2A An example of a cross section of a semiconductor device 500 of a comparative example is shown. The semiconductor device 500 of this example is different from the semiconductor device 100 of the embodiment in that it does not have an electric field relaxation region 17. The semiconductor device 500 has an emitter region 512, a base region 514, an accumulation region 516, and a drift region 518 in the mesa portion 60. In the semiconductor device 500, the base region 514 and the accumulation region 516 are arranged adjacent to each other. Since the semiconductor device 500 does not have the electric field relaxation region 17, the electric field is concentrated between the base region 514 and the accumulation region 516.

[0082] The semiconductor device 500 can improve the IE effect by using the accumulation region 516, and increase the amount of carriers accumulated in the steady state to reduce the on-state voltage. The higher the concentration of the accumulation region 516, the higher the IE effect can be. Therefore, it is preferred to design it with a high concentration. However, if the peak of the doping concentration of the accumulation region 516 reaches 1E16cm -3 When the concentration is high in the above manner, the leakage current between CE may increase instantaneously.

[0083] Figure 2B An example of the doping concentration distribution in the depth direction of the semiconductor device 500 of the comparative example is shown. The doping concentration distribution of this example is Figure 2A Doping concentration distribution of the A-A' cross section.

[0084] The depth D1' shows the depth of the lower end of the emitter region 512 based on the front surface 21 of the semiconductor substrate 10. The depth D1' corresponds to the boundary position between the emitter region 512 and the base region 514. The depth D1' is the depth of the junction of the doping concentration distribution between the N-type emitter region 512 and the P-type base region 514.

[0085] The depth D2' shows the depth of the lower end of the base region 514 with respect to the front surface 21 of the semiconductor substrate 10. The depth D2' corresponds to the boundary position between the base region 514 and the accumulation region 516. The depth D2' is the depth of the junction of the doping concentration distribution between the P-type base region 514 and the N-type accumulation region 516.

[0086] The depth D3′ shows the depth of the lower end of the accumulation region 516 with respect to the front surface 21 of the semiconductor substrate 10. The depth D3′ corresponds to the depth at which the concentration becomes the same as that of the drift region 518. The peak P2′ of the doping concentration of the accumulation region 516 is 1E16 cm -3In the semiconductor device 500 , the peak P2 ′ of the doping concentration of the accumulation region 516 is lower than the peak P1 ′ of the doping concentration of the base region 514 .

[0087] Thus, at the interface where the P-type base region 514 and the N-type accumulation region 516 are in direct contact, the carrier density is increased by the accumulation region 516, and the electric field is easily concentrated. If the electric field is concentrated, leakage current between CE is easily generated.

[0088] Figure 2C The measured waveform of the current Ices of the semiconductor device 500 of the comparative example is shown. The vertical axis shows the voltage Vce (V) between CEs and the current Ices (A) between CEs, and the horizontal axis shows time (sec). In this example, the change of the current Ices when the voltage Vce is scanned at a predetermined scan speed is shown.

[0089] The voltage Vce is swept from 0V to 1330V at a rate of dv / dt = 0.4 kV / ms. If the voltage Vce rises, the current Ices rises instantaneously at a predetermined voltage. For example, the instantaneous increase in the leakage current between CE is due to the peak concentration of the accumulation region 516 being 1E16 cm -3 The concentration is above 100, and the electric field is concentrated at the boundary between the base region 514 and the storage region 516. The voltage Vce at which the leakage current increases is sometimes related to the voltage at which the depletion layer reaches the buffer region 20. Since the depletion layer reaches the buffer region 20, the electric field is not further applied in the depth direction, and the electric field on the front surface 21 side becomes high sharply, thereby increasing the leakage current. Here, the peak concentration shows the concentration of the peak of the doping concentration.

[0090] Figure 2D FIG. 5 shows a simulated waveform of the current Ices of the semiconductor device 500 of the comparative example. The vertical axis shows the voltage Vce (V) between CEs and the current Ices (A) between CEs, and the horizontal axis shows time (sec). Figure 2C The voltage Vce is scanned under the same scanning conditions as Figure 2C Similarly to the case of , it was confirmed that the current Ices increases instantaneously with the increase in the voltage Vce.

[0091] On the other hand, the semiconductor device 100 can suppress the increase of leakage current between CEs generated when the accumulation region 16 is highly concentrated by providing the electric field relaxation region 17, and improve the IE effect. As a result, the loss caused by the leakage current between CEs is reduced. However, if the film thickness W of the electric field relaxation region 17 is set too large, the IE effect is reduced. Therefore, the film thickness W of the electric field relaxation region 17 is appropriately selected according to the peak concentration of the accumulation region 16.

[0092] Figure 3AAn example of the doping concentration distribution of the electric field relaxation region 17 is shown. The electric field relaxation region 17 of this example is changed to four different doping concentration distributions A1 to A4 by changing the conditions. In addition, for comparison, the doping concentration distribution A0 of the semiconductor device 500 is also shown.

[0093] Doping concentration profile A0 shows the doping concentration profile of the semiconductor device 500 without the electric field relaxation region 17. In this example, the base region 514 is in contact with the accumulation region 516. The peak concentration of the accumulation region 516 is lower than the peak concentration of the base region 514.

[0094] Doping concentration distributions A1 to A4 show the doping concentration distribution of the semiconductor device 100 having the electric field relaxation region 17 of a predetermined film thickness. Doping concentration distributions A1 to A4 show the distribution of doping concentration when the film thickness W of the electric field relaxation region 17 is increased in sequence. By increasing the film thickness W of the electric field relaxation region 17, the peak concentration of the accumulation region 16 can be increased. By increasing the peak concentration of the accumulation region 16, the IE effect can be improved and the on-voltage can be reduced.

[0095] Figure 3B The change of the current Ices corresponding to the film thickness W of the electric field relaxation region 17 is shown. In this example, the film thickness W of the electric field relaxation region 17 is changed to 0μm, 0.3μm, 0.6μm or 0.9μm. As the film thickness W of the electric field relaxation region 17 becomes larger, the depletion layer is more likely to expand in the depth direction, and the electric field relaxation effect is greater. Therefore, as the film thickness W of the electric field relaxation region 17 becomes larger, the rise of the current Ices is suppressed.

[0096] Figure 4A The relationship between the peak concentration in the accumulation region 16 and the film thickness W in the electric field relaxation region 17 is shown. The vertical axis shows the film thickness W (μm) in the electric field relaxation region 17, and the horizontal axis shows the peak concentration in the accumulation region 16 (cm -3 ) In this example, the film thickness W of the electric field relaxation region 17 required for relaxing the electric field corresponding to the peak concentration of the accumulation region 16 is shown.

[0097] The film thickness W of the electric field relaxation region 17 required for suppressing leakage current varies according to the peak concentration of the accumulation region 16. In the electric field relaxation region 17, the depletion layer is easy to extend and the electric field can be relaxed. The thicker the film thickness W of the electric field relaxation region 17, the more the electric field is relaxed, and the higher the effect of suppressing leakage current.

[0098] The higher the peak concentration of the accumulation region 16, the harder it is for the depletion layer to extend, so the electric field is easily concentrated. The lower the doping concentration of the accumulation region 16, the easier it is for the depletion layer to extend, and the easier it is for the electric field to disperse. Therefore, the higher the peak concentration of the accumulation region 16, the greater the film thickness W of the electric field relaxation region 17 required to suppress leakage current.

[0099] For example, the doping concentration of the accumulation region 16 is 1E16 cm -3 Above and 4E16cm -3 Below. The doping concentration in the accumulation region 16 is 1E16cm -3 In the case of , the film thickness W of the electric field relaxation region 17 is 0.4 μm. The doping concentration in the accumulation region 16 is 2.5E16 cm -3 In the case of , the film thickness W of the electric field relaxation region 17 is 1.0 μm. The doping concentration in the accumulation region 16 is 3E16 cm -3 In the case of , the film thickness W of the electric field relaxation region 17 is 1.3 μm. The doping concentration in the accumulation region 16 is 4E16 cm -3 In the case of , the film thickness W of the electric field relaxation region 17 is 1.8 μm.

[0100] If the film thickness W of the electric field buffering region 17 is too large, the accumulation region 16 may exist at a deep position at the bottom of the trench, resulting in a decrease in withstand voltage. Therefore, by setting the film thickness W of the electric field buffering region 17 to 3.0 μm or less, the decrease in withstand voltage can be suppressed. It should be noted that the film thickness W of the electric field buffering region 17 may be larger than the value in this example.

[0101] Figure 4B The vertical axis shows the relationship between the peak concentration in the accumulation region 16 and the integrated concentration in the electric field relaxation region 17. -2 ), the horizontal axis shows the peak concentration (cm -3 The integrated concentration of the electric field relaxation region 17 indicates a value calculated by integrating the doping concentration distribution within the range of the film thickness W of the electric field relaxation region 17 .

[0102] The integrated concentration of the electric field relaxation region 17 is 5E14 cm -2 Above and 5E15cm -2 By appropriately setting the integrated concentration of the electric field relaxation region 17 , the electric field between the base region 14 and the electric field relaxation region 17 can be relaxed, and leakage current can be suppressed. The leakage current is the leakage current of the current Ices flowing between the collector electrode 24 and the emitter electrode 52 .

[0103] Figure 4C The relationship among the peak concentration in the accumulation region 16 , the film thickness W in the electric field relaxation region 17 , and the integrated concentration in the electric field relaxation region 17 is shown.

[0104] The film thickness W of the electric field relaxation region 17 is set to suppress leakage current between CE when high voltage is applied. In one example, the film thickness W of the electric field relaxation region 17 is set to relax the electric field between the storage region 16 and the base region 14 and suppress leakage current.

[0105] For example, the film thickness W of the electric field relaxation zone 17 is greater than the film thickness of the accumulation zone 16. By increasing the film thickness of the electric field relaxation zone 17, it is easy to suppress leakage current. In addition, the film thickness W of the electric field relaxation zone 17 can be less than the film thickness of the accumulation zone 16. The film thickness W of the electric field relaxation zone 17 can be greater than 0.4 μm and less than 3.0 μm. The film thickness W of the electric field relaxation zone 17 can be greater than 1.0 μm and less than 1.8 μm. The film thickness W of the electric field relaxation zone 17 can be greater than 1.5 μm and less than 2.0 μm. Furthermore, the integrated concentration of the electric field relaxation zone 17 can be 5E14 cm -2 Above and 5E15cm -2 the following.

[0106] Figure 5 An example of an enlarged view of a cross-sectional view of the semiconductor device 100 according to the embodiment is shown. This figure is an enlarged view of the mesa portion 60 sandwiched between the adjacent dummy trench portions 30 and gate trench portions 40 .

[0107] The width W1 indicates the distance between the center of the dummy trench portion 30 and the center of the gate trench portion 40 . That is, the width W1 is the distance between the trench portions. The width W2 indicates the width of the mesa portion 60 .

[0108] The length L1 is the film thickness of the emitter region 12. The length L1 corresponds to the film thickness from the front surface 21 of the semiconductor substrate 10 to the depth D1. For example, the length L1 is 0.3 μm or more and 0.8 μm or less.

[0109] The length L2 is the film thickness of the base region 14. The length L2 corresponds to the film thickness from the depth D1 to the depth D2.

[0110] The length W is the film thickness of the electric field relaxation region 17. The length W corresponds to the film thickness from the depth D2 to the depth D3. For example, the length W is greater than or equal to 0.4 μm and less than or equal to 3.0 μm.

[0111] Length L4 is the film thickness of the accumulation region 16. Length L4 corresponds to the film thickness from depth D3 to depth D4. In one example, the film thickness of the accumulation region 16 is greater than or equal to 0.5 μm and less than or equal to 1.5 μm. For example, the film thickness of the accumulation region 16 is 1.0 μm.

[0112] Length L5 is the distance from lower end D4 of reservoir region 16 to the lower end of dummy trench 30 or gate trench 40 protruding downward from the lower surface of reservoir region 16. Reservoir region 16 preferably has a film thickness that does not exceed the lower end of dummy trench 30 or gate trench 40.

[0113] Here, in a semiconductor device having a groove portion, the density of holes injected from the collector due to conductivity modulation decreases as it approaches the emitter. As a result, the carrier density becomes lower on the emitter side, and the on-resistance cannot be sufficiently reduced. The semiconductor device 100 of this example can increase the carrier density on the emitter side by providing the accumulation region 16 below the base region 14.

[0114] In this way, by increasing the maximum value of the doping concentration in the accumulation region 16, the on-resistance and on-voltage of the semiconductor device 100 can be reduced. On the other hand, if the total dose in the accumulation region 16 is set too large, leakage current is generated due to the increase in the electric field between the base region 14 and the accumulation region 16. Therefore, the film thickness W of the electric field relaxation region 17 is preferably set within a range that can sufficiently relax the electric field between the base region 14 and the accumulation region 16.

[0115] In one example, the film thickness W of the electric field relaxation region 17 is preferably smaller than the length L4 of the film thickness of the storage region 16. In addition, the film thickness W of the electric field relaxation region 17 is less than the sum of the lengths L1+L2 of the emitter region 12 and the base region 14. The film thickness W of the electric field relaxation region 17 may also be less than the length L2 of the base region 14. In addition, the film thickness W of the electric field relaxation region 17 may be less than the length L5 of the protruding portion of the gate groove portion 40, or may be less than half of L5.

[0116] On the other hand, by setting the accumulation region 16 to a low doping concentration, the depletion layer is easily expanded and the concentration of the electric field can be alleviated. In this case as well, the electric field alleviation region 17 of 0.4 μm or more can be provided.

[0117] Figure 6 Another example of the doping concentration distribution of the semiconductor device 100 of the embodiment is shown. The semiconductor device 100 of this embodiment has a peak P3 in the electric field relaxation region 17 .

[0118] Peak P3 is provided in the electric field relaxation zone 17. Peak P3 is lower than the half value Ph of peak P2. The doping concentration of the electric field relaxation zone 17 can be any value as long as it is lower than the half value Ph of peak P2 of the accumulation zone 16. The electric field relaxation zone 17 can also have a plurality of peaks. In this case, the concentration of each segment of the electric field relaxation zone 17 formed in a plurality of segments can be any value as long as it is lower than the half value Ph of peak P2 of the accumulation zone 16. For example, the doping concentration of the electric field relaxation zone 17 can be gradually increased toward the back side 23 of the semiconductor substrate 10, or can be gradually decreased toward the back side 23 of the semiconductor substrate 10. As far as the distribution of doping concentration is concerned, as long as the integrated concentration of the electric field relaxation zone 17 is 5E14cm -2 Above and 5E15cm -2 The following are sufficient, but not limited to these.

[0119] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, it is known that the method of making such changes or improvements can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: have: A drift region of a first conductivity type, which is disposed on a semiconductor substrate; A base region of a second conductivity type, which is disposed above the drift region; An accumulation region of the first conductivity type, which is disposed between the base region and the drift region and has a doping concentration higher than that of the drift region; as well as an electric field relaxation region, which is disposed between the base region and the accumulation region and has a doping concentration lower than a peak of a doping concentration of the accumulation region, The boundary between the electric field relaxation region and the accumulation region is the half-value position of the peak of the accumulation region. The integrated concentration in the electric field relaxation zone is 5E14cm -2 Above and 5E15cm -2 the following.

2. The semiconductor device according to claim 1, wherein: The electric field relaxation region has a film thickness of 0.4 μm or more and 3.0 μm or less.

3. The semiconductor device according to claim 1, wherein: The electric field relaxation region has a film thickness of 1.0 μm or more and 1.8 μm or less.

4. The semiconductor device according to claim 1, wherein: The electric field relaxation region has a film thickness of 1.5 μm or more and 2.0 μm or less.

5. The semiconductor device according to claim 1, wherein: The film thickness of the electric field relaxation region is greater than or equal to the film thickness of the storage region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The electric field relaxation region includes a region having the same doping concentration as that of the drift region.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the electric field relaxation region has a peak smaller than a half value of the peak of the doping concentration of the accumulation region.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the accumulation region is lower than a peak of the doping concentration of the base region.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the accumulation region is 1E16 cm -3 Above and 4E16cm -3 the following.

10. The semiconductor device according to any one of claims 1 to 5, characterized in that The film thickness of the accumulation region is greater than or equal to 0.5 μm and less than or equal to 1.5 μm.

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