Ion beam etching with sidewall cleaning

Abstract

A patterned magnetoresistive random access memory (MRAM) stack is formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, wherein the main etch comprises using ion beam etching (IBE). After the main etch, a gap fill dielectric material is deposited into the spaces between the patterned MRAM stacks, and the gap fill dielectric material is selectively etched or otherwise formed to an etch depth above the depth of the underlying layer. After the gap fill dielectric material is formed, at least some of the gap fill dielectric material and any conductive material deposited on the sidewalls of the patterned MRAM stack is removed by performing an IBE trim etch.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] Magnetic random access memory (MRAM) is a non-volatile memory that uses magnetoresistive effects such as tunneling magnetoresistance (TMR). MRAM has high integration density like static random access memory (SRAM) and high-speed performance like dynamic random access memory (DRAM). Since MRAM stack materials are highly non-volatile and sensitive to reactive chemicals, ion beam etching technology is usually used to etch MRAM stacks.

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that could not be determined as prior art at the time the application was filed. Summary of the invention

[0005] An ion beam etching method is provided. The method includes: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, and wherein etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. The method also includes: forming a gap-filling dielectric material in a space between the patterned MRAM stacks; and performing an IBE trim etch to remove at least some of the gap-filling dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stack.

[0006] In some implementations, the gap-fill dielectric material is formed to a sufficient depth above the lower layer between the substrate and the plurality of MRAM layers so that the IBE trim etch does not cause a recess in the lower layer. In some implementations, the sufficient depth above the lower layer is between about 1 nm and about 20 nm above the upper surface of the lower layer. In some implementations, forming the gap-fill dielectric material in the space between the patterned MRAM stacks includes depositing the gap-fill dielectric material in the space between the patterned MRAM stacks and above the patterned MRAM stacks. In some implementations, forming the gap-fill dielectric material in the space between the patterned MRAM stacks includes selectively etching the gap-fill dielectric material to an etch depth above the depth of the tunnel barrier layer. In some implementations, the gap-fill dielectric material includes silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof. In some implementations, the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed in a manner that does not cause a vacuum to be broken between operations. In some implementations, the ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and wherein performing the IBE trim etch comprises applying a second ion beam having an energy between about 20 eV and about 400 eV to the substrate. In some implementations, performing the IBE trim etch is performed in a manner that does not etch through an underlying layer disposed below the plurality of MRAM layers.

[0007] Another aspect relates to an apparatus for performing ion beam etching. The apparatus includes: an ion beam source chamber; a process chamber coupled to the ion beam source chamber; and a controller. The controller is configured to provide instructions to perform the following operations: position a substrate in the process chamber, dispose a plurality of MRAM layers on the substrate, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer; etch through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, wherein etching through the plurality of MRAM layers includes etching through at least the tunnel barrier layer by ion beam etching (IBE); form a gap fill dielectric material in a space between the patterned MRAM stacks; and perform an IBE trim etch to remove at least some of the gap fill dielectric material and conductive material deposited on the sidewalls of the patterned MRAM stack.

[0008] In some implementations, the controller configured to provide instructions for forming the gapfill dielectric material is further configured to provide instructions to deposit the gapfill dielectric material in the space between the patterned MRAM stacks and over the patterned MRAM stacks. In some implementations, the controller configured to provide instructions for forming the gapfill dielectric material is further configured to provide instructions to selectively etch the gapfill dielectric material to an etch depth above the depth of the tunnel barrier layer. In some implementations, the gapfill dielectric material is formed to a sufficient depth above an underlying layer between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not cause a recess in the underlying layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view of an exemplary MRAM stack on a substrate according to some implementations.

[0010] Figure 2 Schematic diagram of a cross-section of an MRAM layer undergoing ion beam etching (IBE) and sidewall redeposition.

[0011] Figure 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some implementations.

[0012] Figure 4A and 4B A schematic cross-sectional view of ion beam etching through multiple MRAM layers and underlying layers is shown.

[0013] Figure 5 A flow chart of an exemplary method of ion beam etching according to some implementations is shown.

[0014] Figures 6A-6F A cross-sectional schematic diagram of the process of performing main etch, gap fill, planarization, etch back, IBE trim etch, and packaging operations according to some implementations is shown.

[0015] Figure 7 A block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown.

[0016] Figure 8 An alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown.

[0017] Fig. 9 A block diagram of an exemplary processing system for performing a planarization and / or etching process according to some implementations is shown. DETAILED DESCRIPTION

[0018] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. It should be understood by those skilled in the art that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The following specific embodiments assume that the present disclosure is implemented on a wafer. However, the present disclosure is not limited to this. The workpiece may have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various articles, such as printed circuit boards, etc.

[0019] introduce

[0020] Electronic devices use integrated circuits that include memory to store data. One type of memory commonly used in electronic circuits is DRAM. DRAM stores individual bits of data in individual capacitors on the integrated circuit. The capacitors can be charged or discharged to represent two states of the bit. Because the charge of the capacitor leaks slowly, the data is gradually lost unless the charge of the capacitor is regularly refreshed. In contrast to non-volatile memory, DRAM is a volatile memory because the data is lost when power is removed.

[0021] Unlike conventional RAM chip technology, data in MRAM is not stored as charge or current, but rather through a magnetic storage element. The magnetic storage element can be formed by two ferromagnetic plates, each of which can maintain magnetization and be separated by a thin non-magnetic insulating layer. One of the two ferromagnetic plates can be a permanent magnet set to a specific polarity, and the other of the two ferromagnetic plates can be changed to match the specific polarity of the external magnetic field to store memory. This configuration involving two ferromagnetic plates and a thin non-magnetic insulating layer is called a magnetic tunnel junction. MRAM is a non-volatile memory because it has the ability to maintain the stored data even if the power is removed.

[0022] Figure 11 is a schematic cross-sectional view of an exemplary MRAM stack on a substrate according to some implementation schemes. The MRAM stack 100 is disposed on a dielectric layer 110, such as SiO2, and the dielectric layer 110 is disposed on a silicon or glass substrate (not shown). In the case of an embedded MRAM, since the embedded MRAM may be an MRAM embedded in a non-memory circuit (such as a metallization layer), there are various structures (not shown) between the substrate and the MRAM stack 100, including transistor levels of logic circuits and 3 to 5 metallization layers. These structures are covered by the dielectric layer 110 or inserted in the dielectric layer 110. The MRAM stack 100 may include a top electrode layer 120 and a bottom electrode layer 130. The bottom electrode layer 130 is disposed on the dielectric layer 110 and may include a single layer of metal, or a multilayer stack including multiple metal layers and other material layers (e.g., dielectric materials). The top electrode layer 120 is disposed above the bottom electrode layer 130 and may include a single layer of metal, or a multilayer stack including multiple metal layers and other material layers (e.g., dielectric materials). The MRAM stack 100 may be arranged into an MRAM cell array connected by metal word lines and bit lines. In some implementations, the bottom electrode layer 130 is connected to the word lines, and the top electrode layer 120 is connected to the bit lines.

[0023] The MRAM stack 100 may include a memory element or a magnetoresistive effect element, wherein the memory element or the magnetoresistive effect element may be disposed between the top electrode layer 120 and the bottom electrode layer 130. The memory element or the magnetoresistive effect element may be a multilayer film or a magnetic tunnel junction (MTJ) stack 140. The MTJ stack 140 may include a first magnetic layer 150, a second magnetic layer 160, and a barrier layer 170 between the first magnetic layer 150 and the second magnetic layer 160. In addition, the MTJ stack 140 may include a plurality of MTJ stacks and a plurality of barrier layers, each barrier layer being positioned between a pair of magnetic layers. It should be understood that the MTJ stack 140 is illustrative and not restrictive, and may include other layers not shown in the drawings. Figure 1. The first magnetic layer 150 is designed to function as a free magnetic layer, while the second magnetic layer 160 has a fixed magnetization direction. In some implementations, each of the first magnetic layer 150 and the second magnetic layer 160 includes a magnetic material, such as cobalt (Co), nickel (Ni), iron (Fe), or a combination thereof (e.g., CoNi, CoFe, NiFe, CoNiFe). Each of the first magnetic layer 150 and the second magnetic layer 160 may also include a non-magnetic material, such as boron (B), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), aluminum (Al), silicon (Si), germanium (Ge), gallium (Ga), oxygen (O), nitrogen (N), carbon (C), platinum (Pt), palladium (Pd), ruthenium (Ru), or phosphorus (P) to form a magnetic compound (e.g., CoFeB). It should be understood that each of the first magnetic layer 150 and the second magnetic layer 160 may include one or more sublayers. In some implementations, the second magnetic layer 160 may be coupled and disposed on an anti-ferromagnetic layer (not shown). The MTJ stack 140 further includes a tunnel barrier layer, or barrier layer 170, located between the first magnetic layer 150 and the second magnetic layer 160, wherein the barrier layer 170 may include a non-magnetic insulating material such as magnesium oxide (MgO). Therefore, the MTJ stack 140 may include a pair of ferromagnetic layers (i.e., the first magnetic layer 150 and the second magnetic layer 160) that together produce a magnetoresistance effect, and a non-magnetic intermediate layer (i.e., the barrier layer 170) therebetween. When the magnetization of the first magnetic layer 150 changes direction relative to the magnetization of the second magnetic layer 160, the resistivity of the MTJ stack 140 changes, exhibiting a low resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially parallel, and exhibiting a high resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially anti-parallel. Therefore, the MRAM stack 100 may have two stable states, allowing the MRAM stack 100 to be used as a volatile memory.

[0024] In some implementations, the top electrode layer 120 may be used as a hard mask layer. During processing, the top electrode layer 120 may be deposited on the first magnetic layer 150 to pattern the MTJ stack 140 below. However, it should be understood that the positions of the first magnetic layer 150 and the second magnetic layer 160 may be opposite, so that the top electrode layer 120 is deposited on the second magnetic layer 160. In some implementations, the top electrode layer 120 includes tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or other refractory metals. The MTJ stack 140 may be formed on the bottom electrode layer 130, wherein the bottom electrode layer 130 includes a conductive material, such as Ta, Ti, W, TiN, TaN, Pt, Ru, etc.

[0025] It should be understood that the MRAM stack 100 may include components not necessarily shown in FIG. Figure 1 The layers in the MRAM stack 100 are not necessarily limited to metals or conductive materials, but may also include one or more dielectric material layers.

[0026] Etching MRAM stack (including Figure 1 There may be many challenges in the materials in the MRAM stack 100). Hard materials are usually etched by chemical etching processes such as reactive ion etching (RIE). However, it is difficult to perform reactive ion etching on materials such as cobalt, iron, nickel, and other magnetic elements because these materials do not easily form volatiles when exposed to typical etchant chemicals. Therefore, many materials in the MRAM stack require more corrosive etchant chemicals. On the other hand, some materials in the MRAM stack cannot withstand such corrosive etchant chemicals. For example, a tunnel barrier layer such as MgO cannot withstand reactive chemicals, wherein the reactive chemicals may include free radicals, ions, and neutral substances including fluorine, chlorine, iodine, oxygen, or hydrogen. These chemicals may cause reactions with the tunnel barrier layer, thereby damaging the tunnel barrier layer and adversely affecting the electrical and magnetic properties of the MRAM stack. In some cases, the tunnel magnetoresistance (TMR) effect in the MRAM stack is impaired.

[0027] Ion beam etching (IBE) has been widely used in various industries to pattern thin films. Ion beam etching (also known as ion milling) provides a highly directional beam of charged particles to etch features on a substrate. For purely physical etching processes, ion beam etching can be applied using an inert gas; however, in some cases, ion beam etching can be applied using a reactive species to increase material etching using a chemical / reactive component. In general, ion beam etching can physically etch through hard materials by using individual particles to abrade exposed targets to dislodge atoms and molecules. Ion beam etching can be used to etch materials in an MRAM stack while avoiding reactive chemicals that may degrade sensitive layers (e.g., tunnel barriers).

[0028] Features in the MRAM stack may be patterned by ion beam etching. Ion beam etching may generally be chemically non-reactive and physically etches the layers and materials exposed by the hard mask. This may cause atoms and molecules to be sputtered from the target. The sputtered atoms and molecules may be directed toward the exposed sidewalls of the MRAM stack and cause redeposition on the exposed sidewalls. Thus, etching and redeposition may occur simultaneously. By performing ion beam etching at lower energy and a different impact angle than the ion beam etching used to pattern the MRAM stack, the redeposited material is cleaned from the sidewalls of the MRAM stack.

[0029] Figure 2 2 is a cross-sectional schematic diagram of an MRAM layer subjected to ion beam etching and sidewall redeposition. MRAM stacks 220a, 220b are formed on substrate 210. Each of the MRAM stacks 220a, 220b may include a pair of magnetic layers, wherein a tunnel barrier layer (e.g., MgO) may be sandwiched between the magnetic layers. It should be understood that in some implementations, each of the MRAM stacks 220a, 220b may include multiple tunnel barrier layers, each sandwiched between a pair of magnetic layers. Examples of layers and materials in the MRAM stacks 220a, 220b have been described above with respect to Figure 1 The MRAM stack 100 in the embodiment is described. The patterning process of conventional MRAM includes hard mask patterning, top electrode patterning, MTJ patterning, and bottom electrode patterning. It should be understood that ion beam etching can be used for some or all of the aforementioned patterning processes, wherein ion beam etching can be used for MTJ patterning. Reactive ion etching or ion beam etching can be used for patterning of the top electrode and patterning of the bottom electrode. In order to pattern the MRAM stack 220a, 220b, an ion beam 225 can be applied to the substrate 210 to physically etch the layers and materials exposed by the hard mask. The ion beam 225 sputters atoms and molecules from the surface exposed to the ion beam 225. As Figure 2As shown, the sputtered atoms and molecules 275 may be directed toward and redeposited on the sidewalls of the MRAM stack 220a, 220b. Some layers on the substrate 210 (e.g., layers of the MTJ stack) may include metal atoms such as Fe, Co, and Ni atoms. As the ion beam etch proceeds through the MTJ stack, these metal atoms may be displaced and redeposited on the sidewalls of the MRAM stack 220a, 220b. When the conductive material is redeposited on the sidewalls of the tunnel barrier layer (which may be only a few nanometers thick), the magnetic layer may short-circuit in the MRAM stack 220a, 220b.

[0030] The ion beam 225 applied to the substrate 210 can be directed at an angle. The angle of incidence of the ion beam 225 can be adjusted to control parameters such as etching rate, uniformity, shape, surface topography, and target surface composition. In some cases, the angle of incidence of the ion beam 225 is adjusted to clean the sidewalls of the redeposited material. A lower angle of incidence of the ion beam 225 (i.e., more vertical) may cause more redeposition of material, while a higher angle of incidence (i.e., less vertical) optimized for the ion beam 225 can form a cleaner sidewall surface by removing the redeposited material. In addition, with the increase in device density and the increase in aspect ratio, the feasibility of using a higher angle of incidence when cleaning the sidewall surface is more limited.

[0031] Ion beam etching equipment

[0032] Figure 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some implementations. The ion beam etching apparatus 310 includes a processing chamber 312 having a substrate holder 314 for supporting a substrate 316. The substrate 316 may be a semiconductor wafer. The multiple MRAM layers described earlier may be formed on the substrate 316. The multiple MRAM layers may include one or more magnetic layers and a tunnel barrier layer or multiple tunnel barrier layers. The multiple MRAM layers may also include an upper electrode layer and a lower electrode layer. The substrate 316 may be attached to the substrate holder 314 using any suitable technique. For example, the substrate 316 is mechanically or electrostatically connected to the substrate holder 314. In some implementations, the substrate holder 314 provides precise tilting and rotation and may include an electrostatic clamp (ESC) to engage the substrate 316.

[0033] The ion beam etching apparatus 310 further includes an ion beam source chamber 322, wherein the processing chamber 312 may be located outside the ion beam source chamber 322 and coupled to the ion beam source chamber 322. The ion beam source chamber 322 may be separated from the processing chamber 312 by an ion extractor 340 and / or a mechanical shutter 348. An induction coil 332 may be arranged around the outer wall of the ion beam source chamber 322. A plasma generator 334 supplies RF power to the induction coil 332. The plasma generator 334 may include an RF source 336 and a matching network 338. When in use, a gas mixture is introduced into the ion beam source chamber 322 and RF power is supplied to the induction coil 332 to generate a plasma in the ion beam source chamber 322, wherein the plasma generates ions.

[0034] The ion beam etching apparatus 310 also includes a gas delivery system 350, which is fluidically connected to the ion beam source chamber 322. The gas delivery system 350 delivers one or more gas mixtures to the ion beam source chamber 322. The gas delivery system 350 may include one or more gas sources 352, valves 354, mass flow controllers (MFCs) 356, and mixing manifolds 358 that are fluidically connected to the ion beam source chamber 322. In some implementations, the gas delivery system 350 is configured to deliver an inert gas, such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or krypton (Kr). In some implementations, the gas delivery system 350 delivers a gas mixture that also includes reactant chemicals and an inert gas.

[0035] The ion extractor 340 extracts positive ions from the plasma and accelerates the positive ions in a beam toward the substrate 316. The ion extractor 340 may include a plurality of electrodes forming a grid or grid system. Figure 3 As shown, the ion extractor 340 includes three electrodes, wherein a first electrode 342, a second electrode 344, and a third electrode 346 are presented in order starting from the gas delivery system 350. A positive voltage is applied to the first electrode 342 and a negative voltage is applied to the second electrode 344 so that the ions are accelerated due to their potential difference. The third electrode 346 is grounded. The potential difference between the second electrode 344 and the third electrode 346 is controlled to control the energy and dispersion of the ion beam. A mechanical shutter 348 can be adjacent to the ion extractor 340. A neutralizer 360 can supply electrons into the processing chamber 312 to neutralize the charge of the ion beam passing through the ion extractor 340 and the mechanical shutter 348, wherein the neutralizer 360 can have its own gas delivery system using an inert gas (e.g., argon or xenon). In some implementations, the ion extractor 340 and / or the mechanical shutter 348 can be controlled so that the ion beam is delivered to the substrate 316 continuously or in pulses.

[0036] A position controller 366 may be used to control the position of the substrate holder 314. In particular, the position controller 366 may control the tilt angle and rotation of the substrate holder 314 relative to the tilt axis to position the substrate 316. In some implementations, an endpoint detector 368 may be used to sense the position of the ion beam relative to the substrate 316 and / or the substrate holder 314. A pump 370, such as a turbomolecular pump, may be used to control the pressure within the process chamber 312 and exhaust reactants from the process chamber 312.

[0037] The ion beam etching device 310 may also include a controller 390. The controller 390 (which may include one or more physical controllers or logic controllers) controls some or all operations of the ion beam etching device 310. In some implementations, the controller 390 may be used to control the plasma generator 334, the gas delivery system 350, the neutralizer 360, the position controller 366, and the pump 370. The controller 390 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or a computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with the controller 390 and may be provided over a network. In some implementations, the controller 390 executes system control software. The system control software may include instructions for controlling the timing and / or magnitude of application of any one or more of the following chamber operating conditions: mixture and / or composition of gases, gas flow rate, chamber pressure, chamber temperature, substrate / substrate holder temperature, substrate position, substrate holder tilt, substrate holder rotation, voltage applied to the grid, frequency and power applied to the coil or other plasma generating components, and other parameters of a particular step performed by the tool. The system control software may further control sweep operations and cleaning operations via pump 370. The system control software may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operation of the process tool components required to perform various process tool steps. The system control software may be encoded in any computer readable programming language.

[0038] In some implementations, the system control software includes input / output control (IOC) sequencing instructions for controlling the above parameters. For example, each stage of the semiconductor manufacturing process may include one or more instructions executed by the controller 390. For example, instructions for setting process conditions for a stage may be included in a corresponding recipe stage. In some implementations, the recipe stages may be arranged in sequence so that the steps in the ion beam etching process are performed in a specific order for the processing stage. For example, the recipe may be configured to perform a separation etch using ion beam etching at high energy and a trim etch using ion beam etching at low energy.

[0039] Other computer software and / or programs may be employed in some implementations. Examples of programs or portions of programs used for this purpose include substrate positioning programs, process gas composition control programs, pressure control programs, heater control programs, and RF power supply control programs.

[0040] Controller 390 may control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, gas level, etc. reaches a certain threshold), operating times (e.g., opening a valve at certain times in a process), or based on instructions received from a user.

[0041] In general, the controller 390 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions may be instructions that are communicated to the controller 390 in the form of various separate settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor substrate or system. In some implementations, the operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during patterning of an MRAM stack on a substrate.

[0042] In some implementations, the controller 390 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 390 may be in the "cloud" or may be all or part of a wafer fab host system that may allow remote access to substrate processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller 390 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller 390 is configured to interface with or control. Thus, as described above, the controller 390 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller 390 for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0043] As described above, depending on one or more processing steps to be performed by the tool, the controller 390 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the facility, a host computer, another controller, or tools used in the material transport of substrate containers to and from tool locations and / or load ports in a semiconductor manufacturing facility. The foregoing examples of tools with which the controller 390 may communicate are described in Figure 7-9 middle.

[0044] Ion beam etching with sidewall cleaning

[0045] In the present disclosure, a dielectric gap fill material is deposited between an IBE separation etch process for patterning an MRAM stack and an IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack. In general, the IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack results in sputtering of metal or conductive material that may be redeposited on the sidewalls. Sputtering of metal or conductive material may occur at locations where the etch front of the IBE trim etch process includes the metal or conductive material. One solution to avoid such sputtering is to provide a thick layer of dielectric material, such as silicon oxide (SiO2), as an etch front. The thick layer of dielectric material may be provided below the MRAM layer or below the magnetic layer in the MTJ stack. The thickness of the thick layer of dielectric material may be at least about 40 nm, at least about 50 nm, at least about 75 nm, or at least about 100 nm. In this way, any material that is redeposited on the sidewalls during ion beam etching is a dielectric material rather than a conductive material. However, providing a thick layer of dielectric material below the magnetic layer in the MTJ stack may be impractical, increase overhead, complicate the manufacturing process, increase cost, and even reduce performance. For example, many MRAM devices are embedded memories located between metallization layers in an integrated circuit (IC), and the thickness of the dielectric layer in which the MRAM device resides may not be easily changed.

[0046] Figure 4A and 4B A schematic cross-sectional view of ion beam etching through multiple MRAM layers and lower layers is shown. The MRAM stack 400 may include a first magnetic layer 450, a tunnel barrier layer 470, and a second magnetic layer 460, wherein the tunnel barrier layer 470 is between the first magnetic layer 450 and the second magnetic layer 460. The first magnetic layer 450 may also be referred to as a free layer and is designed to be used as a free magnetic layer, and the second magnetic layer 460 may be referred to as a reference layer and is designed to have a fixed magnetization direction. In some implementations, the first magnetic layer 450 and the second magnetic layer 460 may include magnetic materials such as Co, Ni, Fe, Pt, or a combination thereof. The tunnel barrier layer 470 may include a non-magnetic insulating material such as MgO. The combination of the first magnetic layer 450, the tunnel barrier layer 470, and the second magnetic layer 460 produces a magnetoresistance effect. The MRAM stack 400 is disposed on a substrate 410, and the lower layer 430 is between the substrate 410 and the MRAM stack 400. The lower layer 430 may include one or more layers of dielectric material, such as silicon oxide (SiO2). In some implementations, a hard mask layer or an electrode layer (not shown) may be disposed above the MRAM stack 400. In some implementations, the electrode layer (not shown) may be disposed between the lower layer 430 and the substrate 410. In some implementations, the MRAM stack 400 may include a plurality of tunnel barrier layers, each of which is sandwiched between a first magnetic layer and a second magnetic layer.

[0047] Ion beam etching that can etch through the layers of the MRAM stack 400 can be performed to form a patterned MRAM stack, wherein the patterned MRAM stack can include lines, pillars, or other patterned features. The ion beam etching to form the patterned MRAM stack can be performed at high power and relatively low angles of incidence. In addition, after forming the patterned MRAM stack, ion beam etching can be performed to clean the sidewalls of the patterned MRAM stack to remove undesirable material that has been redeposited on the sidewalls. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack can be performed at relatively low power and relatively high angles of incidence, and the angle of incidence is normal to the substrate surface.

[0048] exist Figure 4A In the embodiment, the ion beam 425 can be directed at a certain angle to clean the sidewalls of the patterned MRAM stack. For example, the substrate 410 can be tilted or rotated to adjust the ion impact angle of the ion beam 425. The ion beam 425 impacts the sidewalls of the patterned MRAM stack to remove unwanted materials. The ion beam 425 also impacts the lower surface of the MRAM stack 400 and causes sputtering of atoms and molecules at the lower surface. The sputtered atoms and molecules 475 can be directed to the sidewalls of the patterned MRAM stack, which results in redeposition on the sidewalls of the patterned MRAM stack. When the etching front of the ion beam 425 has a conductive material (such as a metal), at least some of the conductive material may be redeposited on the sidewalls of the patterned MRAM stack. In the embodiment, the ion beam 425 can be directed at the sidewalls of the patterned MRAM stack, which results in redeposition on the sidewalls of the patterned MRAM stack. Figure 4A When the etching front of the ion beam 425 includes the second magnetic layer 460 , magnetic components having Co, Ni, Pt, or Fe may be redeposited on the walls of the patterned MRAM stack, thereby degrading the electrical and magnetic properties of the MRAM stack 400 .

[0049] Instead of an etch front having a conductive material, the etch front may include a dielectric material. Figure 4BIn the process, the ion beam 425 impacts the lower surface of the MRAM stack 400, so that the sputtered atoms and molecules 475 are directed to the exposed surface of the patterned MRAM stack. The etching front of the ion beam 425 includes the lower layer 430, in which the dielectric material such as SiO2 can be redeposited on the sidewalls of the patterned MRAM stack. The atoms and molecules 475 sputtered from the dielectric material of the lower layer 430 may not degrade the electrical and magnetic properties of the MRAM stack 400. Therefore, the overetching can be performed to etch through the lower layer 430 while making any back sputtering harmless to the patterned MRAM stack. The thickness of the lower layer 430 can be sufficient to serve as an etching front for ion beam etching to properly clean the sidewalls of the patterned MRAM stack. However, as described above, it may not be desirable to include a sufficiently thick lower layer 430 between the substrate 410 and the MRAM stack 400, especially having a thick lower layer 430 may be impractical in various devices.

[0050] In the present disclosure, the MRAM stack is not provided with an underlying layer of dielectric material of sufficient thickness as an etch front during cleaning, which has an underlying layer of dielectric material of sufficient thickness to cause the redeposited sidewall material to be removed before the dielectric material is etched away. In the present disclosure, an IBE main etch process is performed to form a patterned MRAM stack, and then a gap fill dielectric material is deposited in the space between the patterned MRAM stack. The gap fill dielectric material can be etched back or otherwise formed to a sufficient depth so that the deposited gap fill dielectric material remains during all or most of the subsequent IBE trim etch cleaning step. In some implementations, the thickness of the deposited gap fill dielectric material extends above the depth of the tunnel barrier layer. After depositing the gap fill dielectric material, an IBE over-etch or trim etch process is performed to clean the sidewalls of the patterned MRAM stack, wherein the etch front during the IBE trim etch process includes the gap fill dielectric material.

[0051] Figure 5 A flow chart of an exemplary ion beam etching method according to some implementations is shown. Figure 5 The operations of process 500 may include additional, fewer, or different operations. Figure 5 The description of processing 500 is Figures 6A-6F 5 is a series of cross-sectional schematic diagrams showing main etching, gap filling, planarization, etch back, IBE trim etching, and packaging operations. The operations of process 500 may be performed using an ion beam etching apparatus (e.g., Figure 3 The process is performed using the ion beam etching equipment 310).

[0052] At block 510 of process 500, a plurality of MRAM layers disposed on a substrate are etched through to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer. Etching through the plurality of MRAM layers includes ion beam etching (IBE) to etch through at least the tunnel barrier layer. In some implementations, etching through the plurality of MRAM layers includes ion beam etching to etch through the plurality of MRAM layers. In some implementations, etching through the plurality of MRAM layers includes reactive ion etching (RIE) to etch through some of the plurality of MRAM layers, and ion beam etching to etch through at least the tunnel barrier layer. In some implementations, the plurality of MRAM layers include two or more tunnel barrier layers, wherein ion beam etching is performed to etch through the two or more tunnel barrier layers. A hard mask may be formed on the plurality of MRAM layers for patterning the MRAM stack. The hard mask may be formed of, for example, W, Ti, Ta, TiN, or other refractory metals. Etching through the plurality of MRAM layers at block 510 may also be referred to as "main etching," "cut etching," "separation etching," "first etching," or "IBE separation etching."

[0053] Etching through multiple MRAM layers may include etching through an MTJ stack including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer between the first magnetic layer and the second magnetic layer. The first magnetic layer may be positioned above the tunnel barrier layer, and the second magnetic layer may be positioned below the tunnel barrier layer. The tunnel barrier layer may include a non-magnetic insulating material, such as MgO. Each of the first magnetic layer and the second magnetic layer may include a magnetic element, such as Co, Ni, Pt, Fe, or a combination thereof. In some implementations, etching through the MTJ stack may include ion beam etching through the MTJ stack. After etching through at least the second magnetic layer, the etching may stop at the lower layer or dielectric layer. Etching through multiple MRAM layers may include ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, but not etching through the lower layer. Therefore, the main etching or the separation etching may be performed until the interface between the lower layer and the multiple MRAM layers being etched, wherein the lower layer may include a dielectric material, such as SiO2. The main etching may be performed on the upper surface of the lower layer, and the main etching may be stopped on the lower layer using optical emission spectroscopy or an endpoint detector.

[0054] When the ion beam etching etches through at least some of the MRAM layer, an ion beam of an inert gas can be generated from the ion beam source chamber. The ion beam source chamber can be coupled to a processing chamber where the substrate is located. The ion beam can be generated in the ion beam source chamber using a gas mixture containing an inert gas. The inert gas may include helium (He), neon (Ne), argon (Ar), xenon (Xe), krypton (Kr), or a combination thereof. In some implementations, the gas mixture may include one or more reactive gases to increase material etching using chemical / reactive components. In some implementations, the gas mixture has no or substantially no reactive gas. RF power can be applied to a coil surrounding the ion beam source chamber to generate a plasma, and ions are extracted from the plasma to form an ion beam. A voltage is applied to an ion extractor (such as a grid) to extract ions to form an ion beam, and the ion beam can be accelerated toward the processing chamber. Controlling the voltage applied to the ion capture device can be used to control the etching rate when ion beam etching is performed. The high voltage ion beam may be between about 400V and about 2000V for "fast" etching with a high etching rate, and the low voltage ion beam may be between about 30V and about 400V for "soft" etching with a low etching rate. The ion beam etching (main etching or separation etching) for etching through at least some of the multiple MRAM layers including the tunnel barrier layer to form a patterned MRAM stack may be performed at a relatively high voltage. Therefore, the main etching for etching through the multiple MRAM layers to form a patterned MRAM stack may be performed at a high voltage between about 400V and about 2000V. On the other hand, the trim etching or over etching for cleaning the sidewalls of the patterned MRAM stack may be performed at a low voltage between about 30V and about 400V.

[0055] In some implementations, etching through at least some of the plurality of MRAM layers may include applying an ion beam having an ion energy between about 200 eV and about 10,000 eV to the substrate. The main etch may be performed at a high ion energy compared to the trim etch to efficiently etch the material in the MRAM layer. In some implementations, the main etch or the separate etch may be performed for 10 minutes or less, 3 minutes or less, or 1 minute or less. In some implementations, the main etch may be performed in an ion beam etching apparatus having an ion beam source chamber coupled to a process chamber. Exemplary ion beam etching is described above. Figure 3 middle.

[0056] In some implementations, reactive ion etching may be used to etch some of the MRAM layers. Specifically, reactive ion etching may be applied to film layers other than the tunnel barrier layer because reactive species from the reactive ion etching may damage the tunnel barrier layer. Ion beam etching may be performed after reactive ion etching to etch through the tunnel barrier layer. In some implementations, reactive ion etching may be applied to a hard mask layer or an electrode layer disposed above the tunnel barrier layer. In some implementations, reactive ion etching may be applied to a first magnetic layer disposed above the tunnel barrier layer. In some implementations, reactive ion etching may be applied to a second magnetic layer disposed below the tunnel barrier layer. In some implementations, reactive ion etching may be applied to an electrode layer disposed below the second magnetic layer. However, ion beam etching may be used instead of reactive ion etching to etch any of the above-mentioned MRAM layers. Therefore, the order of the main etching when etching through multiple MRAM layers may include IBE after RIE, IBE after RIE and then RIE, RIE after IBE, or IBE throughout.

[0057] The main etch may cause conductive material to be redeposited onto the sidewalls of the patterned MRAM stack. The redeposited conductive material may come from one or more magnetic layers in the plurality of MRAM layers. Typically, when etching one or more magnetic layers in the plurality of MRAM layers, etching byproducts are produced that may be redeposited onto the exposed surface. The etching byproducts may include atoms or molecules of a metal or conductive material. When an ion beam is applied to the plurality of MRAM layers, these etching byproducts are sputtered. One or more magnetic layers may include non-volatile materials, wherein the non-volatile materials may include magnetic materials, such as Co, Ni, Pt, Fe, etc. When such etching byproducts are redeposited onto the side surfaces of the tunnel barrier layer, the MTJ stack is adversely affected and may result in a short circuit.

[0058] Etching through multiple MRAM layers forms a patterned MRAM stack, wherein the patterned MRAM stack is a line, a column, or other patterned feature. The main etch forms spaces between the patterned MRAM stacks. In some implementations, the patterned MRAM stack is a plurality of columns with a high aspect ratio, wherein the aspect ratio of the patterned MRAM stack is at least 5:1, at least 7:1, at least 10:1, or at least 20:1. In some implementations, the pitch between adjacent MRAM stacks may be equal to or less than about 300 nm, between about 10 nm and about 300 nm, or between about 30 nm and about 250 nm.

[0059] In some implementations, the substrate can be positioned in a processing chamber of an ion beam etching apparatus prior to block 510 of process 500. A plurality of MRAM layers can be disposed on the substrate, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer.

[0060] Fig. 6A 6. A schematic cross-sectional view of an exemplary main etch according to some implementations is shown. A plurality of MRAM layers 650, 660, and 670 are positioned above a substrate 610, and a lower layer 630 is positioned between the plurality of MRAM layers 650, 660, and 670 and the substrate 610. Aspects of the plurality of MRAM layers 650, 660, and 670 and the lower layer 630 are shown in FIG. Figure 1 and Figure 2 . A plurality of MRAMs 1650, 660, and 670 include at least a first magnetic layer 650, a second magnetic layer 660, and a tunnel barrier layer 670 between the first magnetic layer 650 and the second magnetic layer 660. As described above, the plurality of MRAM layers 650, 660, and 670 may include a plurality of tunnel barriers each sandwiched between a first magnetic layer and a second magnetic layer. A main etch is performed to form a patterned MRAM stack 620a, 620b. The main etch may stop on the upper surface of the lower layer 630. In some implementations, the main etch or the separation etch is performed through at least the tunnel barrier layer 670 when forming the patterned MRAM stack 620a, 620b. An ion beam for the main etch or the separation etch may be provided with a relatively high ion energy and a relatively low incident angle, the incident angle being a normal direction relative to the substrate surface. A residue 605 comprising a metal or conductive material is formed on the sidewalls of the patterned MRAM stack 620a, 620b due to the main etch. Sputtered atoms and / or molecules from ion beam etching of the plurality of MRAM layers 650, 660, and 670 may cause accumulation of residue 605. The residue 605 may form on the tunnel barrier layer 670 and degrade the performance of the tunnel barrier layer 670.

[0061] Back to Figure 5 , at block 520 of process 500, a gap fill dielectric material is formed in the space between the patterned MRAM stacks. In some implementations, the gap fill dielectric material may be formed along the sidewalls and lower surface of the patterned MRAM stack. In some implementations, the gap fill dielectric material may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma enhanced chemical vapor deposition (PECVD). However, it should be understood that the gap fill dielectric material may be deposited using any other suitable deposition technique, such as atomic layer deposition (ALD). For example, the gap fill dielectric material may be deposited in the space between the patterned MRAM stacks using a deposition technique to achieve bottom-up filling.

[0062] In some implementations, the gap-fill dielectric material comprises any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, germanium nitride, magnesium oxide, or a combination thereof. For example, the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide. The gap-fill dielectric material may comprise a silicon nitride layer and a silicon oxide layer, or may comprise only a silicon nitride layer. In some implementations, it is desirable to avoid direct contact of the silicon oxide with the patterned MRAM stack. The above-mentioned dielectric material may fill the space between the patterned MRAM stacks, or at least fill the space above the lower layer. Forming the gap-fill dielectric material in the space between the patterned MRAM stacks may also be referred to as a "gap-fill" or "dielectric gap-fill" process.

[0063] In some implementations, the gap fill may be performed in a deposition chamber such as a CVD, PVD, or PECVD chamber. The gap fill may be performed after the main etch and before the IBE trim etch. In some implementations, the main etch and the gap fill may be performed by an integrated tool or a multi-station processing tool. The main etch operation at block 510 and the gap fill at block 520 may be performed in a manner that does not result in a vacuum break between operations.

[0064] In some implementations, forming a gap fill dielectric material in the space between the patterned MRAM stacks includes depositing the gap fill dielectric material in the space between the patterned MRAM stacks and above the patterned MRAM stacks, and selectively etching the gap fill dielectric material to a sufficient depth above the underlying layer. In some implementations, the sufficient depth above the underlying layer may correspond to a sufficient thickness to leave at least some gap fill dielectric material after a subsequent trim etch at block 530. The gap fill dielectric material may be initially deposited above the patterned MRAM stack to create excess material. The gap fill deposition process is typically conformal to some extent, resulting in material being deposited along the sidewalls, lower surface, and upper surface of the patterned MRAM stack. The gap fill deposition process may result in a somewhat "loaf of bread" shape because the deposition rate may vary between the upper surface of the patterned MRAM stack and the lower surface of the patterned MRAM stack. . This typically results in an uneven topography from the gap fill. Therefore, an excess amount of gapfill dielectric material may be deposited when filling the space between the patterned MRAM stacks, wherein the excess amount of gapfill dielectric material may be non-uniform in thickness across the upper surface of the gapfill dielectric material. In other words, some portions of the gapfill dielectric material are thicker than other portions.

[0065] After depositing excess material of the gap fill dielectric material over the patterned MRAM stack, the excess material may be removed. In some implementations, process 500 also includes planarizing the gap fill dielectric material deposited over the patterned MRAM stack. For example, the excess material may be removed using chemical mechanical polishing (CMP) or etching.

[0066] In addition to or in lieu of planarization of the excess material, the deposited gap fill dielectric material may be selectively etched using a dry etch or wet etch technique, wherein the gap fill dielectric material is selectively etched to a depth above the underlying layer. In some implementations, the depth may be between an upper surface of the tunnel barrier layer and an upper surface of the first magnetic layer, between a lower surface of the tunnel barrier layer and a lower surface of the second magnetic layer, or between a lower surface of the second magnetic layer and an upper surface of the underlying layer. When the multiple MRAM layers include multiple tunnel barriers having multiple first / second magnetic layers, the depth may be measured relative to the lowest tunnel barrier layer and the lowest first / second magnetic layer. In some implementations, the selective etch is a plasma etch that selectively removes the gap fill dielectric material but does not remove or substantially remove any hard mask layer or MRAM layer. The etch may have an etch selectivity ratio greater than about 10:1 between the gap fill dielectric material and the hard mask layer or MRAM layer, meaning that the etch rate of the gap fill dielectric material etch is greater than ten times the etch rate of the hard mask layer or MRAM layer. For example, the gap filling dielectric material can be etched with fluorine plasma in a reactive ion etch (RIE) or chemical downstream etch (CDE) chamber. If the dielectric material is silicon oxide, it can also be removed using hydrogen fluoride (HF) vapor. The sufficient depth above the lower layer can be between about 1nm to about 20nm above the depth of the lower layer, between about 2nm to about 15nm above the depth of the lower layer, or between about 3nm to about 10nm above the depth of the lower layer. In some implementations, selective etching can be performed to remove the gap filling dielectric material without exposing any lower layer. In some implementations, selective etching can be performed to remove the gap filling dielectric material without significantly etching through the lower layer. As used herein, "substantially etching" etching through the lower layer may constitute etching through at least 3nm or at least 5nm of the lower layer. In some implementations, the sufficient depth above the lower layer may be located above the tunnel barrier layer. As described above, exposing the tunnel barrier layer to the reactant chemicals may damage the tunnel barrier layer. The selective etch leaves the remaining gap fill dielectric material to serve as an etch front during the IBE trim etch used to clean the sidewalls of the patterned MRAM stack. In some implementations, the selective etch can be stopped at an etch depth just above the depth of the tunnel barrier layer or at a sufficient depth above the underlying layer using appropriate endpoint detection techniques such as optical emission spectroscopy (OES) or interferometer endpoint detection (IEP). The selective etch may also be referred to as an "etch back" process or an "isotropic etch back" process.

[0067] Figure 6B Shows that some implementations are being Fig. 6A Schematic diagram of a cross-sectional view of an exemplary gap filling process after the main etch of . After the main etch, the gap filling dielectric material 680 is deposited in the space between the patterned MRAM stacks 620a, 620b using a suitable deposition technique (e.g., CVD, PVD, or PECVD). In some implementations, the gap filling dielectric material 680 is conformally deposited along the exposed surfaces (e.g., sidewalls) of the patterned MRAM stacks 620a, 620b for gap filling. Thus, any recess, gap, groove, opening, or space is filled by the gap filling dielectric material 680. Excess material of the gap filling dielectric material 680 is deposited above the patterned MRAM stacks 620a, 620b. In some implementations, the gap filling dielectric material 680 comprises silicon nitride or a combination of silicon nitride and silicon oxide.

[0068] Figure 6C Shows that some implementations are being Figure 6B Schematic diagram of a cross-sectional view of an exemplary planarization process after a gap fill process. After depositing excess gap fill dielectric material 680, the upper surface of the excess material may be uneven. For example, the uneven topography may result in more dielectric gap fill dielectric material 680 in the field area than in the gap fill area, which may result in a loaf-like shape. A planarization process (such as CMP or etching) may be performed to smooth the topography and remove excess material.

[0069] Fig.6D Shows that some implementations are being Figure 6CSchematic cross-sectional view of an exemplary etch-back process after a planarization process of . After the planarization process or the gap filling process, the etch-back process is performed to selectively remove the gap filling dielectric material 680 relative to the multiple MRAM layers 650, 660 and 670 or at least relative to the first magnetic layer 650. In some implementations, the etch-back process selectively removes the gap filling dielectric material 680 relative to the hard mask layer. The etch-back process can be a dry etch or a wet etch. The dry etch can be a plasma etch. The etch-back process can be performed to remove the gap filling dielectric material 680 to an etch depth above the lower layer 630. In some implementations, the etch-back process can be performed to remove the gap filling dielectric material 680 to an etch depth slightly above the depth of the tunnel barrier layer 670. In particular, the etch-back process can be performed to an etch depth slightly above the interface between the tunnel barrier layer 670 and the first magnetic layer 650. For example, the remaining gap filling dielectric material 680 can be located at an etch depth of several nanometers above the upper surface of the tunnel barrier layer 670. In this manner, the tunnel barrier layer 670 is not exposed to the etch-back process. However, it should be understood that some implementations involving conformal deposition processes may not require this etch-back or planarization process.

[0070] Back to Figure 5 , at box 530 of process 500, ion beam etching is performed to remove at least some of the gap fill dielectric material and conductive material deposited on the sidewalls of the patterned MRAM stack. The ion beam etching after forming the gap fill dielectric material above the lower layer is used to clean the sidewalls of the patterned MRAM stack. The ion beam etching that cleans the sidewalls of the patterned MRAM stack can remove the gap fill dielectric material to an etching depth below the depth of the tunnel barrier layer. In some implementations, the etching depth below the depth of the tunnel barrier layer does not reach the depth of the lower layer. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack may also be referred to as "over etching", "trim etching", "IBE trim etching", "sidewall cleaning etching", or "low power trim etching".

[0071] The material deposited on the sidewalls of the patterned MRAM stack may include a metal or a conductive material. The metal or conductive material may be sputtered during the main etching at box 510 and redeposited on the sidewalls of the patterned MRAM stack. In other words, after the main etching, the potentially damaged material that is sputtered back may be located on the sidewalls of the patterned MRAM stack. In some implementations, some metals may include W, Ta, Ti, or TiN from a hard mask layer or an electrode layer, and some metals may include Co, Ni, Pt, or Fe from a first or second magnetic layer. The metal or conductive material forms undesirable residues on the sidewalls of the patterned MRAM stack and degrades the electrical and magnetic properties of the MTJ stack. Ion beam etching is performed at box 530, where ion beam etching is performed at low power and an optimized incident angle to remove undesirable residues.

[0072] When ion beam etching is performed to remove redeposited material on the sidewalls of the patterned MRAM stack, an ion beam may be generated from an ion beam source chamber using a gas mixture containing an inert gas. In some implementations, the gas mixture may contain one or more reactive gases to increase material etching using chemical / reactive components. In some implementations, the gas mixture does not have or substantially does not have reactive gases. Ion beam etching may be performed at a relatively low voltage to remove redeposited material on the sidewalls of the patterned MRAM stack. In some implementations, etching to remove redeposited material on the sidewalls of the patterned MRAM stack may include applying an ion beam having an energy between about 20 eV and about 400 eV to the substrate. IBE trim etching may be performed at a low ion energy relative to the main etching to remove undesirable residues. In some implementations, the IBE trim etching may be performed for about 1 minute or longer, 3 minutes or longer, 5 minutes or longer, or 10 minutes or longer. In some implementations, the IBE trim etch may be performed in alternating first and second directions with or without rotating the substrate.Low ion energy is desirable for trimming to reduce ion-induced mixing effects of the MTJ layer.

[0073] In some implementations, the IBE trim etch can be performed in an ion beam etching tool (e.g. Figure 3The IBE trim etch may be performed after gap fill, after planarization, or after etch back. In some implementations, the IBE trim etch and gap fill may be performed by an integrated tool or a multi-station processing tool. The gap fill operation at box 520 and the IBE trim etch at box 530 may be performed in a manner that does not cause a vacuum break between operations. In some implementations, the main etch at box 510, the gap fill at box 520, and the IBE trim etch at box 530 may be performed in a manner that does not cause a vacuum break between operations.

[0074] The metal or other conductive material is preferably not exposed during the IBE trim etch. The remaining gap fill dielectric material is used as an etch front during the IBE trim etch to significantly reduce any backsputtering of the metal or conductive material. In contrast, with the etch front of the gap fill dielectric material, any backsputtering of the dielectric material does not adversely affect the electrical and magnetic properties of the MTJ stack. The IBE trim etch can remove the gap fill dielectric material to an etch depth below the interface between the tunnel barrier layer and the second magnetic layer without etching into the underlying layer. This maintains the initial etch front from the main etch at block 510 and avoids recessing or substantially recessing into the underlying layer.

[0075] In some implementations, the IBE trim etch removes material deposited on the sidewalls of the patterned MRAM stack. The exposed sidewalls of the patterned MRAM stack have no or substantially no metal or conductive material deposited on the sidewalls of the patterned MRAM stack. The threshold for when the sidewalls are considered sufficiently clean can be set by the short circuit performance of the MRAM device. It is measured as the proportion of short circuit devices among all devices. Typically, only one or less of a million devices will be short circuited. Therefore, any remaining residue is sufficiently thin to cause minimal impact on the off-state impedance of the MRAM device. For example, "substantially free" with respect to redeposited conductive material can mean a deposition thickness of less than about 1.5 nm, less than about 1.0 nm, or less than about 0.5 nm. Therefore, any redeposited conductive material on the tunnel barrier layer after the IBE trim etch is negligible or non-existent. The IBE trim etch can be performed for a sufficient time to remove the undesirable material so that the exposed sidewalls of the patterned MRAM stack have no or substantially no redeposited conductive material.

[0076] Fig. 6E Shows that some implementations are being Fig.6DSchematic diagram of a cross-sectional view of an exemplary IBE trim etch process after an etch back process of . The remaining gap fill dielectric material 680 serves as an etch front during the IBE trim etch process. During the IBE trim etch process, an ion beam 625 is provided at a relatively low ion energy and an optimized incident angle to clean the sidewalls of the patterned MRAM stacks 620a, 620b. As the IBE trim etch process is performed, the ion beam 625 removes the residue 605 from the sidewalls of the patterned MRAM stacks 620a, 620b. Sputtered atoms and / or molecules 675 from the ion beam 625 may be directed toward the sidewalls of the patterned MRAM stacks 620a, 620b. However, the sputtered atoms and / or molecules 675 include dielectric material from the remaining gap fill dielectric material 680, which does not adversely affect the characteristics of the patterned MRAM stacks 620a, 620b. The IBE trim etch process proceeds to an etch depth below the depth of the tunnel barrier layer 670 and above the underlying layer 630. In some implementations, the IBE trim etch process does not penetrate significantly into the underlying layer 630. The exposed sidewalls of the patterned MRAM stack 620a, 620b are free of residues 605 including conductive or magnetic materials.

[0077] In some implementations, process 500 further includes conformally depositing an encapsulation material on at least the exposed sidewalls of the patterned MRAM stack after performing the IBE trim etch at block 530. The encapsulation material may include a suitable dielectric material, such as silicon nitride. The encapsulation material may be deposited to avoid or minimize damage to the tunnel barrier layer that may be exposed to air.

[0078] Fig. 6F Shows that some implementations are being Fig. 6E Schematic diagram of a cross-sectional view of an exemplary encapsulation process after an IBE trim etch process. The encapsulation layer 690 comprises a dielectric material (e.g., silicon nitride) and is conformally deposited on the exposed surfaces of the patterned MRAM stacks 620a, 620b. The encapsulation layer 690 is conformally deposited along the sidewalls of the patterned MRAM stacks 620a, 620b and is used to protect at least the tunnel barrier layer 670 from being exposed to the surrounding environment.

[0079] Figure 7A block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown. The processing system 700 can be a multi-station processing tool having one or more processing stations. The processing system 700 can include an inbound load lock 702 and an outbound load lock 704, one or both of which can include a plasma generation source. A robot 706 at atmospheric pressure is configured to move a substrate from a box loaded through a cabin 708 to the inbound load lock 702 via an atmospheric interface 710. In the inbound load lock 702, the robot 706 places the substrate onto a platform 712, and then the atmospheric port 710 is closed and the load lock 702 is evacuated. The chamber transfer port 716 is opened, the chamber 714 is processed, and another substrate handling system 718 serving as another robot places the substrate into one of the processing stations 780, 782, or from the loading station to the processing station 790 for processing. Although Figure 7 The implementation depicted in FIG. 1 includes a load lock, but it will be appreciated that in some implementations direct access of substrates into a processing station may be provided.

[0080] The processing chamber 714 shown includes three processing stations 780, 782 and 790. The processing station 790 can be a removable module and can be suitable for processing more than one substrate at a time. In this example, the processing station 790 includes four substations, namely Figure 7 Implement numbers 1 to 4 as shown in the scheme.

[0081] Each processing station (780, 782, and each of 1, 2, 3, and 4) may have a heated pedestal and a gas line inlet. It should be understood that in some implementations, each processing station may have different or multiple purposes. For example, in some implementations, processing station 780 may be used to deposit gap fill dielectric material on a substrate, where the deposition technique may be CVD, PECVD, or other suitable deposition techniques. In some implementations, processing station 782 may be used to perform a main etch by IBE, and processing station 790 may be used to perform an IBE trim etch. In certain other implementations, processing station 790 may be used to perform ion beam etching for both the main etch and the IBE trim etch. Processing station 782 may be used to perform other processes, such as CMP, selective etch back, or CVD / PECVD / PVD. In some implementations, processing station 790 may have multiple substations 1-4 for performing multiple IBE trim etch processes or other processes. The IBE trim etch may take longer than the main etch and deposition processes. Although the processing station 790 is shown to include four substations, it should be understood that a processing station according to the present disclosure may include any number of substations. In addition, although the processing system 700 includes three processing stations (780, 782, and 790), it should be understood that in some implementations, the device may include more or less than three processing stations because each processing station may be a removable or modifiable module. For example, in some implementations, the processing system 700 may have four or more processing stations, but in some other implementations, the processing system 700 may have two or fewer processing stations. In some implementations, additional processing stations may be used for planarization processing, such as CMP. In some implementations, additional processing stations may be used for selective etching back to remove gap filling dielectric material.

[0082] In some implementations, the processing system 700 may be an integrated multi-station processing tool for performing IBE (main etch and trim etch) and CVD / PECVD / PVD. For example, processing stations 780, 782, and 790 may be used to perform main etching, gap filling, trim etching, and packaging operations. The operations of main etching, gap filling, trim etching, and packaging may be performed in a manner that does not cause a vacuum to be broken between operations. Additional operations of planarization (e.g., CMP) and / or selective etching back (e.g., plasma etching) may be performed in a separate tool or an integrated multi-station processing tool. It should be understood that since the tunnel barrier layer of the MTJ stack will not be exposed to air or the surrounding environment during planarization or selective etching back, such operations may be performed in a separate tool. The tunnel barrier layer is protected by the gap filling dielectric material during planarization or selective etching back.

[0083] Figure 7A substrate handling system 718 is shown for transferring substrates within the processing system 700. In some implementations, the substrate handling system 718 can transfer substrates between various processing stations and / or between a processing station and a load lock. In addition, the processing station 790 can include a separate substrate handling system 760 for moving a substrate from another loading station 762 to the processing station 790. It should be understood that any suitable substrate handling system can be used. Non-limiting examples include a substrate turntable and a substrate handling robot.

[0084] In various implementations, integration of various stations can address footprint reduction issues and can efficiently transfer substrates between operations without causing a vacuum breach. Figure 7 Also shown is an implementation of a system controller 750 for controlling processing conditions and hardware states of the processing system 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. Aspects of the system controller 750 are described above with reference to Figure 3 Depending on the process step or steps to be performed by the tool, the system controller 750 may communicate with one or more of: circuits or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within a factory, a host computer, another controller, or tools used in material transport to transport substrate containers to and from tool locations.

[0085] Figure 8 An alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown. Processing system 800 includes a conveyor module 803. Conveyor module 803 provides a clean pressurized environment to minimize the risk of contamination when the substrate being processed moves between various reactor modules. Multi-station reactors 807, 808, and 809 mounted to conveyor module 803 are referred to as reactors or tool modules or simply modules in this context, and each reactor is capable of ion beam etching and / or deposition. Reactors 807, 808, and 809 may include multiple stations 811, 813, 815, and 817 that can be operated in sequence or not in sequence according to the disclosed implementations. Each of stations 811, 813, 815, and 817 may be a heated pedestal or substrate support, one or more gas inlets or showerheads, or a dispersion plate. One or more of modules 807, 808, and 809 are capable of ion beam etching, wherein ion beam etching can be used to perform main etching and / or trim etching. Therefore, one or more of modules 807, 808 and 809 may include a Figure 3807, 808 and 809. Another one or more of modules 807, 808 and 809 may be capable of performing deposition operations such as CVD / PECVD / PVD. Thus, the operations of main etching, gap filling, trim etching and packaging may be performed in a manner that does not result in a vacuum break between operations.

[0086] The processing system 800 may also include one or more substrate source modules 801 in which substrates are stored before and after processing. The atmospheric robot 804 and the atmospheric transfer chamber 819 may first remove the substrate from the source module 801 and transfer it to the load lock 821. The second substrate transfer device (usually a robot arm unit) in the transfer module 803 moves the substrate from the load lock 821 to a module on the transfer module 803 in a pressurized (e.g., vacuum) environment or moves the substrate between modules.

[0087] In various implementations, the system controller 829 is used to control processing conditions and activities during processing. The system controller 829 typically includes one or more memory devices and one or more processors. Aspects of the system controller 829 are described above with reference to Figure 3 Depending on the process step or steps to be performed by the tool, the system controller 829 may communicate with one or more of: circuits or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within a factory, a host computer, another controller, or tools used in material transport to transport substrate containers to and from tool locations.

[0088] Fig. 9 A block diagram of an exemplary processing system for performing planarization and / or etching processes is shown according to some implementations. Processing systems 700 and 800 can be integrated multi-station processing tools for performing ion beam etching and deposition, and can transfer the substrate to processing system 900 for performing planarization and / or selective etching processes.

[0089] The processing system 900 may include a vacuum transfer module 938 (VTM). The configuration of multiple transfer modules for transferring substrates between multiple storage facilities and processing modules may be referred to as a "cluster tool architecture" system. An airlock 930 (also referred to as a load lock or transfer module) is shown located in a vacuum transfer module 938 having four processing modules 920a, 920b, 920c, and 920d, which may be individually optimized to perform various operations. For example, one or more of the processing modules 920a, 920b, 920c, and 920d may be used for selective etching. One or more of the processing modules 920a, 920b, 920c, and 920d may be used for planarization, such as CMP. In some implementations, one or more of the processing modules 920a, 920b, 920c, and 920d may be used for ion beam etching or deposition. The airlock 930 and process modules 920a, 920b, 920c, and 920d may be referred to as "stations." Each station has a facet 936 that interfaces the station with a vacuum transfer module 938. Sensors 1-18 are used within each facet 936 to detect the passage of a substrate 926 as it moves between stations.

[0090] The robot 922 may be used to transfer substrates 926 between stations. In one implementation, the robot 922 may have a single arm, and in another implementation, the robot 922 has dual arms, where each arm has an end effector 924 for picking up a substrate (e.g., substrate 926) for transfer. A front end robot 932 in an atmospheric transfer module (ATM) 940 is used to transfer substrates 926 from a wafer box or a front opening unit (FOUP) 934 in a load port module (LPM) 942 to an air lock 930. The module center 928 within the processing modules 920a, 920b, 920c, and 920d is a location for placing the substrate 926. An alignment device 944 in the ATM 940 is used to align the substrate.

[0091] In an exemplary processing method, a substrate is placed into one of the FOUPs 934 in the LPM 942. The front-end robot 932 transfers the substrate from the FOUP 934 to the alignment device 944, which can properly center the substrate 926 before the substrate 926 is etched or processed. After alignment, the substrate 926 is moved into the air lock 930 by the front-end robot 932. Since the air lock module has the ability to match the environment between the ATM and the VTM, the substrate 926 can be moved between the two pressure environments without being damaged. The robot 922 moves the substrate 926 from the air lock 930 to one of the processing modules 920a, 920b, 920c and 920d via the vacuum transfer module 938. In order to achieve this substrate movement, the robot 922 uses the end effector 924 on each of its arms. Once the substrate 926 has been processed, the robot 922 moves the substrate 926 from the processing modules 920a, 920b, 920c, and 920d into the airlock 930. From here, the front end robot 932 can move the substrate 926 to one of the FOUPs or to the alignment device 944. Fig. 9 The tools in the above are used to implement Figure 3 Depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of: circuits or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within a factory, a host computer, another controller, or tools used in material transport to transport substrate containers to and from tool locations.

[0092] in conclusion

[0093] In the above description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, well-known process operations are not described in detail to avoid obscuring the disclosed embodiments. Although the disclosed embodiments are described in conjunction with specific embodiments, it should be understood that this is not intended to limit the disclosed embodiments.

[0094] Although the foregoing embodiments have been described in detail for the purpose of clear understanding, it is apparent that certain changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and equipment of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. An ion beam etching method, the method comprising: Etching through a plurality of MRAM layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, wherein etching through the plurality of MRAM layers includes ion beam etching through at least the tunnel barrier layer; forming a gap-fill dielectric material in spaces between the patterned magnetoresistive random access memory stacks; and performing an ion beam trim etch to remove at least some of the gap fill dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stack, in, The gap-fill dielectric material remaining after the ion beam etch trim etch reaches a depth below the tunnel barrier layer and is located above an underlying layer disposed between the substrate and the plurality of magnetoresistive random access memory layers.

2. The method of claim 1 , wherein the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of magnetoresistive random access memory layers such that performing the ion beam trim etch does not cause a recess in the underlying layer. 3 . The method of claim 2 , wherein the sufficient depth above the underlying layer is between 1 nm and 20 nm above an upper surface of the underlying layer.

4. The method of claim 1 , wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks comprises: The gap-fill dielectric material is deposited in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

5. The method of claim 4, wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks further comprises: The gap-fill dielectric material is selectively etched to an etch depth above a depth of the tunnel barrier layer.

6. The method according to claim 5, further comprising: The gap-fill dielectric material disposed over the patterned MRAM stack is planarized.

7. The method of any one of claims 1-6, wherein the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof.

8. The method of claim 7, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

9. The method of any one of claims 1-6, wherein the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the ion beam etch trim etch are performed in a manner that does not result in a vacuum breach between operations.

10. The method of claim 1 , wherein the plurality of magnetoresistive random access memory layers comprises a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, wherein the underlayer comprises a dielectric material, and wherein the tunnel barrier layer comprises a non-magnetic insulating material.

11. The method of claim 10, wherein etching through the plurality of magnetoresistive random access memory layers comprises the ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer but not through the underlying layer.

12. The method of claim 10, wherein etching through the plurality of MRAM layers comprises reactive ion etching (RIE) through the first magnetic layer and ion beam etching through the tunnel barrier layer.

13. The method of claim 10, wherein etching through the plurality of MRAM layers comprises etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, wherein etching through the plurality of MRAM layers stops on the underlying layer.

14. The method of any one of claims 1-6, wherein ion beam etching to etch through at least the tunnel barrier layer comprises applying a first ion beam having an energy between 200 eV and 10,000 eV to the substrate, and wherein performing ion beam trim etching comprises applying a second ion beam having an energy between 20 eV and 400 eV to the substrate.

15. The method according to any one of claims 1 to 6, wherein the ion beam etching trim etching is performed in a manner not to etch through an underlying layer disposed below the plurality of magnetoresistive random access memory layers.

16. The method of any one of claims 1-6, wherein the conductive material comprises tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe) platinum (Pt), ruthenium (Ru) or a combination thereof, and wherein after performing the ion beam etching trim etching, the sidewalls of the patterned magnetoresistive random access memory stack are substantially free of the conductive material deposited on the sidewalls of the patterned magnetoresistive random access memory stack.

17. The method according to any one of claims 1 to 6, further comprising: After performing the ion beam etch trim etch, an encapsulation material is conformally deposited onto at least the sidewalls of the patterned magnetoresistive random access memory stack.

18. An apparatus for performing ion beam etching, the apparatus comprising: Ion beam source chamber; a processing chamber coupled to the ion beam source chamber; A controller configured to provide instructions to: Disposing a plurality of magnetoresistive random access memory layers on a substrate in the processing chamber, the plurality of magnetoresistive random access memory layers comprising one or more magnetic layers and a tunnel barrier layer; Etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, wherein etching through the plurality of MRAM layers comprises etching through at least the tunnel barrier layer by ion beam etching (ion beam etching); forming a gap-fill dielectric material in spaces between the patterned magnetoresistive random access memory stacks; as well as An ion beam etching trim etch is performed to remove at least some of the gap filling dielectric material and the conductive material deposited on the sidewalls of the patterned magnetoresistive random access memory stack, wherein the gap filling dielectric material remaining after the ion beam etching trim etch reaches a depth below the tunnel barrier layer and is located above a lower layer disposed between the substrate and the plurality of magnetoresistive random access memory layers.

19. The apparatus of claim 18, wherein the controller configured to provide instructions for forming the gap-fill dielectric material is further configured to provide instructions to: The gap-fill dielectric material is deposited in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

20. The apparatus of claim 19, wherein the controller configured to provide instructions to form the gap-fill dielectric material is further configured to provide instructions to: The gap-fill dielectric material is selectively etched to an etch depth above a depth of the tunnel barrier layer.

21. The apparatus of claim 20, wherein the controller is further configured to provide instructions to: Prior to selectively etching the gap-fill dielectric material, the gap-fill dielectric material deposited over the patterned magnetoresistive random access memory stack is planarized.

22. The apparatus of any of claims 18-21, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

23. The apparatus of any one of claims 18-21, wherein the controller configured to provide instructions to ion beam etch through at least the tunnel barrier layer is further configured to provide instructions to apply a first ion beam having an energy between 200 eV and 10,000 eV to the substrate, and wherein the controller configured to provide instructions to perform the ion beam trim etching is further configured to apply a second ion beam having an energy between 20 eV and 400 eV to the substrate.

24. The apparatus of any one of claims 18-21, wherein the gap-fill dielectric material is formed to a sufficient depth above an underlying layer between the substrate and the plurality of magnetoresistive random access memory layers so that performing the ion beam trim etch does not cause a recess in the underlying layer.

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