Analog Current Generation Circuit and Method for Power Conversion Circuit

Abstract

The present invention discloses an analog current generation circuit and method for a power conversion circuit to provide an analog sensing current. The analog sensing current includes an AC component current and a DC component current. The analog current generation circuit includes a first current circuit, a second current circuit, a synthesis circuit, and a correction circuit. The first current circuit generates a ramp signal to serve as the AC component current. The second current circuit is coupled to the output stage of the power conversion circuit to provide a sensing current. The sensing current generates a DC component current after being sampled and held. The synthesis circuit is respectively coupled to the first current circuit and the second current circuit to synthesize the AC component current and the DC component current into an analog sensing current. The correction circuit is respectively coupled to the first current circuit, the second current circuit, and the synthesis circuit to dynamically adjust the ramp signal according to the analog sensing current and the sensing current. The present invention predicts the change of the actual inductor current in an all-analog manner, effectively overcomes the problems of inability to obtain the instantaneous sensing current waveform, high circuit cost, high control difficulty, etc., and can also instantaneously correct the AC component current through the correction circuit to improve the accuracy of the sensing current.

Description

Technical Field

[0001] The present invention relates to a power conversion circuit, and more particularly to an analog current generation circuit and method for a power conversion circuit. Background Art

[0002] In the field of buck or boost power conversion circuits, as the system operating frequency increases, when the switching switch of the output stage of the power conversion circuit switches at high speed, the on-time of the switching switch is very short, resulting in the inability of the traditional current sensing circuit to immediately sense the waveform of the inductor current.

[0003] To improve the above deficiencies, there is an existing method of obtaining the sensed current through the Sample&Hold method. The problem with this method is that the sensed current waveform is not immediate enough; another existing method is to synthesize a complete current waveform by combining a part of the analog current and a part of the sensed current. Its disadvantages include high circuit cost and high control difficulty. Therefore, the above problems encountered in the prior art still need to be solved urgently. Summary of the Invention

[0004] The present invention provides an analog current generation circuit and method for a power conversion circuit to effectively solve the above problems encountered in the prior art.

[0005] According to a specific embodiment of the present invention, there is an analog current generation circuit for a power conversion circuit. In this embodiment, the analog current generation circuit is used to provide an analog sensed current. The analog sensed current includes an AC component current and a DC component current. The current sensing circuit includes a first current circuit, a second current circuit, a synthesis circuit, and a correction circuit. The first current circuit generates a ramp signal as the AC component current. The second current circuit is coupled to the output stage of the power conversion circuit to provide a sensed current. The sensed current is sampled and held to generate a DC component current. The synthesis circuit is respectively coupled to the first current circuit and the second current circuit to synthesize the AC component current and the DC component current into an analog sensed current. The correction circuit is respectively coupled to the first current circuit, the second current circuit, and the synthesis circuit to dynamically adjust the ramp signal according to the analog sensed current and the sensed current.

[0006] In one embodiment, the output stage is coupled to an inductor, and the sensed current is related to the inductor current flowing through the inductor.

[0007] In one embodiment, the analog current generation circuit further includes at least one sample and hold circuit, coupled between the second current circuit and the synthesis circuit, to perform a sample and hold process on the sensed current to generate a DC component current.

[0008] In one embodiment, the calibration circuit includes a subtraction circuit that receives an analog sense current and a sense current to generate a difference signal, and the calibration circuit generates a calibration signal according to the difference signal and sends it to the first current circuit.

[0009] In one embodiment, the calibration circuit further includes an integration circuit and a comparison circuit. The integration circuit receives the difference signal to generate a difference voltage, and the comparison circuit generates a calibration signal according to the difference voltage.

[0010] Another specific embodiment according to the present invention is an analog current generation method. In this embodiment, the analog current generation method provides an analog sense current. The analog sense current includes an AC component current and a DC component current. The analog current generation method includes: (a) providing a ramp signal as the AC component current; (b) performing a sampling and holding process on the sense current to generate the DC component current; (c) synthesizing the AC component current and the DC component current to form the analog sense current; and (d) dynamically adjusting the ramp signal according to the analog sense current and the sense current.

[0011] In one embodiment, the sense current is related to an inductor current flowing through an output inductor.

[0012] In one embodiment, step (d) further includes: adjusting the slope of the ramp signal.

[0013] In one embodiment, step (d) further includes: integrating the difference between the analog sense current and the sense current to adjust the ramp signal.

[0014] In one embodiment, step (b) includes: (b1) obtaining the sense current; and (b2) performing at least one sampling and holding on the valley value of the sense current according to a pulse width modulation signal at a second time to obtain the DC component current.

[0015] Compared with the prior art, the analog current generation circuit and the analog current generation method of the power conversion circuit of the present invention set the AC component current (i.e., the waveform of the analog sense current), determine the DC component current (i.e., the valley value of the analog sense current) according to the minimum value of the sense current, and then synthesize the two to form the analog sense current. Since the analog current generation circuit and the analog current generation method of the present invention predict the change of the actual inductor current in a fully analog manner, they can effectively overcome the problems of the prior art such as inability to obtain the instantaneous sense current waveform, high circuit cost, and high control difficulty. Moreover, the AC component current (i.e., the waveform of the analog sense current) can be corrected in real time through the calibration circuit to improve the accuracy of the sense current.

[0016] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the power conversion circuit of the present invention.

[0018] Figure 2 Schematic diagram of the analog current generation circuit in the power conversion circuit of the present invention.

[0019] Figure 3A Schematic diagram of the analog current generation circuit applied to a buck power converter of the present invention.

[0020] Figure 3B Schematic diagram of the analog current generation circuit applied to a boost power converter of the present invention.

[0021] Figure 4A Waveform timing diagram of obtaining the DC component current through the sampling and holding circuit.

[0022] Figure 4B Waveform timing diagram of synthesizing the AC component current and the DC component current into an analog sense current through the synthesis circuit.

[0023] Figure 5A and Figure 5B Schematic diagram and waveform timing diagram respectively showing poor accuracy of the DC component current generated when the analog current generation circuit samples through only a single sampling and holding circuit.

[0024] Figure 6A and Figure 6B Schematic diagram and waveform timing diagram respectively showing better accuracy of the DC component current generated when the analog current generation circuit samples through two cascaded sampling and holding circuits.

[0025] Figure 7A and Figure 7B Schematic diagram and waveform timing diagram of a calibration process of the analog sense current of the analog current generation circuit.

[0026] Figure 8A and Figure 8B Schematic diagram and waveform timing diagram of another calibration process of the analog sense current of the analog current generation circuit.

[0027] Figure 9 Flowchart of the analog current generation method of the present invention

[0028] Description of main component symbols:

[0029] 1 Power conversion circuit

[0030] 10 Control circuit

[0031] 12 Integrated driver

[0032] 100 Error amplifier

[0033] 102 Comparison Circuit

[0034] 104 Pulse Width Modulation Circuit

[0035] 106 Current Sensing Circuit

[0036] 120 Drive Circuit

[0037] 122 Analog Current Generation Circuit

[0038] M1 First Switch

[0039] M2 Second Switch

[0040] OS Output Stage

[0041] L Inductor

[0042] C Capacitor

[0043] R Resistor

[0044] FB First Pin

[0045] PWM1 Second Pin

[0046] CSP Third Pin

[0047] CSN Fourth Pin

[0048] PWM2 Fifth Pin

[0049] IOUT Sixth Pin

[0050] SW Seventh Pin

[0051] VIN Input Voltage

[0052] VOUT Output Voltage

[0053] VFB Feedback Voltage

[0054] RAMP Ramp Signal

[0055] COMP Comparison Signal

[0056] CG1 First Current Circuit

[0057] CG2 Second Current Circuit

[0058] SH Sample and Hold Circuit

[0059] ADD Synthesis Circuit

[0060] 1220 Calibration Circuit

[0061] SUB Subtraction Circuit

[0062] INT Integrating Circuit

[0063] COM Comparison Circuit

[0064] ADJ Adjustment Circuit

[0065] RSET Setting Resistor

[0066] GND Ground Terminal

[0067] IRP AC Component Current (Ramp Signal)

[0068] ISEN Sensing Current

[0069] IDC DC Component Current

[0070] IOUT Analog Sensing Current

[0071] IDIF Difference Signal

[0072] VDIF Difference Voltage

[0073] VREF Reference Voltage

[0074] CS Correction Signal

[0075] IL Inductor Current

[0076] SW Switch Control Signal

[0077] SWB Inverted Switch Control Signal

[0078] COU Counter

[0079] DAC Digital-to-Analog Circuit

[0080] CTV Count Value

[0081] 3 Analog Current Generation Circuit

[0082] 30 Second Current Circuit

[0083] 32 Sample-and-Hold Circuit

[0084] 34 Correction Circuit

[0085] 36 First Current Circuit

[0086] IDC1 Minimum Value of Sensing Current (Valley Value)

[0087] t1 to t6 Time

[0088] 50 Second Current Circuit

[0089] 52 Sample-and-Hold Circuit

[0090] 54 Sampling and Holding Circuit

[0091] The sensed current after sampling of ISEN’

[0092] SH1 to SH2 First Sampling Circuit to Second Sampling Circuit

[0093] m Scaling ratio of sensed current

[0094] S1 to S4 Current area

[0095] SUB1 to SUB2 First Subtraction Circuit to Second Subtraction Circuit

[0096] IDIFA to IDIFB First Difference to Second Difference

[0097] IACC Accumulated current

[0098] IDIF1 to IDIF2 Difference signal

[0099] VTI1 to VTI2 Voltage to current circuit

[0100] 90 Correction circuit

[0101] MUL Multiplication circuit

[0102] IS Output current

[0103] Idis Discharge current source

[0104] VRP Ramp voltage

[0105] S10 to S16 Steps Detailed implementation manners

[0106] Now, reference will be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments will be described in the drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0107] According to a specific embodiment of the present invention, an analog current generation circuit is provided. In this embodiment, the analog current generation circuit can be applied to a switched-mode power conversion circuit (such as a buck power conversion circuit or a boost power conversion circuit) to provide an analog sensed current in a fully analog manner, but not limited thereto.

[0108] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the power conversion circuit 1. As Figure 1As shown, the power conversion circuit 1 includes a control circuit (Controller) 10, an integrated driver (DrMOS) 12, an inductor L, and a capacitor C. The integrated driver 12 is coupled to the control circuit 10. One end of the inductor L is coupled to the integrated driver 12. The control circuit 10 is coupled to the other end of the inductor L. One end of the capacitor C is coupled to the other end of the inductor L, and the other end of the capacitor C is coupled to the ground terminal GND.

[0109] The control circuit 10 includes an error amplifier 100, a comparison circuit 102, a pulse width modulation circuit 104, a current sensing circuit 106, a first pin FB, a second pin PWM1, a third pin CSP, and a fourth pin CSN.

[0110] The input terminal + of the error amplifier 100 is coupled to the first pin FB, and its input terminal - receives a reference voltage VREF, for generating an error amplification signal COMP according to the reference voltage VREF and the feedback voltage VFB of the first pin FB.

[0111] The input terminal + of the comparison circuit 102 is coupled to the output terminal of the error amplifier 100, and its input terminal - receives a ramp signal RAMP, for comparing the error amplification signal COMP with the ramp signal RAMP to generate a comparison result.

[0112] The pulse width modulation circuit 104 is respectively coupled to the output terminal of the comparison circuit 102, the current sensing circuit 106, and the second pin PWM1, for generating a pulse width modulation signal according to the comparison result of the error amplification signal COMP and the ramp signal RAMP and outputting it through the second pin PWM1. The current sensing circuit 106 is respectively coupled to the pulse width modulation circuit 104, the third pin CSP, and the fourth pin CSN, for providing a sensing current and outputting it through the third pin CSP and the fourth pin CSN.

[0113] The integrated driver 12 includes a driving circuit 120, an analog current generating circuit 122, a first switch M1, a second switch M2, a fifth pin PWM2, a sixth pin IOUT, and a seventh pin SW. The fifth pin PWM2 is coupled to the second pin PWM1 of the control circuit 10. The driving circuit 120 is respectively coupled to the fifth pin PWM2, the control end of the first switch M1, and the control end of the second switch M2. The sixth pin IOUT is coupled to the third pin CSP of the control circuit 10. One ends of the resistor R and the capacitor C are both coupled between the third pin CSP and the sixth pin IOUT, and the other ends of the resistor R and the capacitor C are both coupled to the reference voltage VREF. The first switch M1 is coupled between the input voltage VIN and the second switch M2, and the control end of the first switch M1 is coupled to the driving circuit 120. The second switch M2 is coupled between the first switch M1 and the analog current generating circuit 122, and the control end of the second switch M2 is coupled to the driving circuit 120. The analog current generating circuit 122 is respectively coupled to the sixth pin IOUT and both ends of the second switch M2.

[0114] One end of the inductor L is coupled to between the first switch M1 and the second switch M2 through the seventh pin SW, and the other end of the inductor L is coupled to the output voltage VOUT. The inductor current IL flowing through the inductor L comes from between the first switch M1 and the second switch M2. The capacitor C is coupled between the output voltage VOUT and the ground terminal GND. In this embodiment, the output stage OS of the power conversion circuit 1 includes the first switch M1, the second switch M2, the inductor L, and the capacitor C, but is not limited thereto.

[0115] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the analog current generating circuit 122 in the power conversion circuit 1.

[0116] As Figure 2 shown, the analog current generating circuit 122 includes a first current circuit CG1, a second current circuit CG2, a sampling and holding circuit SH, a synthesizing circuit ADD, and a correction circuit 1220, and has an optional setting resistor pin PIN.

[0117] The setting resistor pin PIN is coupled to one end of an external setting resistor RSET, and the other end of the setting resistor RSET is coupled to the ground terminal GND. The first current circuit CG1 is respectively coupled to the setting resistor pin PIN, the synthesizing circuit ADD, and the correction circuit 1220. The second current circuit CG2 is respectively coupled to the sampling and holding circuit SH, the correction circuit 1220, and both ends of an external second switch M2 (not shown in Figure 2)。The sampling and holding circuit SH is coupled between the second current circuit CG2 and the synthesizing circuit ADD. The synthesizing circuit ADD is respectively coupled to the first current circuit CG1, the sampling and holding circuit SH, and the calibration circuit 1220. The calibration circuit 1220 is respectively coupled to the second current circuit CG2, the synthesizing circuit ADD, and the first current circuit CG1.

[0118] It should be noted that the first current circuit CG1 is coupled to the set resistor RSET through the set resistor pin PIN, and the resistance value of the set resistor RSET is related to the inductance value of the inductor L, so that the initial waveform of the first current generated by the first current circuit CG1 is closer to the true current waveform, but not limited thereto.

[0119] The first current circuit CG1 generates a ramp signal as the AC component current IRP and provides it to the synthesizing circuit ADD. The second current circuit CG2 is coupled to the output stage OS of the power conversion circuit 1 to respectively provide the sense current ISEN to the sampling and holding circuit SH and the calibration circuit 1220. In practical applications, the sense current ISEN is related to the inductor current IL flowing through the inductor L in the output stage OS, but not limited thereto.

[0120] When the sampling and holding circuit SH receives the sense current ISEN, the sampling and holding circuit SH will perform sampling and holding processing on the sense current ISEN and then generate a DC component current IDC to the synthesizing circuit ADD. In practical applications, the DC component current IDC is a fixed current value and is the minimum value (valley value) of the sense current ISEN / inductor current IL, but not limited thereto.

[0121] When the synthesizing circuit ADD respectively receives the AC component current IRP from the first current circuit CG1 and the DC component current IDC from the sampling and holding circuit SH, the synthesizing circuit ADD will synthesize the AC component current IRP and the DC component current IDC into an analog sense current IOUT and output it to the calibration circuit 1220.

[0122] When the calibration circuit 1220 respectively receives the sense current ISEN from the second current circuit CG2 and the analog sense current IOUT from the synthesizing circuit ADD, the calibration circuit 1220 will generate a calibration signal CS to the first current circuit CG1 according to the sense current ISEN and the analog sense current IOUT, so as to dynamically adjust the slope of the ramp signal (i.e., the AC component current IRP provided to the synthesizing circuit ADD) generated by the first current circuit CG1, so that the analog sense current IOUT is m times the inductor current IL, where m is the sense current scaling ratio.

[0123] In one embodiment, as Figure 2As shown, the calibration circuit 1220 includes a subtraction circuit SUB, an integration circuit INT, a comparison circuit COM, and an adjustment circuit ADJ. The subtraction circuit SUB is respectively coupled to the second current circuit CG2, the synthesis circuit ADD, and the integration circuit INT. The integration circuit INT is coupled between the subtraction circuit SUB and the input terminal + of the comparison circuit COM. The input terminal - of the comparison circuit COM receives a reference voltage VREF. The output terminal of the comparison circuit COM is coupled to the adjustment circuit ADJ. The adjustment circuit ADJ is coupled to the first current circuit CG1.

[0124] When the subtraction circuit SUB respectively receives the sensed current ISEN from the second current circuit CG2 and the analog sensed current IOUT from the synthesis circuit ADD, the subtraction circuit SUB subtracts the analog sensed current IOUT from the sensed current ISEN to generate a difference signal IDIF to the integration circuit INT.

[0125] When the integration circuit INT receives the difference signal IDIF, the integration circuit INT integrates the difference signal IDIF from a first time to a second time to generate a difference voltage VDIF to the input terminal + of the comparison circuit COM.

[0126] When the input terminal + and the input terminal - of the comparison circuit COM respectively receive the difference voltage VDIF and the reference voltage VREF, the comparison circuit COM compares the difference voltage VDIF with the reference voltage VREF and outputs its comparison result VCOM to the adjustment circuit ADJ. The adjustment circuit ADJ generates a calibration signal CS to the first current circuit CG1 according to the comparison result VCOM, so as to dynamically adjust the slope of the ramp signal (i.e., the AC component current IRP provided to the synthesis circuit ADD) generated by the first current circuit CG1, such that the analog sensed current IOUT is m times the inductor current IL, where m is the sensed current scaling ratio.

[0127] In an embodiment, the adjustment circuit ADJ includes a counter COU and a digital-to-analog circuit DAC. The counter COU is coupled to the output terminal of the comparison circuit COM and the digital-to-analog circuit DAC. The digital-to-analog circuit DAC is coupled to the counter COU and the first current circuit CG1.

[0128] When the counter COU receives the comparison result VCOM of the difference voltage VDIF provided by the comparison circuit COM and the reference voltage VREF, if the comparison result VCOM indicates that the difference voltage VDIF is greater than the reference voltage VREF, it represents that the analog sensing current IOUT is too large. At this time, the count value CTV provided by the counter COU will be decreased by 1. If the comparison result VCOM indicates that the difference voltage VDIF is less than or equal to the reference voltage VREF, it represents that the analog sensing current IOUT is too small. At this time, the count value CTV provided by the counter COU will be increased by 1. In fact, the reference voltage VREF can be zero, but not limited thereto.

[0129] Then, the digital-to-analog circuit DAC sends a correction signal CS to the first current circuit CG1 according to the count value CTV of the counter COU, so as to dynamically adjust the slope of the ramp signal (i.e., the AC component current IRP provided to the synthesis circuit ADD) generated by the first current circuit CG1 by adjusting the variable current source in the first current circuit CG1.

[0130] In practical applications, the analog current generation circuit of the present invention can be applied to various switched DC-DC power converters, such as a buck power conversion circuit or a boost power conversion circuit, but not limited thereto. In addition, the analog current generation circuit of the present invention selects the switch with a relatively long on-time in the output stage for current sensing, but not limited thereto.

[0131] Taking the buck power converter as an example, please refer to Figure 3A , its output stage OS includes a first switch M1, a second switch M2, an inductor L and a capacitor C. The first switch M1 and the second switch M2 are connected in series between the input voltage VIN and the ground terminal GND, and the control terminals of the first switch M1 and the second switch M2 are respectively controlled by the switch control signals SW and SWB that are inverted with respect to each other. One end of the inductor L is coupled between the first switch M1 and the second switch M2, and the other end of the inductor L is coupled to the output voltage VOUT. The capacitor C is coupled between the output voltage VOUT and the ground terminal GND.

[0132] The analog current generation circuit 3 includes a second current circuit 30, a sample and hold circuit 32, a correction circuit 34, a synthesis circuit ADD and a first current circuit 36. The sample and hold circuit 32 is coupled between the second current circuit 30 and the synthesis circuit ADD. The synthesis circuit ADD is respectively coupled to the sample and hold circuit 32, the first current circuit 36 and the correction circuit 34. The correction circuit 34 is respectively coupled to the second current circuit 30, the synthesis circuit ADD and the first current circuit 36. The first current circuit 36 is respectively coupled to the synthesis circuit ADD and the correction circuit 34.

[0133] It should be noted that for a buck power converter, in applications with a high transformer ratio, the conduction time of the low-side switch (i.e., the second switch M2) in the output stage OS is relatively long. Therefore, the second current circuit 30 will select the second switch with a longer conduction time and couple it to both ends of the second switch M2 for current sensing, so as to provide a sensing current ISEN related to the inductor current IL flowing through the inductor L to the sample and hold circuit 32 and the correction circuit 34.

[0134] The first current circuit 36 receives the input voltage VIN, the output voltage VOUT, and the switching control signal SW of the first switch M1 respectively, and generates a ramp signal as the AC component current IRP based on these and supplies it to the synthesis circuit ADD.

[0135] When the sample and hold circuit 32 receives the sensing current ISEN related to the inductor current IL, the sample and hold circuit 32 will perform sample and hold processing on the sensing current ISEN and then generate a DC component current IDC to the synthesis circuit ADD.

[0136] For example, as Figure 4A and Figure 4B shown, at time t1, the switching control signal SW for controlling the first switch M1 changes from a high level to a low level, that is, the first switch M1 is non-conductive and the second switch M2 is conductive. Therefore, the second current circuit 30 coupled to both ends of the second switch M2 starts to provide the sensing current ISEN, and the sensing current ISEN, like the inductor current IL, will decrease from a higher current value until time t2.

[0137] At time t2, the switching control signal SW changes from a low level to a high level again, that is, the first switch M1 is conductive and the second switch M2 is non-conductive. Therefore, the second current circuit 30 coupled to both ends of the second switch M2 stops providing the sensing current ISEN, and the current value IDC1 of the sensing current ISEN at time t2 is the minimum value (valley value) of the sensing current ISEN / inductor current IL, and the DC component current IDC can be obtained based on the current value IDC1.

[0138] When the synthesis circuit ADD receives the AC component current IRP from the first current circuit 36 and the DC component current IDC from the sample and hold circuit 32 respectively, the synthesis circuit ADD will synthesize the AC component current IRP and the DC component current IDC into an analog sensing current IOUT and output it to the correction circuit 34. For example, the synthesis circuit ADD can be an adder circuit or a circuit node for adding the AC component current IRP and the DC component current IDC to each other to obtain the analog sensing current IOUT.

[0139] When the calibration circuit 34 receives the sensed current ISEN from the second current circuit 30 and the analog sensed current IOUT from the synthesis circuit ADD respectively, the calibration circuit 34 generates a calibration signal CS based on the sensed current ISEN and the analog sensed current IOUT to the first current circuit 36, so as to dynamically adjust the slope of the ramp signal generated by the first current circuit 36 (i.e., the AC component current IRP provided to the synthesis circuit ADD), such that the analog sensed current IOUT is m times the inductor current IL, where m is the sensed current scaling ratio.

[0140] Taking a boost-type power conversion circuit as an example, please refer to Figure 3B , whose output stage OS includes a first switch M1, a second switch M2, an inductor L, and a capacitor C. The first switch M1 and the second switch M2 are connected in series between the output voltage VOUT and the ground terminal GND, and the control terminals of the first switch M1 and the second switch M2 are controlled by switch control signals SWB and SW that are inverted with respect to each other. One end of the inductor L is coupled between the first switch M1 and the second switch M2, and the other end of the inductor L is coupled to the input voltage VIN. The capacitor C is coupled between the output voltage VOUT and the ground terminal GND.

[0141] The analog current generation circuit 3 includes a second current circuit 30, a sample and hold circuit 32, a calibration circuit 34, a synthesis circuit ADD, and a first current circuit 36. The sample and hold circuit 32 is coupled between the second current circuit 30 and the synthesis circuit ADD. The synthesis circuit ADD is coupled to the sample and hold circuit 32, the first current circuit 36, and the calibration circuit 34 respectively. The calibration circuit 34 is coupled to the second current circuit 30, the synthesis circuit ADD, and the first current circuit 36 respectively. The first current circuit 36 is coupled to the synthesis circuit ADD and the calibration circuit 34 respectively.

[0142] For a boost-type power conversion circuit, in applications with a high transformer ratio, the conduction time of the high-side switch (i.e., the first switch M1) in its output stage OS is relatively long. Therefore, the second current circuit 30 selects the first switch M1 with a long conduction time and is coupled to both ends of the first switch M1 for current sensing, so as to provide the sensed current ISEN related to the inductor current IL flowing through the inductor L to the sample and hold circuit 32 and the calibration circuit 34.

[0143] The generation method of the analog sensed current IOUT of the boost-type power conversion circuit is similar to that of the buck-type power conversion circuit, so it will not be elaborated here.

[0144] Next, please refer to Figure 5A and Figure 5B, if only one sample-and-hold circuit 52 is used in the analog current generation circuit, during the sampling period of the sample-and-hold circuit 52 (for example, Figure 5B from time t2 to t3, the sampling signal VSH is HIGH), the DC component current IDC generated by it will have the same waveform as the sensed current ISEN and cannot be maintained at a fixed current value IDC1, resulting in poor accuracy.

[0145] Therefore, in a preferred embodiment, as shown in Figure 6A and Figure 6B , the analog current generation circuit may include two sample-and-hold circuits 52 and 54 connected in series with each other. By sampling and holding the inductor current IL for the first time from time t1 to t2 to generate the sensed current ISEN, and sampling and holding the sensed current ISEN for the second time from time t2 to t3 to generate the sampled sensed current ISEN', the DC component current IDC generated by it can always be maintained at a fixed current value IDC1, thereby effectively improving its accuracy.

[0146] In practical applications, the calibration circuit 34 can subtract the analog sensed current IOUT provided by the synthesis circuit ADD from the sensed current ISEN provided by the second current circuit 30 to obtain a difference, perform an operation on the difference, and then fine-tune the slope of the ramp signal (i.e., the AC component current IRP provided to the synthesis circuit ADD) provided by the first current circuit 36 according to the operation result, thereby calibrating the analog sensed current IOUT provided by the synthesis circuit ADD to make it closer to the actual inductor current IL.

[0147] Next, two embodiments will be described in detail.

[0148] First, taking the schematic diagram of the analog sensed current IOUT calibration process shown in Figure 7A as an example, the subtraction circuit SUB subtracts the analog sensed current IOUT from the sensed current ISEN to obtain a difference. After filtering out noise through the switch circuit S1, the difference is then accumulated through the integration circuit INT to obtain a difference signal IDIF. Then, a calibration signal CS is generated according to the current value of the difference signal IDIF to correspondingly adjust the parameters of the first current circuit 36, such as the slope of the AC component current IRP, but not limited thereto.

[0149] For example, if the current value of the difference signal IDIF is greater than 0 (ampere), the calibration signal CS will be adjusted downward and the difference signal IDIF will be reset. If the current value of the difference signal IDIF is equal to 0 (ampere), the calibration signal CS will remain unchanged and the difference signal IDIF will be reset. If the current value of the difference signal IDIF is less than 0 (ampere), the calibration signal CS will be adjusted upward and the difference signal IDIF will be reset.

[0150] AsFigure 7B As shown, the subtraction circuit SUB subtracts the current area S1 of the analog sense current IOUT from the current area S2 of the sense current ISEN between time t2 and time t3 to obtain a difference, and then the integration circuit INT accumulates the difference to generate a difference signal IDIF to generate a correction signal CS, so that the slope of the alternating current component current IRP generated by the first current circuit 36 is adjusted accordingly.

[0151] It should be noted that when the correction signal CS is larger, the amplitude of the output ramp signal RAMP will be larger. At a fixed frequency, the slope of the ramp signal RAMP will be larger. Therefore, the slope of the alternating current component current IRP can be finely adjusted accordingly. Each time the correction signal CS is updated, the integration circuit INT will be reset to start accumulating again. The analog current generation circuit of the power conversion circuit of the present invention continuously repeats the above correction steps, so that the waveform of the analog sense current IOUT can approach the actual inductor current IL.

[0152] Next, if taking Figure 8A the schematic diagram of the analog sense current IOUT correction process shown as an example, the correction circuit may include a first subtraction circuit SUB1, a first sampling circuit SH1, a second sampling circuit SH2, a second subtraction circuit SUB2, and an integration circuit INT. The first subtraction circuit SUB1 receives the analog sense current IOUT and the sense current ISEN and subtracts the analog sense current IOUT from the sense current ISEN to obtain a difference signal IDIF1. The first sampling circuit SH1 samples the difference signal IDIF1 at a first time (i.e., Figure 8B time t2 in Figure 8B ) to obtain a first difference IDIFA. The second sampling circuit SH2 samples the difference signal IDIF1 at a second time (i.e., Figure 8B time t3 in Figure 8B ) to obtain a second difference IDIFB. The second subtraction circuit SUB2 receives the first difference IDIFA and the second difference IDIFB and subtracts the first difference IDIFA from the second difference IDIFB to obtain a difference signal IDIF2, which is then accumulated by the integration circuit INT to obtain an accumulated current IACC. Then, a correction signal CS is generated according to the current value of the accumulated current IACC to correspondingly adjust the parameters of the first current circuit 36, such as the slope of the alternating current component current IRP, but not limited thereto.

[0153] For example, if the current value of the accumulated current IACC is greater than 0 (ampere), the correction signal CS will be adjusted downward and the accumulated current IACC will be reset. If the current value of the accumulated current IACC is equal to 0 (ampere), the correction signal CS will remain unchanged and the accumulated current IACC will be reset. If the current value of the difference signal IDIF is less than 0 (ampere), the correction signal CS will be adjusted upward and the accumulated current IACC will be reset.

[0154] As shown in Figure 8B FIG. 1, after the first subtraction circuit SUB1 subtracts the current area S1 of the analog sense current IOUT from the current area S2 of the sense current ISEN, the difference signal IDIF1 is sampled by the first sampling circuit SH1 and the second sampling circuit SH2 at times t2 and t3 respectively to obtain a first difference IDIFA and a second difference IDIFB corresponding to times t2 and t3 respectively. Then, the difference between the first difference IDIFA and the second difference IDIFB is accumulated by the integration circuit INT to obtain an accumulated current IACC, and the correction signal CS is adjusted correspondingly based on this.

[0155] It should be noted that when the correction signal CS is larger, the amplitude of the ramp signal RAMP generated by the first current circuit 36 will be larger. At a fixed frequency, this will make the slope of the ramp signal RAMP larger. Therefore, the waveform of the AC component current IRP can be finely adjusted accordingly. Each time the correction signal CS is updated, the integration circuit INT will be reset to start accumulating again. The analog current generation circuit of the power conversion circuit of the present invention continuously repeats the above correction steps, so that the waveform of the analog sense current IOUT can approach the actual inductor current IL.

[0156] Another specific embodiment according to the present invention is an analog current generation method. In this embodiment, the analog current generation method can be applied to a switching power conversion circuit (such as a buck power conversion circuit or a boost power conversion circuit) to provide an analog sense current in a fully analog manner, and the analog sense current includes an AC component current and a DC component current, but is not limited thereto.

[0157] Please refer to Figure 9 , Figure 9 FIG. 2, which is a flowchart of the analog current generation method for this embodiment. As shown in Figure 9 FIG. 2, the analog current generation method includes the following steps:

[0158] Step S10: Provide a ramp signal as the AC component current;

[0159] Step S12: Sample and hold the sense current signal to generate a DC component current;

[0160] Step S14: Synthesize the AC component current and the DC component current to form an analog sense current; and

[0161] Step S16: Dynamically adjust the ramp signal according to the analog sense current and the sense current.

[0162] In practical applications, step S10 can set the information of the output inductor through an externally set resistor to generate a ramp signal, but it is not limited thereto; the sensed current signal described in step S12 is related to the inductor current flowing through the output inductor, but it is not limited thereto; step S16 adjusts the slope of the ramp signal, but it is not limited thereto.

[0163] In one embodiment, step S16 further includes integrating the difference between the analog sensed current and the sensed current to adjust the ramp signal, but it is not limited thereto.

[0164] In another embodiment, step S16 further includes obtaining the difference between the sensed current and the analog sensed current, and integrating the difference from the first time to the second time to adjust the ramp signal, but it is not limited thereto.

[0165] In yet another embodiment, step S12 further includes obtaining the sensed current signal, and at least once sampling and maintaining the valley value of the sensed current signal according to the pulse width modulation signal at the second time to obtain the DC component current, but it is not limited thereto.

[0166] Compared with the prior art, the analog current generation circuit and the analog current generation method of the power conversion circuit of the present invention set the AC component current (i.e., the waveform of the analog sensed current) according to the external output inductor value, and determine the DC component current (i.e., the valley value of the analog sensed current) according to the minimum value of the sensed current, and then synthesize the two into the analog sensed current. Since the analog current generation circuit and the analog current generation method of the present invention predict the change of the actual inductor current in a fully analog manner, it can effectively overcome the problems of the prior art that it is impossible to obtain the instantaneous sensed current waveform, high circuit cost, high control difficulty, etc., and can also instantaneously correct the AC component current (i.e., the waveform of the analog sensed current) through the correction circuit to improve the accuracy of the sensed current.

Claims

1. An analog current generation circuit for a power conversion circuit to provide an analog sense current, characterized in that, The above-mentioned simulated sensing current includes an AC component current and a DC component current. The above-mentioned analog current generation circuit includes: A first current circuit that generates a ramp signal to serve as the above-mentioned AC component current; A second current circuit coupled to the output stage of the above-mentioned power conversion circuit to provide a sensing current, wherein the above-mentioned sensing current generates the above-mentioned DC component current after sampling and holding processing; A synthesis circuit respectively coupled to the above-mentioned first current circuit and the above-mentioned second current circuit to synthesize the above-mentioned AC component current and the above-mentioned DC component current into the above-mentioned simulated sensing current; and A correction circuit respectively coupled to the above-mentioned first current circuit, the above-mentioned second current circuit, and the above-mentioned synthesis circuit to dynamically adjust the above-mentioned ramp signal according to the above-mentioned simulated sensing current and the above-mentioned sensing current; Wherein, the above-mentioned correction circuit includes a first subtraction circuit, a first sampling circuit, a second sampling circuit, a second subtraction circuit, an integration circuit, and a comparison circuit. The above-mentioned first subtraction circuit receives the above-mentioned simulated sensing current and the above-mentioned sensing current. The above-mentioned first sampling circuit obtains a first difference at a first time. The above-mentioned second sampling circuit obtains a second difference at a second time. The above-mentioned second subtraction circuit receives the above-mentioned first difference and the above-mentioned second difference to generate a difference signal. The above-mentioned integration circuit receives the above-mentioned difference signal to generate a difference voltage. The above-mentioned comparison circuit generates a correction signal to the above-mentioned first current circuit according to the above-mentioned difference voltage to dynamically adjust the above-mentioned ramp signal.

2. The analog current generation circuit according to claim 1, wherein The above-mentioned output stage is coupled to an inductor, and the above-mentioned sensing current is related to the inductor current flowing through the above-mentioned inductor.

3. The analog current generation circuit according to claim 2, wherein The above-mentioned first current circuit is coupled to a set resistor, and the above-mentioned first current circuit uses the above-mentioned set resistor to generate the above-mentioned ramp signal, wherein the resistance value of the above-mentioned set resistor is related to the inductance value of the above-mentioned inductor.

4. The analog current generation circuit according to claim 1, wherein The above-mentioned analog current generation circuit further includes at least one sampling and holding circuit coupled between the above-mentioned second current circuit and the above-mentioned synthesis circuit to perform the above-mentioned sampling and holding processing on the above-mentioned sensing current to generate the above-mentioned DC component current.

5. A method for generating an analog current to provide an analog sense current, characterized in that, The above-mentioned simulated sensing current includes an AC component current and a DC component current. The above method includes: (a) Providing a ramp signal to serve as the above-mentioned AC component current; (b) Performing sampling and holding processing on the sensing current to generate the above-mentioned DC component current; (c) Synthesizing the above-mentioned AC component current and the above-mentioned DC component current into the above-mentioned simulated sensing current; and (d) Dynamically adjusting the above-mentioned ramp signal according to the above-mentioned simulated sensing current and the above-mentioned sensing current Wherein, step (d) further includes: (d1) Obtaining the difference between the above-mentioned sensing current and the above-mentioned simulated sensing current; and (d2) Integrating the above-mentioned difference from a first time to a second time, and generating a correction signal to the AC component current according to the integration result to adjust the above-mentioned ramp signal.

6. The generation method according to claim 5, characterized in that, The above-mentioned sensing current is related to the inductor current flowing through the output inductor.

7. The generation method according to claim 5, wherein Step (a) further includes: Setting information of the output inductor through an external set resistor to generate the above-mentioned ramp signal.

8. The generation method according to claim 5, characterized in that, Step (d) further includes: Adjusting the slope of the above-mentioned ramp signal.

9. The production method according to claim 5, characterized in that, Step (b) includes: (b1) Obtaining the above-mentioned sensing current; and (b2) At least one sampling and maintaining is performed on the valley value of the sensed current at a second time according to the pulse width modulation signal to obtain the DC component current.

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