Display driver circuit

Abstract

A display driving circuit for driving a display panel, comprising: a first memory, the first memory being configured to store main image data received from outside the display driving circuit; a second memory, the second memory being configured to store first additional image data in a normal mode, and to store second additional image data in an always-on display (AOD) mode having lower power consumption than the normal mode; a normal mode controller, the normal mode controller being configured to operate in the normal mode according to the first additional image data stored in the second memory; and an AOD mode controller, the AOD mode controller being configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0045439 filed on April 14, 2020, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0088464 filed on July 16, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a display driving circuit for driving a display panel to display an image on the display panel. Background Art

[0004] The display device may include a display panel that displays an image and a display driving circuit that drives the display panel. The display driving circuit may receive image data from a processor and apply an image signal corresponding to the received image data to a data line of the display panel, thereby driving the display panel. The display device may be implemented in various forms, such as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, and an active matrix OLED (AMOLED) display.

[0005] With the development of information technology, the use of small electronic devices is increasing. Small electronic devices may include smart phones, tablet computers, portable multimedia players (PMPs), laptop personal computers, and wearable devices. Since most small electronic devices operate based on power from batteries, it is very important to reduce power consumption. Therefore, it is also important to reduce the power consumption of display devices included in small electronic devices. Summary of the invention

[0006] A display driving circuit operating in a normal mode and an always-on-display (AOD) mode is provided.

[0007] According to one aspect of the present disclosure, a display driving circuit for driving a display panel includes: a first memory, the first memory being configured to store main image data received from outside the display driving circuit; a second memory, the second memory being configured to store first additional image data in a normal mode, and to store second additional image data in an always-on display (AOD) mode having lower power consumption than the normal mode; a normal mode controller, the normal mode controller being configured to operate in the normal mode according to the first additional image data stored in the second memory; and an AOD mode controller, the AOD mode controller being configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory.

[0008] According to one aspect of the present disclosure, a display driving circuit for driving a display panel includes: a first memory, the first memory being configured to store first main image data in a normal mode, and to store second main image data in an always-on display (AOD) mode having lower power consumption than the normal mode; a distributor, the distributor being configured to receive the first main image data and the second main image data from the first memory, and to distribute the first main image data and the second main image data according to a mode selection signal; a decoder, the decoder being configured to receive the first main image data from the distributor, and to decode the received first main image data, and to generate the decoded first main image data; a normal mode controller, the normal mode controller being configured to operate in the normal mode according to the decoded first main image data; and an AOD mode controller, the AOD mode controller being configured to receive the second main image data from the distributor, and to operate in the AOD mode according to the second main image data.

[0009] According to one aspect of the present disclosure, a display driving circuit for driving a display panel includes: a first memory, the first memory being configured to store merged image data received from outside the display driving circuit; an image modification circuit, the image modification circuit being configured to extract additional image data from the merged image data and generate main image data; an internal time information generation circuit, the internal time information generation circuit being configured to generate internal time information based on a clock signal and time information; and an always-on display (AOD) mode controller, the AOD mode controller being configured to operate in an AOD mode having lower power consumption than a normal mode according to the main image data, the additional image data and the internal time information. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing a display system according to an embodiment;

[0012] Figure 2 is a diagram for describing an image displayed on a display panel according to a signal received by the display panel from a display driving circuit according to an embodiment;

[0013] Figure 3 is a block diagram showing a display system according to an embodiment;

[0014] Figure 4 is a block diagram showing a display device according to an embodiment;

[0015] Figure 5 is a block diagram showing a display system according to an embodiment;

[0016] Figure 6 is a block diagram showing a display system according to an embodiment;

[0017] Figure 7 is a block diagram showing a display system according to an embodiment;

[0018] Figure 8 is a block diagram showing a display system according to an embodiment;

[0019] Fig. 9 is a block diagram showing a display system according to an embodiment;

[0020] Fig.10 is a block diagram showing a display system according to an embodiment;

[0021] Fig.11 is a diagram illustrating the operation of a display driving circuit for adjusting the brightness of an AOD area according to an embodiment; and

[0022] Fig.12 is a diagram illustrating a touch screen module according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram illustrating a display system according to an embodiment of the present disclosure.

[0025] The display system 10 according to an embodiment of the present disclosure may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, an Internet of Things device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, a global positioning system receiver, an advanced driver assistance system (ADAS), a vehicle device, furniture, or various measuring devices.

[0026] Reference Figure 1 , the display system 10 may include a processor 100, a display driver integrated circuit (IC) 200, and a display panel 300. In an embodiment, the display driver IC 200 may be a display driver circuit. In an exemplary embodiment, the display driver IC 200 and the display panel 300 may be implemented as a module, and the module may be referred to as a display device. For example, the display driver IC 200 may be mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), a flexible printed circuit (FPC), etc., to be attached to the display panel 300 using a tape automatic bonding (TAB) method, or may be mounted on a non-display area of ​​the display panel 300 using a chip on glass (COG) or a chip on plastic (COP) method.

[0027] The display system 10 can operate in a normal mode and an always-on display (AOD) mode, and the AOD mode can consume less power than the normal mode. The normal mode can represent a mode in which a screen is displayed through the display panel 300 when the processor 100 is in an active state, and can represent a state in which steady-state power is provided to the processor 100. The normal mode can represent a mode in which the processor 100 controls the display driver IC 200 to display an image through the display panel 300. The AOD mode can represent a mode in which a screen is displayed through the display panel 300 when the processor 100 is in an inactive state. The inactive state can represent a shutdown state that needs to be started to switch to an active state. The inactive state can represent a state in which the power provided to the processor 100 is limited, and can represent a state in which a power lower than the power provided in the normal mode is provided.

[0028] The processor 100 may generally control the display system 10. The processor 100 may generate image data MIDT and AIDT to be displayed on the display panel 300, and transmit the image data MIDT and AIDT, time information TI, and a command (eg, a mode change command MCMD) to the display driver IC 200.

[0029] The processor 100 may be an application processor. However, the embodiment is not limited thereto, and the processor 100 may be implemented with various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, and a graphics processor. In an exemplary embodiment, the processor 100 may be implemented as an integrated circuit (IC), and may be implemented as a mobile application processor (AP) or a system on chip (SoC). The processor 100 may identify whether to change the display system 10 from a normal mode to an AOD mode, or determine whether to change the display system 10 from an AOD mode to a normal mode.

[0030] For example, the processor 100 may monitor whether a user input is detected within a specified time, maintain the normal mode based on recognizing that the user input is detected within the specified time, and change the mode to the AOD mode based on recognizing that the user input is not detected within the specified time. As another example, the processor 100 may monitor whether a user input for deactivating the display panel 300 is detected, and change the mode from the normal mode to the AOD mode based on confirming that the user input for deactivating the display panel 300 is detected.

[0031] The processor 100 may transmit a mode change command MCMD for mode change to the display driver IC 200. The display driver IC 200 may operate by changing the mode from the normal mode to the AOD mode or may operate by changing the mode from the AOD mode to the normal mode in response to the mode change command MCMD.

[0032] The display driver IC 200 may convert the image data MIDT and AIDT received from the processor 100 into an image signal IS for driving the display panel 300, and supply the image signal IS to the display panel 300, thereby displaying an image on the display panel 300. In the normal mode, the display driver IC 200 may receive the main image data MIDT, which may be full-frame image data corresponding to the entire or complete area of ​​the display panel 300, and receive the additional image data AIDT corresponding to a partial area of ​​the display panel 300 from the processor 100. In the AOD mode, the display driver IC 200 may receive the main image data MIDT, which may be background image data, and receive the additional image data AIDT corresponding to the AOD area 310 of the display panel 300 from the processor 100.

[0033] The display driver IC 200 may include an AOD mode controller 230. In an exemplary embodiment, the AOD mode controller 230 may perform an AOD mode using the main image data MIDT, the additional image data AIDT, and the time information TI. For example, the AOD mode controller 230 may generate a control signal using the main image data MIDT, the additional image data AIDT, and the time information TI so that an AOD image combined with a background image and an additional image is displayed on the display panel 300.

[0034] The display panel 300 may be a display on which an actual image is displayed, such as a display unit, and may be one of the display devices that receive an electrically transmitted image signal IS and display a 2D image, such as a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, a plasma display panel (PDP), etc. The display panel 300 may be implemented as another type of flat panel display or a flexible display panel. In the AOD mode, an image may be displayed on the AOD region 310 of the display panel 300. In an exemplary embodiment, the AOD region 310 may be a partial region of the display panel 300. For example, the AOD region 310 may be a region that displays an image when the display system 10 operates in the AOD mode or the low power mode. The AOD region 310 may not be a fixed region on the display panel 300, and the position, size, number, etc. of the AOD region 310 on the display panel 300 may change according to time or driving conditions.

[0035] The display driver IC 200 according to the exemplary embodiment of the present disclosure can store the additional image data received in the AOD mode in the memory in which the additional image data received in the normal mode is stored. Therefore, by not including a separate memory for executing the AOD mode, the cost increase caused by using a dedicated memory can be prevented.

[0036] In addition, the display driver IC 200 may receive encoded background image data in normal mode and may receive unencoded background image data in AOD mode. The display driver IC may not perform a decoding operation on the background image data in AOD mode, thereby reducing power consumption required for the decoding operation.

[0037] Figure 2 is a diagram for describing an image displayed on a display panel according to a signal received by the display panel from a display driver IC according to an exemplary embodiment of the present disclosure.

[0038] Reference Figure 1 and Figure 2, the display panel 300 may receive the AOD image signal AIS from the display driver IC 200. The AOD image signal AIS may include a background image signal BIS and an additional image signal AAIS, and may be a combination of the background image signal BIS and the additional image signal AAIS. The display panel 300 may display an actual image according to the AOD image signal AIS. The additional image according to the additional image signal AAIS may be, for example, a clock. Figure 2 In FIG. 1 , an image according to the additional image signal AAIS is shown as a digital clock, but the embodiment is not limited thereto, and in FIG. Figure 2 In the embodiment, the image according to the additional image signal AAIS may be an analog clock.

[0039] For example, in the AOD mode, the AOD mode controller 230 may generate a control signal to display an additional image in the shape of a digital clock on the display panel 300 using the additional image data AIDT including information about numbers and / or a colon (:) and the time information TI including current time information. In an embodiment, for example, in the AOD mode, the AOD mode controller 230 may generate a control signal to display an additional image in the shape of an analog clock on the display panel 300 using the additional image data AIDT including information about the shapes of the hour hand, minute hand, and second hand and the time information TI including current time information.

[0040] Figure 3 is a block diagram showing a display system 10 according to an exemplary embodiment of the present disclosure, which may correspond to Figure 1 A display system 10.

[0041] Reference Figure 3 , the display system 10 may include a processor 100, a display driver IC 200, and a display panel 300. The processor 100 may include an encoder 110 and a selector 120. The main image data MIDT compressed by being encoded by the encoder 110 may be output from the processor 100. The processor 100 may send additional image data AIDT, and through a selection operation of the selector 120, the processor 100 may send first additional image data AIDT_N in a normal mode, and send second additional image data AIDT_A in an AOD mode. In an exemplary embodiment, the selector 120 may be implemented as a multiplexer, and may be configured such that an output signal changes with a change in an operating mode.

[0042] The display driver IC 200 may receive the main image data MIDT and the additional image data AIDT from the processor 100, and convert the main image data MIDT and the additional image data AIDT into an image signal IS for driving the display panel 300. By supplying the image signal IS to the display panel 300, an image may be displayed on the display panel 300. For example, an image of the display panel 300 according to the first additional image data AIDT_N may refer to an image displayed in a rounded display area of ​​the display panel 300. Also, for example, an image of the display panel 300 according to the second additional image data AIDT_A may refer to an additional image displayed on the AOD area 310 of the display panel 300.

[0043] The display driver IC 200 may include an interface (I / F) circuit IFC, a first memory 210, a decoder 220, an AOD mode controller 230, a second memory 240, a distributor 250, a normal mode controller 260, and an internal time information generation circuit 270, which may be related to, for example, a real-time clock (RTC). The AOD mode controller 230 may be a control logic circuit for executing the AOD mode, and the normal mode controller 260 may be a control logic circuit for executing the normal mode. However, Figure 3 An exemplary configuration of the display driver IC 200 is shown, and the display driver IC 200 may further include Figure 3 In an embodiment, the display driver IC 200 may not include other components not shown. Figure 3 One or more components among the interface circuit IFC, the first memory 210, the decoder 220, the AOD mode controller 230, the second memory 240, the distributor 250, the normal mode controller 260 and the internal time information generating circuit 270 are shown.

[0044] The interface circuit IFC may receive main image data MIDT, additional image data AIDT, time information TI, and mode change command MCMD from the processor 100 through a channel. The interface circuit IFC may transmit the main image data MIDT, additional image data AIDT, time information TI, and mode change command MCMD to other components inside the display driver IC 200.

[0045] In an exemplary embodiment, the interface circuit IFC may support an RGB interface, a CPU interface, a serial interface, a mobile display digital interface (MDDI), an inter-integrated circuit (Inter Integrated Circuit, I2C) interface, a serial peripheral interface (SPI), a microcontroller unit (MCU) interface, a mobile industrial processor interface (MIPI), an embedded display port (eDP) interface, a D-sub (D-sub) interface, an optical interface, a high-definition multimedia interface (HDMI), etc. In addition, in an exemplary embodiment, the interface circuit IFC may support a mobile high-definition link (MHL) interface, a secure digital (SD) card / multimedia card (MMC) interface, or an infrared data association (IrDA) standard interface.

[0046] In an exemplary embodiment, when the mode is changed from the normal mode to the AOD mode, the interface circuit IFC may receive the main image data MIDT, the additional image data AIDT, and the time information TI, and then block a channel connected to the processor 100 for a predetermined time.

[0047] The first memory 210 may store the main image data MIDT received through the interface circuit IFC, and may transmit the main image data MIDT to the decoder 220. The decoder 220 may decode the main image data MIDT, and may transmit the decoded main image data MIDT_D as background image data to the AOD mode controller 230 in the AOD mode. In an embodiment, although Figure 3 Although not shown in the figure, the decoder 220 may transmit the decoded main image data MIDT_D as full frame image data to the normal mode controller 260 in the normal mode.

[0048] The second memory 240 may store the additional image data AIDT received through the interface circuit IFC, and transmit the additional image data AIDT to the distributor 250. The second memory 240 may store the first additional image data AIDT_N in the normal mode, and transmit the first additional image data AIDT_N to the distributor 250. In an embodiment, the second memory 240 may store the second additional image data AIDT_A in the AOD mode, and transmit the second additional image data AIDT_A to the distributor 250.

[0049] The first memory 210 and the second memory 240 may include volatile and / or nonvolatile memory, and for example, the first memory 210 and the second memory 240 may each include at least one of a volatile memory (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), or a synchronous DRAM (SDRAM)) and a nonvolatile memory (e.g., a programmable read-only memory (PROM), an erasable PROM (EPROM), a flash read-only memory (ROM), or a flash memory). In an exemplary embodiment, the first memory 210 may be a graphic random access memory (GRAM), and the second memory 240 may be an SRAM.

[0050] The distributor 250 may transmit the received additional image data AIDT to one of the AOD mode controller 230 and the normal mode controller 260 in response to the mode selection signal MS. The mode selection signal MS may be a signal that changes according to the mode change command MCMD. The distributor 250 may transmit the first additional image data AIDT_N to the normal mode controller 260 in the normal mode in response to the mode selection signal MS, and transmit the second additional image data AIDT_A to the AOD mode controller 230 in the AOD mode. In an exemplary embodiment, the distributor 250 may be implemented as a demultiplexer and may transmit the signal to be output in different configurations as the operating mode changes.

[0051] The internal time information generation circuit 270 can receive the time information TI through the interface circuit IFC. In the AOD mode, the internal time information generation circuit 270 can generate the internal time information ITI according to the time information TI and the clock signal CLK. The internal time information generation circuit 270 can send the internal time information ITI to the AOD mode controller 230.

[0052] In an exemplary embodiment, the display driver IC 200 may include an oscillator that generates a clock signal CLK. The internal time information generating circuit 270 may generate the internal time information ITI using the clock signal CLK generated inside the display driver IC 200.

[0053] In an exemplary embodiment, when the processor 100 changes from the normal mode to the AOD mode, the processor 100 may send the time information TI to the display driver IC 200, and after a predetermined time in the AOD mode, the display driver IC 200 may block the reception of the time information TI. Therefore, the internal time information generating circuit 270 may continuously update the internal time information ITI by using the clock signal CLK based on the received time information TI.

[0054] The AOD mode controller 230 may receive the decoded main image data MIDT_D as background image data from the decoder 220, receive the second additional image data AIDT_A from the distributor 250, and receive the internal time information ITI from the internal time information generating circuit 270. The AOD mode controller 230 may perform an AOD mode operation using the decoded main image data MIDT_D, the second additional image data AIDT_A, and the internal time information ITI. In an embodiment, the AOD mode controller 230 generates a control signal, such as a control signal, using the main image data MIDT_D, the second additional image data AIDT_A, and the internal time information ITI. Figure 4 CTRL1 and CTRL2 in order to display the AOD image on the display panel 300.

[0055] The normal mode controller 260 may receive the main image data MIDT_D as full frame image data from the decoder 220, and may receive the first additional image data AIDT_N from the distributor 250. The normal mode controller 260 may perform a normal mode using the main image data MIDT_D and the first additional image data AIDT_N. Because the normal mode controller 260 and the AOD mode controller 230 operate in different operating modes, they may operate exclusively with each other. In other words, the normal mode controller 260 will not operate in the AOD mode, and the AOD mode controller 230 will not operate in the normal mode.

[0056] In the display driver IC 200 according to the present disclosure, controllers that operate exclusively with each other (e.g., the AOD mode controller 230 and the normal mode controller 260) may share the second memory 240, that is, share the same memory. In an embodiment according to the AOD mode or the normal mode, the second memory 240 may store the second additional image data AIDT_A used in the AOD mode controller 230, or store the first additional image data AIDT_N used in the normal mode controller 260. Therefore, the display driver IC 200 may not include a separate memory for storing the second additional image data AIDT_A when operating in the AOD mode, thereby preventing an increase in cost due to the use of a dedicated memory.

[0057] Figure 4 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0058] Reference Figure 4, the display device may include a display driver IC 200 and a display panel 300, and the display driver IC 200 may include a controller CT, a data line driver DDRV, and a scan line driver SDRV. However, in an embodiment, the display driver IC 200 may not include the scan line driver SDRV, and the scan line driver SDRV may be included in the display system 10 as a component separate from the display driver IC 200.

[0059] The display panel 300 may include a plurality of pixels PX arranged in a matrix form, and each of the plurality of pixels PX outputs a visual signal, thereby displaying an image in units of frames. The display panel 300 includes scan lines SL0 to SLN arranged in a row direction, data lines DL1 to DLM arranged in a column direction, and pixels PX formed at intersections of the scan lines SL0 to SLN and the data lines DL1 to DLM. The display panel 300 includes a plurality of horizontal lines (or rows), and one horizontal line includes pixels PX connected to one gate line.

[0060] The scan line driver SDRV sequentially supplies a gate turn-on signal to the scan lines SL0 to SLN in response to the first control signal CTRL1 provided from the controller CT, so that the scan lines SL0 to SLN can be sequentially selected. In response to the gate turn-on signal output from the scan line driver SDRV, the scan lines SL0 to SLN are sequentially selected, and a display operation can be performed by applying a gray voltage corresponding to the pixel PX to the pixel PX connected to the selected scan line through the data lines DL1 to DLM. During a period in which the gate turn-on signal is not supplied to the scan lines SL0 to SLN, a gate turn-off signal (e.g., a gate voltage of a logic high level) can be supplied to the scan lines SL0 to SLN.

[0061] In response to the second control signal CTRL2, the data line driver DDRV may convert the image data DATA into an image signal as an analog signal and provide the image signal to the data lines DL1 to DLM. The data line driver DDRV may include a plurality of channel amplifiers, and each of the plurality of channel amplifiers may provide an image signal to at least one corresponding data line.

[0062] The controller CT may control all operations of the display system 10. The controller CT may be implemented in hardware, software, or a combination of hardware and software. For example, the controller CT may be implemented in digital logic circuits and registers that perform the following functions. The controller CT may include an AOD mode controller 230 and a normal mode controller 260 that operate in different operating modes. In an exemplary embodiment, Figure 4 The normal mode controller 260 may correspond to Figure 3 and Figure 5The normal mode controller 260 and Figure 6 In an exemplary embodiment, Figure 4 The AOD mode controller 230 may correspond to Figure 3 and Figure 5 AOD mode controller 230, Figure 6 AOD mode controller 230B, Figure 8 AOD mode controller 230C, Fig. 9 The AOD mode controller 230D and Fig.10 AOD mode controller 230E.

[0063] The AOD mode controller 230 may perform an AOD mode operation using the main image data MIDT, the second additional image data AIDT_A, and the internal time information ITI. In an embodiment, the AOD mode controller 230 generates control signals CTRL1 and CTRL2 using the main image data MIDT_D, the second additional image data AIDT_A, and the internal time information ITI, thereby displaying an AOD image on the display panel 300.

[0064] Figure 5 1 is a block diagram showing a display system 10A according to an exemplary embodiment of the present disclosure. In an embodiment, the display system 10A may correspond to Figure 1 The display system 10. Figure 5 In the description of Figure 3 The same reference numerals are repeated in the description.

[0065] Reference Figure 5 , the display system 10A may include a processor 100A, a display driver IC 200A, a display panel 300, and an oscillator 400A. The oscillator 400A may generate a clock signal CLK and send the clock signal CLK to the display driver IC 200A. In an embodiment, the display driver IC 200A may be a display driving circuit.

[0066] In an exemplary embodiment, the oscillator 400A may be a component in a sensor hub included in the display system 10A. The sensor hub may include at least one sensor and a controller that controls the at least one sensor. The sensor hub may include, for example, a temperature / humidity sensor, a biometric sensor, an atmospheric pressure sensor, a gyroscope sensor, etc.

[0067] The display driver IC 200A may include an internal time information generating circuit 270A, and the internal time information generating circuit 270A may receive a clock signal CLK generated by an oscillator 400A outside the display driver IC 200A. For example, the internal time information generating circuit 270A may receive the clock signal CLK through the interface circuit IFC. The internal time information generating circuit 270A may generate internal time information ITI by using the clock signal CLK, and provide the internal time information ITI to the AOD mode controller 230. The AOD mode controller 230 may provide the image signal IS to the display panel 300, thereby displaying an additional image on the display panel 300 based on the internal time information ITI.

[0068] In an exemplary embodiment, the oscillator 400A may generate a clock signal CLK in response to a control signal CS received from the processor 100A, and transmit the clock signal CLK to the display driver IC 200A. When the mode is changed from the normal mode to the AOD mode, the processor 100A may transmit the control signal CS to the oscillator 400A, and when the AOD mode is executed, the oscillator 400A may generate the clock signal CLK. In an embodiment, the oscillator 400A may not generate the clock signal CLK in the normal mode.

[0069] In an exemplary embodiment, the oscillator 400A may generate a clock signal CLK by performing a normal mode and an AOD mode, and may transmit the clock signal CLK to the display driver IC 200A. The display driver IC 200A may generate the internal time information ITI using an internal clock signal generated by an oscillator included in the display driver IC 200A in the normal mode, and may generate the internal time information ITI by using the clock signal CLK generated by the external oscillator 400A in the AOD mode.

[0070] Compared to including an oscillator generating a clock signal inside the display driver IC 200A, when the display driver IC 200A uses an external clock signal CLK in the AOD mode, the clock signal CLK generated by the oscillator having relatively high performance can be used to generate the internal time information ITI. The display driver IC 200A according to the exemplary embodiment of the present disclosure uses the clock signal ECLK generated by the oscillator 400A outside the display driver IC 200A to generate the internal time information ITI, so that the number of wake-up operations in which the processor 100A periodically sends the time information TI in order to improve the accuracy of the internal time information ITI can be reduced. Therefore, the power consumption of the display driver IC according to the wake-up operation can be reduced.

[0071] Figure 6is a block diagram showing a display system 10B according to an exemplary embodiment of the present disclosure. In an embodiment, the display system 10B may correspond to Figure 1 The display system 10. Figure 6 In the description of Figure 3 Repeated description of the same reference numerals in the drawings.

[0072] Reference Figure 6 , the display system 10B may include a processor 100B, a display driver IC 200B, and a display panel 300. In an embodiment, the display driver IC 200B may be a display driving circuit. The processor 100B may include an encoder 130 and a selector 140. In an exemplary embodiment, the selector 140 may be implemented as a multiplexer and may be configured so that the output signal changes with the change of the operating mode.

[0073] The processor 100B may transmit the first main image data MIDT_N encoded by the encoder 130 to the display driver IC 200B in the normal mode. In an embodiment, in the AOD mode, the processor 100B may transmit the unencoded (or, for example, uncompressed) second main image data MIDT_A to the display driver IC 200B without passing through the encoder 130. The first main image data MIDT_N may be full-frame image data of the display panel 300, and the second main image data MIDT_A may represent background image data for displaying a background image on the display panel 300 in the AOD mode.

[0074] For example, in the normal mode, the selector 140 may select and output the compressed internal main image data received from the encoder 130, and the processor 100B may transmit the compressed internal main image data as the first main image data MIDT_N to the display driver IC 200B. In the AOD mode, the selector 140 may select and output the internal main image data that is not compressed by the encoder 130, and the processor 100B may transmit the uncompressed internal main image data as the second main image data MIDT_A to the display driver IC 200B.

[0075] The processor 100B may extract only an important area of ​​the background image, such as a 1 / 3 area of ​​the entire area, in the AOD mode, and transmit the background image data corresponding to the extracted area to the display driver IC 200B as the second main image data MIDT_A in an uncompressed state that has not passed through the encoder 130. For example, the size of the data corresponding to the extracted effective area may be determined according to the bandwidth of a channel for transmitting the main image data MIDT from the processor 100B to the display driver IC 200B.

[0076] The processor 100B may send the additional image data AIDT to the display driver IC 200B. In an exemplary embodiment, as shown in FIG. Figure 3 As described in, the processor 100B can send the first additional image data in the normal mode, for example Figure 3 In AIDT_N, the second additional image data can be sent in AOD mode, for example Figure 3 AIDT_A in.

[0077] The display driver IC 200B may receive the main image data MIDT and the additional image data AIDT received from the processor 100B and convert the main image data MIDT and the additional image data AIDT into an image signal IS for driving the display panel 300. By supplying the image signal IS to the display panel 300, an image may be displayed on the display panel 300.

[0078] The display driver IC 200B includes an interface circuit IFC, a first memory 210B, a distributor 215B, a decoder 220B, a normal mode controller 260B, an AOD mode controller 230B, a second memory 240B, and an internal time information generating circuit 270. The AOD mode controller 230B may be a control logic circuit for executing the AOD mode, and the normal mode controller 260B may be a control logic circuit for executing the normal mode.

[0079] The first memory 210B may store the main image data MIDT received through the interface circuit IFC and transmit the main image data MIDT to the distributor 215B. The first memory 210B may store the first main image data MIDT_N in the normal mode and may store the second main image data MIDT_A in the AOD mode.

[0080] The distributor 215B may send the received main image data MIDT to one of the AOD mode controller 230B and the normal mode controller 260B in response to the mode selection signal MS. The mode selection signal MS may be a signal that changes according to the mode change command MCMD. The distributor 215B may send the first main image data MIDT_N to the decoder 220B in the normal mode in response to the mode selection signal MS, and send the second main image data MIDT_A to the AOD mode controller 230B in the AOD mode. In an exemplary embodiment, the distributor 215B may be implemented as a demultiplexer, and may send the signal to be output in different configurations as the operating mode changes.

[0081] The decoder 220B may decode the first main image data MIDT_N and transmit the decoded first main image data MIDT_ND as full frame image data to the normal mode controller 260B.

[0082] The second memory 240B may store the additional image data AIDT transmitted from the processor 100B and transmit the additional image data AIDT to the AOD mode controller 230B. Figure 3 As described in the above, the second memory 240B can store the first additional image data in the normal mode, for example Figure 3 AIDT_N in, and storing the second additional image data in AOD mode, such as Figure 3 In an exemplary embodiment, the first memory 210B may be a GRAM, and the second memory 240B may be an SRAM.

[0083] The internal time information generating circuit 270 may receive the time information TI through the interface circuit IFC. In the AOD mode, the internal time information generating circuit 270 may generate the internal time information ITI according to the time information TI and the clock signal CLK. The clock signal CLK may be generated by an oscillator inside the display driver IC 200B, or may be generated by an oscillator outside the display driver IC 200B, as described with reference to FIG. Figure 5 As described.

[0084] The AOD mode controller 230B may receive the second main image data MIDT_A as background image data from the distributor 215B, the additional image data AIDT_A from the second memory 240B, and the internal time information ITI from the internal time information generating circuit 270. The AOD mode controller 230B may perform the AOD mode by using the second main image data MIDT_A, the additional image data AIDT_A, and the internal time information ITI.

[0085] The second main image data MIDT_A may be data from which part of data not required to be displayed on the display panel is removed. In an exemplary embodiment, the AOD mode controller 230B may control the data line driver, for example Figure 4 The DDRV in the display panel 300 is used to prevent the display panel 300 from displaying an area determined to be unnecessary to be displayed on the display panel 300 based on the second main image data MIDT_A.

[0086] Because the processor 100B transmits the second main image data MIDT_A, which is uncompressed background image data that is not compressed in the AOD mode, the display driver IC 200B may not decode the second main image data MIDT_A, but may directly process the second main image data MIDT_A in the AOD mode controller 230B. The display driver IC 200B according to the present disclosure receives the second main image data MIDT_A that is not encoded in the AOD mode as background image data, thereby reducing power consumption required for decoding the background image data.

[0087] Figure 7 is a block diagram showing a display system 10C according to an embodiment of the present disclosure.

[0088] Reference Figure 7 , the display system 10C may include a processor 100C, a display driver IC 200C, and a display panel 300. In an embodiment, the display driver IC 200C may be a display driving circuit. In an exemplary embodiment, the display driver IC 200C and the display panel 300 may be implemented as one module. The display system 10C may operate in a variety of operating modes (e.g., a normal mode and an AOD mode).

[0089] The processor 100C may generally control the display system 10C. The processor 100C may generate the merged image data MD to be displayed on the display panel 300 in the AOD mode, and transmit the merged image data MD and the time information TI to the display driver IC 200C.

[0090] The merged image data MD may be data in which the main image data and the additional image data are merged as background image data. In an exemplary embodiment, when merging the main image data and the additional image data, the processor 100C may merge the additional image data required for executing the AOD mode into a data region determined to be unnecessary in the main image data, for example, into a data region corresponding to a portion that is black-processed and displayed on the display panel 300 in the AOD mode.

[0091] The display driver IC 200C converts the combined image data MD received from the processor 100C in the AOD mode into an image signal IS for driving the display panel 300 and supplies the image signal IS to the display panel 300 , so that an image may be displayed on the display panel 300 .

[0092] The display driver IC 200C may include an image modification circuit 225C and an AOD mode controller 230C. The image modification circuit 225C may extract main image data and additional image data from the merged image data MD. The AOD mode controller 230C may drive the display panel 300 to display an image in which a background image and an additional image are combined using the main image data and additional image data output from the image modification circuit 225C.

[0093] Since the display driver IC 200C according to an exemplary embodiment of the present disclosure automatically generates the image signal IS for displaying the AOD image on the display panel 300 within the display driver IC 200C using the merged image data MD transmitted from the processor 100C, the processor 100C can prevent power consumption for transmission of separate additional image data for the AOD mode.

[0094] Figure 8 is a block diagram illustrating an example of a display system 10C according to an exemplary embodiment of the present disclosure. Fig. 9 1 is a block diagram showing a display system 10D according to an exemplary embodiment of the present disclosure. In an embodiment, the display system 10D may correspond to Figure 7 Display system 10C. Figure 8 and Fig. 9 In the Figure 3 Repeated description of the same reference numerals in the drawings.

[0095] Reference Figure 8 , the display system 10C may include a processor 100C, a display driver IC 200C, and a display panel 300 .

[0096] The processor 100C may output merged image data MD in which the main image data and the additional image data are merged in the AOD mode, and may send the merged image data MD to the display driver IC 200C. The processor 100C may send an address ADDR indicating the position of the merged additional image data in the merged image data MD to the display driver IC 200C. However, in an embodiment, the processor 100C may not send the address ADDR to the display driver IC 200C, and the processor 100C and the display driver IC 200C may have previously agreed (e.g., determined or set) the position of the additional image data in the merged image data MD. For example, the address ADDR indicating the position of the additional image data in the merged image data MD may be preset in the image modification circuit 225C.

[0097] In an exemplary embodiment, the processor 100C may include the encoder 150, and the combined image data MD output from the processor 100C may be data encoded to correspond to the bandwidth of the channel connecting the processor 100C to the display driver IC 200C. However, the embodiment is not limited thereto, and if it is determined that compression is not required according to the bandwidth of the combined image data MD channel, the processor 100C may output the uncompressed combined image data MD.

[0098] In an exemplary embodiment, when merging the main image data and the additional image data, the processor 100C merges the additional image data required for executing the AOD mode into the data region determined to be unnecessary in the main image data, so that the merged image data MD can be output. In this case, the data region determined to be unnecessary in the main image data may be, for example, a data region corresponding to a portion displayed as black on the display panel 300 in the AOD mode. In an embodiment, the data region may be a region of the display panel 300 other than the AOD region 310.

[0099] The display driver IC 200C may include an interface circuit IFC, a first memory 210C, a decoder 220C, an image modification circuit 225C, an AOD mode controller 230C, a second memory 240C, and an internal time information generation circuit 270. In an exemplary embodiment, the first memory 210C may be a GRAM, and the second memory 240C may be an SRAM. In an exemplary embodiment, when the processor 100C transmits the uncompressed merged image data MD, the display driver IC 200C may not include the decoder 220C.

[0100] The first memory 210C may store the merged image data MD received through the interface circuit IFC and transmit the merged image data MD to the decoder 220C. The decoder 220C may decode the merged image data MD as compressed data and transmit the decoded merged image data MD_D to the image modification circuit 225C.

[0101] The image modification circuit 225C may extract the additional image data AIDT from the decoded merged image data MD_D. The image modification circuit 225C may send the additional image data AIDT to the second memory 240C. The second memory 240C may store the additional image data AIDT and may send the additional image data AIDT to the AOD mode controller 230C.

[0102] In an exemplary embodiment, the image modification circuit 225C may receive the address ADDR through the interface circuit IFC. The image modification circuit 225C may extract the additional image data AIDT from the decoded merged image data MD_D based on the address ADDR. However, in an embodiment, the display driver IC 200C according to the present disclosure may not receive the address ADDR separately, but may preset an address indicating the position of the additional image data AIDT in the decoded merged image data MD_D in the display driver IC 200C.

[0103] The image modification circuit 225C may set a data area obtained by extracting additional image data AIDT from the decoded merged image data MD_D as a black processing area to generate main image data MIDT as background image data. The image modification circuit 225C may transmit the main image data MIDT to the AOD mode controller 230C.

[0104] The internal time information generating circuit 270 may receive the time information TI through the interface circuit IFC. In the AOD mode, the internal time information generating circuit 270 may generate the internal time information ITI according to the time information TI and the clock signal CLK. The clock signal CLK may be generated by an oscillator inside the display driver IC 200C, or may be generated by an oscillator outside the display driver IC 200C, as described with reference to FIG. Figure 5 As described.

[0105] The AOD mode controller 230C may drive the display panel 300 using the main image data MIDT, the additional image data AIDT, and the internal time information ITI to display an AOD image on the display panel 300. The AOD mode controller 230C may provide an image signal IS corresponding to the main image data MIDT to the display panel 300, and provide an image signal IS corresponding to the additional image data AIDT to the display panel 300.

[0106] In this case, the AOD mode controller 230C may modify a portion of the additional image data AIDT and then provide the image signal IS according to the modified data to the display panel 300. For example, the extracted additional image data AIDT may be modified to change the size, position, or brightness of an additional image (e.g., an image of a clock indicating time), or the extracted additional image data AIDT may be modified to move or rotate the additional image.

[0107] Since the display driver IC 200C according to the present disclosure configures the AOD image using the merged image data MD sent from the processor 100C, a high-quality AOD image can be configured compared to configuring the AOD image autonomously in the display driver circuit. In addition, since the processor 100C sends the merged image data MD, power consumption can be reduced.

[0108] Reference Fig. 9 ,and Figure 8 Compared with the display driver IC 200C of the display driver IC 200D, the display driver IC 200D does not include a second memory, and may include an interface circuit IFC, a first memory 210C, a decoder 220C, an image modification circuit 225D, an AOD mode controller 230D, and an internal time information generation circuit 270. The image modification circuit 225D can extract additional image data AIDT from the decoded merged image data MD_D, and send the extracted additional image data AIDT to the AOD mode controller 230D. Therefore, since the display driver IC 200D does not include a separate second memory for storing the additional image data AIDT, it is not necessary to have a dedicated memory for the AOD mode controller 230D, so that the manufacturing cost of the display driver IC 200D can be reduced. In an embodiment, the display driver IC 200D may be a display driving circuit.

[0109] Figure 8 and Fig. 9 It is shown that the display driver ICs 200C and 200D decode the merged image data MD and then extract the additional image data AIDT from the decoded merged image data MD, but the display driver ICs 200C and 200D according to the present disclosure are not limited thereto. If the received merged image data MD does not need to be decoded, the display driver ICs 200C and 200D may extract the additional image data AIDT without decoding the received merged image data MD. In an embodiment, the display driver ICs 200C and 200D may perform a decoding operation after extracting the main image data and the additional image data from the received merged image data MD.

[0110] Fig.10 1 is a block diagram showing a display system 10E according to an exemplary embodiment of the present disclosure. In an embodiment, the display system 10E may correspond to Figure 7 Display system 10C. Fig.10 In the Figure 3 and Figure 8 Repeated description of the same reference numerals in the drawings.

[0111] Reference Fig.10, the display system 10E may include a processor 100E, a display driver IC 200E, and a display panel 300. In an embodiment, the display driver IC 200E may be a display driving circuit.

[0112] The processor 100E may output merged image data MD' in which the main image data and the additional image data are merged in the AOD mode, and may send the merged image data MD' to the display driver IC 200E. The processor 100E may send an address ADDR indicating the position of the merged additional image data in the merged image data MD' to the display driver IC 200E. However, in an embodiment, the processor 100E may not send the address ADDR to the display driver IC 200E, but the processor 100E and the display driver IC 200E may both have a preset position of the merged additional image data in the merged image data MD'. In an exemplary embodiment, the processor 100E may include an encoder 150E, and after encoding the data corresponding to the main image data by the encoder 150E, the processor 100E may merge the data corresponding to the additional image data with the encoded data to output the merged image data MD'.

[0113] The display driver IC 200E may include an interface circuit IFC, a first memory 210E, a decoder 220E, an image modification circuit 225E, an AOD mode controller 230E, and an internal time information generation circuit 270. The first memory 210E may store the merged image data MD' received through the interface circuit IFC and transmit the merged image data MD' to the image modification circuit 225E.

[0114] The image modification circuit 225E may extract the additional image data AIDT from the merged image data MD'. The image modification circuit 225E may send the additional image data AIDT to the AOD mode controller 230E. The image modification circuit 225E may set a data area obtained by extracting the additional image data AIDT from the merged image data MD' as a black processing area, such as an area displayed as black, to generate main image data MIDT as background image data. The image modification circuit 225E may send the main image data MIDT to the decoder 220E. The decoder 220E may decode the main image data MIDT, and may send the decoded main image data MIDT_D as background image data to the AOD mode controller 230E in the AOD mode.

[0115] The AOD mode controller 230E may drive the display panel 300 to display an AOD image on the display panel 300 using the decoded main image data MIDT_D, the additional image data AIDT, and the internal time information ITI.

[0116] Fig.11 is a diagram illustrating an operation of adjusting the brightness of an AOD area by a display driving circuit according to an exemplary embodiment of the present disclosure.

[0117] Reference Fig.11 , Figures 1 to 10 The display driver ICs 200, 200A, 200B, 200C, 200D, and 200E shown periodically or non-periodically amplify and reduce the pixel data values ​​of the portion to be displayed on the AOD region to increase and decrease the brightness of the AOD region 310 periodically or non-periodically over time. Therefore, the brightness of the AOD region 310 can increase or decrease over time, such as flickering. As shown in the figure, at time t1 and time t3, the brightness of the AOD region 310 can be high, and at time t2 and time t4, the brightness of the AOD region 310 can be low.

[0118] In an embodiment, the display driver ICs 200, 200A, 200B, 200C, 200D, and 200E may drive the display panel 300 such that the size or position of the additional image corresponding to the additional image data in the AOD area 310 changes over time. In an embodiment, the display driver ICs 200, 200A, 200B, 200C, 200D, and 200E may drive the display panel 300 such that the additional image corresponding to the additional image data in the AOD area 310 rotates over time.

[0119] Fig.12 is a diagram illustrating a touch screen module according to an exemplary embodiment of the present disclosure.

[0120] Reference Fig.12 , the touch screen module 2000 may include a display device 1000, a polarizing plate 2010, a touch panel 2030, a touch controller 2040, and a window glass 2020. The display device 1000 may include a display panel 1010, a printed board 1020, and a display driving circuit 1030. The display driving circuit 1030 may be based on the reference Figures 1 to 10 The display driver ICs 200 , 200A, 200B, 200C, 200D, and 200E of the embodiments of the present disclosure are described.

[0121] The window glass 2020 may be made of a material such as acrylic or tempered glass, and may protect the touch screen module 2000 from scratches caused by external impact or repeated touches. A polarizing plate 2010 may be provided to improve the optical properties of the display panel 1010. The display panel 1010 may be formed by patterning a transparent electrode on the printed board 1020. The display panel 1010 may include a plurality of pixels for displaying a frame. The display drive circuit 1030 may operate in a normal mode and an AOD mode. For example, if a user's touch is not detected within a predetermined time, the touch screen module 2000 may change the mode from a normal mode to an AOD mode, and the display drive circuit 1030 may generate an image signal to display an AOD image in the AOD region of the display panel 1010.

[0122] The touch screen module 2000 may further include a touch panel 2030 and a touch controller 2040. The touch panel 2030 may be formed by patterning a transparent electrode such as indium tin oxide (ITO) on a glass substrate or a polyethylene terephthalate (PET) film. In an exemplary embodiment, the touch panel 2030 may be formed on the display panel 1010. For example, the pixels of the touch panel 2030 may be formed by merging with the pixels of the display panel 1010. The touch controller 2040 may detect the occurrence of a touch on the touch panel 2030, calculate the touch coordinates, and send the touch coordinates to a host (e.g., a processor). The touch controller 2040 may be integrated in one semiconductor chip together with the display driver circuit 1030.

[0123] While embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display driving circuit for driving a display panel, the display driving circuit include: a first memory configured to store main image data received from outside the display driving circuit; a second memory configured to store first additional image data in a normal mode and to store second additional image data in an always-on display mode having lower power consumption than the normal mode; a normal mode controller configured to operate in the normal mode according to the first additional image data stored in the second memory; an always-on display mode controller configured to operate in the always-on display mode according to the main image data stored in the first memory and the second additional image data stored in the second memory; as well as A decoder, the decoder being configured to: receiving the main image data from the first memory; Decoding the received main image data; as well as The decoded main image data is sent to the always-on display mode controller.

2. The display driving circuit according to claim 1 , further comprising an internal time information generating circuit, wherein the internal time information generating circuit is configured to receive a clock signal and time information, and generate internal time information based on the clock signal and the time information, in, The always-on display mode controller operates in the always-on display mode based on the internal time information.

3. The display driving circuit according to claim 2, in, The clock signal is received from outside the display driving circuit.

4. The display driving circuit according to claim 1, further comprising a distributor, wherein the distributor is configured to: receiving the first additional image data and the second additional image data from the second memory; sending the first additional image data to the normal mode controller according to a mode selection signal; and The second additional image data is sent to the always-on display mode controller according to the mode selection signal.

5. The display driving circuit according to claim 1, in, The normal mode controller is inoperative in the always-on display mode, and Wherein, the always-on display mode controller does not work in the normal mode.

6. The display driving circuit according to claim 1, in, The first memory includes a graphics random access memory and the second memory includes a static random access memory.

7. A display driving circuit for driving a display panel, the display driving circuit include: a first memory configured to store first main image data in a normal mode and to store second main image data in an always-on display mode having lower power consumption than the normal mode; a distributor configured to receive the first main image data and the second main image data from the first memory and distribute the first main image data and the second main image data according to a mode selection signal; a decoder configured to receive the first main image data from the distributor, decode the received first main image data, and generate decoded first main image data; a normal mode controller, the normal mode controller being configured to operate in the normal mode according to the decoded first main image data; as well as An always-on display mode controller is configured to receive the second main image data from the distributor and operate in the always-on display mode according to the second main image data.

8. The display driving circuit according to claim 7, further comprising a second memory, wherein the second memory is configured to store the first additional image data in the always-on display mode; in, The always-on display mode controller is further configured to operate in the always-on display mode according to the second main image data and the first additional image data.

9. The display driving circuit according to claim 8, in, The second memory is further configured to store second additional image data in the normal mode, The normal mode controller is further configured to operate in the normal mode according to the decoded first main image data and the second additional image data.

10. The display driving circuit according to claim 7, wherein the display driving circuit further comprises: include: an oscillator configured to generate a clock signal; as well as an internal time information generating circuit configured to generate internal time information based on the clock signal and time information received from outside the display driving circuit, Wherein, the always-on display mode controller is further configured to operate in the always-on display mode based on the internal time information.

11. The display driving circuit according to claim 7, further comprising an internal time information generating circuit, wherein the internal time information generating circuit is configured to generate internal time information based on a clock signal received from outside the display driving circuit and time information received from the outside, in, The always-on display mode controller is further configured to operate in the always-on display mode based on the internal time information.

12. A display driving circuit for driving a display panel, the display driving circuit include: a first memory configured to store merged image data received from outside the display driving circuit; image modification circuitry configured to extract additional image data from the merged image data and generate primary image data; an internal time information generating circuit configured to generate internal time information based on the clock signal and the time information; as well as An always-on display mode controller is configured to operate in an always-on display mode having lower power consumption than a normal mode according to the main image data, the additional image data, and the internal time information.

13. The display driving circuit according to claim 12, further comprising a decoder, wherein the decoder is configured to: receiving the merged image data from the first memory; Decoding the received combined image data; and sending the decoded merged image data to the image modification circuit, in, The image modification circuit is further configured to extract the additional image data from the decoded merged image data.

14. The display driving circuit according to claim 12, further comprising a second memory, wherein the second memory is configured as: receiving the additional image data from the image modification circuitry; storing the received additional image data; and The additional image data is provided to the always-on display mode controller.

15. The display driving circuit according to claim 12, further comprising a decoder, wherein the decoder is configured to: receiving the primary image data from the image modification circuit; Decoding the received main image data; as well as The decoded main image data is sent to the always-on display mode controller.

16. The display driving circuit according to claim 12, in, The clock signal is received from the outside.

17. The display driving circuit according to claim 12, in, The image modification circuit is further configured to generate the main image data by setting a data region obtained by extracting the additional image data from the combined image data as a black processing region after extracting the additional image data from the combined image data.

18. The display driving circuit according to claim 12, in, The image modification circuit is further configured to extract the additional image data from the merged image data based on an address received from the outside.

19. The display driving circuit according to claim 12, in, an address indicating a location of the additional image data in the combined image data is pre-stored in the image modification circuit, Wherein, the image modification circuit is further configured to extract the additional image data from the merged image data based on the address.

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