Wafer etching method

Abstract

The present invention discloses a wafer etching method, comprising: a pre-etching step of etching a wafer covered with a patterned mask layer to form an etched groove of a preset depth on the surface of the wafer; an oxidation etching step of oxidizing the bottom and sidewall surfaces of the etched groove to form an oxide layer, etching the oxide layer to obtain a smooth deposition surface; a deposition step of depositing a polymer layer on the smooth deposition surface; an etching step of etching the bottom and sidewalls of the etched groove; and repeating the deposition and etching steps until an etched groove of a target depth is formed. The deposition step forms an oxide layer with a smooth interface on the bottom and sidewalls of the etched groove, and etches the oxide layer to obtain a smooth deposition surface, which is conducive to subsequent deposition to obtain a uniform and continuous polymer layer and improves the uniformity of the etching process. Etching the oxide layer can also increase the aspect ratio of the etched groove, which is conducive to the deep silicon structure of the etched groove for reactants and by-products to enter and exit.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and more particularly, relates to a wafer etching method. Background Art

[0002] Deep silicon etching is a crucial process for manufacturing microstructures in industrial production, with applications in fields such as microelectromechanical systems (MEMS), microfluidic devices, and advanced packaging. In actual production, improving etching processability in large chambers and on large wafers can reduce production costs. For example, the wafer sizes currently used in mainstream production lines are 6-inch, 8-inch, and 12-inch.

[0003] Deep silicon etching is typically performed using the Bosch process, which employs an etch-deposition cycle. During the deposition step, C₄F₄ gas is introduced to form a protective film on the sidewalls and bottom of the etched trench. During the etching step, the protective film on the sidewalls and bottom is removed, while the exposed Si at the bottom is etched. As the cycle progresses, the etching depth gradually increases until the target depth is reached. As wafer size increases, the etcher's etching uniformity becomes increasingly challenging. This uniformity can be further divided into the uniformity of the etch profile and the uniformity of the etch depth. Due to edge effects, the electromagnetic field distorts at the edges, causing the etch profile to tilt, reducing the uniformity of the overall etch profile. Furthermore, the plasma's gas flow field can also tilt the etching angle. Therefore, determining which factor, the electromagnetic field or the gas flow field, plays a more significant role in the etching step, and their specific quantitative relationship, is crucial in determining the uniformity of the final etch profile.

[0004] In the existing method of depositing polymers in deep silicon structures, CF-based gases, such as C4F8, are passed into the chamber while applying source RF power to excite the CF gas into a plasma state and then deposited on the bottom and sidewalls of the deep silicon structure. Figure 1a Schematic diagram showing the deposition of fluorocarbon polymer on the top and sidewalls of a structure having deep groove patterns formed therein in the prior art. Figure 1b FIG. 1 shows a schematic diagram of depositing a fluorocarbon polymer on the bottom of a structure having a deep groove pattern formed thereon in the prior art. Figure 1a and Figure 1b As shown, the film formation is continuous at the bottom of the deep silicon structure, but discontinuous at the sidewalls. Where there is no deposition film on the sidewalls, lateral etching of Si will occur.

[0005] During the etching process, the etcher will form two dynamic fields, including electromagnetic field and flow field. When the excitation power is applied to the gas entering the chamber, plasma will be formed. At the same time, the lower electrode applies a vertical downward traction force. The combined effect of these two powers leads to the continuous etching. On the one hand, a certain electric field is distributed on the surface of the upper and lower electrodes during the etching process. Usually, the intensity in the middle is larger and uniform, and the intensity at the edge is smaller and uneven. This uneven distribution of the electric field causes the plasma to have a high density at the center and a low density at the edge. The edge position also tilts the direction of the electric field due to the edge effect. Figure 2 A schematic diagram of the distribution of electromagnetic fields in the existing etching process is shown in FIG. Figure 2 As shown in FIG, this distributed electric field inevitably leads to an inclined edge of the etched morphology. Existing methods for improving the uniformity of the etched morphology are also mostly performed by changing the uneven distribution of the electric field.

[0006] On the other hand, the flow field enters the interior of the chamber from the top of the chamber. Due to the structure of the lower electrode, the airflow distribution on the surface of the lower electrode is also uneven. Figure 3 A schematic diagram showing the distribution of the airflow field on the surface of the lower electrode in the existing etching process is shown in FIG. Figure 3 As shown in the figure, the uneven distribution of gas leads to a certain degree of unevenness after it is ionized into plasma state. The etching result is formed by the combined effect of the above two fields. Figure 4a A schematic diagram showing the etching profile at 1 mm from the wafer edge tilting toward the wafer center after the conventional etching process is shown. Figure 4b A schematic diagram showing the etching profile at 3 mm from the wafer edge tilting toward the wafer center after the conventional etching process is shown. Figure 5a A schematic diagram showing that the etching profile at 1 mm from the wafer edge is tilted away from the wafer center after the conventional etching process. Figure 5b The figure shows the schematic diagram of the etching morphology at 3mm from the wafer edge tilting away from the wafer center after the existing etching process. At different positions on the lower electrode surface, the etching morphology caused by the electromagnetic field and airflow field has different inclinations. Usually, the etching morphology has the following two situations: Figure 4a and Figure 4b As shown, the tilt direction of the etching morphology is consistent with the tilt direction of the edge electromagnetic field, as shown in Figure 5a and Figure 5b As shown, the tilt direction of the etching morphology is consistent with the tilt direction of the edge airflow field. In the prior art, the tilt direction of the etching morphology is used to determine whether the electromagnetic field or the airflow field has a greater impact on the etching process. If the tilt direction of the etching morphology is consistent with the tilt direction of the edge airflow field, the etching process will be judged as follows: Figure 4a and Figure 4b The results are consistent, and the electromagnetic field needs to be optimized. If the etching morphology is tilted in the same direction as Figure 5a and Figure 5bIf the results are consistent, the airflow field is optimized. This method of optimizing the electromagnetic field and airflow field through the final process results makes it difficult to grasp the quantitative relationship between the influence of the electromagnetic field and the airflow field on etching, and cannot quickly and effectively find out whether one of the electromagnetic field and the airflow field needs to be adjusted, or both quantities need to be adjusted. It takes a lot of manpower and time to determine the extent of the influence of the electromagnetic field and the airflow field on the etching process based on the process results, and also requires a large number of wafers.

[0007] Therefore, a wafer etching method is needed to form a continuous and uniform polymer film on the sidewalls and bottom of a deep silicon structure in a deposition process, thereby improving the uniformity of the etching process. Summary of the Invention

[0008] The object of the present invention is to provide a wafer etching method, which can deposit a continuous and uniform polymer layer on the bottom and sidewalls of an etching groove in a deposition process, thereby improving the uniformity of the etching process.

[0009] In order to achieve the above object, the present invention provides a wafer etching method, comprising:

[0010] A pre-etching step of etching the wafer covered with the patterned mask layer to form an etched groove of a preset depth on the surface of the wafer;

[0011] an oxidation etching step, oxidizing the bottom and sidewall surfaces of the etched groove to form an oxide layer, and etching the oxide layer to obtain a smooth deposition surface;

[0012] a deposition step of depositing a polymer layer on the smooth deposition surface;

[0013] an etching step of etching the bottom and sidewalls of the etched groove;

[0014] The deposition step and the etching step are repeated until an etched groove with a target depth is formed.

[0015] Preferably, it also includes:

[0016] The unevenness of the deposited polymer layer on the inner and outer walls of the etching groove at a preset position on the edge of the wafer is calculated to obtain the influence factors of the airflow field and the electromagnetic field on etching respectively; and the electromagnetic field and / or the airflow field are optimized according to the influence factors.

[0017] Preferably, the calculating of the unevenness of the deposited polymer layer on the inner and outer walls of the etched groove at a preset position on the edge of the wafer includes:

[0018] Calculate the first unevenness P1 of the deposited polymer layer on the inner and outer walls of the etched groove at a preset position on the edge of the wafer when the lower electrode is not activated in the deposition step and only the air flow field acts;

[0019] Calculate the second non-uniformity P2 of the polymer layer deposited on the inner and outer walls of the etching groove at a preset position on the wafer edge under the joint action of the gas flow field and the electromagnetic field when the deposition step is started for the electrode.

[0020] Preferably, calculate the first non-uniformity P1 through the following formula:

[0021]

[0022] where h1 is the thickness value of the polymer layer deposited on the inner wall of the etching groove; h2 is the thickness value of the polymer layer deposited on the outer wall of the etching groove.

[0023] Preferably, calculate the second non-uniformity P2 through the following formula:

[0024]

[0025] where h3 is the thickness value of the polymer layer deposited on the inner wall of the etching groove; h4 is the thickness value of the polymer layer deposited on the outer wall of the etching groove; P1 is the first non-uniformity.

[0026] Preferably, obtain the influence factors of the gas flow field and the electromagnetic field on etching through the following formulas respectively;

[0027] The influence factor of the gas flow field on etching is N1, and N1 is calculated through the following formula:

[0028] N1 = ;

[0029] The influence factor of the electromagnetic field on etching is N2, and N2 is calculated through the following formula: N2 = .

[0030] Preferably, optimize the electromagnetic field and / or the gas flow field according to the influence factors, including:

[0031] When N2 ≤ 20%, optimize the gas flow field;

[0032] When N1 ≤ 20%, optimize the electromagnetic field;

[0033] When 20% < N1 < 80% and 20% < N2 < 80%, optimize the electromagnetic field and the gas flow field respectively.

[0034] Preferably, optimizing the gas flow field includes: measuring the tilt angle of the etching groove at a preset position on the wafer edge;

[0035] adjusting the height of the focus ring according to the tilt angle; when the etched groove at the preset position on the edge of the wafer tilts toward the center of the wafer, the height of the focus ring is reduced by 1 mm for every 0.7° of the tilt angle; when the etched groove at the preset position on the edge of the wafer tilts away from the center of the wafer, the height of the focus ring is increased by 1 mm for every 0.7° of the tilt angle;

[0036] Optimizing the electromagnetic field includes:

[0037] Measuring the tilt angle of the etched groove at a preset position on the edge of the wafer;

[0038] The bottom opening diameter of the conical guide tube is adjusted according to the tilt angle; when the etching groove at the preset position of the wafer edge is tilted toward the center of the wafer, the bottom opening diameter of the conical guide tube is reduced by 10 mm for every 0.5° of the tilt angle; when the etching groove at the preset position of the wafer edge is tilted away from the center of the wafer, the bottom opening diameter of the conical guide tube is increased by 10 mm for every 0.5° of the tilt angle;

[0039] In which, the focusing ring and the conical guide tube are arranged in a semiconductor device for performing the wafer etching method. The focusing ring is arranged around the wafer to adjust the electromagnetic field distribution at the edge of the wafer, and the conical guide tube is arranged on the top of the wafer to adjust the airflow density distribution at the edge of the wafer.

[0040] Preferably, in the oxidation etching step, the upper electrode and the lower electrode are opened simultaneously, and oxygen is used to oxidize the bottom and sidewalls of the etching groove.

[0041] The beneficial effects of the present invention are:

[0042] 1. In the deposition process, the bottom and sidewall surfaces of the etched groove are oxidized to form an oxide layer. Since the protruding parts of the bottom and sidewalls of the etched groove have a large area exposed to oxygen and a fast oxidation rate, whereas the concave parts have a small area exposed to oxygen and a slow oxidation rate, an oxide layer with a smooth interface is formed on the bottom and sidewalls of the etched groove. Etching the oxide layer to obtain a smooth deposition surface is beneficial to subsequent deposition of a uniform and continuous polymer layer, improving the uniformity of the etching process. Etching the oxide layer can also expand the aspect ratio of the etched groove, which is beneficial to the deep silicon structure of the etched groove for reactants and by-products to enter and exit.

[0043] 2. Calculate the unevenness of the deposited polymer layer on the inner and outer walls of the etched groove at the preset position on the wafer edge, obtain the etching influence factors of the airflow field and electromagnetic field on the wafer edge position, and optimize the electromagnetic field and / or airflow field according to the influence factors to improve the etching morphology uniformity of the etched groove.

[0044] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention may be implemented in various forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present invention more thorough and complete and to fully convey the scope of the present invention to those skilled in the art.

[0046] Figure 1a A schematic diagram showing the deposition of fluorocarbon polymer on the top and sidewalls of a deep trench structure formed in the prior art is shown.

[0047] Figure 1b A schematic diagram showing the deposition of fluorocarbon polymer on the bottom of a deep trench structure formed in the prior art is shown.

[0048] Figure 2 A schematic diagram of the distribution of the electromagnetic field in the existing etching process is shown.

[0049] Figure 3 A schematic diagram showing the distribution of the airflow field on the surface of the lower electrode in the existing etching process is shown.

[0050] Figure 4a A schematic diagram showing that the etching profile 1 mm away from the wafer edge is tilted toward the center of the wafer after the existing etching process.

[0051] Figure 4b A schematic diagram showing that the etching profile at 3 mm from the wafer edge is tilted toward the center of the wafer after the conventional etching process.

[0052] Figure 5a A schematic diagram showing that the etching profile 1 mm away from the wafer edge is tilted away from the wafer center after the existing etching process.

[0053] Figure 5b A schematic diagram showing that the etching profile 3 mm away from the wafer edge is tilted away from the wafer center after the existing etching process.

[0054] Figure 6 A deposition process flow chart of a wafer etching method according to an embodiment of the present invention is shown.

[0055] Figure 7a A schematic diagram of the etching groove structure before the deposition step is performed in one embodiment of the present invention is shown.

[0056] Figure 7b A schematic diagram of the etching groove structure after oxidation in one embodiment of the present invention is shown.

[0057] Figure 7c A schematic diagram of the etching groove structure after the oxide layer is etched in one embodiment of the present invention is shown.

[0058] Figure 7d A schematic diagram of the etching groove structure after depositing a polymer layer in one embodiment of the present invention is shown.

[0059] Figure 8a A cross-sectional view of the air flow field in a reaction chamber of an etcher illustrating the ICP principle according to one embodiment is shown.

[0060] Figure 8b A top view of the air flow field in a reaction chamber of an etcher showing the ICP principle of one embodiment.

[0061] Figure 9a An electron microscope scanning image of the inner wall of an etched groove before deposition in one embodiment is shown.

[0062] Figure 9b An electron microscope scanning image of the outer wall of the etched groove before deposition in one embodiment is shown.

[0063] Figure 9c An electron microscope scanning image of the inner wall of an etched groove located at the center of a wafer after deposition in one embodiment is shown.

[0064] Figure 9d An electron microscope scanning image of the outer wall of an etched groove located at the center of a wafer after deposition in one embodiment is shown.

[0065] Figure 9e An electron microscope scanning image of the inner wall of an etched groove located at the edge of a wafer after deposition in one embodiment is shown.

[0066] Figure 9f An electron microscope scanning image of the outer wall of an etched groove located at the edge of a wafer after deposition in one embodiment is shown.

[0067] Figure 10a An electron microscope scanning image of the wafer surface before deposition in one embodiment is shown.

[0068] Figure 10b An electron microscope scanning image of the wafer surface after deposition without activating the lower electrode in one embodiment is shown.

[0069] Figure 10c An electron microscope scanning image of the wafer surface after the lower electrode is activated for deposition in one embodiment is shown.

[0070] Figure 11a A diagram showing a corresponding relationship between the distance from the wafer edge and the first non-uniformity caused by the airflow field according to an embodiment is shown.

[0071] Figure 11bA diagram showing a corresponding relationship between the distance from the wafer edge and the second non-uniformity caused by the electromagnetic field according to an embodiment is shown.

[0072] Figure 12 A schematic structural diagram of an ICP etcher according to an embodiment is shown.

[0073] Description of reference numerals:

[0074] 1. Reaction chamber; 2. Wafer tray; 3. Conical air inlet; 4. Focusing ring; 5. RF coil; 6. Wafer; 7. Air inlet; 11. Etched part; 12. Oxide layer; 13. Surface to be deposited; 14. Polymer layer. DETAILED DESCRIPTION

[0075] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Instead, these embodiments are provided to make the present invention more thorough and complete and to fully convey the scope of the present invention to those skilled in the art.

[0076] Example 1

[0077] Figure 6 FIG1 shows a deposition process flow chart of a wafer etching method according to an embodiment of the present invention. Figure 7a FIG. 1 shows a schematic diagram of the etching groove structure before the deposition step in one embodiment of the present invention.

[0078] Figure 7b FIG. 1 shows a schematic diagram of the structure of the etched groove after oxidation in one embodiment of the present invention. Figure 7c FIG. 1 shows a schematic diagram of the etching groove structure after the oxide layer is etched in one embodiment of the present invention. Figure 7d A schematic diagram of the etching groove structure after depositing a polymer layer in one embodiment of the present invention is shown.

[0079] A wafer etching method according to an embodiment of the present invention includes:

[0080] A pre-etching step of etching the wafer covered with the patterned mask layer to form an etched groove of a preset depth on the surface of the wafer;

[0081] an oxidation etching step, wherein the bottom and sidewall surfaces of the etched groove are oxidized to form an oxide layer, and the oxide layer is etched to obtain a smooth deposition surface;

[0082] a deposition step of depositing a polymer layer on the smooth deposition surface;

[0083] an etching step of etching the bottom and sidewalls of the etched groove;

[0084] The deposition step and the etching step are repeated until an etched groove of a target depth is formed.

[0085] There are two problems with the traditional deposition step of deep silicon etching. On the one hand, the plasma has a certain mean free path, which makes it difficult for reactants to enter the etching groove of the deep silicon structure, and it is also difficult for products to come out of the etching groove of the deep silicon structure; on the other hand, since the etching groove of the deep silicon structure is obtained by the Bosch process, its sidewall is not smooth and has a scallop structure, such as Figure 7a As shown, the process recipe of the deposition steps shown in Table 1 is used to deposit the bottom and sidewalls of the etched groove. This deposition process is difficult to obtain a continuous and uniform polymer layer.

[0086]

[0087] Table 1 Process recipe of traditional deposition steps

[0088] In view of the problems existing in the above-mentioned traditional deposition process, the traditional deposition steps are improved.

[0089] like Figure 6 As shown, the deposition step of an embodiment of the present invention adopts the process recipe shown in Table 2.

[0090] Step 1: In the oxidation etching step, the upper electrode and the lower electrode are opened at the same time, and oxygen is used to oxidize the bottom and sidewalls of the etching groove.

[0091] like Figure 7a As shown, before deposition is performed on the etched groove, the etched portion 11 of the deposition groove has a scallop structure. The outside of the etched groove is wafer silicon. O2 is introduced into the reaction chamber to oxidize the bottom and sidewalls of the etched groove. Since the protruding portion of the shell structure has a large area exposed to oxygen, the oxidation rate is fast, while the concave portion has a small area exposed to oxygen and the oxidation rate is slow, so that an oxide layer 12 with a smooth interface is formed on the bottom and sidewalls of the etched groove, as shown in FIG. Figure 7b shown.

[0092] Step 2: Etching the oxide layer to obtain a smooth deposition surface;

[0093] The etching gas used for etching the oxide layer is C4F8, and the oxide layer formed in step 1 is etched to obtain a smooth surface 13 to be deposited. Figure 7c As shown, it is beneficial to obtain a uniform and continuous polymer layer during deposition, and etching can also expand the aspect ratio of the etched groove to a certain extent, which is beneficial for reactants and by-products to enter and exit the deep silicon structure.

[0094] Step 3: Without starting the lower electrode, a polymer layer is deposited on the bottom and sidewalls of the etched groove.

[0095] By introducing C4F8 gas into the reaction chamber, a continuous and smooth polymer layer 14 can be obtained on the bottom and sidewalls of the etched groove without applying power to the lower electrode, thereby avoiding lateral etching of silicon caused by the discontinuity of the polymer layer 4 on the sidewalls of the etched groove in the subsequent etching steps. The polymer layer 4 is a fluorocarbon polymer deposited in the etched groove with a thickness of microns, such as Figure 7d shown.

[0096]

[0097] Table 2 Deposition steps and process formula of the present invention

[0098] Oxygen is introduced during the deposition process. Since the protruding parts of the bottom and sidewalls of the etched grooves have a large area in contact with oxygen and a fast oxidation rate, while the concave parts have a small area in contact with oxygen and a slow oxidation rate, an oxide layer with a smooth interface is formed on the bottom and sidewalls of the etched grooves. The oxide layer is etched to obtain a smooth deposition surface, which is conducive to the subsequent deposition of a uniform and continuous polymer layer and improves the uniformity of the etching process. Etching the oxide layer can also expand the aspect ratio of the etched groove, which is conducive to the deep silicon structure of the etched groove for reactants and by-products to enter and exit.

[0099] Example 2

[0100] Figure 8a A cross-sectional view of the air flow field in the reaction chamber of an etching machine according to the ICP principle of an embodiment is shown. Figure 8b A top view of the air flow field in a reaction chamber of an etcher showing the ICP principle of one embodiment. Figure 9a FIG1 shows an electron microscope scanning image of the inner wall of the etched groove before deposition in one embodiment. Figure 9b An electron microscope scanning image of the outer wall of the etched groove before deposition in one embodiment is shown. Figure 9c An electron microscope scanning image of the inner wall of an etched groove located at the center of a wafer after deposition in one embodiment is shown. Figure 9d An electron microscope scanning image of the outer wall of the etched groove located at the center of the wafer after deposition in one embodiment is shown. Figure 9e An electron microscope scanning image of the inner wall of an etched groove located at the edge of a wafer after deposition in one embodiment is shown. Figure 9f An electron microscope scanning image of the outer wall of the etched groove located at the edge of the wafer after deposition in one embodiment is shown. Figure 10a FIG1 shows an electron microscope scanning image of the wafer surface before deposition in one embodiment. Figure 10b FIG1 shows an electron microscope scanning image of the wafer surface after deposition without activating the lower electrode in one embodiment. Figure 10c FIG1 shows an electron microscope scanning image of the wafer surface after the lower electrode is started to deposit in one embodiment. Figure 11aFIG. 1 shows a corresponding relationship diagram of the first pair of non-uniformities caused by the distance from the wafer edge and the airflow field according to an embodiment. Figure 11b FIG. 1 shows a corresponding relationship diagram of the distance from the wafer edge to the second non-uniformity caused by the electromagnetic field according to an embodiment. Figure 12 A schematic structural diagram of an ICP etcher according to an embodiment is shown.

[0101] A wafer etching method according to an embodiment of the present invention includes:

[0102] A pre-etching step of etching the wafer covered with the patterned mask layer to form an etched groove of a preset depth on the surface of the wafer;

[0103] The pre-etching step also includes: calculating the unevenness of the deposited polymer layer on the inner and outer walls of the etching groove at a preset position on the edge of the wafer, and obtaining the influence factors of the airflow field and the electromagnetic field on etching respectively; and optimizing the electromagnetic field and / or airflow field according to the influence factors.

[0104] As an example, the etching groove closest to the edge of the wafer is selected to calculate the non-uniformity of the deposited polymer layer on its inner and outer walls.

[0105] This embodiment uses an ICP principle etcher, that is, an inductively coupled plasma etcher. When the upper electrode power is turned on, the electromagnetic field only exists in the upper reaction chamber and will not affect the wafer surface. At this time, the wafer surface only has the effect of the gas flow field, such as Figure 8a and Figure 8b As shown in the figure, when the bottom electrode power is turned on, the electromagnetic field and gas flow field act simultaneously on the wafer surface. Therefore, the magnitude of the electromagnetic field and gas flow field effects can be distinguished by comparing the process results with and without the bottom electrode turned on. In addition, if the bottom electrode power is turned off, etching cannot proceed, but polymer layer deposition can proceed normally without the bottom electrode power turned on.

[0106] Without activating the lower electrode, a polymer layer was deposited on the etched grooves on the wafer surface using the same deposition process recipe as shown in Table 2. Since the lower electrode was not activated during the deposition step in Example 1 of the present invention, the effect of the electromagnetic field on the wafer surface was negligible, and the difference in thickness of the polymer layer deposited on the inner and outer walls of the etched grooves was only affected by the gas flow field.

[0107] like Figures 9a to 9fThe electron microscope scanning results show that the deposition thickness on both the inner and outer walls of the etched groove at the center of the wafer is almost the same, indicating that the gas flow field at the center of the wafer is evenly distributed. However, there is a significant difference in the deposition thickness on the inner and outer walls of the etched groove at the edge of the wafer, with the outer wall thickness being significantly thinner than the inner wall thickness. Due to the exhaust structure of the etcher's reaction chamber, the airflow direction at the edge of the wafer points to the outside of the wafer, so the deposition thickness becomes thinner under the action of the airflow field. The mechanism is that the charged ions carried by the airflow physically bombard the deposits, resulting in a thicker polymer layer on the side opposite to the airflow direction.

[0108] To verify the rationality of the above mechanism, a deposition process recipe as shown in Table 3 was designed. The lower electrode power was turned on, and the electric field generated by the lower electrode was used to make the charged ions in the plasma move toward the wafer surface. The movement of charged ions entrained by the airflow was simulated and compared with the results without turning on the lower electrode power.

[0109]

[0110] Table 3 Deposition formula for starting the lower electrode power

[0111] The results are as follows Figures 10a to 10c As shown, before deposition, there is a thin layer of silicon dioxide covered by a photoresist on the surface of the wafer. When the lower electrode is not activated, a polymer layer can be deposited on the surface, while when a certain lower electrode is activated, no polymer layer is deposited.

[0112] It can be seen that the deposition experiment on the etching groove closest to the edge of the wafer can obtain the quantitative relationship between the influence of the electromagnetic field and the gas flow field on etching.

[0113] The deposition experiment steps of this embodiment are as follows:

[0114] Step 1: Select an etching groove closest to the edge of the wafer;

[0115] Step 2: Calculate the non-uniformity of the deposited polymer layer on the inner and outer walls of the etched groove at a preset position on the wafer edge, including:

[0116] Calculate the first non-uniformity P1 of the deposited polymer layer on the inner and outer walls of the etched groove at a preset position on the edge of the wafer when the lower electrode is not activated during the deposition step and only the air flow field is applied;

[0117] The first unevenness P1 is calculated by the following formula: ;

[0118] Wherein, h1 is the thickness of the polymer layer deposited on the inner wall of the etching groove; h2 is the thickness of the polymer layer deposited on the outer wall of the etching groove.

[0119] As an example, without starting the lower electrode and under the action of the airflow field, the thickness of the polymer layer deposited on the outer wall of the etching groove is measured to be h2=2um, and the thickness of the polymer layer deposited on the inner wall of the etching groove is measured to be h1=2.5um. Under the influence of the airflow field, the first unevenness P1 of the polymer layer deposited on the inner and outer walls of the etching groove is -11.1%.

[0120] As a preferred solution, the second unevenness P2 of the deposited polymer layer on the inner and outer walls of the etched groove at a preset position on the wafer edge is calculated when the lower electrode is started in the deposition step and under the combined action of the airflow field and the electromagnetic field.

[0121] The second unevenness P2 is calculated by the following formula:

[0122]

[0123] Where h3 is the thickness of the polymer layer deposited on the inner wall of the etched groove; h4 is the thickness of the polymer layer deposited on the outer wall of the etched groove; and P1 is the first unevenness. The first unevenness P1 is the unevenness due to the airflow field, and the second unevenness P2 is the unevenness due to the electromagnetic field.

[0124] As an example, when the lower electrode is started and the air flow field and electromagnetic field are acted upon, the thickness of the polymer layer deposited on the outer wall of the etching groove is measured to be h3=6.3um, and the thickness of the polymer layer deposited on the inner wall of the etching groove is measured to be h4=6um. Under the combined influence of air flow and electromagnetic field, the second unevenness P2 of the polymer layer deposited on the inner and outer walls of the etching groove is -13.4%.

[0125] As a preferred solution, the influence factors of the airflow field and the electromagnetic field on etching are obtained respectively by the following formulas; the influence factor of the airflow field on etching is N1, which is calculated by the following formula:

[0126] N1= ;

[0127] The influence factor of electromagnetic field on etching is N2, which is calculated by the following formula:

[0128] N2= .

[0129] As an example, the first unevenness P1 of the polymer layer deposited on the inner and outer walls of the etched groove is -11.1%, and the second unevenness P2 of the polymer layer deposited on the inner and outer walls of the etched groove is -13.4%. The influence factor N1 of the airflow field on etching is 54.7%, and the influence factor N2 of the electromagnetic field on etching is 45.3%, with the two factors acting in opposite directions.

[0130] As an example, Figure 11a and Figure 12 As shown in Figure b, the influence factors of the electromagnetic field and the gas flow field at different positions of the wafer are obtained in a 12-inch etcher of a certain model, as well as the numerical values of the first non-uniformity and the second non-uniformity at different positions of the wafer. The first non-uniformity P1 is the non-uniformity affected by the gas flow field, and the second non-uniformity P2 is the non-uniformity affected by the electromagnetic field. For example, at a position 15 mm away from the wafer edge, the first non-uniformity caused by the gas flow field is -4.56%, and the non-uniformity caused by the combined action of the gas flow field and the electromagnetic field is +6.08%, and the second non-uniformity caused by the electromagnetic field is +10.64%. Therefore, the influence factor N2 of the electromagnetic field on etching is 70%, and the influence factor N1 of the gas flow field on etching is 30%, and the two are in opposite directions.

[0131] As a preferred solution, optimize the electromagnetic field and / or the gas flow field according to the influence factor, including:

[0132] When N2 ≤ 20%, optimize the gas flow field;

[0133] When N1 ≤ 20%, optimize the electromagnetic field;

[0134] When 20% < N1 < 80% and 20% < N2 < 80%, optimize the electromagnetic field and the gas flow field respectively.

[0135] Specifically, when the influence factor of the gas flow field or the current field is less than or equal to 20%, the influence of this gas flow field or electromagnetic field on etching can be ignored, and only the electromagnetic field or gas flow field with an influence factor greater than 80% needs to be optimized. When the influence factor N1 of the gas flow field on etching is 54.7% and the influence factor N2 of the electromagnetic field on etching is 45.3%, it is necessary to optimize both the electromagnetic field and the gas flow field simultaneously.

[0136] Obtain the relationship between the influence of the current and the flow field on the etching uniformity. Furthermore, according to the magnitudes of the influence factors of the electromagnetic field and the flow field, different methods can be comprehensively selected to solve the problem of etching topography tilt, such as debugging the corresponding hardware configuration and process parameters of the etcher, etc., which can improve the uniformity of the process results in subsequent etching steps.

[0137] The wafer etching method of this embodiment uses a semiconductor device that executes the wafer etching process. This semiconductor device uses an ICP etcher, such as Figure 12 As shown, a focusing ring 4 is provided outside the wafer 6 in the etcher, and a conical deflector 3 is provided on top of the wafer 6. The focusing ring 4 is arranged around the wafer and is used to adjust the electromagnetic field distribution at the wafer edge. This etcher also includes a reaction chamber 1, a wafer tray 2, a radio frequency coil 5, and an air inlet 7. The conical air inlet 3 is provided on top of the wafer and is used to adjust the gas flow density distribution at the wafer 6 edge.

[0138] As a preferred solution, optimizing the airflow field includes: measuring the tilt angle of the etching groove at a preset position on the edge of the wafer.

[0139] The height of the focus ring 4 is adjusted according to the tilt angle. The focus ring 4 can be replaced and its height adjusted to adjust the electromagnetic field distribution at the edge of the wafer 1, thereby reducing the problem of tilted etching morphology caused by uneven electromagnetic field.

[0140] When the etched groove at the preset position on the wafer edge tilts toward the wafer center, the height of the focus ring is reduced by 1mm for every 0.7° tilt angle. When the etched groove at the preset position on the wafer edge tilts away from the wafer center, the height of the focus ring is increased by 1mm for every 0.7° tilt angle.

[0141] Optimizing the electromagnetic field includes: measuring the tilt angle of the etched groove at a preset location on the edge of the wafer;

[0142] According to the inclination angle of the etching morphology, the size of the bottom opening of the conical guide tube 3 is replaced and adjusted. When the etching groove at the preset position of the wafer edge is tilted toward the center of the wafer, the diameter of the bottom opening of the conical guide tube 3 is reduced by 10mm for every 0.5° inclination angle; when the etching groove at the preset position of the wafer edge is tilted away from the center of the wafer, the diameter of the bottom opening of the conical guide tube is increased by 10mm for every 0.5° inclination angle;

[0143] For example, if the deposition experiment shows that the electromagnetic field influence factor on etching is greater than 80%, the RF power in the original etching process parameters can be adjusted, or the air flow field of related hardware such as the RF coil can be optimized. If the deposition experiment shows that the electromagnetic field influence factor on etching is greater than 80%, the gas flow in the original etching process parameters can be adjusted, or related hardware such as the etcher's air inlet and exhaust channels can be optimized.

[0144] This method calculates the unevenness of the deposited polymer layer on the inner and outer walls of the etching groove at a preset position on the edge of the wafer, obtains the etching influence factors of the airflow field and the electromagnetic field on the edge of the wafer, and optimizes the electromagnetic field and / or airflow field according to the influence factors, thereby improving the etching morphology uniformity of the etching groove.

[0145] While the embodiments of the present invention have been described above, the above description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A wafer etching method, characterized in that: Including: A pre-etching step of etching a wafer covered with a patterned mask layer to form an etching groove with a preset depth on the surface of the wafer; An oxidation etching step of oxidizing the bottom and sidewall surfaces of the etching groove to form an oxide layer and etching the oxide layer to obtain a smooth deposition surface; A deposition step of depositing a polymer layer on the smooth deposition surface; An etching step of etching the bottom and sidewalls of the etching groove; Repeating the deposition step and the etching step until an etching groove with a target depth is formed; The deposition step further includes: Calculating the non-uniformity caused by the thickness difference of the polymer layer deposited on the inner and outer walls of the etching groove at a preset position on the wafer edge, and respectively obtaining the influence factors of the gas flow field and the electromagnetic field on etching; optimizing the electromagnetic field and / or the gas flow field according to the influence factors.

2. The wafer etching method according to claim 1, wherein: The calculating the non-uniformity caused by the thickness difference of the polymer layer deposited on the inner and outer walls of the etching groove at a preset position on the wafer edge includes: Calculating a first non-uniformity P1 caused by the thickness difference of the polymer layer deposited on the inner and outer walls of the etching groove at a preset position on the wafer edge when the lower electrode is not started in the deposition step and only under the action of the gas flow field; Calculating a second non-uniformity P2 caused by the thickness difference of the polymer layer deposited on the inner and outer walls of the etching groove at a preset position on the wafer edge when the lower electrode is started in the deposition step and under the combined action of the gas flow field and the electromagnetic field.

3. The wafer etching method according to claim 2, wherein: Calculating the first non-uniformity P1 through the following formula: Where, h1 is the thickness value of the polymer layer deposited on the inner wall of the etching groove; h2 is the thickness value of the polymer layer deposited on the outer wall of the etching groove.

4. The wafer etching method according to claim 3, wherein: Calculating the second non-uniformity P2 through the following formula: Where, h3 is the thickness value of the polymer layer deposited on the inner wall of the etching groove; h4 is the thickness value of the polymer layer deposited on the outer wall of the etching groove; P1 is the first non-uniformity.

5. The wafer etching method according to claim 4, wherein: Respectively obtaining the influence factors of the gas flow field and the electromagnetic field on etching through the following formula; The influence factor of the gas flow field on etching is N1, and N1 is calculated through the following formula: N1= ； The influence factor of the electromagnetic field on etching is N2, which is calculated by the following formula: N2= .

6. The wafer etching method according to claim 4, wherein: Optimizing the electromagnetic field and / or the gas flow field according to the influence factors includes: When N2≤20%, optimizing the gas flow field; When N1≤20%, optimizing the electromagnetic field; When 20%<N1<80% and 20%<N2<80%, respectively optimizing the electromagnetic field and the gas flow field.

7. The wafer etching method according to claim 6, wherein Optimizing the gas flow field includes: Measuring the tilt angle of the etching groove at a preset position on the wafer edge; Adjusting the height of the focus ring according to the tilt angle; when the etching groove at the preset position on the wafer edge tilts towards the wafer center, for every 0.7° of the tilt angle, reducing the height of the focus ring by 1 mm; when the etching groove at the preset position on the wafer edge tilts away from the wafer center, for every 0.7° of the tilt angle, increasing the height of the focus ring by 1 mm; Optimizing the electromagnetic field includes: Measuring the tilt angle of the etching groove at a preset position on the wafer edge; The bottom opening diameter of the conical guide tube is adjusted according to the tilt angle; when the etching groove at the preset position of the wafer edge is tilted toward the center of the wafer, the bottom opening diameter of the conical guide tube is reduced by 10 mm for every 0.5° of the tilt angle; when the etching groove at the preset position of the wafer edge is tilted away from the center of the wafer, the bottom opening diameter of the conical guide tube is increased by 10 mm for every 0.5° of the tilt angle; In which, the focusing ring and the conical guide tube are arranged in a semiconductor device for performing the wafer etching method. The focusing ring is arranged around the wafer to adjust the electromagnetic field distribution at the edge of the wafer, and the conical guide tube is arranged on the top of the wafer to adjust the airflow density distribution at the edge of the wafer.

8. The wafer etching method according to claim 1, wherein: In the oxidation etching step, the upper electrode and the lower electrode are opened at the same time, and oxygen is used to oxidize the bottom and sidewalls of the etching groove.

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