Ohmic contact formation in SiC-based electronic devices

Abstract

Embodiments of the present application relate to forming ohmic contacts in SiC-based electronic devices. A method for manufacturing a SiC-based electronic device includes the steps of: implanting a P-type dopant substance onto the front side of a solid body composed of SiC having N-type conductivity, thereby forming an implanted region extending from the front side in the solid body and having a top surface coplanar with the front side; and generating a laser beam directed toward the implanted region to heat the implanted region to a temperature between 1500°C and 2600°C, thereby forming a carbon-rich electrical contact region at the implanted region. The carbon-rich electrical contact region forms an ohmic contact.

Description

Technical Field

[0001] The present disclosure relates to a SiC-based electronic device and a method for manufacturing the same, and in particular to forming an ohmic electrical contact region in the SiC-based electronic device. Background Art

[0002] Semiconductor materials have a wide band gap, especially a band gap energy value Eg greater than 1.1eV, low on-resistance (R ON ), high thermal conductivity, high operating frequencies, and high charge carrier saturation rates make these semiconductor materials ideal for producing electronic components, such as diodes or transistors, particularly for power applications. Silicon carbide (SiC), a material that exhibits these characteristics and is designed for use in the manufacture of electronic components, is a material. In particular, silicon carbide, in its various polymorphs (e.g., 3C-SiC, 4H-SiC, and 6H-SiC), outperforms silicon in terms of the aforementioned properties.

[0003] Electronic devices fabricated on silicon-carbon substrates offer numerous advantages over similar devices fabricated on silicon substrates, including low output impedance during conduction, low leakage current, high operating temperature, and high operating frequency. In particular, SiC Schottky diodes exhibit high switching performance, making SiC electronic devices particularly advantageous for high-frequency applications. Current applications place high demands on the device's electrical properties and long-term reliability. Summary of the Invention

[0004] The present disclosure will provide a SiC-based electronic device and a method for manufacturing a SiC-based electronic device, thereby overcoming the shortcomings of the prior art.

[0005] The present disclosure is directed to a metal oxide semiconductor field effect transistor (MOSFET), comprising: a substrate having a first conductivity type and having a first surface and a second surface; and a first doped region having a second conductivity type. A second doped region is present in the first doped region, the second doped region having the first conductivity type, and a first gate on the first surface overlaps a first edge of the second doped region. A second gate on the first surface overlaps a second edge of the second doped region, and a first ohmic contact is between the first gate and the second gate, the first ohmic contact is in the second doped region, and the first ohmic contact is between the second surface and the first surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a better understanding of the present disclosure, preferred embodiments of the present disclosure will now be described by way of non-limiting examples only with reference to the accompanying drawings, in which:

[0007] Figure 1 shows in cross-section an MPS device according to a known embodiment;

[0008] Figure 2A and Figure 2B The method for manufacturing a Figure 1 intermediate steps of MPS devices; and

[0009] Figures 3A to 3C The cross-sectional view shows a method according to known technology. Figure 2A and Figure 2B After the step of Figure 1 The steps of forming ohmic contacts in MPS devices;

[0010] Figure 4 The top view shows a method according to the known technology. Figures 3A to 3B Undesirable areas formed by manufacturing steps;

[0011] Figure 5 shows in cross-section a MOSFET device according to a known embodiment;

[0012] Figure 6 An MPS device according to an embodiment of the present disclosure is shown in cross-section;

[0013] 7A to 7D The cross-sectional view shows a method for manufacturing a Figure 6 Steps for MPS devices;

[0014] Figure 8 Pictured Figure 6 Voltage-current curve of the MPS device;

[0015] Figure 9 A MOSFET device according to an embodiment of the present disclosure is illustrated in cross-sectional view;

[0016] Figure 10 A cross-sectional view shows a method for manufacturing a Figure 9 the steps of:

[0017] Figure 11 A cross-sectional view shows a method for manufacturing a Figure 9 steps of the MOSFET device. DETAILED DESCRIPTION

[0018] Figure 1 A hybrid PiN-Schottky (MPS) device 1 of known type is shown in a side or cross-sectional view in a (triaxial) Cartesian reference system having X, Y, Z axes.

[0019] The MPS device 1 comprises: a substrate 3 consisting of N-type SiC having a first doping concentration, provided with a surface 3a opposite to the surface 3b and having a thickness of approximately 350 μm; a drift layer (epitaxially grown) 2 consisting of N-type SiC having a second doping concentration lower than the first doping concentration, the drift layer extending above the surface 3a of the substrate 3 and having a thickness between 5 and 15 μm; an ohmic contact region 6 (e.g., consisting of nickel silicide) extending above the surface 3b of the substrate 3; a cathode metallization layer 16 extending above the ohmic contact region 6; an anode metallization layer 8 extending above the top surface 2a of the drift layer 2; a plurality of junction-barrier (JB) elements 9 in the drift layer 2, facing the top surface 2a of the drift layer 2 and each comprising a corresponding P-type implant region 9′ and an ohmic contact 9″ consisting of a metal material; and an edge termination region or guard ring 10 (optional), in particular a P-type implant region, which completely surrounds the JB elements 9.

[0020] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. In particular, a Schottky junction (semiconductor-metal) is formed by portions of the drift layer 2 being in direct electrical contact with corresponding portions of the anode metallization 8.

[0021] The region of the MPS device 1 including the JB element 9 and the Schottky diode 12 (ie, the region included in the guard ring 10 ) is the active region 4 of the MPS device 1 .

[0022] refer to Figure 2A and Figure 2B , used to manufacture Figure 1 Step 1 of the MPS device is envisioned ( Figure 2A ) a step of mask implantation of a dopant substance (e.g., boron or aluminum) of a second conductivity type (P). Figure 2A The implantation is illustrated by arrow 18. A mask 11 is used for the implantation, in particular a hard mask made of silicon oxide or tetraethyl orthosilicate (TEOS). The implantation region 9' and the edge termination region 10 are thus formed. Then, Figure 2B , the mask 11 is removed, and a thermal annealing step is performed for diffusion and activation in Figure 2A The thermal annealing is performed, for example, at a temperature above 1600° C. (for example, between 1700° C. and 1900° C. and in some cases even higher).

[0023] refer to Figures 3A to 3C , and then perform a further step of forming an ohmic contact 9″. Figure 3A, a deposition mask 13 composed of silicon oxide or TEOS is formed to cover the surface area of ​​the drift layer 2 except the implantation region 9' (and the edge termination region 10, if present). In other words, the mask 13 has a through opening 13a at the implantation region 9' (and optionally at least a portion of the edge termination region 10). Then Figure 3B , nickel deposition is performed on the mask 13 and in the through-opening 13a ( Figure 3B The nickel thus deposited reaches and contacts the implantation region 9' and the edge termination region 10 via the through-opening 13a.

[0024] refer to Figure 3C A nickel silicide ohmic contact 9″ can be formed at the through-opening 13 a by a chemical reaction between the deposited nickel and the silicon of the drift layer 2, followed by thermal annealing at a high temperature (between 900° C. and 1200° C.) for a period of time from 1 minute to 120 minutes. In practice, the deposited nickel reacts where it contacts the surface material of the drift layer 2, forming Ni2Si (i.e., an ohmic contact). Next, a step of removing the metal extending above the mask 13 and removing the mask 13 is performed.

[0025] The applicant has discovered that by Figure 4 As illustrated by the examples in FIG. 1 , in any case, a reaction occurs between the nickel of the metal layer 14 and the mask 13 in direct contact, although the reaction is limited. Figure 4 yes Figure 3B A top view (in plane XY) of a portion of a device, in particular the portion delimited by the dashed line and the portion delimited by the dashed line Figure 3B A top view of the area identified by reference numeral 15 in FIG. Figure 4 Involved in Figure 3B and Figure 3C An intermediate manufacturing step between the steps of , that is, the mask 13 is still present, but the nickel layer 14 is removed. Figure 4 It can be noted that irregular regions or islands 17 extend above the mask 13 and are due to undesired reactions between the silicon and nickel of the mask 13. The applicant has further noted that similar jagged regions extend beneath the mask 13, i.e. on the surface 2a of the drift layer 2. Figure 4In the figure, these jagged areas are identified by reference numeral 16 and are composed of a conductive material (including nickel). In the case where the extension of the jagged area 16 in the plane XY (especially along X) is greater than the corresponding extension of the implanted area 9', a short circuit will occur, which may lead to device failure. Specifically, in the case where the undesired conductive area is to extend in the area dedicated to the Schottky contact, an ohmic contact or a quasi-ohmic contact (a Schottky contact with a low barrier) will be formed on the N-type region (resistance from an electrical standpoint). As a result, a continuous current will flow in both forward bias and reverse bias, resulting in a loss of diode characteristics.

[0026] The same problem is encountered during the formation of ohmic contacts at the body and source regions of SiC MOSFET devices.

[0027] Figure 5 A MOSFET device 20 is shown, which includes a semiconductor body 22 composed of a semiconductor material (including a substrate and, optionally, one or more epitaxial layers), the semiconductor body having a top surface 22a and a bottom surface 22b. The semiconductor body 22 has, for example, an N-doping. A drain region or doped region 24, formed, for example, by implanting an N-type dopant substance (N+ doping), extends at the bottom surface 22b. At the top surface 22a, a body region 25 (having a P-doping) surrounds a source region 28 (N+ doping). A gate structure 26, comprising a stack formed by a gate conductive layer 26a (e.g., polysilicon) and a gate dielectric layer 26b, extends above the top surface 22a, partially overlapping the source region or doped region 28. A corresponding insulating layer or dielectric layer 29 (e.g., composed of silicon oxide or TEOS) covers the gate structure 26.

[0028] Top metal layer 30 is in electrical contact with source region 28 and body region 25 at respective surface portions 36 and 37 , respectively, so as to bias source region 28 and body region 25 at the same bias voltage during use.

[0029] To improve the electrical contact between the top metal layer 30 and the body region 25, an interface region (having a P+ doping) 34 is formed in the body region 25, facing the top surface 22a at a surface portion 37. Typically, an interface ohmic contact layer 38 composed of silicide is formed at the interface region 34 to form an ohmic contact between the metal 30 and the body region 25. Similarly, another interface ohmic contact layer 39 composed of silicide is formed at the surface portion 36 to form an ohmic contact between the metal 30 and the source region 28.

[0030] As reference Figures 3A to 3CAs described, the formation of the interface ohmic contact layers 38 and 39 envisages the deposition of an intermediate metal layer (in particular nickel) using the insulating layer 29 in a manner similar to that previously described for the mask 13. This intermediate metal layer therefore extends over the insulating layer 29 and over the surface portions 36 and 37 in contact with the interface region 34 and the source region 28.

[0031] As reference Figure 3C As described, at the surface portions 36 and 37 (more particularly at the interface region 34 and the source region 28), an ohmic contact consisting of nickel silicide can be formed by a chemical reaction between the deposited nickel and the silicon of the semiconductor body 22, followed by a thermal annealing at high temperature (between 900° C. and 1200° C. for a period of time ranging from 1 minute to 120 minutes). Next, a step is performed to remove the metal extending above the insulating layer 29. The insulating layer 29, which has a function in the final device, is not removed.

[0032] However, as previously described, the applicant has noted that the reaction between the nickel of the metal layer 14 and the insulating layer 29 in direct contact (similar to Figure 4 ). As a result, irregular regions or islands extend above insulating layer 29 and are attributed to an undesirable desired reaction between the silicon and nickel of insulating layer 29. Since these islands are conductive, they are potentially problematic for the operation of device 20, especially if their extension results in the creation of an undesirable short circuit or other type of undesirable electrical connection. The insulation of polysilicon 26 covered by oxide 29 is non-uniform and often has a minimum at the highest point of polysilicon step 26. If a reaction of nickel with silicon of oxide occurs in this region, there is a high risk of creating a gate-to-source short circuit due to the formation of an electrical bridge between metal 30 and polysilicon 26.

[0033] The present disclosure will be described with reference to two possible embodiments, in particular with reference to a hybrid PiN-Schottky (MPS) device ( Figure 6 、 7A to 7D) and the reference MOSFET device ( Figures 9 to 11 ); however, as will be apparent from the subsequent description, the present disclosure is generally applicable to any SiC-based electronic device.

[0034] Figure 6 A hybrid PiN-Schottky (MPS) device 50 according to an aspect of the present invention is shown in side or cross-sectional view in a (triaxial) Cartesian reference system having X, Y, and Z axes.

[0035] The MPS device 50 comprises: a substrate 53 composed of N-type silicon carbide (SiC) having a first doping concentration, provided with a surface 53a opposite to a surface 53b and having a thickness in the range of 50 μm and 350 μm, more particularly between 160 μm and 200 μm, for example substantially equal to 180 μm; a drift layer 52 composed of N-type SiC (in an epitaxially grown manner) having a second doping concentration lower than the first doping concentration, the drift layer extending above the surface 53a of the substrate 53 and having a thickness between 5 and 15 μm; an ohmic contact region or layer 56 (e.g. composed of nickel silicide) extending above the surface 53b of the substrate 53; a cathode metallization layer 57, e.g. composed of titanium nickel vanadium silver (Ti / NiV / Ag) or titanium nickel vanadium gold (Ti / NiV / Au), which extends over the ohmic contact region 56; an anode metallization layer 58, for example composed of titanium aluminum silicon copper (Ti / AlSiCu) or nickel aluminum silicon copper (Ni / AlSiCu), which extends over the top surface 52a of the drift layer 52; a passivation layer 69 on the anode metallization layer 58, for protecting the anode metallization layer; a plurality of junction-barrier (JB) elements 59 in the drift layer 52, which face the top surface 52a of the drift layer 52 and each include a corresponding P-type implantation region 59′ and an ohmic contact 59″; and an edge termination region or guard ring 60 (optional), in particular a P-type implantation region, which completely surrounds the junction-barrier (JB) element 59.

[0036] One or more Schottky diodes 62 are formed at the interface between drift layer 52 and anode metallization 58, lateral to implant region 59'. Specifically, a (semiconductor-metal) Schottky junction is formed by portions of drift layer 52 that are in direct electrical contact with corresponding portions of anode metallization 58.

[0037] The region of the MPS device 50 including the JB element 59 and the Schottky diode 62 (ie, the region included in the guard ring 60 ) is the active region 54 of the MPS device 50 .

[0038] According to one aspect of the present disclosure, each ohmic contact 59" is formed by one or more carbon-rich layers, including, for example, a graphite layer or a graphene multilayer. More particularly, each ohmic contact 59" has a Si / C amorphous layer on the surface 52a, where after phase separation between silicon atoms and carbon atoms of the SiC substrate, carbon atoms are dominant (e.g., at least twice as high, in particular, two to one hundred times as high) compared to silicon atoms. Beneath the amorphous layer, each ohmic contact 59" may include a layer including carbon clusters (e.g., a graphite layer) having a thickness greater than that of the amorphous layer. As a result of the manufacturing process illustrated below, the ohmic contact 59" is formed due to thermal decomposition of silicon carbide.

[0039] According to another aspect of the present disclosure, the ohmic contact 59″ is self-aligned with the injection region 59′ on the surface 52a (i.e., in a top view of the plane XY, the ohmic contact 59″ has the same shape and extension as the injection region 59′). In this case, the electrical contact between the anode metallization layer 58 and the injection region 59′ occurs exclusively via the ohmic contact 59″. This feature translates into a technical advantage, since the extension area of ​​the ohmic contact can be maximized without the risk of short-circuiting with adjacent ohmic contacts. In fact, since each ohmic contact 59″ has the same shape and extension as the corresponding injection region 59′, there is no risk of the ohmic contact exceeding an undesired lateral extension of the injection region 59′. Maximizing the area of ​​the ohmic contact allows maximizing the current carried by the ohmic contact.

[0040] In addition, according to another aspect of the present disclosure, the ohmic contact 59" does not extend beyond the surface 52a along Z; in other words, the ohmic contact 59" has a top surface 59a that is coplanar with the surface 52a (i.e., aligned along X) and extends at a depth within the ohmic contact 59' (along Z) to a depth between one nanometer and tens of nanometers (e.g., between 1m and 20m) measured from the surface 52a.

[0041] Each ohmic contact 59" provides an electrical connection having a resistivity value lower than the resistivity value of the region that houses it. In particular, each ohmic contact 59" has a resistivity lower than the resistivity of the corresponding region 59' that houses it.

[0042] Explicit reference is made to the method for fabricating the MPS device 50 ( 7A to 7D ) step, the step of forming the ohmic contact 59' is described below.

[0043] refer to Figure 7A , a wafer 100 is provided, which includes a SiC substrate 53 (particularly 4H-SiC; however, other polytypes may be used, such as, but not exclusively, 2H-SiC, 3C-SiC, and 6H-SiC).

[0044] The substrate 53 has a first conductivity type (in this embodiment, N-type doping), and is provided with a front surface 53a and a rear surface 53b opposite to each other along the axis Z. The substrate 53 has a thickness between 1·10 19 and 1.10 22 atoms / cm 3 dopant concentration between .

[0045] The front surface of the wafer 100 corresponds to the front surface 53a, and the rear surface of the wafer 100 corresponds to the rear surface 53b. The resistivity of the substrate 30 is, for example, between 2 mΩ·cm and 40 mΩ·cm.

[0046] For example, a drift layer 52 is formed on the front surface 53a of the substrate 53 by epitaxial growth. The drift layer is composed of silicon carbide, which has a first conductivity type (N) and a dopant concentration lower than that of the substrate 53, for example, between 1·10 14 and May 10 16 The drift layer 52 is composed of SiC, in particular 4H-SiC, although other SiC polytypes such as 2H, 6H, 3C or 15R may be used.

[0047] Drift layer 52 has a thickness defined between a top side 52 a and a bottom side 52 b (the bottom side is in direct contact with a front surface 53 a of substrate 53 ).

[0048] Then, Figure 7B On the top side 52a of the drift layer 52, a hard mask 70 is formed, for example, by deposition of a photoresist, or TEOS or some other material designed for this purpose. The hard mask 70 has a thickness between 0.5 μm and 2 μm, or in any case has a thickness capable of blocking the same as that hereinafter referred to. Figure 7B The thickness of the implant is described. Hard mask 70 extends in the area of ​​wafer 100 where active region 54 of MPS device 50 will be formed in a subsequent step.

[0049] In the top view, in the plane XY, the hard mask 70 covers the region of the top side 52a of the drift layer 52 where the Schottky cell (diode 62) will be formed, and exposes the region of the top side 52a of the drift layer 52 where the implantation region 59' will be formed, which has been referred to. Figure 6 Marking.

[0050] Then, a step of implanting a dopant substance (for example boron or aluminum) of the second conductivity type (here P type) is performed using the hard mask 70 (implantation is indicated in the figure by arrow 72). Figure 7B The guard ring 60 (if present) is also formed in the step of forming the PDMS layer.

[0051] In the embodiment provided as an example, Figure 7B The implantation step includes using an implantation energy between 30keV and 400keV and a 12 atoms / cm 2 and 1.10 15 atoms / cm 2 One or more implants of a dopant substance of the second conductivity type are performed at a dose between 1·10 and 1·10 18 atoms / cm 3 The implanted region 59' is thus formed to have a depth, measured from the surface 52a, of between 0.4 μm and 1 μm.

[0052] Next, Figure 7C , removing the mask 70, and Figure 7D , resulting in a thermal budget on surface 52a that is designed to favor growth on implanted region 59'.

[0053] For this purpose, a laser source 80 is used which is configured to generate a beam 82 in order to locally heat the surface 52 a (in particular the implantation region 59 ′) to a temperature of approximately 1500° C. to 2600° C. Taking into account the maximum depth of the implantation region 59 ′, a temperature of approximately 2000° C. at the level of the surface 52 a is sufficient to ensure a temperature within the range indicated above, even at the maximum depth reached by the implantation region 59 ′ (for example 1 μm).

[0054] This temperature favors the formation of an ohmic contact (e.g., as already described, comprising graphite and / or graphene) only on the implanted regions 59 ′, and not on the surface 52 a where no implanted regions 59 ′ are provided. This effect, known per se, is described, for example, by Maxime G. Lemaitre, “Low-temperature, site selective graphitization of SiC via ion implantation and pulsed laser annealing,” Applied Physics Letters 100, 193105 (2012).

[0055] In one embodiment, by heating the entire wafer 100 and moving the laser 80 appropriately, a portion of the implanted region 59 ′ is converted into an ohmic contact 59 ″.

[0056] In another embodiment, the conversion of a surface portion of the implantation region 59 ′ into the ohmic contact 59 ″ is obtained by heating the useful surface of the wafer 100 . Here, “useful surface” means the portion of the surface of the drift layer 52 including the implantation region 59 ′, for example externally delimited by the edge termination region 10 ; the useful surface may not correspond to the entire surface of the wafer 100 (for example, excluding possible portions of the wafer 100 laterally with respect to the active area 54 , which are of no significance during use of the MPS device 50 as long as they do not participate in the transport of charges).

[0057] According to another embodiment, a mask having areas transparent to the light beam 82 (i.e., the light beam 82 passes through them) and areas opaque to the light beam 82 (i.e., the light beam 82 does not pass through them, or passes through them in an attenuated form so as not to significantly heat the portion of the wafer 100 extending underneath) can be arranged on the surface 52a (in contact with the surface 52a or at a distance therefrom). The transparent areas of the mask are aligned with the implantation areas 59′ to enable the formation of ohmic contacts 59″.

[0058] Optionally, and independently of the embodiment used, an implantation region 59' is formed at the same time (in particular, the dopant is activated to obtain a value between approximately 1·10 17 atoms / cm 3 and 1.10 20 atoms / cm 3 concentration of the dopant species between ) and an ohmic contact 59" for each implanted region.

[0059] Additionally, since the ohmic contacts are formed only on the implanted regions 59', there is self-alignment between the implanted regions 59' and the corresponding ohmic contacts 59" even in the absence of a mask.

[0060] At the implantation region 59′, the increase in local and surface temperature causes the formation of the ohmic contact 59″; transversely to the implantation region 59′, this effect is not noticed. The formation of the ohmic contact 59″ occurs at temperatures between 1200°C and 2600°C. According to the present disclosure, these temperatures are reached at the surface part of the implantation region 59′ (a few nanometers, for example 1-20 nm). For greater depths, the temperature decreases to values ​​such as no longer causing the formation of the ohmic contact 59″. The ohmic contact 59″ is therefore self-limiting. Therefore, the ohmic contact 59″ does not extend throughout the thickness of the respective implantation region, but only at its surface level.

[0061] The laser 80 is, for example, a UV excimer laser. Other types of lasers having a wavelength in the visible light region may also be used.

[0062] The configuration parameters and driving parameters of the laser 80 optimized for achieving the purpose of the present disclosure are as follows:

[0063] Wavelength: between 290nm and 370nm, especially 310nm;

[0064] Pulse duration: between 100ns and 300ns, especially 160ns;

[0065] Number of pulses: between 1 and 10, especially 2;

[0066] Energy density: (2) 1.6 and 4 J / cm 2 between, especially (3) 2.6J / cm2 (considered at the level of surface 52a); and

[0067] Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 52 a ).

[0068] The spot area of ​​the light beam 82 at the level of the surface 52a is, for example, between 0.7 and 1.5 cm 2 between.

[0069] To cover the entire wafer 100 or a sub-region of the wafer 100 to be heated, one or more scans of the laser 80 are therefore performed in the plane XY (eg multiple scans parallel to each other and to the X and / or Y axes).

[0070] However, the present applicants have discovered that, utilizing the previously identified parameters, desired electrical performance can be achieved for the MPS device 50. In this regard, Figure 8 Experimental data illustrating the variation of conduction current as a function of the voltage applied between the anode and cathode of an MPS device 50 is shown. Curve S1 relates to electrical measurements on a PiN diode before laser treatment, while curve S2 relates to electrical measurements on the PiN diode after laser treatment, thereby forming an ohmic contact. The profiles of curves S1 and S2 confirm the expected behavior.

[0071] Figure 9 A MOSFET device 90 is shown in accordance with aspects of the present disclosure.

[0072] and Figure 5 Technical elements and characteristics of the MOSFET device 90 that are common to the MOSFET device 20 are illustrated using the same reference numerals and are not described again.

[0073] Unlike MOSFET device 20, MOSFET device 90 has an ohmic contact 91 at interface region 34 between metal 30 and body region 25. Additionally, MOSFET device 90 has another ohmic contact 92 at surface portion 36 between metal 30 and source region 28.

[0074] According to one aspect of the present disclosure, both ohmic contacts 91 and ohmic contacts 92 are formed by one or more carbon-rich layers or carbon-based layers, which include, for example, layers having carbon layers, graphite layers or graphene multilayers. More particularly, each ohmic contact 91, 92 has a Si / C amorphous layer on the surface 52a, where after phase separation between silicon atoms and carbon atoms of the SiC substrate, carbon atoms are dominant (for example, at least twice as high, in particular two to one hundred times as high) compared to silicon atoms. Underneath the amorphous layer, each ohmic contact 91, 92 may have a layer (for example, a graphite layer) comprising carbon clusters, which has a thickness greater than that of the amorphous layer. As a result of the manufacturing process illustrated below, the ohmic contact 59" is formed due to thermal decomposition of silicon carbide.

[0075] According to another aspect of the present disclosure, ohmic contacts 91 and ohmic contacts 92 are self-aligned with interface region 34 and with source region 28 on surface 22 a (i.e., in a top view of plane XY, ohmic contacts 91 and 92 have the same shape and extension as interface region 34 and source region 28, respectively).

[0076] Ohmic contacts 91 and 92 extend deep within semiconductor body 22 (along Z) to a depth between 1 nanometer and several tens of nanometers, for example between 1 and 20 nm, measured from surface 22 a .

[0077] Each ohmic contact 91, 92 provides an electrical connection having a resistivity value lower than the resistivity value of the region in which it is housed. In particular, each ohmic contact 91, 92 has a resistivity lower than the resistivity of the corresponding region 34, 28 in which it is housed.

[0078] The steps for forming the ohmic contacts 91 and 92 are described below with reference to Figure 10 To describe.

[0079] In particular, Figure 10 Wafer 200 is shown including MOSFET device 90 at an intermediate fabrication stage, wherein body region 25 , interface region 34 , source region 28 , gate structure 26 , and insulating layer 29 have been formed (in a manner known per se).

[0080] To form ohmic contacts 91 , 92 , a thermal budget is created on surface 22 a that is designed to favor generation at interface region 34 and source region 28 of respective ohmic contacts 91 , 92 .

[0081] For this purpose a laser source 95 is used which is configured to generate a beam 96 so as to heat the surface 22a locally, in particular in the region of the interface 34 and the source 28, to a temperature of approximately 1200 to 2600°C.

[0082] The temperature in the aforementioned range facilitates the formation of carbon-rich regions and graphite / graphene layers only at the interface region 34 and the source region 28 , and not at the surface region 22 a , where the interface 34 and source 28 regions do not extend.

[0083] In one embodiment, the transformation of the interface region 34 and the source region 28 into respective ohmic contacts is achieved by heating the entire wafer 200 and moving the laser 95 appropriately.

[0084] In another embodiment, the interface region 34 and the source region 28 are selectively heated by appropriately directing the light beam 96 , thereby transforming the interface region 34 and the source region 28 into respective ohmic contacts.

[0085] In another embodiment, a mask (not shown) may be disposed on wafer 200, the mask having regions that are transparent to light beam 96 (i.e., light beam 96 passes through them) and regions that are opaque to light beam 96 (i.e., light beam 96 does not pass through them, or passes through them in an attenuated form so as not to significantly heat the masked portion of wafer 200). The transparent regions of the mask are aligned with interface region 34 and source region 28 to enable formation of corresponding ohmic contacts, while protecting portions of wafer 200 that are not intended to be ohmically contacted by laser 95.

[0086] Applicants have discovered that the energy of light beam 96 required to form ohmic contact 92 at source region 28 (having N+ doping) is different than the energy required to form ohmic contact 91 at interface region 34 (having P+ doping).

[0087] The energy of beam 96 required to optimize the ohmic performance of contact 92 at source region 28 (having N+ doping) may be different from the energy used to optimize the ohmic performance of contact 91 at interface region 34 (having P+ doping). For this purpose, the operating parameters of laser 95 can be adjusted to generate corresponding beams 96 at interface region 34 and source region 28, each beam being designed to generate a corresponding layer having ohmic performance.

[0088] In any case, the applicant has found that, given the same energy of the light beam, formation of ohmic contact 92 at source region 28 (with N+ doping) and formation of ohmic contact 91 at interface region 34 (with P+ doping) can occur.

[0089] In detail, at the source region 28 and the interface region 34, the configuration parameters and actuation parameters of the laser 95 optimized for achieving the purpose of the present disclosure are as follows:

[0090] Wavelength: between 290nm and 370nm, especially 310nm;

[0091] Pulse duration: between 100ns and 300ns, especially 160ns;

[0092] Number of pulses: between 1 and 10, especially 2;

[0093] Energy density: (2) 1.6 and 4 J / cm 2 between, especially (3) 2.6J / cm 2 (considered at the level of surface 22a); and

[0094] Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 22 a ).

[0095] The spot area of ​​the light beam 82 at the level of the surface 22a is, for example, between 0.7 and 1.5 cm 2 between.

[0096] To cover the entire wafer 200 or a sub-region of the wafer 200 to be heated, one or more scans of the laser 95 are therefore performed in the plane XY (eg multiple scans parallel to each other and to the X and / or Y axes).

[0097] Alternatively, Figure 11 , a mask 97 may be arranged on the wafer 200, said mask being provided with respective windows 97a, 97b at (i.e., in vertical alignment therewith) the interface region 34 and the source region 28. The remaining parts 97c of the mask 97 are completely opaque to the light beam 96, i.e., they are not passed through by the light beam 96 (or in any case they are passed through in an insignificant manner and so as not to generate heating on underlying structures of the wafer 200 that could cause damage or some other type of undesirable phenomenon).

[0098] For example, in cases where it is beneficial to modify some characteristics of the light beam incident on the interface region 34, the window 97a at the interface region 34 is provided with a filter 98 designed to modify the characteristics of the light beam 96. In the opposite case, there is no filter 98. The window 97b at the source region 28 does not have any filter; that is, it is transparent to the light beam 96 and the light beam 96 passes through it in a substantially unchanged form as far as its characteristics are concerned.

[0099] In the remainder of this disclosure, it will be considered that both windows 97a and 97b have no filters, and that the mask 97 will have the function of protecting (via the opaque portions 97c) the areas that are not heated by the light beam 96 .

[0100] In particular, in this embodiment, the light beam is generated by controlling the laser 95 in the following manner:

[0101] Wavelength: between 290nm and 370nm, especially 310nm;

[0102] Pulse duration: between 100ns and 300ns, especially 160ns;

[0103] Number of pulses: between 1 and 10, especially 2;

[0104] Energy density: (2) 1.6 and 4 J / cm 2 between, especially (3) 2.6J / cm 2 (considered at the level of surface 22a); and

[0105] Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 22 a ).

[0106] The spot area of ​​the light beam 82 at the level of the surface 22a is, for example, between 0.7 and 1.5 cm 2 between.

[0107] To cover the entire wafer 200 or a sub-region of the wafer 200 to be heated, one or more scans of the laser 95 are therefore performed in the plane XY (eg multiple scans parallel to each other and to the X and / or Y axes).

[0108] The light beam 96 thus generated is directed towards the source region 28 (N+) through the window 97b and towards the interface region 34 (P+) through the window 97a.

[0109] Obviously, according to another embodiment, a filter may also be introduced at the window 97b and the light beam 96 generated in an appropriate manner (ie such that the filtered light beam is designed to generate an ohmic contact at the source region 28).

[0110] Since ohmic contacts are formed only at the P-implant region and the N-implant region, there is self-alignment between the interface region 34 / source region 28 and the corresponding ohmic contacts 91 / 92 .

[0111] With reference to the fabrication of MPS devices, the transformation of SiC into carbon-rich layers and / or graphite layers and / or graphene layers is achieved on the basis of the technical considerations already described previously.

[0112] The laser 95 is, for example, a UV excimer laser. Other types of lasers having a wavelength in the visible light region may also be used.

[0113] The advantages provided by the present invention are apparent from an inspection of the disclosed features provided in accordance with the present invention.

[0114] In particular, according to the present disclosure, ohmic contacts on either a P+ region or an N+ region may be provided using a single process without the deposition of any metal layer, thus overcoming the disadvantages associated with the known techniques previously identified and described.

[0115] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without thereby departing from the scope of the present disclosure as defined by the appended claims.

[0116] In particular, as previously noted, the present disclosure is not limited to ohmic contact formation for MPS devices or MOSFETs, but extends to ohmic contact formation in general vertical conduction electronic devices such as Schottky diodes, JBS diodes, MOSFETs, IGBTs, JFETs, DMOS, etc.

[0117] The present disclosure is directed to a method for manufacturing a SiC-based electronic device (50; 90), comprising: implanting a P-type dopant substance onto a front side (52a; 22a) of a solid body (52; 22) of SiC having N-type conductivity, thereby forming an implantation region (59′; 34), the implantation region extending in the solid body from the front side (52a; 22a) and having a top surface coplanar with the front side (52a; 22a); and generating a first laser beam (82; 96) directed toward the implantation region (59′; 34) so ​​as to heat the implantation region (59′; 34) to a temperature between 1500° C. and 2600° C., thereby forming a first carbon-rich electrical contact region (59″; 91) at the implantation region (59′; 34). The method comprises forming a first ohmic contact region (59″; 91), comprising forming one or more graphene layers and / or graphite layers within the implantation region (59′; 34). The first laser beam (82; 96) is generated according to the following parameters: wavelength: between 290 nm and 370 nm, in particular 310 nm; pulse duration: between 100 ns and 300 ns, in particular 160 ns; number of pulses: between 1 and 10, in particular 2; and energy density: between 1.6 and 4 J / cm 2 between, especially 2.6J / cm 2 .

[0118] The first electrical contact region (59"; 91) forms a first ohmic contact having a top surface thereof coinciding with a top surface of the implanted region (59'; 34). The first electrical contact region (59"; 91) has a thickness between 1 nm and 20 nm. The material of the solid is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC. The electronic device (50; 90) is one of the following: a hybrid PiN-Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, and a DMOS.

[0119] The electronic device (50) is a hybrid PiN-Schottky (MPS) diode, and the method includes the steps of forming the solid body, including: arranging an N-type SiC substrate having a front side and a back side thereof opposite to each other, and on the front side of the substrate, epitaxially growing a drift layer (52) composed of N-type SiC; forming a first electrical terminal (58), the first electrical terminal (58) being in electrical contact with a doped region (59') via a first electrical contact region (59") and being in direct electrical contact with the drift layer (52) laterally to the doped region (59'), thereby forming a junction-barrier (JB) diode with the doped region (59') and forming a Schottky diode with the drift layer (52); and forming a second electrical terminal (57) on the back side of the substrate.

[0120] The electronic device (90) is a MOSFET, and the method includes the following steps: forming a first body region (25) of P type on the front side (22a) of the solid (22); forming the injection region (34) in the first body region (25); forming a second body region (25) of P type on the front side (22a) of the solid (22), the second body region extending transversely to the first body region (25); forming an N type source region (28) in the second body region (25); generating a second laser beam (96) toward the source region (28) so as to heat the source region (28) to a temperature between 1500° C. and 2600° C., thereby forming a second carbon-rich electrical contact region (92) at the source region (28).

[0121] The second laser beam (96) is generated according to the following parameters: wavelength: between 290 nm and 370 nm, in particular 310 nm; pulse duration: between 100 ns and 300 ns, in particular 160 ns; number of pulses: between 1 and 10, in particular 2; and energy density: between 2 and 4 J / cm 2 between, especially 3J / cm 2. Forming the second ohmic contact region (92) includes forming one or more graphene layers and / or graphite layers within the source region (28). The first electrical contact region (59"; 34) forms a first ohmic contact having a top surface thereof coinciding with a top surface of the injection region (59'; 34). The second electrical contact region (59"; 91) has a thickness between 1 nm and 20 nm.

[0122] The present disclosure is also directed to a SiC-based electronic device (50; 90), comprising: a solid (52; 22) consisting of SiC having N-type conductivity; an implantation region (59′; 34) extending on a front side (52a; 22a) of the solid (52; 22) and comprising a P-type dopant substance, the implantation region having a top surface coplanar with the front side (52a; 22a) of the solid; and a first carbon-rich electrical contact region (59″; 91) extending at the implantation region (59′; 34). The first electrical contact region (59″; 91) comprises one or more graphene layers and / or graphite layers within the implantation region (59′; 34).

[0123] The first electrical contact region (59"; 91) forms an ohmic contact having a top surface thereof coinciding with a top surface of the implanted region (59'; 34). The electrical contact region (59") has a thickness between 1 nm and 20 nm. The solid material is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC. The device is selected from one of a hybrid PiN-Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, and a DMOS. A device of the hybrid PiN-Schottky (MPS) diode type, wherein a solid body comprises an N-type SiC substrate having a front side and a back side thereof opposite to each other, and a drift layer (52) consisting of N-type SiC on the front side of the substrate, and a first electrical terminal (58) in electrical contact with a doped region (59') via a first region of an ohmic contact (59") and in direct electrical contact with the drift layer (52) laterally to the doped region (59'), thereby forming a junction-barrier (JB) diode with said doped region (59'), and The device (90) is a MOSFET, comprising: a first P-type body region (25) on the front side (22a) of the solid body (22), accommodating the implant region (34); a second P-type body region (25) extending transversely to the first body region (25) on the front side (22a) of the solid body (22); an N-type source region (28) in the second body region (25); and a second carbon-rich electrical contact region (92) in the source region (28).

[0124] The second electrical contact region (92) includes one or more graphene layers and / or graphite layers within the source region (28). The second electrical contact region (92) forms an ohmic contact with a top surface thereof that coincides with a top surface of the source region (28). The electrical contact region (92) has a thickness between 1 nm and 20 nm.

[0125] The various embodiments described above can be combined to provide further embodiments.Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0126] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which the claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A method for manufacturing a SiC-based electronic device, comprising: providing a SiC substrate having a dopant of a second conductivity type, the SiC substrate having a first surface opposite to a second surface along a first direction; forming a first doped region by implanting a dopant of a first conductivity type into the SiC substrate through the first surface of the SiC substrate from the outside, wherein the first conductivity type is different from the second conductivity type, and the first doped region extends in the SiC substrate from the first surface of the SiC substrate to the second surface of the SiC substrate along the first direction; forming a second doped region in the first doped region, the second doped region having the second conductivity type; forming a first gate on the first surface of the SiC substrate, wherein the first gate overlaps with a first edge of the second doped region along the first direction; forming a second gate on the first surface of the SiC substrate, wherein the second gate overlaps with a second edge of the second doped region along the first direction; as well as forming a first carbon-rich electrical contact region at the first doped region between the first gate and the second gate, wherein the first carbon-rich electrical contact region is in the second doped region; wherein a top surface of the first doped region, a top surface of the second doped region, and a top surface of the first carbon-rich electrical contact region are coplanar with the first surface of the SiC substrate; In the first direction, the thickness of the first doped region, the thickness of the second doped region, and the thickness of the first carbon-rich electrical contact region decrease in sequence.

2. The method of claim 1 , wherein forming the first carbon-rich electrical contact region comprises: The first doped region is heated to a temperature in the range of 1500° C. and 2600° C. using a first laser beam, and one or more graphene layers are formed in the doped region.

3. The method of claim 1 , wherein forming the first carbon-rich electrical contact region comprises: One or more graphite layers are formed in the first doped region. The method of claim 1 , wherein the first carbon-rich electrical contact region has a shape and an extension that coincide with a shape and an extension of the first doped region in a top plan view.

5. The method of claim 1 , wherein forming the first carbon-rich electrical contact region comprises: A first ohmic contact is formed having a top surface of the second doped region. The method of claim 1 , wherein the first carbon-rich electrical contact region has a thickness in the range of 1 nm and 20 nm. The method according to claim 1 , wherein a material of the SiC substrate is selected from one of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

8. The method of claim 1 , further comprising forming a MOSFET by: forming a P-type first body region at the first surface of the SiC substrate; forming the doped region in the first body region; forming a P-type second body region at the first surface of the SiC substrate, wherein the second body region extends laterally to the first body region; forming an N-type source region in the second body region; as well as A second carbon-rich electrical contact region is formed at the source region by heating the source region to a temperature in the range of 1500° C. and 2600° C. using a second laser beam.

9. The method of claim 8, wherein forming the second carbon-rich electrical contact region comprises: One or more layers are formed in the source region, the one or more layers having graphene, graphite, or a combination of graphene and graphite. 10 . The method of claim 9 , wherein the second carbon-rich electrical contact region has a thickness in the range of 1 nm and 20 nm.

11. An electronic device comprising: a substrate having a first conductivity type and having a first surface opposite to the second surface along a first direction; a first doped region having a second conductivity type; a second doped region in the first doped region, the second doped region having the first conductivity type; a first gate on the first surface of the substrate, the first gate overlapping a first edge of the second doped region along the first direction; a second gate on the first surface of the substrate, the second gate overlapping a second edge of the second doped region along the first direction; a first ohmic contact between the first gate and the second gate, the first ohmic contact being in the second doped region, wherein a top surface of the first doped region, a top surface of the second doped region, and a top surface of the first ohmic contact are coplanar with the first surface of the substrate; In the first direction, the thickness of the first doped region, the thickness of the second doped region, and the thickness of the first ohmic contact decrease in sequence.

12. The electronic device according to claim 11, further comprising: a third doped region spaced apart from the first doped region, the third doped region having the second conductivity type; a fourth doping region in the third doping region, the fourth doping region having the first conductivity type, and the first gate overlapping the fourth doping region; a fifth doping region adjacent to the fourth doping region in the third doping region, the fifth doping region having the second conductivity type; A second ohmic contact is provided on the fifth doped region, wherein the second ohmic contact is provided between the second surface and the first surface of the substrate. 13 . The electronic device of claim 12 , wherein the first ohmic contact and the second ohmic contact comprise carbon clusters.

14. An electronic device comprising: a substrate having a first surface opposite to a second surface along a first direction; a first gate on the first surface of the substrate; a second gate on the first surface of the substrate; a first doped region between the first gate and the second gate along a second direction perpendicular to the first direction, the first doped region having a first conductivity type, and a top surface of the first doped region being coplanar with the first surface of the substrate; a second doped region between the first gate and the second gate along the second direction in the first doped region, the second doped region having a second conductivity type different from the first conductivity type, and a top surface of the second doped region being coplanar with a top surface of the first doped region; a third doped region having a first conductivity type, wherein a top surface of the third doped region is coplanar with the first surface of the substrate, and the third doped region overlaps with a first portion of the first gate; a fourth doping region of the second conductivity type in the third doping region, wherein a top surface of the fourth doping region is coplanar with a top surface of the third doping region; a fifth doping region of the first conductivity type in the third doping region, wherein a top surface of the fifth doping region is coplanar with a top surface of the third doping region, and a first portion of the third doping region completely separates the fifth doping region from the fourth doping region along the second direction; as well as A first ohmic contact is formed in the second doping region, wherein a top surface of the first ohmic contact is coplanar with the first surface of the substrate.

15. The electronic device according to claim 14, further comprising: A dielectric layer is formed on the first gate and the second gate, a portion of the substrate is exposed between a portion of the dielectric layer between the first gate and the second gate, and the first ohmic contact is formed in the portion of the substrate.

16. The electronic device according to claim 15, further comprising: A second ohmic contact is provided in the substrate, the first gate being between the first ohmic contact and the second ohmic contact. The electronic device of claim 16 , wherein the second ohmic contact is in the fifth doped region.

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