Semiconductor Device and Manufacturing Method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. A semiconductor device and a manufacturing method are provided. In an embodiment, dielectric fins are formed to assist in isolating adjacent semiconductor fins. The dielectric fins are formed using a deposition process, where the deposition time and temperature are used to increase the resistance of the dielectric fins to subsequent etching processes.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing methods thereof. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided. The method includes forming an opening in a dielectric material located between semiconductor fins, and depositing a first dielectric material in the opening. Depositing the first dielectric material includes: delivering a first precursor material in a pulsed manner for a first time between about 20 seconds and about 120 seconds; delivering a second precursor material in a pulsed manner for a second time between about 70 seconds and about 200 seconds, the second precursor material being different from the first precursor material; and delivering a third precursor material in a pulsed manner for a third time between about 20 seconds and about 120 seconds, the third precursor material being different from both the first precursor material and the second precursor material.

[0005] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided. The method includes: depositing a barrier layer to line an opening in a dielectric material between semiconductor fins, depositing the barrier layer including: introducing a first precursor material for a first time; after introducing the first precursor material, introducing a second precursor material for a second time, the second precursor material being different from the first precursor material; and after introducing the second precursor material, introducing a third precursor material for a third time, the third precursor material being different from both the first precursor material and the second precursor material; filling the remaining portion of the opening by depositing a bulk material, depositing the bulk material including: introducing the first precursor material for a fourth time longer than the first time; after introducing the first precursor material to deposit the bulk material, introducing the second precursor material for a fifth time longer than the second time; and after introducing the second precursor material to deposit the bulk material, introducing the third precursor material for a sixth time longer than the third time.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, including: semiconductor fins extending through a dielectric material; and hybrid dielectric fins extending from within the dielectric material, the hybrid dielectric fins including: a barrier layer including a first material having a first composition; and a bulk material including the first material having a second composition different from the first composition, the second composition having a greater carbon concentration than the first composition. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 8A 、 Figure 8B 、 Figure 9 、 Figure 10 、 Figure 11 、Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B are cross-sectional views of intermediate stages of manufacturing a FinFET according to some embodiments. Detailed Description

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and in and of itself does not indicate a relationship between the various embodiments and / or configurations being discussed.

[0011] Additionally, spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper,” etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] Embodiments will now be described with reference to specific embodiments of forming a hybrid dielectric fin in an isolation region. However, the embodiments described herein are not intended to be limited to the exact embodiments described, and these ideas may be implemented in various applications. All such applications are fully intended to be included within the scope of the embodiments.

[0013] Figure 1 FIG. 0 shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fin 52 protrudes between adjacent isolation regions 56 from above them. Although the isolation regions 56 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including isolation regions. Additionally, although the fin 52 is illustrated as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0014] A gate dielectric layer 92 is along the sidewalls and on top of the top surface of the fin 52, and a gate electrode 94 is on top of the gate dielectric layer 92. Source / drain regions 82 are provided on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross-sections used in later figures are further shown. Cross-section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of the current between the source / drain regions 82 of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52 and in the direction of the current, for example, between the source / drain regions 82 of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0015] Some embodiments discussed herein are in the context of a FinFET formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments consider aspects for use in planar devices, such as planar FETs, nanostructures (e.g., nanosheets, nanowires, gate-all-around structures, etc.) nanoscale field-effect transistors (NSFETs), etc.

[0016] Figures 2 to 20B is a cross-sectional view of an intermediate stage of manufacturing a FinFET according to some embodiments. Figures 2 to 7A and FIG. 8 - Figure 11 shows Figure 1 the reference cross-section A-A shown, except for multiple fins / FinFETs. Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A ,Figure 19A and Figure 20A along Figure 1 as shown by the reference cross-section A-A, while Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 18C , Figure 19B and Figure 20B along Figure 1 as shown by a similar cross-section B-B, except for the plurality of fins / FinFETs. Figure 14C and Figure 14D along Figure 1 as shown by the reference cross-section C-C, except for the plurality of fins / FinFETs.

[0017] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium indium phosphoarsenide; or combinations thereof.

[0018] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, such as n-type FinFETs. The p-type region 50P can be used to form p-type devices, such as PMOS transistors, such as p-type FinFETs. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P.

[0019] In Figure 3In [description], fins 52 are formed in substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching process can be anisotropic.

[0020] The fins can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the fins 52. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that obtainable using a single direct lithography process otherwise. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) can be retained over the fins 52.

[0021] In Figure 4 In [description], an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitride, etc. or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it to another material, such as an oxide), etc. or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52. Thereafter, a fill material, such as those discussed above, can be formed over the liner.

[0022] In Figure 5In [the figure], a removal process is applied to the insulating material 54 to remove the excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, etc. can be utilized. The planarization process exposes the fin 52 such that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where a mask remains on the fin 52, the planarization process can expose the mask or remove the mask such that after the planarization process is completed, the top surface of the mask or the fin 52 is flush with the insulating material 54 respectively.

[0023] Figure 6 A removal process for forming the first opening 601 is shown to initiate a process for forming the dielectric hybrid fin 901 ( Figure 6 not shown in [the figure], but described and illustrated below with reference to Figure 9 which). In an embodiment, one or more suitable photolithographic masking and etching processes can be used to form the first opening 601. Additionally, any suitable dimensions can be utilized.

[0024] Figures 7A - 7B The formation of the barrier layer 701 for lining the first opening 601 is shown. In an embodiment, the barrier layer 701 can be a dielectric material that helps isolate a subsequently formed material (e.g., the bulk material 801) from the insulating material 54. For example, in some embodiments, the barrier layer 701 can be a dielectric material such as silicon carbonitride (SiCN), however, any suitable material can be used.

[0025] Figure 7B A deposition system 731 that can be used to receive precursor materials to assist in depositing the barrier layer 701 is shown. In an embodiment, the deposition system 731 receives precursor materials from a plurality of precursor delivery systems (e.g., the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705), and forms a material layer on the substrate 50 within the deposition chamber 733.

[0026] In an embodiment, the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 can work in concert with each other to supply one or more different precursor materials to a deposition chamber 733 in which one or more substrates 50 are placed. However, the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 can have physical components that are similar to each other. For example, the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 can each include a gas supply source 709 and a flow controller 711. In an embodiment where the first precursor is stored in a gaseous state, the gas supply source 709 can supply the first precursor to the deposition chamber 733. The gas supply source 709 can be a container such as a gas storage tank that is local to or remote from the deposition chamber 733. Alternatively, the gas supply source 709 can be a facility that independently prepares the first precursor and delivers it to the flow controller 711. Any suitable source for the first precursor can be used as the gas supply source 709, and all such sources are fully intended to be included within the scope of the embodiment.

[0027] The gas supply source 709 can supply the required precursor to the flow controller 711. The flow controller 711 can be used to control the flow of the precursor to one or more precursor gas controllers 713 and ultimately to the deposition chamber 733, thereby also contributing to the control of the pressure within the deposition chamber 733. The flow controller 711 can be, for example, a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, a liquid source controller vaporizer, a combination of these, etc. However, any suitable method for controlling and regulating the flow of the first precursor can be utilized, and all such components and methods are fully intended to be included within the scope of the embodiment.

[0028] Additionally, in an embodiment where the first precursor is stored in a solid or liquid state, the gas supply source 709 can store a carrier gas and can introduce the carrier gas into a precursor tank that stores the first precursor in a solid or liquid state. The carrier gas is then used to push and transport the first precursor as the first precursor evaporates or sublimes into the gaseous portion of the precursor tank before being sent to the precursor gas controller 713. Any suitable combination of methods and units can be utilized to provide the first precursor, and all such combinations of units are fully intended to be included within the scope of the embodiment.

[0029] The first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 can supply their respective precursor materials to one or more of a series of precursor gas controllers 713. The precursor gas controllers 713 connect and isolate the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 from the deposition chamber 733 to deliver the desired precursor materials to the deposition chamber 733. The precursor gas controllers 713 can include devices such as valves, flow meters, sensors, etc. to control the delivery rate of each precursor and can be controlled by instructions received from the control unit 715.

[0030] When receiving instructions from the control unit 715, the precursor gas controllers 713 can open and close valves to connect one or more of the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705 to the deposition chamber 733 and introduce the desired precursor materials into the deposition chamber 733 and one or more injection units 719 through one or more manifolds 717. The injection unit 719 can be used to disperse the selected precursor material(s) into the deposition chamber 733 and can be designed to disperse the precursor material evenly to minimize undesired process conditions that may be caused by uneven dispersion. In a particular embodiment, the injection unit 719 can be formed, for example, by coiled tubing that includes a plurality of holes distributed throughout the tubing, allowing the precursor material to be evenly dispersed in the deposition chamber 733. However, any suitable shape can be used.

[0031] However, as will be recognized by those of ordinary skill in the art, introducing the precursor material into the deposition chamber 733 through a single unit as described above is intended to be illustrative only and not intended to be limiting to the embodiments. Any number of separate and independent injectors, such as three separate and independent injectors, or other openings for introducing the precursor material into the deposition chamber 733 can also be used. All such combinations and other introduction points are fully intended to be included within the scope of the embodiments.

[0032] The deposition chamber 733 can receive the desired precursor materials and expose the precursor materials to the substrate 50, and the deposition chamber 733 can be of any desired shape that is suitable for dispersing the precursor materials and bringing the precursor materials into contact with the substrate 50. In Figure 7BIn the illustrated embodiment, the deposition chamber 733 has a cylindrical sidewall and a bottom. However, the deposition chamber 733 is not limited to a cylindrical shape and any other suitable shape can be used, such as a hollow square tube, an octagon, etc. Additionally, the deposition chamber 733 can be surrounded by a housing 723 made of a material inert to various process materials. Thus, although the housing 723 can be any suitable material capable of withstanding the chemical reactions and pressures involved in the deposition process, in one embodiment, the housing 723 can be steel, stainless steel, nickel, aluminum, alloys thereof, combinations thereof, etc.

[0033] Within the deposition chamber 733, a plurality of substrates 50 can be placed within a rack on a mounting rack 725 for positioning and controlling the substrates 50 during the deposition process. The mounting rack 725 can include a heating mechanism for heating the substrates 50 during the deposition process. Additionally, although Figure 7B the mounting rack 725 is shown, a single mounting platform for supporting a single wafer can be included within the deposition chamber 733.

[0034] Additionally, the deposition chamber 733 can include heating elements and / or heating lamps configured to control the temperature of the precursor gas (e.g., the first precursor) entering the deposition chamber 733 and the exhaust gas leaving the deposition chamber 733. According to an embodiment, when the precursor enters the manifold 717, the heating element maintains or raises the temperature of the precursor to a process temperature above the boiling point of the precursor to ensure that the precursor remains in the gas phase and maintains an appropriate flow rate of the precursor at the injection unit 719. Additionally, when the exhaust gas exits the deposition chamber 733, the heating element maintains or raises the temperature of the exhaust gas at the exhaust outlet 727 to a temperature above the boiling point of the exhaust gas to maintain an appropriate exhaust rate of the exhaust gas.

[0035] According to some embodiments, the deposition chamber 733 further includes a cooling element and a coolant source. The cooling element is located within the housing 723 near the injection unit 719 and the rack 725. The control unit 715 controls a valve at the coolant source to release the coolant into the cooling element. Thus, when the precursor gas exits the injection unit 719 during the deposition process and is at the location of the substrate 50, the temperature of the precursor gas is controlled to a desired process temperature.

[0036] One or more vacuum pumps 729 (e.g., two vacuum pumps 729, one for one precursor such as DCS and the other for other precursors such as ammonia and propane) can be connected to the exhaust outlet 727 of the deposition chamber 733 to assist in exhausting the exhaust gas. Under the control of the control unit 715, the exhaust outlet 727 can also be used to reduce and control the pressure within the deposition chamber 733 to a desired pressure and can also be used to discharge the precursor material from the deposition chamber 733 to prepare for the introduction of the next precursor material.

[0037] The control unit 715 can be used to control the precursor gas controller 713, the vacuum pump 729, the heating element, the coolant source, and / or the cooling element. The control unit 715 can be any form of computer processor and can be used in an industrial environment to control process machines. In an embodiment, the control unit 715 can include a processing unit, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a specific application. The control unit 715 can be equipped with a display and one or more input / output components, such as instruction output, sensor input, a mouse, a keyboard, a printer, combinations thereof, etc. The processing unit can include a central processing unit (CPU), a memory, a mass storage device, a video adapter, an I / O interface, and / or a network interface connected to a bus.

[0038] The bus can be one or more of any type of several bus architectures including a memory bus or a memory controller, a peripheral bus, or a video bus. The CPU can include any type of electronic data processor, and the memory can include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). The mass storage device can include any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus. The mass storage device can include, for example, one or more of a hard disk drive, a disk drive, or an optical disk drive.

[0039] The video adapter and the I / O interface provide an interface for coupling external input and output devices to the processing unit. Examples of input and output devices include, but are not limited to, a display coupled to the video adapter and I / O components coupled to the I / O interface, such as a mouse, a keyboard, a printer, etc. Other devices can be coupled to the processing unit, and additional or fewer interface cards can be used. For example, a serial interface card (not shown) can be used to provide a serial interface for a printer.

[0040] The network interface couples the processing unit to an external network to facilitate network communication and provide network access to external resources via one or more wired and / or wireless links (e.g., local area network (LAN) and / or wide area network (WAN)). The network access and network communication can use one or more circuit-switched networks and / or packet-switched networks. In an embodiment, the control unit 715 can be a system locally connected to the precursor gas controller 713 and / or the vacuum pump 729 via one or more wired and / or wireless connections. In another embodiment, the control unit 715 can be a system remote from the precursor gas controller 713 and / or the vacuum pump 729 and can be connected to and control the precursor gas controller 713 and the vacuum pump 729 via remote wired and / or wireless connections. In an embodiment, the control unit 715 can be a distributed system (including one or more processing units of one or more network servers) and / or can employ one or more network services for controlling the precursor gas controller 713 and / or the vacuum pump 729.

[0041] It should be noted that the control unit 715 can include other components. For example, the control unit 715 can include a power supply, cables, a motherboard, a removable storage medium, a housing, etc. These other components, although not shown in Figure 7B are considered to be part of the control unit 715.

[0042] In addition, the deposition system 731 can also include additional structures that can be used for other deposition processes, thus allowing multiple deposition processes to be performed in the same chamber. For example, in some embodiments, the deposition system 731 can include additional precursor delivery systems, such as a fourth precursor delivery system 735 (with a precursor such as oxygen), a fifth precursor delivery system 737 (with a precursor such as hexachlorodisilane (HCD)), and a sixth precursor delivery system 739 (with a precursor such as triethylamine). Any suitable delivery system with any suitable number of precursor delivery systems can be used.

[0043] To initiate the deposition process, the first precursor material can be placed in one or more of the first precursor delivery system 702, the second precursor delivery system 703, and / or the third precursor delivery system 705. In an embodiment where the barrier layer 701 is silicon carbonitride (SiCN), the first precursor material can be a silicon-containing precursor, such as dichlorosilane (DCS), etc. However, any suitable precursor for any suitable material can be used.

[0044] The second precursor material can be placed in another one of the first precursor delivery system 702, the second precursor delivery system 703, and / or the third precursor delivery system 705. In an embodiment where the barrier layer 701 is silicon carbonitride (SiCN) and the first precursor material is dichlorosilane, the second precursor material can be a carbon-containing precursor, such as propane (C3H6) and the like. However, any suitable precursor for any suitable material can be used.

[0045] The third precursor material can be placed in yet another one of the first precursor delivery system 702, the second precursor delivery system 703, and / or the third precursor delivery system 705. In an embodiment where the barrier layer 701 is silicon carbonitride (SiCN), the first precursor material is dichlorosilane, and the second precursor material is propane, the third precursor material can be a nitrogen-containing precursor, such as ammonia (NH3) and the like. However, any suitable precursor for any suitable material can be used.

[0046] Once the first precursor material, the second precursor material, and the third precursor material are respectively placed in the first precursor delivery system 702, the second precursor delivery system 703, and the third precursor delivery system 705, the formation of the barrier layer 701 can be initiated by placing one or more of the substrates 50 (e.g., 100 substrates 50) in the mounting rack 725 (e.g., a wafer boat) and then raising the mounting rack 725 into the deposition chamber 733.

[0047] Once the mounting rack 725 is placed, the pressure inside the deposition chamber 733 can be adjusted to the desired process pressure. In an embodiment, the pressure can be adjusted to about 4660 Pa. Additionally, the temperature inside the deposition chamber 733 can be raised to the desired process temperature, such as a desired process temperature between about 500 °C and about 700 °C, such as about 620 °C, 640 °C, or 680 °C. In a very specific embodiment, the process temperature can be raised from a temperature of about 300 °C to a process temperature of about 640 °C. However, any suitable process conditions can be utilized.

[0048] Then, after a leak check, an optional pre-purge can be performed. In an embodiment, the pre-purge can be performed by introducing one or more of the first precursor material, the second precursor material, or the third precursor material into the deposition chamber 733 before the start of an atomic layer deposition cycle (discussed further below). For example, in an embodiment where the barrier layer 701 is silicon carbonitride formed using ammonia as the third precursor material, the pre-purge can be performed by introducing the third precursor material into the deposition chamber 733 at any suitable flow rate and time.

[0049] Once the pre-purge (if any) is complete, the control unit 715 can initiate an atomic layer deposition cycle by sending an instruction to the precursor gas controller 713 to connect the first precursor delivery system 702 to the deposition chamber 733. Once connected, the first precursor delivery system 702 can deliver the first precursor material to the injection unit 719 through the precursor gas controller 713 and the manifold 717. The injection unit 719 can then disperse the first precursor material into the deposition chamber 733, where the first precursor material can be adsorbed and react with each exposed surface.

[0050] In one embodiment where the barrier layer 701 is silicon carbonitride, the first precursor material (e.g., DCS) can flow into the deposition chamber 733 at any suitable flow rate, with a carrier gas introduced at any suitable flow rate. Additionally, the substrate 50 can be rotated to help ensure uniform flow over the substrate 50. However, any suitable flow rate can be used.

[0051] Further, to better control the composition of the individual elements within the barrier layer 701, the time for the first precursor material to enter the deposition chamber 733 in a pulsed manner is controlled. For example, in one embodiment, the first precursor material can be pulsed over a first time period between about 3 seconds and about 20 seconds (e.g., about 12 seconds). However, any suitable time can be utilized.

[0052] Figure 7C A close-up view of the surface of the insulating material 54 is shown, and in an embodiment where it is desired to form a silicon carbonitride layer using dichlorosilane, under these process conditions, dichlorosilane will react with the exposed surface (e.g., the insulating material 54) to provide a surface where silicon is chemically bonded to the underlying surface, while the opposite surface terminates in hydrogen and chlorine atoms exposed to the ambient atmosphere within the deposition chamber 733. Additionally, the reaction of dichlorosilane with the underlying structure will be self-limiting, providing a monolayer of molecules once this step is complete.

[0053] After the self-limiting reaction is complete, a first purge process can be used to purge the first precursor material in deposition chamber 733. For example, control unit 715 can instruct precursor gas controller 713 to disconnect first precursor delivery system 702 (which contains the first precursor material to be purged from deposition chamber 733) and connect purge gas delivery system 707 to deliver a purge gas to deposition chamber 733. In an embodiment, purge gas delivery system 707 can be a gas cylinder or other facility that provides a purge gas (such as nitrogen, argon, xenon, or other gases) to deposition chamber 733 for a purge flow between about 2 slm and about 20 slm (e.g., about 10 slm) for a period of time between about 3 s and about 20 s. Additionally, control unit 715 can also activate vacuum pump 729 to apply a pressure differential to deposition chamber 733 to assist in removing the first precursor material. The purge gas together with vacuum pump 729 can purge the first precursor material from deposition chamber 733.

[0054] After purging the first precursor material, introducing a second precursor material (e.g., propane) into deposition chamber 733 can be initiated by control unit 715, which sends an instruction to precursor gas controller 713 to disconnect purge gas delivery system 707 and connect second precursor delivery system 703 (which contains the second precursor material) to deposition chamber 733. Once connected, second precursor delivery system 703 can deliver the second precursor material into injection unit 719. Then, injection unit 719 can disperse the second precursor material into deposition chamber 733.

[0055] In the embodiment of forming a silicon carbonitride layer using dichlorosilane as the first precursor material and propane as the second precursor material discussed above, the second precursor material can be introduced into deposition chamber 733 at any suitable flow rate, with the carrier gas at any suitable flow rate. However, as would be recognized by one of ordinary skill in the art, these flow rates are only illustrative, as any suitable process conditions can be utilized while remaining within the scope of the embodiment.

[0056] Additionally, to better control the composition of the individual elements within barrier layer 701, control the time at which the second precursor material enters deposition chamber 733 in a pulsed manner. For example, in one embodiment, the second precursor material can be delivered in a pulsed manner for a second time between about 3 seconds and about 70 seconds (e.g., about 60 seconds). However, any suitable time can be utilized.

[0057] Figure 7DA close-up view of the surface of the barrier layer 701 is shown, and in an embodiment where dichlorosilane is desired to be used as the first precursor material and propane is used as the second precursor material to form a silicon carbonitride layer, under these process conditions, propane will react with the exposed surface (e.g., the reaction product of the first precursor material) to provide a surface in which carbon is chemically bonded to the underlying surface (e.g., silicon), while the opposite surface terminates in hydrogen atoms exposed to the ambient atmosphere within the deposition chamber 733.

[0058] After the reaction of the second precursor material has been completed, a second purge process can be used to purge the second precursor material from the deposition chamber 733. For example, the control unit 715 can instruct the precursor gas controller 713 to disconnect the second precursor delivery system 703 (containing the second precursor material to be purged from the deposition chamber 733) and connect the purge gas delivery system 707 to deliver a purge gas to the deposition chamber 733. In an embodiment, the purge gas delivery system 707 can deliver the purge gas at a flow rate between about 2 slm and about 20 slm (e.g., about 10 slm) for a period of time between about 3 s and about 70 s. Additionally, the control unit 715 can also activate the vacuum pump 729 in order to apply a pressure differential to the deposition chamber 733 to assist in removing the second precursor material. The purge gas together with the vacuum pump 729 can purge the second precursor material from the deposition chamber 733.

[0059] After purging the second precursor material, introducing a third precursor material (e.g., ammonia) into the deposition chamber 733 can be initiated by the control unit 715, which sends an instruction to the precursor gas controller 713 to disconnect the purge gas delivery system 707 and connect the third precursor delivery system 705 (containing the third precursor material) to the deposition chamber 733. Once connected, the third precursor delivery system 705 can deliver the third precursor material to the injection unit 719. Then, the injection unit 719 can disperse the third precursor material into the deposition chamber 733.

[0060] In the embodiment discussed above of forming a silicon carbonitride layer using dichlorosilane as the first precursor material, propane as the second precursor material, and ammonia as the third precursor material, the third precursor material can be introduced into the deposition chamber 733 at any suitable flow rate, where the carrier gas is at any suitable flow rate. However, as those of ordinary skill in the art will recognize, these flow rates are only illustrative, as any suitable process conditions can be utilized while remaining within the scope of the embodiment.

[0061] In addition, to better control the composition of each element within the barrier layer 701, the time for the third precursor material to enter the deposition chamber 733 in a pulsed manner is controlled. For example, in one embodiment, the third precursor material can be delivered in a pulsed manner for a third time between about 3 seconds and about 20 seconds (e.g., about 16 seconds). However, any suitable time can be utilized.

[0062] Figure 7E A close-up view of the surface of the barrier layer 701 is shown, and in an embodiment where it is desired to use dichlorosilane as the first precursor material, propane as the second precursor material, and ammonia as the third precursor material to form a silicon carbonitride layer, under these process conditions, the ammonia will react with the exposed surface to provide a surface in which nitrogen is chemically bonded to the underlying surface (e.g., silicon and carbon), while the opposite surface terminates in hydrogen atoms exposed to the ambient atmosphere within the deposition chamber 733.

[0063] After the reaction of the third precursor material has been completed, a third purge process can be used to purge the third precursor material from the deposition chamber 733. For example, the control unit 715 can instruct the precursor gas controller 713 to disconnect the third precursor delivery system 705 (containing the third precursor material to be purged from the deposition chamber 733) and connect the purge gas delivery system 707 to deliver the purge gas to the deposition chamber 733. In an embodiment, the purge gas delivery system 707 can deliver the purge gas at a flow rate between about 2 slm and about 20 slm (e.g., about 10 slm) for a period of time between about 3 s and about 20 s. Additionally, the control unit 715 can also activate the vacuum pump 729 in order to apply a pressure differential to the deposition chamber 733 to assist in removing the third precursor material. The purge gas together with the vacuum pump 729 can purge the third precursor material from the deposition chamber 733.

[0064] After the deposition chamber 733 has been purged using the third purge process, the first cycle for forming the barrier layer 703 is completed, and a second cycle similar to the first cycle can be started. For example, the repeating cycle can introduce the first precursor material, purge with the purge gas, deliver the second precursor material in a pulsed manner, purge with the purge gas, deliver the third precursor material in a pulsed manner, and purge with the purge gas.

[0065] It can be seen that each cycle of the first precursor material, the second precursor material, and the third precursor material can deposit another layer of the desired material (e.g., SiCN) for the barrier layer 701. Additionally, each cycle also resets the exposed surface such that the exposed surface is ready to receive the next cycle of the first precursor material, the second precursor material, and the third precursor material. These cycles can be repeated any suitable number of times to form the barrier layer 701 to any desired thickness.

[0066] Once the deposition cycle has been completed, a removal process may be performed to remove the substrate 50 from the deposition system 731. In one embodiment, the removal process may include a gas line purge, a post-purge (using, for example, a third precursor material), ramping the temperature down from, for example, 640 °C to about 300 °C, and backfilling the environment within the deposition chamber to ambient atmosphere. Once this operation has been performed, the substrate 50 may be removed from the deposition system 731.

[0067] By utilizing the processes and times described above, a barrier layer 701 may be formed with a desired first composition. For example, using the times and temperatures described above, the barrier layer may be formed to have a silicon composition between about 39.3 atomic percent and about 42.13 atomic percent, a carbon composition between about 15.1 atomic percent and about 17.93 atomic percent, and a nitrogen composition between about 37.1 atomic percent and about 39.93 atomic percent. However, any suitable composition may be used.

[0068] Figure 8A The formation of a bulk material 801 is shown to fill and / or overfill the first opening 601 above the barrier layer 701. In an embodiment, the bulk material 801 is a dielectric material that supplements the barrier layer 701 to form a hybrid dielectric fin 901. In a particular embodiment, the bulk material 801 is the same material as the barrier layer 701 (e.g., SiCN), although in other embodiments, the material of the bulk material 801 may be different from the material of the barrier layer 701.

[0069] In an embodiment where the bulk material 801 is the same material as the material of the barrier layer 701, the bulk material 801 may be deposited in the same deposition chamber 733 as the barrier layer 701 by adjusting the deposition parameters but using the same precursors (e.g., a first precursor material (e.g., DCS), a second precursor material (e.g., propane), and a third precursor material (e.g., ammonia)).

[0070] For example, once the barrier layer 701 has been formed to have a first composition, an atomic layer deposition cycle for forming the bulk material 801 may be initiated by the control unit 715, which ramps the temperature of the deposition chamber 733 up to a second temperature that is higher than the deposition temperature of the barrier layer 701, e.g., about 640 °C. However, any suitable temperature may be utilized.

[0071] Once the temperature has stabilized, the control unit 715 can send an instruction to the precursor gas controller 713 to connect the first precursor delivery system 702 to the deposition chamber 733. Once connected, the first precursor delivery system 702 can deliver the first precursor material to the injection unit 719 through the precursor gas controller 713 and the manifold 717. The injection unit 719 can then disperse the first precursor material into the deposition chamber 733, where the first precursor material can be adsorbed and react with each exposed surface.

[0072] In an embodiment where a silicon carbonitride layer is formed as the bulk material 801, the first precursor material (e.g., DCS) can flow into the deposition chamber 733 at any suitable flow rate, where the carrier gas is at any suitable flow rate. However, any suitable flow rate can be used.

[0073] Additionally, to better control the composition of each element within the bulk material 801, the time for the first precursor material to enter the deposition chamber 733 in a pulsed manner is controlled. For example, in one embodiment, the first precursor material can be delivered in pulses for a fourth time that is longer than the first time (for depositing the barrier layer 701) and is between about 20 seconds and about 120 seconds (e.g., about 60 seconds). However, any suitable time can be utilized.

[0074] After the reaction of the first precursor material has been completed, a fourth purge process can be used to purge the first precursor material in the deposition chamber 733. For example, the control unit 715 can instruct the precursor gas controller 713 to disconnect the first precursor delivery system 702 (containing the first precursor material to be purged from the deposition chamber 733) and connect the purge gas delivery system 707 to deliver the purge gas to the deposition chamber 733. In an embodiment, the purge gas can be introduced at a purge flow between about 2 slm and about 20 slm (e.g., about 10 slm). Additionally, the control unit 715 can also activate the vacuum pump 729 to apply a pressure differential to the deposition chamber 733 to assist in removing the first precursor material. The purge gas together with the vacuum pump 729 can purge the first precursor material from the deposition chamber 733.

[0075] Furthermore, since the deposition of the material for the bulk material 801 uses a longer pulse time for the flow of the first precursor material, the fourth purge process should also be extended. In an embodiment where the first precursor material is delivered in pulses for a time between about 20 seconds and about 120 seconds, the fourth purge process can be performed for a time between about 20 seconds and about 120 seconds. However, any suitable time can be utilized.

[0076] After purging the first precursor material, introducing a second precursor material (e.g., propane) into the deposition chamber 733 can be initiated by the control unit 715, which sends an instruction to the precursor gas controller 713 to disconnect the purge gas delivery system 707 and connect the second precursor delivery system 703 (containing the second precursor material) to the deposition chamber 733. Once connected, the second precursor delivery system 703 can deliver the second precursor material into the injection unit 719. Then, the injection unit 719 can disperse the second precursor material into the deposition chamber 733.

[0077] In the embodiment of forming a silicon carbonitride layer using dichlorosilane as the first precursor material and propane as the second precursor material discussed above, the second precursor material can be introduced into the deposition chamber 733 at any suitable flow rate, with the carrier gas at any suitable flow rate. However, as those of ordinary skill in the art will recognize, these flow rates are only illustrative, as any suitable process conditions can be utilized while remaining within the scope of the embodiment.

[0078] Additionally, to better control the composition of each element within the bulk material 801, the time for the second precursor material to enter the deposition chamber 733 in a pulsed manner is controlled. For example, in one embodiment, the second precursor material can be delivered in a pulsed manner for a fifth time that is longer than the second time (e.g., delivering the second precursor material in a pulsed manner during deposition of the barrier layer 701), and between about 70 seconds and about 200 seconds (e.g., about 120 seconds). However, any suitable time can be utilized.

[0079] After the reaction of the second precursor material has been completed, a fifth purge process can be used to purge the second precursor material from the deposition chamber 733. For example, the control unit 715 can instruct the precursor gas controller 713 to disconnect the second precursor delivery system 703 (containing the second precursor material to be purged from the deposition chamber 733) and connect the purge gas delivery system 707 to deliver the purge gas to the deposition chamber 733. In an embodiment, the purge gas delivery system 707 can deliver the purge gas at a flow rate between about 2 slm and about 20 slm (e.g., about 10 slm). Additionally, the control unit 715 can also activate the vacuum pump 729 to apply a pressure differential to the deposition chamber 733 to assist in removing the second precursor material. The purge gas together with the vacuum pump 729 can purge the second precursor material from the deposition chamber 733.

[0080] Additionally, since the deposition of the material for the bulk material 801 uses a longer pulse time for the flow of the second precursor material, the fifth purge process should also be extended. In an embodiment where the second precursor material is delivered in a pulsed manner for a time between about 70 seconds and about 200 seconds, the fifth purge process can be performed for a time between about 70 seconds and about 200 seconds. However, any suitable time can be utilized.

[0081] After purging the second precursor material, the introduction of the third precursor material (e.g., ammonia) into the deposition chamber 733 can be initiated by the control unit 715. The control unit 715 sends an instruction to the precursor gas controller 713 to disconnect the purge gas delivery system 707 and connect the third precursor delivery system 705 (containing the third precursor material) to the deposition chamber 733. Once connected, the third precursor delivery system 705 can deliver the third precursor material to the injection unit 719. Then, the injection unit 719 can disperse the third precursor material into the deposition chamber 733.

[0082] In the embodiment discussed above for forming a silicon carbonitride layer using dichlorosilane as the first precursor material, propane as the second precursor material, and ammonia as the third precursor material, the third precursor material can be introduced into the deposition chamber 733 at any suitable flow rate, where the carrier gas is at any suitable flow rate. However, as would be recognized by those of ordinary skill in the art, these flow rates are only illustrative as any suitable process conditions can be utilized while remaining within the scope of the embodiment.

[0083] Additionally, to better control the composition of each element within the bulk material 801, the time for the third precursor material to enter the deposition chamber 733 in a pulsed manner is controlled. For example, in one embodiment, the third precursor material can be delivered in a pulsed manner for a sixth time between about 20 seconds and about 120 seconds (e.g., about 60 seconds). However, any suitable time can be utilized.

[0084] After the reaction of the third precursor material is complete, a sixth purge process can be used to purge the third precursor material in the deposition chamber 733. For example, the control unit 715 can instruct the precursor gas controller 713 to disconnect the third precursor delivery system 705 (containing the third precursor material to be purged from the deposition chamber 733) and connect the purge gas delivery system 707 to deliver the purge gas to the deposition chamber 733. In an embodiment, the purge gas delivery system 707 can deliver the purge gas at a flow rate between about 2 slm and about 20 slm (e.g., about 10 slm). Additionally, the control unit 715 can also activate the vacuum pump 729 to apply a pressure differential to the deposition chamber 733 to assist in removing the third precursor material. The purge gas together with the vacuum pump 729 can purge the third precursor material from the deposition chamber 733.

[0085] In addition, since the deposition of the material for the bulk material 801 uses a longer pulse time for the flow of the third precursor material, the sixth purge process should also be extended. In an embodiment where the third precursor material is delivered in a pulsed manner for a time between about 20 seconds and about 120 seconds, the sixth purge process can be performed for a time between about 20 seconds and about 120 seconds. However, any suitable time can be utilized.

[0086] After the deposition chamber 733 has been purged using the sixth purge process, the first cycle for forming the bulk material 801 is complete, and a second cycle similar to the first cycle can be started. For example, the repeating cycle can introduce the first precursor material, purge with a purge gas, deliver the second precursor material in a pulsed manner, purge with a purge gas, deliver the third precursor material in a pulsed manner, and purge with a purge gas.

[0087] It can be seen that each cycle of the first precursor material, the second precursor material, and the third precursor material can deposit another layer of the desired material (e.g., SiCN) for the bulk material 801. Additionally, each cycle additionally resets the exposed surface such that the exposed surface is ready to receive the next cycle of the first precursor material, the second precursor material, and the third precursor material. These cycles can be repeated any suitable number of times to form the barrier layer 801 to any desired thickness.

[0088] Figure 8B is shown Figure 8A A close-up view of the dashed box labeled 803 in. It can be seen that during the deposition process of the bulk material 801 within the first opening 601, the material of the bulk material 801 will grow from each surface and eventually fuse together when the two surfaces come into contact. Thus, in some embodiments, the bulk material 801 can have a seam 805 located within the bulk material 801. In other embodiments, a subsequent annealing process or elevated temperature can cause the material of the bulk material 801 to expand to help close any voids.

[0089] By utilizing the times and temperatures as described above, the bulk material 801 can be formed to have a desired second composition that is different from the first composition of the barrier layer 701. For example, using the times as described above, the bulk material 801 can be formed to have the following composition: a silicon composition greater than the barrier layer 701 and between about 45.7 atomic percent and about 48.73 atomic percent, a carbon composition greater than the barrier layer 701 and between about 19.1 atomic percent and about 22.13 atomic percent, and a nitrogen composition less than the barrier layer 701 and between about 26.1 atomic percent and about 29.13 atomic percent. However, any suitable composition can be used.

[0090] Figure 9Once the bulk material 801 has been deposited, the bulk material 801 and the barrier layer 701 can be planarized with the insulating material 54 and the fin 52 so as to remove the excess materials of the barrier layer 701 and the bulk material 801 from the outside of the first opening 601 and form a dielectric hybrid fin 901. In an embodiment, chemical mechanical polishing process can be used to perform the planarization. However, any suitable planarization process (e.g., grinding process or etch-back process) can be used.

[0091] By utilizing the combination of the barrier layer 701 and the bulk material 801, the total etch rate of the hybrid fin 901 during subsequent etching processes (e.g., the recess of the insulating material 54 described below Figure 10 can be reduced. For example, although the barrier layer 701 may experience removal of about during subsequent etching, the bulk material 801 may experience a smaller reduction, e.g., about Such a reduction enables the entire hybrid fin 901 to better withstand the etching process and prevent subsequent penetration of harmful chemicals, resulting in smaller devices or higher yields.

[0092] In Figure 10 , the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed such that the upper portions of the fins 52 and the hybrid fins 901 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 56. Additionally, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof as shown. The top surface of the STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 56 can be recessed using an acceptable etching process, e.g., an etching process selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the materials of the fins 52 and the hybrid fins 901). For example, oxide removal using, e.g., dilute hydrofluoric acid (dHF) can be used.

[0093] Regarding Figures 2 to 11 The process described above is merely an example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form fins. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fins 52. For example, Figure 5The fin 52 therein can be recessed, and a material different from that of the fin 52 can be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material and the epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and trenches are etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and subsequent implantations, although in-situ and implant doping can be used together.

[0094] Further, it may be advantageous to epitaxially grow a material in the n-type region 50N (e.g., NMOS region) that is different from the material in the p-type region 50P (e.g., PMOS region). In various embodiments, the upper portion of the fin 52 can be formed of silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0095] In addition, in Figure 10 , appropriate wells (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well can be formed in the n-type region 50N, and an n well can be formed in the p-type region 50P. In some embodiments, a P well or an N well is formed in both the n-type region 50N and the p-type region 50P.

[0096] In embodiments having different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a photoresist and / or other masks (not shown). For example, a photoresist can be formed over the fin 52 and the STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent the n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., and the concentration of the n-type impurities implanted into this region is equal to or less than 10 18 cm -3 , for example, at about 1016 cm -3 and about 10 18 cm -3 Therebetween. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0097] After implantation into the p-type region 50P, a photoresist is formed over the fins 52 and STI regions 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation is performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., and the concentration of the p-type impurities implanted into this region is equal to or less than or less than 10 18 cm -3 e.g., at about 10 16 cm -3 and about 10 18 cm -3 Therebetween. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0098] After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0099] During Figure 11In [the figure], a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized (e.g., by CMP). The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group including: amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 62 can be made of other materials that have a high etch selectivity with respect to the etching of isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). The mask layer 64 can include one or more layers of, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown as only covering the fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 56, thus extending over the STI region and between the dummy gate layer 62 and the STI region 56.

[0100] Figures 12A to 20B Various additional steps in manufacturing an exemplary device are shown. Figures 12A to 20B Features of either the n-type region 50N or the p-type region 50P are shown. For example, Figures 12A to 20B the structures shown in [the figure] can be applicable to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

[0101] In Figure 12A and Figure 12B [the figure], acceptable lithography and etching techniques can be used for the mask layer 64 (see Figure 11)It is patterned to form a mask 74. Then, the pattern of the mask 74 can be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers the corresponding channel regions 58 of the fins 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0102] In addition, in Figure 12A and Figure 12B , a gate seal spacer 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. Thermal oxidation or deposition (followed by anisotropic etching) can form the gate seal spacer 80. The gate seal spacer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0103] After forming the gate seal spacer 80, an implantation for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments having different device types, similar to the implantation discussed above in Figure 10 , a mask (e.g., photoresist) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the exposed fins 52 in the p-type region 50P. Then the mask can be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurity can be implanted into the exposed fins 52 in the n-type region 50N. Then the mask can be removed. The n-type impurity can be any of the n-type impurities discussed above, and the p-type impurity can be any of the p-type impurities discussed above. The lightly doped source / drain regions can have an impurity concentration ranging from about 10 15 cm -3 to about 10 19 cm -3 . Annealing can be used to repair implantation damage and activate the implanted impurities.

[0104] In Figure 13A and Figure 13B , gate spacers 86 are formed on the gate seal spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacers 86 can be formed by conformally depositing an insulating material and then performing anisotropic etching on the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.

[0105] Note that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be utilized, or different step sequences may be employed (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer, the spacers may be formed and removed, etc.). Additionally, n-type and p-type devices may be formed using different structures and steps. For example, the LDD region of an n-type device may be formed before forming the gate seal spacer 80, while the LDD region of a p-type device may be formed after forming the gate seal spacer 80.

[0106] In Figure 14A and Figure 14B an epitaxial source / drain region 82 is formed in the fin 52. The epitaxial source / drain region 82 is formed in the fin 52 such that each dummy gate 72 is disposed between an adjacent pair of the corresponding epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain region 82 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, the gate spacer 86 is used to space the epitaxial source / drain region 82 from the dummy gate 72 by an appropriate lateral distance such that the epitaxial source / drain region 82 does not short circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain region 82 may be selected to apply stress in the corresponding channel region 58 to improve performance.

[0107] The epitaxial source / drain region 82 in the n-type region 50N may be formed by masking the p-type region 50P and etching the source / drain regions of the fins 52 in the n-type region 50N to form recesses in the fins 52. Then, the epitaxial source / drain region 82 in the n-type region 50N grows epitaxially in the recesses. The epitaxial source / drain region 82 may include any acceptable material (e.g., suitable for an n-type FinFET). For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region 50N may have a surface that protrudes from the corresponding surface of the fin 52 and may have facets.

[0108] The epitaxial source / drain regions 82 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain regions of the fins 52 in the p-type region 50P to form recesses in the fins 52. Then, the epitaxial source / drain regions 82 in the p-type region 50P grow epitaxially in the recesses. The epitaxial source / drain regions 82 can include any acceptable material (e.g., suitable for a p-type FinFET). For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the p-type region 50P can include materials that apply compressive stress in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the p-type region 50P can have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0109] The epitaxial source / drain regions 82 and / or the fins 52 can be implanted with dopants to form the source / drain regions, similar to the process for forming lightly doped source / drain regions discussed previously, and then annealing is performed. The impurity concentration of the source / drain regions can be between about 10 19 cm -3 to about 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in-situ during growth.

[0110] As a result of the epitaxial process for forming the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has facets that laterally extend outward beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as Figure 14C shown. In other embodiments, after the epitaxial process is completed, the adjacent source / drain regions 82 remain separated, as Figure 14D shown. In the embodiments shown in Figure 14C and Figure 14D , gate spacers 86 are formed to cover a portion of the sidewalls of the fins 52, which extend above the STI region 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etch for forming the gate spacers 86 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 56.

[0111] In Figure 15A and Figure 15B , a first interlayer dielectric (ILD) 88 is deposited on Figure 14A and Figure 14BOver the structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 can include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) that has an etch rate lower than that of the overlying material of the first ILD 88.

[0112] In Figure 16A and Figure 16B , a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and can remove some portions of the gate seal spacers 80 and the gate spacers 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate seal spacers 80, the gate spacers 86, and the first ILD 88 are flush. Thus, the top surface of the dummy gate 72 is exposed through the ILD 88. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0113] In Figure 17A and Figure 17BIn (one or more) etching steps, dummy gate 72 and mask 74 (if present) are removed to form recess 90. A portion of dummy dielectric layer 60 in recess 90 may also be removed. In some embodiments, only dummy gate 72 is removed and dummy dielectric layer 60 remains and is exposed through recess 90. In some embodiments, dummy dielectric layer 60 is removed from recess 90 in a first region of the die (e.g., the core logic region) and remains in recess 90 in a second region of the die (e.g., the input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etch dummy gate 72 with little or no etching of first ILD 88 or gate spacer 86. Each recess 90 exposes and / or covers channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between a pair of adjacent epitaxial source / drain regions 82. During removal, dummy dielectric layer 60 may be used as an etch stop layer when etching dummy gate 72. Then, after removing dummy gate 72, dummy dielectric layer 60 may optionally be removed.

[0114] In Figure 18A and Figure 18B therein, a gate dielectric layer 92 and a gate electrode 94 for replacing the gate are formed. Figure 18C shows Figure 18B a detailed view of region 89. Gate dielectric layer 92 may include one or more layers deposited in recess 90, e.g., deposited on the top surface and sidewalls of fins 52 and on the sidewalls of gate seal spacer 80 / gate spacer 86. Gate dielectric layer 92 may also be formed on the top surface of first ILD 88. In some embodiments, gate dielectric layer 92 includes one or more dielectric layers, e.g., one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, gate dielectric layer 92 includes an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, e.g., a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. The method of forming gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of dummy dielectric layer 60 remains in recess 90, gate dielectric layer 92 may include the material of dummy dielectric layer 60 (e.g., SiO2).

[0115] The gate electrode 94 is deposited respectively over the gate dielectric layer 92 and fills the remaining portion of the recess 90. The gate electrode 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 18B shows a single-layer gate electrode 94, the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and a fill material 94C, as Figure 18C shown. After filling the recess 90, a planarization process such as CMP may be performed to remove the excess portions of the materials of the gate dielectric layer 92 and the gate electrode 94 that are located above the top surface of the ILD 88. Thus, the remaining portions of the materials of the gate electrode 94 and the gate dielectric layer 92 form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0116] Forming the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P may occur simultaneously such that the gate dielectric layer 92 in each region is formed of the same material, and forming the gate electrode 94 may occur simultaneously such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by different processes such that the gate dielectric layer 92 may be different materials, and the gate electrode 94 in each region may be formed by different processes such that the gate electrode 94 may be different materials. When using different processes, various masking steps may be used to mask and expose appropriate regions.

[0117] In Figure 19A and Figure 19B a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask may be disposed between opposite portions of the gate spacer 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack such that a recess is formed directly above the gate stack and between opposite portions of the gate spacer 86. The gate mask 96 including one or more dielectric materials (such as silicon nitride, silicon oxynitride, etc.) is filled in the recess, and then a planarization process is performed to remove the excess portions of the dielectric material that extend above the first ILD 88.

[0118] Also as Figure 19A and Figure 19BAs shown, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. Subsequently formed gate contacts 110 ( Figure 20A and Figure 20B ) pass through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0119] In Figure 20A and 20B , according to some embodiments, the gate contacts 110 and the source / drain contacts 112 are formed to pass through the second ILD 108 and the first ILD 88. Openings for the source / drain contacts 112 are formed to pass through the first ILD 88 and the second ILD 108, and openings for the gate contacts 110 are formed to pass through the second ILD 108 and the gate mask 96. Acceptable lithography and etching techniques can be used to form the openings. Liners (not shown) such as diffusion barrier layers, adhesion layers, etc. and conductive materials are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contacts 112 and the gate contacts 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain region 82, and the gate contacts 110 are physically and electrically coupled to the gate electrode 106. The source / drain contacts 112 and the gate contacts 110 can be formed by different processes or can be formed by the same process. Although each source / drain contact 112 and gate contact 110 is shown as being formed with the same cross-section, it should be understood that each source / drain contact 112 and gate contact 110 can be formed with a different cross-section, which can avoid short-circuiting of the contacts.

[0120] The disclosed FinFET embodiments can also be applied to nanostructure devices, e.g., nanostructure (e.g., nanosheet, nanowire, gate-all-around, etc.) field effect transistors (NSFETs). In an NSFET embodiment, the fin is replaced by a nanostructure formed by patterning a stack of alternating layers of a channel layer and a sacrificial layer. The dummy gate stack and the source / drain regions are formed in a similar manner as in the above embodiments. After the dummy gate stack is removed, the sacrificial layer can be partially or fully removed in the channel region. The replacement gate structure is formed in a similar manner as in the above embodiments, the replacement gate structure can partially or fully fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or fully surround the channel layer in the channel region of the NSFET device. The ILD and the contacts to the replacement gate structure and the source / drain regions can be formed in a similar manner as in the above embodiments. The nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is hereby incorporated by reference in its entirety.

[0121] Figures 21A - 21B Another embodiment is shown in which a barrier layer 701 and a bulk material 801 are connected within a first opening 601 by an intermediate material 2101. Figure 21B is shown Figure 21A a close-up view of the dashed line 2103 in. In this embodiment, after the barrier layer 701 has been deposited, the intermediate material 2101 is deposited before the bulk material 801 is deposited. In an embodiment, the same precursor and the same process as described above for the bulk material 801 can be used to deposit the intermediate material 2101. However, in this embodiment, the temperature of the deposition process is modified to be different from the deposition process of the bulk material 801. For example, in an embodiment in which the bulk material 801 is deposited at a temperature of 640 °C, although any suitable temperature can be utilized, the deposition process of the intermediate material 2101 can be performed at a lower temperature, e.g., the temperature used for the deposition of the barrier layer 701, e.g., about 620 °C. In some embodiments, the intermediate material 2101 can be deposited to any suitable thickness.

[0122] By utilizing the processes and temperatures as described above, the intermediate material 2101 can be formed to have a different composition from the barrier layer 701 or the bulk material 801. For example, when the intermediate material 2101 is formed at a temperature of about 620 °C, the intermediate material 2101 can be formed to have the following composition: a silicon component between about 42.9 atomic percent and about 46.23 atomic percent, a carbon component between about 16.6 atomic percent and about 19.93 atomic percent, and a nitrogen component between about 30.5 atomic percent and about 33.83 atomic percent. However, any suitable composition can be used.

[0123] Once the intermediate material 2101 has been deposited, the bulk material 801 can be deposited to fill and / or overfill the remainder of the first opening 601. In some embodiments, a temperature such as 640° C. can be used to deposit the bulk material 801 as described above with respect to FIG. 8. However, any suitable process can be used.

[0124] Additionally, once the bulk material 801 has been deposited, the remainder of the process can be performed as described above. For example, the bulk material 801, the intermediate material 2101, and the barrier layer 701 can be planarized, the isolation region 56 can be recessed to expose the fins 52, and the gates can be formed. However, any suitable process can be used.

[0125] By using the hybrid fin 901 described herein together with the intermediate material 2101, the overall etch rate of the hybrid fin 901 during subsequent etch processes (such as the recessing of the insulating material 54 described above with respect to Figure 10 can be reduced. For example, while the barrier layer 701 may experience a removal of about during subsequent etching, the intermediate material 2101 can experience a smaller reduction, such as The bulk material 801 can experience an even smaller reduction, such as about Such reductions enable the entire hybrid fin 901 to better withstand the etch process and prevent subsequent penetration of harmful chemicals, resulting in smaller devices or higher yields.

[0126] According to an embodiment, a method of manufacturing a semiconductor device includes: forming an opening in a dielectric material located between semiconductor fins; and depositing a first dielectric material in the opening, wherein depositing the first dielectric material includes: delivering a first precursor material in a pulsed manner for a first time between about 20 seconds and about 120 seconds; delivering a second precursor material in a pulsed manner for a second time between about 70 seconds and about 200 seconds, the second precursor material being different from the first precursor material; and delivering a third precursor material in a pulsed manner for a third time between about 20 seconds and about 120 seconds, the third precursor material being different from both the first precursor material and the second precursor material. In an embodiment, the method further includes: depositing a barrier layer in the opening before depositing the first dielectric material, wherein depositing the barrier layer includes: delivering the first precursor material in a pulsed manner for a fourth time less than the first time; delivering the second precursor material in a pulsed manner for a fifth time less than the second time; delivering the third precursor material in a pulsed manner for a sixth time less than the third time; in an embodiment, the fourth time is between about 3 seconds and about 20 seconds, wherein the fifth time is between about 3 seconds and about 70 seconds, and wherein the sixth time is between about 3 seconds and about 20 seconds. In an embodiment, the first precursor material includes dichlorosilane, wherein the second precursor material includes propane, and wherein the third precursor material includes ammonia. In an embodiment, the first dielectric material includes silicon carbonitride. In an embodiment, the silicon carbonitride has a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%. In an embodiment, the barrier layer has a silicon concentration between about 39.3% and about 42.13%, a carbon concentration between about 15.1% and 17.93%, and a nitrogen concentration between about 37.1% and 39.93%.

[0127] According to another embodiment, a method of manufacturing a semiconductor device includes: depositing a barrier layer to line an opening in a dielectric material between semiconductor fins, depositing the barrier layer including: introducing a first precursor material for a first time; after introducing the first precursor material, introducing a second precursor material for a second time, the second precursor material being different from the first precursor material; and after introducing the second precursor material, introducing a third precursor material for a third time, the third precursor material being different from both the first precursor material and the second precursor material; filling the remaining portion of the opening by depositing a bulk material, depositing the bulk material including: introducing the first precursor material for a fourth time longer than the first time; after introducing the first precursor material to deposit the bulk material, introducing the second precursor material for a fifth time longer than the second time; and after introducing the second precursor material to deposit the bulk material, introducing the third precursor material for a sixth time longer than the third time. In an embodiment, the method further includes: planarizing the barrier layer with the dielectric material and the semiconductor fins; and recessing the dielectric material to expose sidewalls of the semiconductor fins and sidewalls of the barrier layer. In an embodiment, the fourth time is between about 20 seconds and about 120 seconds, wherein the fifth time is between about 70 seconds and about 200 seconds, and wherein the sixth time is between about 20 seconds and about 120 seconds. In an embodiment, the first time is between about 3 seconds and about 20 seconds, and the second time is between about 3 seconds and about 70 seconds, and wherein the third time is between about 3 seconds and about 20 seconds. In an embodiment, the method further includes: depositing an intermediate material before filling the remaining portion of the opening, depositing the intermediate material including: introducing the first precursor material for the fourth time; after introducing the first precursor material to deposit the intermediate material, introducing the second precursor material for the fifth time; and after introducing the second precursor material to deposit the intermediate material, introducing the third precursor material for the sixth time, wherein depositing the intermediate material is performed at the same temperature as depositing the barrier layer. In an embodiment, the bulk material has a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%. In an embodiment, the barrier layer has a silicon concentration between about 39.3% and about 42.13%, a carbon concentration between about 15.1% and 17.93%, and a nitrogen concentration between about 37.1% and 39.93%.

[0128] According to another embodiment, a semiconductor device includes: a semiconductor fin extending through a dielectric material; and a hybrid dielectric fin extending from within the dielectric material, the hybrid dielectric fin including: a barrier layer including a first material having a first composition; and a bulk material including the first material having a second composition different from the first composition, the second composition having a greater carbon concentration than the first composition. In an embodiment, the first material is silicon carbonitride. In an embodiment, the second composition has a carbon concentration of about 19.1%. In an embodiment, the silicon concentration of the second composition is greater than the silicon concentration of the first composition. In an embodiment, the nitrogen concentration of the second composition is less than the nitrogen concentration of the first composition. In an embodiment, the second composition includes a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%.

[0129] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0130] Example 1 is a method of manufacturing a semiconductor device, the method including: forming an opening within a dielectric material located between semiconductor fins; and depositing a first dielectric material within the opening, depositing the first dielectric material including: delivering a first precursor material in a pulsed manner for a first time between about 20 seconds and about 120 seconds; delivering a second precursor material in a pulsed manner for a second time between about 70 seconds and about 200 seconds, the second precursor material being different from the first precursor material; and delivering a third precursor material in a pulsed manner for a third time between about 20 seconds and about 120 seconds, the third precursor material being different from both the first precursor material and the second precursor material.

[0131] Example 2 is the method of Example 1, further including: depositing a barrier layer within the opening before depositing the first dielectric material, depositing the barrier layer including: delivering the first precursor material in a pulsed manner for a fourth time less than the first time; delivering the second precursor material in a pulsed manner for a fifth time less than the second time; delivering the third precursor material in a pulsed manner for a sixth time less than the third time;

[0132] Example 3 is the method described in Example 2, wherein the fourth time is between about 3 seconds and about 20 seconds, wherein the fifth time is between about 3 seconds and about 70 seconds, and wherein the sixth time is between about 3 seconds and about 20 seconds.

[0133] Example 4 is the method described in Example 3, wherein the first precursor material includes dichlorosilane, wherein the second precursor material includes propane, and wherein the third precursor material includes ammonia.

[0134] Example 5 is the method described in Example 4, wherein the first dielectric material includes silicon carbonitride.

[0135] Example 6 is the method described in Example 5, wherein the silicon carbonitride has a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%.

[0136] Example 7 is the method described in Example 6, wherein the barrier layer has a silicon concentration between about 39.3% and about 42.13%, a carbon concentration between about 15.1% and 17.93%, and a nitrogen concentration between about 37.1% and 39.93%.

[0137] Example 8 is a method of manufacturing a semiconductor device, the method comprising: depositing a barrier layer to line an opening in a dielectric material between semiconductor fins, depositing the barrier layer comprising: introducing a first precursor material for a first time; after introducing the first precursor material, introducing a second precursor material for a second time, the second precursor material being different from the first precursor material; and after introducing the second precursor material, introducing a third precursor material for a third time, the third precursor material being different from both the first precursor material and the second precursor material; filling the remaining portion of the opening by depositing a bulk material, depositing the bulk material comprising: introducing the first precursor material for a fourth time longer than the first time; after introducing the first precursor material to deposit the bulk material, introducing the second precursor material for a fifth time longer than the second time; and after introducing the second precursor material to deposit the bulk material, introducing the third precursor material for a sixth time longer than the third time.

[0138] Example 9 is the method described in Example 8, further comprising: planarizing the barrier layer with the dielectric material and the semiconductor fins; and recessing the dielectric material to expose sidewalls of the semiconductor fins and sidewalls of the barrier layer.

[0139] Example 10 is the method described in Example 8, wherein the fourth time is between about 20 seconds and about 120 seconds, wherein the fifth time is between about 70 seconds and about 200 seconds, and wherein the sixth time is between about 20 seconds and about 120 seconds.

[0140] Example 11 is the method described in Example 10, wherein the first time is between about 3 seconds and about 20 seconds, and wherein the second time is between about 3 seconds and about 70 seconds, and wherein the third time is between about 3 seconds and about 20 seconds.

[0141] Example 12 is the method described in Example 8, further comprising: depositing an intermediate material before filling the remaining portion of the opening, wherein depositing the intermediate material comprises: introducing the first precursor material for the fourth time; after introducing the first precursor material to deposit the intermediate material, introducing the second precursor material for the fifth time; and after introducing the second precursor material to deposit the intermediate material, introducing the third precursor material for the sixth time, wherein depositing the intermediate material is performed at the same temperature as depositing the barrier layer.

[0142] Example 13 is the method described in Example 8, wherein the bulk material has a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%.

[0143] Example 14 is the method described in Example 8, wherein the barrier layer has a silicon concentration between about 39.3% and about 42.13%, a carbon concentration between about 15.1% and 17.93%, and a nitrogen concentration between about 37.1% and 39.93%.

[0144] Example 15 is a semiconductor device, comprising: a semiconductor fin extending through a dielectric material; and a hybrid dielectric fin extending from within the dielectric material, the hybrid dielectric fin comprising: a barrier layer comprising a first material having a first composition; and a bulk material comprising the first material having a second composition different from the first composition, the second composition having a greater carbon concentration than the first composition.

[0145] Example 16 is the semiconductor device described in Example 15, wherein the first material is silicon carbonitride.

[0146] Example 17 is the semiconductor device described in Example 15, wherein the second composition has a carbon concentration of about 19.1%.

[0147] Example 18 is the semiconductor device described in Example 15, wherein the silicon concentration of the second component is greater than the silicon concentration of the first component.

[0148] Example 19 is the semiconductor device described in Example 15, wherein the nitrogen concentration of the second component is less than the nitrogen concentration of the first component.

[0149] Example 20 is the semiconductor device described in Example 15, wherein the second component includes a silicon concentration between about 45.7% and 48.73%, a carbon concentration between about 19.1% and about 22.13%, and a nitrogen concentration between about 26.1% and about 29.13%.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming an opening within a dielectric material located between semiconductor fins; and depositing a first dielectric material within the opening, depositing the first dielectric material comprising: pulsed delivery of a first precursor material for a first time between 20 seconds and 120 seconds; pulsed delivery of a second precursor material for a second time between 70 seconds and 200 seconds, the second precursor material being different from the first precursor material; and pulsed delivery of a third precursor material for a third time between 20 seconds and 120 seconds, the third precursor material being different from both the first precursor material and the second precursor material; prior to depositing the first dielectric material, depositing a barrier layer within the opening, depositing the barrier layer comprising: pulsed delivery of the first precursor material for a fourth time less than the first time; pulsed delivery of the second precursor material for a fifth time less than the second time; pulsed delivery of the third precursor material for a sixth time less than the third time.

2. The method according to claim 1, wherein The fourth time is between 3 seconds and 20 seconds, wherein the fifth time is between 3 seconds and 70 seconds, and wherein the sixth time is between 3 seconds and 20 seconds.

3. The method according to claim 2, wherein The first precursor material comprises dichlorosilane, wherein the second precursor material comprises propane, and wherein the third precursor material comprises ammonia.

4. The method according to claim 3, wherein, The first dielectric material comprises silicon carbonitride.

5. The method according to claim 4, wherein The silicon carbonitride has a silicon concentration between 45.7% and 48.73%, a carbon concentration between 19.1% and 22.13%, and a nitrogen concentration between 26.1% and 29.13%.

6. The method according to claim 5, wherein, The barrier layer has a silicon concentration between 39.3% and 42.13%, a carbon concentration between 15.1% and 17.93%, and a nitrogen concentration between 37.1% and 39.93%.

7. A method of manufacturing a semiconductor device, the method comprising: depositing a barrier layer to line an opening in a dielectric material between semiconductor fins, depositing the barrier layer comprising: introducing a first precursor material for a first time; after introducing the first precursor material, introducing a second precursor material for a second time, the second precursor material being different from the first precursor material; and after introducing the second precursor material, introducing a third precursor material for a third time, the third precursor material being different from both the first precursor material and the second precursor material; filling the remainder of the opening by depositing a bulk material, depositing the bulk material comprising: introducing the first precursor material for a fourth time longer than the first time; after introducing the first precursor material to deposit the bulk material, introducing the second precursor material for a fifth time longer than the second time; and after introducing the second precursor material to deposit the bulk material, introducing the third precursor material for a sixth time longer than the third time.

8. The method according to claim 7, further comprising: Planarize the barrier layer with the dielectric material and the semiconductor fin; And Recess the dielectric material to expose the sidewalls of the semiconductor fin and the sidewalls of the barrier layer.

9. The method according to claim 7, wherein The fourth time is between 20 seconds and 120 seconds, wherein the fifth time is between 70 seconds and 200 seconds, and wherein the sixth time is between 20 seconds and 120 seconds.

10. The method according to claim 9, wherein, The first time is between 3 seconds and 20 seconds, and the second time is between 3 seconds and 70 seconds, and wherein the third time is between 3 seconds and 20 seconds.

11. The method according to claim 7 further comprises: Deposit an intermediate material before filling the remaining portion of the opening, wherein depositing the intermediate material includes: Introducing the first precursor material for the fourth time; After introducing the first precursor material to deposit the intermediate material, introducing the second precursor material for the fifth time; and After introducing the second precursor material to deposit the intermediate material, introducing the third precursor material for the sixth time, wherein depositing the intermediate material is performed at the same temperature as depositing the barrier layer.

12. The method according to claim 7, wherein, The bulk material has a silicon concentration between 45.7% and 48.73%, a carbon concentration between 19.1% and 22.13%, and a nitrogen concentration between 26.1% and 29.13%.

13. The method according to claim 7, wherein The barrier layer has a silicon concentration between 39.3% and 42.13%, a carbon concentration between 15.1% and 17.93%, and a nitrogen concentration between 37.1% and 39.93%.

14. A semiconductor device, comprising: A semiconductor fin extending through a dielectric material; And A hybrid dielectric fin extending from within the dielectric material, the hybrid dielectric fin including: A barrier layer, the barrier layer including a first material having a first composition; and A bulk material, the bulk material including the first material having a second composition different from the first composition, the second composition having a greater carbon concentration than the first composition; A dummy dielectric material in physical contact with the semiconductor fin.

15. The semiconductor device according to claim 14, wherein, The first material is silicon carbonitride.

16. The semiconductor device according to claim 14, wherein, The second composition has a carbon concentration of 19.1%.

17. The semiconductor device according to claim 14, wherein, The silicon concentration of the second composition is greater than the silicon concentration of the first composition.

18. The semiconductor device according to claim 14, wherein, The nitrogen concentration of the second composition is less than the nitrogen concentration of the first composition.

19. The semiconductor device according to claim 14, wherein, The second composition includes a silicon concentration between 45.7% and 48.73%, a carbon concentration between 19.1% and 22.13%, and a nitrogen concentration between 26.1% and 29.13%.

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