Bump encapsulation structure and method for preparing bump encapsulation structure

Abstract

Embodiments of the present invention provide a bump packaging structure and a method for preparing the bump packaging structure, which relate to the technical field of semiconductor packaging. The bump packaging structure includes a chip substrate, a solder pad, a protective layer, a metal layer, and a conductive bump. Among them, the metal layer includes an adhesive layer and a conductive layer. By providing the adhesive layer and opening a notch in the adhesive layer, the conductive layer extends into the notch and contacts the solder pad, thereby increasing the bonding area, and further increasing the bonding strength of the metal layer at the bottom of the conductive bump, ensuring firm bonding of the copper pillar bump. At the same time, direct contact between the conductive bump and the chip electrode is avoided, and the problem of electrode cracking is avoided. Moreover, the contact structure between the conductive layer and the solder pad is a segmented contact structure. Compared with directly providing the conductive layer on the solder pad, the present invention reduces the contact area between the conductive layer and the solder pad, thereby weakening the electromigration phenomenon, improving the electrical performance of the metal layer, and extending the service life of the conductive bump.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular, to a bump packaging structure and a method for manufacturing the bump packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, flip-chip packaging structures are widely used in the semiconductor industry. Flip-chip packaging uses bumps for electrical connection between the chip and the substrate. The bump includes a copper pillar, a metal layer (UBM: under bump metalization), and a passivation layer. After the metal layer UBM is fabricated, it is necessary to etch away the excess metal layer. However, over-etching often occurs, resulting in an undercut opening at the bottom of the copper pillar bump. Due to the existence of the undercut opening, the copper pillar bump is not firmly bonded. When the bump chip undergoes a reliability test, the copper pillar bump may fall off. If the bottom of the copper pillar bump is completely connected to the chip electrode, the stress on the copper pillar bump will directly act on the chip electrode, leading to the problem of chip electrode cracking. At the same time, there is an issue of electron migration of metal atoms at the bottom of the copper pillar bump, resulting in a significant reduction in the lifespan of the copper pillar bump. Summary of the Invention

[0003] The objectives of the present invention include, for example, providing a bump packaging structure and a method for manufacturing the bump packaging structure, which can ensure that the copper pillar bump is firmly bonded, avoid the detachment of the copper pillar bump, and avoid the problems of chip electrode cracking and electron migration, thereby significantly improving the service life of the copper pillar bump.

[0004] Embodiments of the present invention may be implemented as follows:

[0005] In a first aspect, the present invention provides a bump packaging structure, comprising:

[0006] A chip substrate;

[0007] A solder pad disposed on one side of the chip substrate;

[0008] A protective layer disposed on one side of the chip substrate, and an opening corresponding to the solder pad is provided on the protective layer to expose the solder pad to the protective layer;

[0009] A metal layer disposed on the side of the solder pad away from the chip substrate and extending from the opening to the surface of the protective layer;

[0010] A conductive bump disposed on the side of the metal layer away from the chip substrate;

[0011] Among them, the metal layer includes an adhesive layer and a conductive layer. The adhesive layer is disposed on a side of the bonding pad away from the chip substrate, the conductive layer is disposed on a side of the adhesive layer away from the chip substrate, a plurality of notches penetrating through to the bonding pad are provided on the adhesive layer, the conductive layer extends to the notches and contacts the bonding pad, and the conductive bump is electrically connected to the conductive layer.

[0012] In an alternative embodiment, the metal layer further includes a barrier layer. The barrier layer is disposed on a side of the conductive layer away from the chip substrate, and the barrier layer is located between the conductive layer and the conductive bump.

[0013] In an alternative embodiment, the metal layer further includes a wetting layer. The wetting layer is disposed on a side of the barrier layer away from the chip substrate, and the wetting layer is located between the barrier layer and the conductive bump to wet the conductive bump in a transitional manner.

[0014] In an alternative embodiment, a plurality of bonding blocks are further provided in the barrier layer. The plurality of bonding blocks penetrate through the barrier layer and are respectively in contact with the conductive layer and the wetting layer.

[0015] In an alternative embodiment, the plurality of bonding blocks are arranged in one-to-one correspondence with the plurality of notches, and the width of each bonding block is the same as the width of the notch.

[0016] In an alternative embodiment, the conductive bump includes a conductive metal column and a solder cap. The conductive metal column is disposed on a side of the metal layer away from the chip substrate, and a convex portion is provided at the bottom of the conductive metal. The convex portion extends into the opening and is connected to the metal layer, and the solder cap is disposed on the top of the conductive metal column.

[0017] In an alternative embodiment, a stop layer is further provided between the conductive metal column and the solder cap. The stop layer is used to block diffusion atoms between the solder cap and the conductive metal column.

[0018] In an alternative embodiment, two side walls of the opening are inclined relative to the bonding pad, and the width of the opening gradually increases in a direction away from the bonding pad.

[0019] In an alternative embodiment, the width of the bonding pad is greater than the width of the opening, so that the protective layer partially covers the bonding pad.

[0020] In a second aspect, the present invention provides a method for manufacturing a bump packaging structure for manufacturing the bump packaging structure according to any one of the foregoing embodiments. The method includes:

[0021] Form a bonding pad on one side of the chip substrate;

[0022] A protective layer is formed on one side of the chip substrate, and an opening corresponding to the bonding pad is formed on the protective layer. The width of the opening is smaller than that of the bonding pad, so that the protective layer partially covers the bonding pad;

[0023] A metal layer is formed on the side of the bonding pad away from the chip substrate, and the metal layer extends from the opening to the surface of the protective layer;

[0024] A conductive bump is formed on the side of the metal layer away from the chip substrate;

[0025] Wherein, the metal layer includes an adhesive layer and a conductive layer. The adhesive layer is arranged on the side of the bonding pad away from the chip substrate, the conductive layer is arranged on the side of the adhesive layer away from the chip substrate. A plurality of notches penetrating through the bonding pad are arranged on the adhesive layer, the conductive layer extends to the notches and contacts the bonding pad, and the conductive bump is electrically connected to the conductive layer.

[0026] The beneficial effects of the embodiments of the present invention include, for example:

[0027] In the bump packaging structure provided by the present invention, a metal layer is arranged on the side of the bonding pad away from the chip substrate, and a conductive bump is arranged on the metal layer. The metal layer includes an adhesive layer and a conductive layer. The adhesive layer is arranged on the side of the bonding pad away from the chip substrate, the conductive layer is arranged on the side of the adhesive layer away from the chip substrate. A plurality of notches penetrating through the bonding pad are arranged on the adhesive layer, the conductive layer extends to the notches and contacts the bonding pad, and the conductive bump is electrically connected to the conductive layer. By arranging the adhesive layer and opening notches on the adhesive layer, the conductive layer extends into the notches and contacts the bonding pad, thereby increasing the bonding area, and further increasing the bonding strength of the metal layer at the bottom of the conductive bump, which can ensure the firm bonding of the copper pillar bump and avoid the copper pillar bump from falling off. At the same time, the electrical connection is realized by additionally arranging the conductive layer, which avoids the direct contact between the conductive bump and the chip electrode, avoids the problem of electrode cracking, and the contact structure between the conductive layer and the bonding pad is a segmented contact structure. Compared with directly arranging the conductive layer on the bonding pad, the present invention reduces the contact area between the conductive layer and the bonding pad, thereby weakening the electromigration phenomenon, improving the electrical performance of the metal layer, and prolonging the service life of the conductive bump. Compared with the prior art, the bump packaging structure provided by the present invention can ensure the firm bonding of the copper pillar bump, avoid the copper pillar bump from falling off, and avoid the problems of chip electrode cracking and electromigration, and greatly prolong the service life of the copper pillar bump. Description of the Drawings

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0029] Figure 1 Schematic diagram of the bump packaging structure provided by the first embodiment of the present invention;

[0030] Figure 2 For Figure 1 Partial enlarged schematic diagram of II in

[0031] Figure 3 Schematic diagram of the bump packaging structure provided by the second embodiment of the present invention;

[0032] Figure 4 For Figure 3 Partial enlarged schematic diagram of IV in

[0033] Figure 5 Step block diagram of the preparation method of the bump packaging structure provided by the third embodiment of the present invention;

[0034] Figures 6 to 12 Process flow chart of the preparation method of the bump packaging structure provided by the third embodiment of the present invention.

[0035] Icon: 100 - bump packaging structure; 110 - chip substrate; 130 - solder pad; 150 - protective layer; 151 - opening; 170 - metal layer; 171 - adhesive layer; 172 - notch; 173 - conductive layer; 175 - barrier layer; 177 - wetting layer; 179 - bonding block; 190 - conductive bump; 191 - conductive metal column; 193 - solder cap; 195 - stop layer. Detailed implementation manners

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0038] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

[0039] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship in which the product of the present invention is usually placed during use. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0040] In addition, if terms such as "first", "second", etc. are used only for distinguishing descriptions, they should not be construed as indicating or implying relative importance.

[0041] As disclosed in the background art, for existing flip chips, it is usually necessary to provide a bump structure at the bottom of the chip to achieve electrical connection between the chip and the substrate. The bump structure is usually composed of copper pillars, UBM, and a passivation layer. After manufacturing the UBM, it is usually necessary to etch and remove the excess metal layer, and there is often an over-etching situation, resulting in an undercut opening at the bottom of the copper pillar bump, which in turn affects the bonding strength of the copper pillar bump and easily causes the problem of the copper pillar bump falling off. Moreover, in the existing technology, the bottom of the copper pillar bump is directly connected to the passivation layer without a wetting layer, resulting in a low bonding force between the passivation layer and the copper pillar, and also easily causing the falling-off situation. If a scheme of directly connecting the copper pillar bump to the chip electrode is adopted, the stress on the copper pillar bump will directly act on the chip electrode, resulting in the problem of chip electrode cracking. At the same time, in the existing technology, the bottom electrical contact area of the copper pillar bump is relatively large, and there is an easy problem of electron migration of the metal atoms at the bottom, resulting in a significant reduction in the service life of the copper pillar bump.

[0042] To solve the above problems, the present invention provides a bump packaging structure and a preparation method thereof, which can ensure firm bonding of the copper pillar bumps, avoid the falling-off of the copper pillar bumps, and avoid the problems of chip electrode cracking and electron migration, and greatly improve the service life of the copper pillar bumps. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0043] First Embodiment

[0044] Referring to Figure 1 and Figure 2 , this embodiment provides a bump packaging structure 100, which has a reliable structure, avoids the problems of electrode cracking and electron migration at the same time, and has a long service life.

[0045] This embodiment provides a bump packaging structure 100, which includes a chip substrate 110, a solder pad 130, a protective layer 150, a metal layer 170, and a conductive bump 190. The solder pad 130 is disposed on one side of the chip substrate 110. The protective layer 150 is disposed on one side of the chip substrate 110, and an opening 151 corresponding to the solder pad 130 is provided on the protective layer 150 so that the solder pad 130 is exposed from the protective layer 150. The metal layer 170 is disposed on the side of the solder pad 130 away from the chip substrate 110 and extends from the opening 151 to the surface of the protective layer 150. The conductive bump 190 is disposed on the side of the metal layer 170 away from the chip substrate 110. Among them, the metal layer 170 includes an adhesive layer 171 and a conductive layer 173. The adhesive layer 171 is disposed on the side of the solder pad 130 away from the chip substrate 110. The conductive layer 173 is disposed on the side of the adhesive layer 171 away from the chip substrate 110. A plurality of notches 172 penetrating through to the solder pad 130 are provided on the adhesive layer 171. The conductive layer 173 extends to the notches 172 and contacts the solder pad 130. The conductive bump 190 is electrically connected to the conductive layer 173.

[0046] In this embodiment, the chip substrate 110 is the body structure of a conventional flip chip, such as a common wafer / silicon wafer. Its electrodes are connected to the solder pads 130, so that its electrode structure is led out by the solder pads 130. The conductive bumps 190 protrude outward and are used to connect to the pads on the substrate. The conductive bumps 190 are electrically connected to the conductive layer 173, and the conductive layer 173 is connected to the solder pads 130, thereby realizing the electrical connection between the chip substrate 110 and the substrate.

[0047] It should be noted that the solder pads 130 in this embodiment are aluminum pads, and at the same time, the protective layer 150 can be made of a polymer dielectric material, such as epoxy, polyimide, benzocyclobutene, etc. When forming the protective layer 150, the protective layer 150 can use a coater to coat the polymer dielectric material uniformly on the chip substrate 110 in a selective coating manner, and then be soft-baked (soft bake) and shaped into a film through a hot plate. Through an exposure machine, its function uses a proximity method to cover the position of the predetermined opening of the protective layer 150 with a photomask and not expose it to light. Again, through a developing method, a developer is used to spray (Spray) to remove the unexposed area to expose the position of the opening 151 corresponding to the solder pad 130. Again, the protective layer 150 is heated in an oven (Oven) to accelerate curing to a fully cured and stable state. Again, a plasma descum machine (Descum) is used to remove the organic pollutants on the surface of the protective layer 150 or the residues in the opening 151, completing the process of exposing the solder pad 130. Among them, the photomask simultaneously covers the position of the opening 151 on the subsequent adhesive layer 171, so that a plurality of photoresist columns corresponding to the positions of the notches 172 can be formed and removed after the subsequent adhesive layer 171 is formed.

[0048] In this embodiment, an adhesive layer 171 is additionally provided. The adhesive layer 171 is preferably a titanium layer (Ti), and the titanium layer has extremely high metal bonding performance. While forming the opening 151 on the solder pad 130, a titanium layer can be electroplated in the opening 151 by using an electroplating process. Specifically, by covering the surrounding area with a photoresist, the excess metal layer 170 can be etched away without an etching process, avoiding the problem of over-etching. Then, a plasma ashing machine is used to remove the excess photoresist, exposing the solder pad 130 and the adhesive layer 171. By providing the adhesive layer 171 and forming a notch 172 in the adhesive layer 171, the conductive layer 173 extends into the notch 172 and contacts the solder pad 130, thereby increasing the bonding area, and further increasing the bonding strength of the metal layer 170 at the bottom of the conductive bump 190, ensuring that the copper pillar bump is firmly bonded and preventing the copper pillar bump from falling off. At the same time, the electrical connection is achieved by additionally providing the conductive layer 173, avoiding direct contact between the conductive bump 190 and the chip electrode, avoiding the problem of electrode cracking. Moreover, the contact structure between the conductive layer 173 and the solder pad 130 is a segmented contact structure. Compared with directly providing the conductive layer 173 on the solder pad 130, the present invention reduces the contact area between the conductive layer 173 and the solder pad 130, thereby weakening the electromigration phenomenon, improving the electrical performance of the metal layer 170, and extending the service life of the conductive bump 190.

[0049] It should be noted that when forming the adhesive layer 171 in this embodiment, first, a photoresist is coated on the chip substrate 110, and the opening 151 position and the predetermined notch 172 position are covered with a photomask. Then, after exposure and development, the opening 151 structure and the photoresist column structure are obtained. Then, the adhesive layer 171 is formed by an electroplating process. After removing the photoresist column structure, a plurality of notches 172 are obtained, completing the manufacturing process of the adhesive layer 171.

[0050] In this embodiment, the two side walls of the opening 151 are inclined relative to the solder pad 130, and the width of the opening 151 gradually increases in the direction away from the solder pad 130. Specifically, after exposure and development to expose the opening 151, the protective layer 150 is still in a stable state where it is not fully plasticized. Under the dual action of gravity and the plasma ashing machine, the two side walls of the opening 151 are inclined relative to each other, so that the surface of the side wall of the opening 151 has good transition, facilitating subsequent electroplating to form the metal layer 170.

[0051] In this embodiment, the width of the solder pad 130 is greater than the width of the opening 151, so that the protective layer 150 partially covers the solder pad 130. Specifically, the protective layer 150 covers the periphery of the solder pad 130 and exposes the middle part of the solder pad 130, so that the protective layer 150 effectively protects the connection between the solder pad 130 and the chip substrate 110, and ensures that the middle part of the solder pad 130 is exposed, making the alignment of the conductive bumps 190 better.

[0052] In this embodiment, the width of the solder pad 130 is greater than the width of the conductive bump 190, and the width of the conductive bump 190 is greater than the width of the opening 151. Specifically, the width of the metal layer 170 is also greater than the width of the opening 151. Here, the width of the conductive bump 190 is less than the width of the solder pad 130, so that the conductive bump 190 can be formed at the middle position of the solder pad 130, saving the material of the conductive bump 190 while ensuring electrical connection. At the same time, the width of the conductive bump 190 here is greater than the width of the opening 151, and the width of the metal layer 170 is greater than the width of the opening 151, so that the metal layer 170 and the conductive bump 190 can also extend to the protective layer 150, thus completely blocking the opening 151, increasing the bonding area and ensuring the fixing effect.

[0053] In this embodiment, both the lower half of the conductive layer 173 and the conductive bump 190 are made of copper, which has good electrical conductivity. And the conductive layer 173 is partially embedded in the notch 172 of the adhesive layer 171, so that the conductive layer 173 contacts the solder pad 130 through the notch 172 to achieve electrical connection, and the bonding force between the conductive layer 173 and the solder pad 130 is improved through the adhesive layer 171, thereby improving the bottom bonding reliability of the conductive bump 190. Here, the conductive layer 173 is a copper layer, and the copper layer has good electrical conductivity. The copper layer extending to the solder pad 130 is separated into multiple copper layer blocks by the adhesive layer 171, so as to achieve the purpose of reducing the area of the copper layer, reducing electron migration and improving the performance of the metal layer 170.

[0054] In this embodiment, the metal layer 170 further includes a barrier layer 175 and a wetting layer 177. The barrier layer 175 is disposed on the side of the conductive layer 173 away from the chip substrate 110, and the barrier layer 175 is located between the conductive layer 173 and the conductive bump 190. The wetting layer 177 is disposed on the side of the barrier layer 175 away from the chip substrate 110, and the wetting layer 177 is located between the barrier layer 175 and the conductive bump 190 to transition and wet the conductive bump 190. Among them, the barrier layer 175 is used to block atomic diffusion between the conductive layer 173 and the conductive bump 190. Also, the barrier layer 175 is made of a conductive metal material, such as nickel, vanadium, chromium, etc., to achieve electrical connection. At the same time, the wetting layer 177 is made of the same material as the bottom of the conductive bump 190, that is, the wetting layer 177 is also a copper layer. The wetting layer 177 is used to transition and wet the upper copper pillar-shaped conductive bump 190, further improving the bottom bonding force of the conductive bump 190.

[0055] It should be noted that in other preferred embodiments of the present invention, the wetting layer 177 may not be provided here, and the barrier layer 175 is directly in contact with the conductive bump 190.

[0056] It should be noted that the barrier layer 175 and the wetting layer 177 can be formed sequentially by an electroplating process. Specifically, after the conductive layer 173 is formed, a layer of conductive metal, such as nickel, vanadium, chromium, etc., is electroplated again to form the barrier layer 175. The material of the barrier layer 175 here needs to be different from that of the conductive layer 173 to achieve the function of blocking atomic diffusion. After the barrier layer 175 is formed, a layer of conductive metal is electroplated again. Here, a copper layer is electroplated to form the wetting layer 177. The wetting layer 177 is made of the same material as the copper pillar of the conductive bump 190 formed subsequently. The bonding between copper materials is relatively good, so as to play a role in transitioning and wetting the surface of the barrier layer 175 and the bottom surface of the conductive bump 190, improving the surface affinity, and improving the bottom bonding force of the conductive bump 190.

[0057] The conductive bump 190 includes a conductive metal pillar 191 and a solder cap 193. The conductive metal pillar 191 is disposed on the side of the metal layer 170 away from the chip substrate 110, and a convex portion is provided at the bottom of the conductive metal. The convex portion extends into the opening 151 and is connected to the metal layer 170. The solder cap 193 is disposed on the top of the conductive metal pillar 191. Specifically, the conductive metal pillar 191 is a copper pillar, and the conductive metal pillar 191 is formed by electroplating a copper layer. The solder cap 193 is used to directly contact the solder pad on the substrate, so as to achieve fixation and electrical connection. The solder of the solder cap 193 can be tin, and a tin ball is formed at the top end of the conductive metal pillar 191.

[0058] It should be noted that after the wetting layer 177 is formed, due to the depression effect of the opening 151, the metal layer 170 is locally depressed downward. At this time, the electroplating process is used again to electroplate copper in the depression formed at the opening 151 and form copper pillars. Then, the plasma descumming machine (Descum) is used again to clean the excess photoresist, forming a structure with copper pillars. Here, a single photoresist layer is used to simultaneously achieve the sputtering of the metal layer 170 and the formation of electroplated copper pillars, greatly reducing the process flow (conventional process flows require separate electroplating of the metal layer 170 and several photolithography processes for the copper pillars). The plasma descumming machine (Descum) is used again to remove the excess photoresist, forming a structure with copper pillars.

[0059] In this embodiment, a stop layer 195 is further provided between the conductive metal pillar 191 and the solder cap 193. The stop layer 195 is used to block the diffusion atoms between the solder cap 193 and the conductive metal pillar 191. Specifically, after the conductive metal pillar 191 is formed, a photoresist / protective film (photoresist) is coated on the surface of the chip substrate 110 again. Then, the photolithography process (exposure / development / baking) is used again to open a slot to expose the copper pillar and form a notch. Then, the electroplating process is used again to electroplate a layer of conductive metal or alloy, such as at least one of nickel and vanadium, in the notch. Again, through printing or evaporation, the solder cap 193 is formed on the notch. The solder cap 193 can be tin. Here, the stop layer 195 is used to prevent the tin atoms on the top solder ball from diffusing to the copper pillar.

[0060] It should be noted that after the solder cap 193 is formed here, the structure with the photoresist layer is refluxed again. After the solder forms solder balls, the plasma descumming machine (Descum) is used again to remove the excess photoresist, forming a structure of copper pillars with solder balls, completing the final structure. By refluxing the structure with the photoresist layer, problems such as the diffusion of the solder to the sidewalls of the copper pillars after solder reflux can be avoided.

[0061] In summary, this embodiment provides a bump packaging structure 100. A metal layer 170 is disposed on a side of a solder pad 130 away from a chip substrate 110, and a conductive bump 190 is disposed on the metal layer 170. The metal layer 170 includes an adhesive layer 171, a conductive layer 173, a barrier layer 175, and a wetting layer 177. By providing the adhesive layer 171 and forming a notch 172 in the adhesive layer 171, the conductive layer 173 extends into the notch 172 and contacts the solder pad 130, thereby increasing the bonding area, further increasing the bonding strength of the metal layer 170 at the bottom of the conductive bump 190, ensuring firm bonding of the copper pillar bump, and preventing the copper pillar bump from falling off. At the same time, electrical connection is achieved by additionally providing the conductive layer 173, avoiding direct contact between the conductive bump 190 and the chip electrode, avoiding the problem of electrode cracking, and the contact structure between the conductive layer 173 and the solder pad 130 is a segmented contact structure. Compared with directly disposing the conductive layer 173 on the solder pad 130, the present invention reduces the contact area between the conductive layer 173 and the solder pad 130, thereby weakening the electromigration phenomenon, improving the electrical performance of the metal layer 170, and extending the service life of the conductive bump 190. In addition, by additionally providing the wetting layer 177, the bottom bonding strength of the conductive bump 190 can be further improved, further ensuring firm bonding of the copper pillar bump and preventing the copper pillar bump from falling off.

[0062] Second Embodiment

[0063] See Figure 3 and Figure 4 This embodiment provides a bump packaging structure 100. Its basic structure, principle, and the resulting technical effects are the same as those of the first embodiment. For a brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding content in the first embodiment.

[0064] The bump packaging structure 100 provided in this embodiment includes a chip substrate 110, a solder pad 130, a protective layer 150, a metal layer 170, and a conductive bump 190. The solder pad 130 is disposed on one side of the chip substrate 110, the protective layer 150 is disposed on one side of the chip substrate 110, and an opening 151 corresponding to the solder pad 130 is provided on the protective layer 150 to expose the solder pad 130 to the protective layer 150. The metal layer 170 is disposed on a side of the solder pad 130 away from the chip substrate 110 and extends from the opening 151 to the surface of the protective layer 150. The conductive bump 190 is disposed on a side of the metal layer 170 away from the chip substrate 110.

[0065] The metal layer 170 includes an adhesive layer 171, a conductive layer 173, a barrier layer 175, and a wetting layer 177. The adhesive layer 171 is disposed on the side of the solder pad 130 away from the chip substrate 110. The conductive layer 173 is disposed on the side of the adhesive layer 171 away from the chip substrate 110. A plurality of notches 172 penetrating through to the solder pad 130 are provided on the adhesive layer 171. The conductive layer 173 extends to the notches 172 and contacts the solder pad 130. The conductive bump 190 is electrically connected to the conductive layer 173. The barrier layer 175 is disposed on the side of the conductive layer 173 away from the chip substrate 110, and the barrier layer 175 is located between the conductive layer 173 and the conductive bump 190. The wetting layer 177 is disposed on the side of the barrier layer 175 away from the chip substrate 110, and the wetting layer 177 is located between the barrier layer 175 and the conductive bump 190 to transition and wet the conductive bump 190.

[0066] In this embodiment, a plurality of bonding blocks 179 are further provided in the barrier layer 175. The plurality of bonding blocks 179 all penetrate through the barrier layer 175 and are respectively in contact with the conductive layer 173 and the wetting layer 177. Specifically, each bonding block 179 is embedded in the barrier layer 175, and its upper and lower side surfaces are respectively in contact with the wetting layer 177 and the conductive layer 173. The bonding block 179 can be made of the same material as the adhesive layer 171, that is, formed of titanium, which improves the bonding force between the barrier layer 175 and the wetting layer 177, and improves the overall reliability of the metal layer 170 to prevent the conductive bump 190 from falling off.

[0067] In this embodiment, in the horizontal direction, the plurality of bonding blocks 179 are arranged in one-to-one correspondence with the plurality of notches 172, and the width of each bonding block 179 is the same as the width of the notch 172. Specifically, the conductive layer 173 is provided between the bonding block 179 and the adhesive layer 171. Here, the bonding block 179 and the adhesive layer 171 adopt an interleaved design, which can further improve the overall reliability of the metal layer 170 and prevent the conductive bump 190 from falling off.

[0068] It should be noted that the bonding block 179 can also extend to the side wall and the top of the barrier layer 175, so as to further improve the bonding force between the wetting layer 177 and the barrier layer 175 at the side wall and the top, and then improve the structural stability of the overall packaging structure and prevent the conductive bump 190 from falling off.

[0069] In the bump packaging structure 100 provided in this embodiment, by providing the bonding block 179 in the barrier layer 175, the bonding force between the barrier layer 175 and the wetting layer 177 is improved, and the overall reliability of the metal layer 170 is improved to prevent the conductive bump 190 from falling off.

[0070] Third Embodiment

[0071] See Figure 5, this embodiment provides a method for manufacturing a bump encapsulation structure for manufacturing the bump encapsulation structure 100 provided in the first embodiment or the second embodiment.

[0072] The method for manufacturing the bump structure provided in this embodiment includes the following steps:

[0073] S1: Form a solder pad 130 on one side of the chip substrate 110.

[0074] Referring to Figure 6 , specifically, a solder pad 130 is pre-formed on the surface of the chip substrate 110, and the solder pad 130 can be formed by electroplating. Of course, a chip substrate 110 with a solder pad 130 can also be directly provided here.

[0075] S2: Form a protective layer 150 on one side of the chip substrate 110.

[0076] Referring to Figure 7 , while forming the protective layer 150, an opening 151 corresponding to the solder pad 130 is opened on the protective layer 150, and the width of the opening 151 is smaller than that of the solder pad 130, so that the protective layer 150 can partially cover the solder pad 130. Specifically, the solder pad 130 in this embodiment is an aluminum pad, and at the same time, the protective layer 150 can be made of a polymer dielectric material, such as epoxy, polyimide benzocyclobutene, etc. When forming the protective layer 150, the protective layer 150 can use a coater to uniformly coat the polymer dielectric material on the chip substrate 110 by selective coating, and then be soft-baked and shaped into a film through a hot plate, and through an exposure machine, its function is to use a mask to cover the position of the predetermined opening of the protective layer 150 by the proximity method without exposing it to light, and then through the development method, use a developer to spray to remove the unexposed area to expose the position of the opening 151 corresponding to the solder pad 130, and then use an oven to heat the protective layer 150 to accelerate curing to a completely cured and stable state, and then use a plasma descum machine to remove organic pollutants on the surface of the protective layer 150 or residues in the opening 151 to complete the process of exposing the solder pad 130.

[0077] S3: Form a metal layer 170 on the side of the solder pad 130 away from the chip substrate 110.

[0078] Referring to Figures 8 to 10, in this embodiment, the metal layer 170 extends from the opening 151 to the surface of the protective layer 150. The metal layer 170 includes an adhesive layer 171, a conductive layer 173, a barrier layer 175, and a wetting layer 177 formed by electroplating in sequence. The adhesive layer 171 is disposed on the side of the solder pad 130 away from the chip substrate 110, and the conductive layer 173 is disposed on the side of the adhesive layer 171 away from the chip substrate 110. A plurality of notches 172 penetrating through to the solder pad 130 are provided on the adhesive layer 171. The conductive layer 173 extends to the notches 172 and is in contact with the solder pad 130. The conductive bumps 190 are electrically connected to the conductive layer 173.

[0079] When forming the opening 151, it is necessary to electroplate the adhesive layer 171. The adhesive layer 171 is preferably a titanium layer (Ti), and the titanium layer has extremely high metal bonding performance. Specifically, after the opening 151 on the solder pad 130 is completed, a photoresist is coated on the surface of the chip substrate 110, and the opening 151 and the positions of the preset notches 172 are exposed. Then, using the electroplating process, a titanium layer is electroplated in the opening 151. Specifically, the surrounding area can be covered with photoresist, so that there is no need for an etching process to etch away the excess metal, avoiding the problem of over-etching. Then, a plasma asher is used to remove the excess photoresist, exposing the solder pad 130 and the adhesive layer 171.

[0080] It should be noted that here the adhesive layer 171 with notches 172 is directly formed by electroplating the titanium layer, avoiding the conventional method of first preparing the adhesive layer 171 and then etching to form the notches 172.

[0081] Preferably, after coating a photoresist / protective glue (photoresist) on the surface of the chip substrate 110, the photoresist columns at the opening 151 of the aluminum pad and the preset notches 172 are exposed again using the photolithography process (exposure / development / baking). Then, using the electroplating process again, a titanium layer is electroplated in the opening 151. The titanium layer has extremely high metal bonding performance. By covering the surrounding area with photoresist, there is no need for an etching process to etch away the excess metal, avoiding the over-etching problem. Then, a plasma asher (Descum) is used again to remove the excess photoresist columns, thus exposing the solder pad 130 and completing the preparation of the adhesive layer 171.

[0082] After the preparation of the adhesive layer 171 is completed, the copper layer is electroplated in the opening 151 again by using the electroplating process to form the conductive layer 173. The copper layer has good electrical conductivity, and the copper layer fills the notch 172 on the adhesive layer 171. The copper layer on the aluminum pad is separated into multiple copper layer blocks, so as to reduce the contact area between the copper layer and the solder pad 130, reduce electromigration, and improve the performance of the metal layer 170 at the bottom of the conductive bump 190. Then, a conductive metal layer is electroplated again to form the barrier layer 175. The material of the barrier layer 175 can be nickel, vanadium, chromium, etc. Then, a copper layer is electroplated again as the wetting layer 177, and the wetting layer 177 is used to transition and wet the barrier layer 175 and the upper copper pillar prepared subsequently, and improve the bonding property of the electroplated copper pillar.

[0083] S4: Form a conductive bump 190 on the side of the metal layer 170 away from the chip substrate 110.

[0084] Specifically, with reference to Figures 10 to 12 , the conductive bump 190 includes a conductive metal pillar 191 and a solder cap 193. After step S2, the copper is electroplated in the opening 151 again by using the electroplating process to form a copper pillar. Then, the plasma descum machine is used again to remove the excess photoresist to form a structure with a copper pillar. By using a single photoresist layer, the sputtering of the metal layer 170 and the formation of the electroplated copper pillar are realized simultaneously, greatly reducing the process flow (the conventional process flow requires separate electroplating of the metal layer 170 and several photolithography processes for the copper pillar). The plasma descum machine is used again to remove the excess photoresist to form a structure with a copper pillar.

[0085] After the copper pillar is formed, the photoresist / protective glue (photoresist) is coated on the surface of the chip substrate 110 again. Then, the photolithography process (exposure / development / baking) is used again to open a slot to expose the copper pillar and form a notch. Then, the electroplating process is used again to electroplate a conductive metal or alloy in the notch, such as at least one of nickel and vanadium. Again, the solder cap 193 is formed on the notch by printing or evaporation. The solder cap 193 can be tin. Here, the stop layer 195 is used to prevent the tin atoms on the top solder ball from diffusing to the copper pillar.

[0086] After the solder cap 193 is formed, the structure with the photoresist layer is reflowed again. After the solder wire forms a solder ball, the plasma descum machine is used again to remove the excess photoresist to form a structure with a solder ball on the copper pillar, completing the final structure. By reflowing the structure with the photoresist layer, problems such as the diffusion of the solder after reflow to the side wall of the copper pillar can be avoided.

[0087] The preparation method of the bump packaging structure provided by the present invention is to set a metal layer 170 on the side of the solder pad 130 away from the chip substrate 110, and set conductive bumps 190 on the metal layer 170. The metal layer 170 includes an adhesive layer 171 and a conductive layer 173. The adhesive layer 171 is set on the side of the solder pad 130 away from the chip substrate 110, and the conductive layer 173 is set on the side of the adhesive layer 171 away from the chip substrate 110. A plurality of notches 172 penetrating through to the solder pad 130 are provided on the adhesive layer 171. The conductive layer 173 extends to the notches 172 and contacts the solder pad 130. The conductive bumps 190 are electrically connected to the conductive layer 173. By setting the adhesive layer 171 and opening the notches 172 on the adhesive layer 171, the conductive layer 173 extends into the notches 172 and contacts the solder pad 130, thereby increasing the bonding area, and further increasing the bonding strength of the metal layer 170 at the bottom of the conductive bumps 190, which can ensure the firm bonding of the copper pillar bumps and avoid the detachment of the copper pillar bumps. At the same time, the electrical connection is realized by additionally setting the conductive layer 173, which avoids the direct contact between the conductive bumps 190 and the chip electrodes and avoids the problem of electrode cracking. And the contact structure between the conductive layer 173 and the solder pad 130 is a segmented contact structure. Compared with directly setting the conductive layer 173 on the solder pad 130, the present invention reduces the contact area between the conductive layer 173 and the solder pad 130, thereby weakening the electromigration phenomenon, improving the electrical performance of the metal layer 170, and improving the service life of the conductive bumps 190.

[0088] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claimed rights.

Claims

1. A bump packaging structure, characterized in that, Comprising: A chip substrate; Bonding pads disposed on one side of the chip substrate; A protective layer disposed on one side of the chip substrate, with openings corresponding to the bonding pads formed on the protective layer to expose the bonding pads to the protective layer; A metal layer disposed on the side of the bonding pad away from the chip substrate and extending from the opening to the surface of the protective layer; Conductive bumps disposed on the side of the metal layer away from the chip substrate; Wherein, the metal layer includes an adhesive layer and a conductive layer. The adhesive layer is disposed on the side of the bonding pad away from the chip substrate, and the conductive layer is disposed on the side of the adhesive layer away from the chip substrate. A plurality of notches penetrating through to the bonding pads are formed on the adhesive layer. The conductive layer extends into the notches and is in contact with the bonding pads. The conductive bumps are electrically connected to the conductive layer; Wherein, the width of the conductive bumps is greater than the width of the openings.

2. The bump encapsulation structure according to claim 1, wherein, The metal layer further includes a barrier layer, which is disposed on the side of the conductive layer away from the chip substrate and is located between the conductive layer and the conductive bumps.

3. The bump encapsulation structure according to claim 2, wherein, The metal layer further includes a wetting layer, which is disposed on the side of the barrier layer away from the chip substrate and is located between the barrier layer and the conductive bumps to wet the conductive bumps in a transitional manner.

4. The bump encapsulation structure according to claim 3, wherein, A plurality of bonding blocks are further disposed in the barrier layer. The plurality of bonding blocks penetrate through the barrier layer and are respectively in contact with the conductive layer and the wetting layer.

5. The bump encapsulation structure according to claim 4, wherein The plurality of bonding blocks are arranged in one-to-one correspondence with the plurality of notches, and the width of each bonding block is the same as the width of the notch.

6. The bump encapsulation structure according to any one of claims 1-5, characterized in that, The conductive bumps include conductive metal columns and solder caps. The conductive metal columns are disposed on the side of the metal layer away from the chip substrate, and convex portions are provided at the bottoms of the conductive metals. The convex portions extend into the openings and are connected to the metal layer. The solder caps are disposed on the tops of the conductive metal columns.

7. The bump encapsulation structure according to claim 6, wherein A stop layer is further disposed between the conductive metal columns and the solder caps to block diffusion atoms between the solder caps and the conductive metal columns.

8. The bump encapsulation structure according to any one of claims 1-5, characterized in that, The two side walls of the opening are inclined relative to the bonding pad, and the width of the opening gradually increases in the direction away from the bonding pad.

9. The bump encapsulation structure according to any one of claims 1-5, characterized in that, The width of the bonding pad is greater than the width of the opening, so that the protective layer partially covers the bonding pad.

10. A method for preparing a bump encapsulation structure, characterized in that, For manufacturing the bump packaging structure according to any one of claims 1-9, the method includes: Forming bonding pads on one side of the chip substrate; Forming a protective layer on one side of the chip substrate and forming openings corresponding to the bonding pads on the protective layer. The width of the openings is smaller than that of the bonding pads, so that the protective layer partially covers the bonding pads; Forming a metal layer on the side of the bonding pad away from the chip substrate, and the metal layer extends from the opening to the surface of the protective layer; Forming conductive bumps on the side of the metal layer away from the chip substrate; Among them, the metal layer includes an adhesive layer and a conductive layer. The adhesive layer is disposed on a side of the bonding pad away from the chip substrate, the conductive layer is disposed on a side of the adhesive layer away from the chip substrate, a plurality of notches penetrating through to the bonding pad are provided on the adhesive layer, the conductive layer extends to the notches and is in contact with the bonding pad, and the conductive bump is electrically connected to the conductive layer.

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