Method for high-density assembly of storage chip by using modular integrated packaging technology

Abstract

The invention relates to the technical field of storage chip packaging, and discloses a high-density assembly method for a storage chip by using a modular integrated packaging technology, which comprises the following steps of: obtaining a storage chip to be assembled and a packaging element, performing high-precision scanning to obtain geometrical shape data, and constructing an assembly model; the method comprises the following steps: defining an assembly constraint for a chip to obtain an assembly relationship, searching a preferred path, constructing and segmenting an assembly space, and adjusting the path through a collision test to obtain a target assembly path. And querying path parameters to construct assembly equipment parameters, and completing parameter configuration through dynamic simulation to obtain target assembly equipment. A chip and an element are sent to a station to obtain a pre-assembled part, pose deviation is adjusted to obtain a target assembled part, and a target device and a path are used for packaging to obtain a preliminarily packaged chip. And through an electrical performance test, if the chip is normal, packaging enhancement processing is carried out, quality classification is carried out after nondestructive testing, then integrated packaging is carried out, and finally a target packaging chip is obtained. According to the invention, the high-density assembly quality of the storage chip can be improved.

Description

Technical Field

[0001] The present invention relates to a high - density assembly method for storage chips using modular integrated packaging technology, belonging to the technical field of storage chip packaging. Background Art

[0002] Storage chips play a core supporting role in modern electronic devices. Their high - density assembly method is the key to whether storage chips can achieve a larger storage capacity and better performance in a limited space. The application of modular integrated packaging technology in the high - density assembly process of storage chips is of great significance. It can integrate and package multiple storage chip modules according to specific rules and methods, enabling storage chips to accommodate more storage units per unit area or volume, thereby improving the overall storage density and data read - write efficiency of storage chips. At the same time, it also helps to optimize the heat dissipation performance of the chips, reduce signal interference, etc., and has a positive impact on improving the applicability of storage chips in various high - performance electronic devices.

[0003] Currently, for the high - density assembly of storage chips, traditional assembly processes are generally adopted. Through manual or semi - automated means, according to the pre - set circuit layout and connection methods, storage chips and related components are assembled and fixed one by one. However, using this method, in the face of large - scale storage chip assembly requirements and the continuous pursuit of higher - density assembly, due to the increased connection complexity between components, cumbersome assembly steps, and the lack of a systematic integration mechanism, problems such as inaccurate component alignment and unstable circuit connection are likely to occur during the assembly process, resulting in an unsatisfactory high - density assembly effect of storage chips and being difficult to meet the high - quality requirements of current electronic devices for storage chips. Summary of the Invention

[0004] The present invention provides a high - density assembly method and system for storage chips using modular integrated packaging technology, and its main purpose is to improve the high - density assembly quality of storage chips.

[0005] To achieve the above object, a high - density assembly method for storage chips using modular integrated packaging technology provided by the present invention includes: Obtain the storage chips to be assembled and packaging components, perform high - precision scanning on the storage chips to be assembled and the packaging components to obtain corresponding geometric shape data, and based on the geometric shape data, construct an assembly model of the storage chips to be assembled; Define assembly constraints for the storage chip to be assembled to obtain an assembly relationship. Based on the assembly relationship, search for an optimal assembly path for the storage chip to be assembled. Based on the optimal assembly path, construct an assembly space for the storage chip to be assembled. Divide the assembly space to obtain multiple small regional spaces. Conduct an assembly collision test on the storage chip to be assembled in the small regional spaces. Based on the test results of the assembly collision test, adjust the path of the optimal assembly path to obtain an adjusted path. Conduct a path test on the adjusted path. When the test result of the path test is excellent, obtain a target assembly path; Query the assembly path parameters of the target assembly path to construct the assembly equipment parameters of the assembly equipment corresponding to the storage chip to be assembled. Based on the assembly equipment parameters, conduct a dynamic simulation on the assembly equipment. Based on the dynamic simulation results, configure the assembly parameters of the assembly equipment to obtain a target assembly equipment; Input the storage chip to be assembled and the packaging components into the assembly station to obtain pre-assembled parts. Calculate the pose deviation of the pre-assembled parts. Based on the pose deviation, adjust the pose of the pre-assembled parts to obtain target assembled parts. According to the target assembly equipment, use the target assembly path to perform chip packaging on the target assembled parts to obtain a preliminary packaged chip; Conduct an electrical performance test on the preliminary packaged chip. When the test result of the electrical performance test is normal, perform a packaging enhancement process on the preliminary packaged chip to obtain a preliminarily processed chip. Conduct a non-destructive test on the preliminarily processed chip. Based on the test results of the non-destructive test, classify the quality of the preliminarily processed chip to obtain a quality classified chip. Perform an integrated packaging on the quality classified chip to obtain a target packaged chip.

[0006] Optionally, the defining assembly constraints for the storage chip to be assembled to obtain an assembly relationship includes: Identify the component features and interface functions of the storage chip to be assembled; Based on the component features, perform component fitting constraints and component alignment constraints on the storage chip to be assembled to obtain a position constraint relationship; Based on the interface functions, perform electrical connection constraints and mechanical connection constraints on the storage chip to be assembled to obtain a link constraint relationship; Query the component structure of the storage chip to be assembled; Based on the component structure, construct the assembly sequence constraints of the storage chip to be assembled; Based on the position constraint relationship, the link constraint relationship, and the assembly sequence constraints, define assembly constraints for the storage chip to be assembled to obtain an assembly relationship.

[0007] Optionally, searching for an optimal assembly path of the storage chip to be assembled based on the assembly relationship includes: Constructing an initial assembly path of the storage chip to be assembled; Using the assembly relationship to screen the initial assembly path to obtain a screened path; Performing pheromone search on the screened path to obtain search pheromone; Updating the search pheromone using the following formula to obtain updated pheromone: where PM represents the updated pheromone, e represents the attenuation coefficient of the search pheromone, represents the concentration of the search pheromone from path i to path j at time t, represents the newly added pheromone concentration, and T represents the time when the search pheromone starts to search; Based on the updated pheromone, calculating the probability value of each path in the screened path being selected, and selecting the assembly path of the storage chip to be assembled based on the probability value to obtain an optimal assembly path.

[0008] Optionally, calculating the probability value of each path in the screened path being selected based on the updated pheromone includes: Querying the pheromone concentration of the updated pheromone; Based on the pheromone concentration, calculating the probability value of each path in the screened path being selected using the following formula: where p represents the probability value, represents the pheromone concentration, represents the pheromone importance factor, represents the heuristic information importance factor, represents the set of the next paths that can be selected at the current node k, represents the heuristic information, that is, the attraction from node k to node j, represents the comprehensive attraction of the path from node k to node j.

[0009] Optionally, performing an assembly collision test on the storage chip to be assembled in the small area space includes: Querying the size information of the small area space to construct an accurate test space for the storage chip to be assembled; Constructing a collision detection rule for the storage chip to be assembled; Querying the optimal assembly path of the storage chip to be assembled to perform assembly simulation on the storage chip to be assembled; During the assembly simulation process, collision detection is performed on the storage chip to be assembled by using the collision detection rules; After the detection result of the collision detection is evaluated, an assembly collision test on the storage chip to be assembled is realized.

[0010] Optionally, the dynamic simulation of the assembly device based on the assembly device parameters includes: Construct a physical model of the assembly device; In the physical model, after defining the motion constraint relationship between the components of the assembly device, an external load and a driving force are applied to the physical model to obtain a preliminary setting model; Set the time range, time step and integration algorithm of the preliminary setting model to obtain a target dynamic model; Use the target dynamic model to perform dynamic simulation on the assembly device.

[0011] Optionally, the calculation of the pose deviation of the pre-assembled part includes: Set a high-precision three-dimensional coordinate system in the assembly station corresponding to the pre-assembled part; Use the preset assembly requirements and the target assembly path to construct the preferred position and preferred attitude parameters of the pre-assembled part; Perform visual positioning on the pre-assembled part to obtain positioning parameters; Use the preferred position and the preferred attitude parameters to construct the preferred coordinates of the pre-assembled part in the three-dimensional coordinate system; Use the positioning parameters to construct the real-time coordinates of the pre-assembled part in the three-dimensional coordinate system; Based on the preferred coordinates and the real-time coordinates, calculate the pose deviation of the pre-assembled part.

[0012] Optionally, according to the target assembly device, using the target assembly path to perform chip packaging on the target assembly part to obtain a preliminary packaged chip, includes: Perform device initialization on the target assembly device to obtain an initialized device; Load the target assembly path into the initialized device to obtain a ready device; Perform surface treatment and pre-linking on the target assembly part to obtain a ready assembly part; Use the ready device to package the ready assembly part to obtain a preliminary packaged chip.

[0013] Optionally, the non-destructive detection of the preliminary processed chip includes: Collect the X-ray image of the preliminary processed chip; Perform image enhancement on the X-ray image to obtain an enhanced image; Use an edge detection algorithm to perform edge detection on the enhanced image to identify the surface defect contour of the preliminary processing chip; Analyze the quantitative features of the surface defect contour to perform surface flaw detection on the preliminary processing chip; Use the enhanced image to identify the circuit wiring features of the preliminary processing chip; After detecting the circuit integrity of the preliminary processing chip using the circuit wiring features, complete the non-destructive testing of the preliminary processing chip.

[0014] Optionally, the integration and packaging of the quality classification chip to obtain a target packaged chip includes: Configure the packaging platform of the quality classification chip; Perform packaging deployment on the target packaged chip in the packaging platform to obtain a deployed chip; Perform material coating on the deployed chip to obtain a coated chip; Perform glue dispensing on the coated chip to obtain a glue-dispensed chip; Perform shell injection molding on the glue-dispensed chip to obtain a target packaged chip.

[0015] To solve the above problems, the present invention also provides a modular integrated packaging technology for a high-density assembly system of storage chips. The system includes: An assembly model construction module, configured to obtain storage chips to be assembled and packaging components, perform high-precision scanning on the storage chips to be assembled and the packaging components to obtain corresponding geometric shape data, and construct an assembly model of the storage chips to be assembled based on the geometric shape data; A path testing module, configured to define assembly constraints for the storage chips to be assembled to obtain an assembly relationship, search for an optimal assembly path of the storage chips to be assembled based on the assembly relationship, construct an assembly space of the storage chips to be assembled based on the optimal assembly path, divide the assembly space into multiple small regional spaces, perform an assembly collision test on the storage chips to be assembled in the small regional spaces, adjust the optimal assembly path based on the test results of the assembly collision test to obtain an adjusted path, perform a path test on the adjusted path, and obtain a target assembly path when the test results of the path test are excellent; The device parameter configuration module is used to query the assembly path parameters of the target assembly path to construct the assembly device parameters of the assembly device corresponding to the storage chip to be assembled. Based on the assembly device parameters, kinetic simulation is performed on the assembly device. Based on the kinetic simulation results, assembly parameter configuration is performed on the assembly device to obtain the target assembly device; The chip preliminary packaging module is used to input the storage chip to be assembled and the packaging components into the assembly station to obtain pre-assembled parts, calculate the pose deviation of the pre-assembled parts, perform pose adjustment on the pre-assembled parts based on the pose deviation to obtain the target assembled parts, and use the target assembly path to perform chip packaging on the target assembled parts according to the target assembly device to obtain the preliminarily packaged chip; The chip integrated packaging module is used to perform electrical performance testing on the preliminarily packaged chip. When the electrical performance test result is normal, perform packaging enhancement processing on the preliminarily packaged chip to obtain the preliminarily processed chip, perform non-destructive testing on the preliminarily processed chip, classify the quality of the preliminarily processed chip based on the detection results of the non-destructive testing to obtain the quality classified chip, and perform integrated packaging on the quality classified chip to obtain the target packaged chip.

[0016] Compared with the problems described in the background art, by performing high-precision scanning on the storage chips and packaging components to be assembled, obtaining accurate geometric shape data, and constructing an assembly model, it is possible to evaluate the assembly scheme in advance in a virtual environment, avoid errors caused by unreasonable spatial layouts, infeasible connection methods, etc. in actual production, thereby significantly improving the assembly accuracy. And by defining the assembly constraints and establishing the assembly relationships, the relative positions, directions, and mating requirements between the storage chips and the packaging components are clarified, further ensuring the accuracy of the assembly and ensuring that the final product meets the design requirements. Also, through the assembly collision test, it can be checked whether the storage chips and the packaging components will collide or interfere with each other in a small-area space under the predetermined preferred assembly path, discover and solve in advance the interference problems that may lead to assembly failures, and reduce the error risk during the assembly process. Further, in the embodiments of the present invention, by constructing the assembly equipment parameters according to the assembly path parameters of the target assembly path and performing dynamic simulation on the assembly equipment, the equipment performance can be evaluated and optimized before actual manufacturing or debugging of the equipment, avoiding equipment failures and quality problems, reducing production costs and risks. And by configuring the assembly parameters according to the results of the dynamic simulation to obtain the target assembly equipment, it is ensured that the finally put-into-use equipment can efficiently, stably, and accurately complete the storage chip assembly task. Further, in the embodiments of the present invention, by inputting the storage chips and packaging components to be assembled into the assembly station to obtain pre-assembled parts, calculating and adjusting the pose deviation to obtain the target assembled parts, the pre-assembled parts can be made close to the ideal state and meet the high-precision requirements of chip packaging. Using the target assembly equipment and the target assembly path to perform chip packaging on the target assembled parts to obtain a preliminary packaged chip ensures the orderliness and high quality of the chip packaging. Even further, in the embodiments of the present invention, by performing electrical performance tests on the preliminary packaged chips, it can be ensured that the electrical performance of the packaged chips meets the design requirements and enables them to work properly. And through the packaging enhancement process, the firmness and protection ability of the packaging can be enhanced, the service life of the chip can be extended, and its stability and durability in different application scenarios can be enhanced. Further, by performing non-destructive testing on the packaged chips, microscopic defects inside the packaging and component position offsets can be discovered, and quality classification can be performed according to the test results to ensure that only chips meeting the quality requirements enter the integrated packaging process, improving the resource utilization efficiency, providing chips of different quality grades for different users or application scenarios. And by performing integrated packaging on the quality-classified chips to obtain the target packaged chips, the final packaging is completed. And by integrating multiple functional modules, the functionality and applicability of the chip are improved, providing high-quality core components for electronic product production, thereby improving the high-density assembly quality of the storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. is a schematic flow chart of a method for high-density assembly of a modular integrated packaging technology for storage chips provided by an embodiment of the present invention; Figure 2This is a module schematic diagram of the high-density assembly method for implementing the modular integrated packaging technology for storage chips provided by an embodiment of the present invention.

[0018] The implementation, functional features, and advantages of the present invention will be further described in conjunction with embodiments and with reference to the accompanying drawings. Detailed implementation manners

[0019] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] An embodiment of the present application provides a high-density assembly method for a modular integrated packaging technology for storage chips. The execution subject of the high-density assembly method for the modular integrated packaging technology for storage chips includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the high-density assembly method for the modular integrated packaging technology for storage chips can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0021] Embodiment 1: Refer to Figure 1 As shown, it is a flowchart of a high-density assembly method for a modular integrated packaging technology for storage chips provided by an embodiment of the present invention. In this embodiment, the high-density assembly method for the modular integrated packaging technology for storage chips includes: S1. Obtain the storage chip to be assembled and packaging components, perform high-precision scanning on the storage chip to be assembled and the packaging components to obtain corresponding geometric shape data, and based on the geometric shape data, construct an assembly model of the storage chip to be assembled.

[0022] In the embodiment of the present invention, obtaining the storage chip to be assembled and packaging components can prepare entity objects for subsequent assembly processes.

[0023] Among them, the storage chip to be assembled refers to a bare die of a storage chip that has not yet been packaged. It is the core component for storing data and has the basic functions of data storage and reading / writing. However, it is relatively fragile in the unpackaged state and needs to be packaged and protected to work stably in various electronic devices. For example, common NAND flash chips, DRAM chips, etc. After the chip manufacturing process is completed, they are storage chips to be assembled at this time, waiting for further packaging. The packaging components refer to various parts used for packaging the storage chip. These components provide physical protection, electrical connection, and heat dissipation functions for the storage chip.

[0024] Furthermore, in the embodiments of the present invention, by performing high-precision scanning on the storage chip to be assembled and the packaging component to obtain corresponding geometric shape data, the actual shape and size of the components can be understood, providing a reliable basis for constructing an accurate assembly model.

[0025] Optionally, the geometric shape data can be obtained by using a high-precision three-dimensional laser scanner. Place the storage chip to be assembled and the packaging component within its scanning range, then use the scanner to emit laser beams onto the surface of the object. Based on the laser reflection time and angle, accurately measure the spatial positions of each point on the surface of the object, collect the point data to form a point cloud, and then convert the point cloud data into accurate geometric shape data through an algorithm, thereby obtaining the three-dimensional geometric shape information of the storage chip to be assembled and the packaging component.

[0026] Furthermore, in the embodiments of the present invention, by constructing the assembly model of the storage chip to be assembled based on the geometric shape data, different assembly schemes can be evaluated in a virtual environment, and potential problems such as unreasonable spatial layout and infeasible connection methods can be discovered in advance, thereby avoiding errors in actual production, saving time and costs, and improving the efficiency and quality of product research and development and production.

[0027] Among them, the assembly model refers to a virtual representation of the storage chip and its packaging components. It is created based on accurate geometric shape data and can be constructed through three-dimensional laser scanning technology. By irradiating the storage chip to be assembled and the packaging component with laser beams, and measuring the time difference between the emission and reflection of the laser beams, as well as the angle of the laser, the three-dimensional coordinates of each point on the surface of the object are calculated, generating a large amount of point cloud data to form the assembly model.

[0028] S2. Define assembly constraints for the storage chip to be assembled to obtain an assembly relationship. Based on the assembly relationship, search for the preferred assembly path of the storage chip to be assembled. Based on the preferred assembly path, construct the assembly space of the storage chip to be assembled. Divide the assembly space to obtain multiple small regional spaces. Conduct an assembly collision test on the storage chip to be assembled in the small regional spaces. Based on the test results of the assembly collision test, adjust the path of the preferred assembly path to obtain an adjusted path. Conduct a path test on the adjusted path. When the test result of the path test is excellent, obtain the target assembly path.

[0029] In the embodiments of the present invention, by defining assembly constraints for the storage chip to be assembled to obtain an assembly relationship, the relative positions, directions, and mating requirements between the storage chip and other packaging components during assembly can be clarified, thereby improving the assembly accuracy and reliability and making the final product meet the design requirements.

[0030] As an embodiment of the present invention, the definition of the assembly constraints for the storage chip to be assembled to obtain the assembly relationship includes: identifying the component features and interface functions of the storage chip to be assembled, performing component fitting constraints and component alignment constraints on the storage chip to be assembled based on the component features to obtain the position constraint relationship, performing electrical connection constraints and mechanical connection constraints on the storage chip to be assembled based on the interface functions to obtain the link constraint relationship, querying the component structure of the storage chip to be assembled, and constructing the assembly sequence constraints of the storage chip to be assembled based on the component structure. The assembly constraints of the storage chip to be assembled are defined based on the position constraint relationship, the link constraint relationship, and the assembly sequence constraints to obtain the assembly relationship.

[0031] Optionally, the component features can be identified by checking the product manuals, design drawings of the storage chip and the packaged components, and using high-precision measurement tools to accurately measure the dimensions, shapes, number of pins, and pin pitches of the components; the interface functions can be determined by querying the functional pins (such as data, power, and control pins) of the storage chip and their functions. The obtaining of the position constraint relationship by performing component fitting constraints and component alignment constraints on the storage chip to be assembled based on the component features can be achieved by importing the models of the storage chip and the packaged components into 3D modeling or assembly planning software, and then for the component fitting constraints, setting the coincidence relationship such as the bottom surface of the storage chip and the upper surface of the substrate; for the component alignment constraints, the alignment relationship between the edge of the storage chip and the specific marks or lines on the substrate can be set to obtain an accurate position constraint relationship. The electrical connection constraints can be obtained by associating the pins of the storage chip and the corresponding pads on the substrate in 3D software and setting the electrical conduction requirements and electrical performance parameters. The mechanical connection constraints can be set by determining the connection method between the heat sink and the storage chip and specifying the connection position, connection firmness, etc. The assembly sequence constraints can be determined by analyzing the structures of the storage chip and its packaged components and, according to the difficulty and logical sequence of assembly, determining which component to assemble first and which component to assemble later in the assembly planning software. For example, first fix the chip on the substrate and then set up the pin connections.

[0032] Furthermore, in the embodiment of the present invention, by searching for the preferred assembly path of the storage chip to be assembled based on the assembly relationship, the assembly constraints of the components can be transformed into operable assembly steps, turning the abstract assembly relationship into a specific assembly action sequence, providing guidance for the operation of the automated assembly equipment.

[0033] As an embodiment of the present invention, searching for an optimal assembly path of the to-be-assembled memory chip based on the assembly relationship includes: constructing an initial assembly path of the to-be-assembled memory chip, using the assembly relationship to perform path screening on the initial assembly path to obtain a screened path, performing pheromone search on the screened path to obtain search pheromone, and updating the search pheromone using the following formula to obtain updated pheromone: where PM represents the updated pheromone, e represents the attenuation coefficient of the search pheromone, represents the concentration of the search pheromone from path i to path j at time t, represents the newly added pheromone concentration, and T represents the time when the search pheromone starts to search; Based on the updated pheromone, calculate the probability value of each path in the screened path being selected, and based on the probability value, select the assembly path of the to-be-assembled memory chip to obtain an optimal assembly path.

[0034] Among them, the search pheromone refers to an information index used to guide the search process in the pheromone search algorithm.

[0035] Optionally, the initial assembly path can be formed by connecting the assembly sequences of each component through analyzing the structure of the chip and the conventional logic of the assembly sequence. For example, for a chip with multiple memory cells and connection modules, it may be constructed in the order of first assembling the core memory cells and then connecting the peripheral circuit modules. The screened path can be obtained by screening the initial assembly path according to the assembly relationship of the memory chip, such as constraints such as physical connection requirements, electrical connection rules, and space limitations between components, removing those assembly steps or connection methods that do not conform to the assembly relationship, and only retaining the paths that meet all assembly conditions. For example, if the installation position of a certain component must be after another component, then the assembly paths that do not conform to this sequence will be excluded. The pheromone search for the screened path to obtain the search pheromone can be implemented using the ant colony algorithm.

[0036] Further, as an optional embodiment of the present invention, calculating the probability value of each path in the screened path being selected based on the updated pheromone includes: querying the pheromone concentration of the updated pheromone, and based on the pheromone concentration, calculating the probability value of each path in the screened path being selected using the following formula: where p represents the probability value, represents the pheromone concentration, represents the importance factor of the pheromone, represents the importance factor of the heuristic information, represents the set of next paths that can be selected at the current node k, represents heuristic information, that is, the attraction from node k to node j, represents the comprehensive attraction of the path from node k to node j.

[0037] Among them, the pheromone concentration refers to a quantitative index used to represent the attraction or priority of different paths or decision options in the pheromone algorithm (such as the ant colony algorithm).

[0038] In the embodiment of the present invention, by constructing the assembly space of the to-be-assembled memory chip based on the assembly preferred path, the assembly path can be visualized and quantified in space, expanding the assembly process from a planar and linear operation step to a three-dimensional operation scenario with a spatial range, providing a spatial basis for subsequent segmentation and collision testing.

[0039] Among them, the assembly space refers to a three-dimensional space area planned for completing the chip assembly operation when assembling the to-be-assembled memory chip, comprehensively considering factors such as the physical size, shape, installation position, connection requirements, operation range of operation tools, and accessibility of personnel or robot arms according to the assembly preferred path.

[0040] Optionally, the assembly space can be constructed by parsing the assembly preferred path, determining the physical space requirements of components, then planning the layout of the assembly space, considering the operation space and tool requirements, and finally verifying through simulation.

[0041] In the embodiment of the present invention, by dividing the assembly space into multiple small regional spaces, it is convenient to manage and inspect each small region separately, making the subsequent collision testing more accurate and efficient.

[0042] Furthermore, in the embodiment of the present invention, by performing an assembly collision test on the to-be-assembled memory chip in the small regional space, it can be checked whether collisions or interferences will occur during the assembly process of the memory chip and the packaging components in each small regional space under the predetermined assembly preferred path, thereby discovering and solving in advance the interference problems that may lead to assembly failures.

[0043] As an embodiment of the present invention, the assembly collision test of the storage chip to be assembled in the small area space includes: querying the dimension information of the small area space to construct an accurate test space for the storage chip to be assembled, constructing a collision detection rule for the storage chip to be assembled, querying the preferred assembly path of the storage chip to be assembled to perform assembly simulation on the storage chip to be assembled, and using the collision detection rule during the assembly simulation to perform collision detection on the storage chip to be assembled. After evaluating the detection results of the collision detection, the assembly collision test of the storage chip to be assembled is realized.

[0044] Among them, the collision detection rule refers to a series of judgment criteria and principles formulated to ensure that there is no physical collision or mutual interference between components during the assembly process and between components and the boundary of the test space when performing an assembly collision test on the storage chip to be assembled.

[0045] Optionally, the accurate test space can obtain the dimension information such as the length, width, height and shape of the small area space through measuring tools or stored design documents, and then create it in computer-aided design (CAD) software or simulation tools using these dimension data. The collision detection rule can be obtained by determining the safety distance standard between different components, defining which component parts cannot overlap or contact, and considering the physical characteristics of the components and the assembly operation, and setting collision rules such as between wires and components, chips and chips, etc. The result evaluation of the collision detection can be realized by analyzing the collision detection results and finding out the positions where collisions occur and the components involved.

[0046] According to the test results of the assembly collision test in the embodiment of the present invention, the preferred assembly path is adjusted, and the obtained adjusted path can modify and optimize the original preferred assembly path according to the problems found in the collision test, so as to improve the feasibility and safety of the assembly path and ensure the smooth progress of the actual assembly process.

[0047] Optionally, the process of adjusting the preferred assembly path based on the test results of the assembly collision test to obtain an adjusted path is as follows: First, analyze the results of the assembly collision test to find out the assembly steps that cause collisions and the position information of the components involved; then, according to this information, modify the assembly order, position or direction of the corresponding components in the preferred assembly path; finally, regenerate an adjusted path that avoids collisions, which can be achieved by adjusting the order of component assembly or changing its position in the assembly space.

[0048] In the embodiment of the present invention, by performing a path test on the adjustment path, when the test result of the path test is excellent, the target assembly path can be obtained, which can ensure the smooth progress of the actual production process and provide a reliable basis for subsequent equipment parameter configuration and actual assembly operations.

[0049] It should be explained that when the test result of the path test is excellent, it means that there is no collision or the degree of collision is within an acceptable range when the storage chip to be assembled is simulated for assembly. Specifically, it needs to be set in combination with the actual application. For example, the number of collisions is less than a fixed number, or when there is a collision, the physical offset caused to the storage chip to be assembled is within a preset range.

[0050] S3. Query the assembly path parameters of the target assembly path to construct the assembly equipment parameters of the assembly equipment corresponding to the storage chip to be assembled. Based on the assembly equipment parameters, perform a dynamic simulation on the assembly equipment. Based on the dynamic simulation result, configure the assembly parameters of the assembly equipment to obtain the target assembly equipment.

[0051] In the embodiment of the present invention, by querying the assembly path parameters of the target assembly path to construct the assembly equipment parameters of the assembly equipment corresponding to the storage chip to be assembled, the requirements of the assembly path can be mapped to the assembly equipment, ensuring that the performance of the equipment matches the assembly task.

[0052] Among them, the assembly path parameters refer to a series of quantitative data describing the movement and operation details of the storage chip and packaging components during the assembly process, such as position coordinates, movement sequence parameters, movement speed, and time parameters, etc.

[0053] Optionally, the assembly equipment parameters can be obtained by using the software module of the storage chip assembly system to extract various data of the target assembly path, including parameter information such as position, speed, acceleration, and movement sequence; then, based on the extracted assembly path parameters, combined with the size, weight, and assembly process requirements of the storage chip, using algorithms or rule libraries, convert them into performance parameters required by the assembly equipment (such as robotic arms, conveyor devices, etc.), such as the working range of the robotic arm, the movement speed range, and the load capacity.

[0054] Furthermore, in the embodiment of the present invention, by performing a dynamic simulation on the assembly equipment based on the assembly equipment parameters, the equipment performance can be evaluated and optimized before actual manufacturing or debugging of the equipment, avoiding serious equipment failures or quality problems in actual production, and reducing production costs and risks.

[0055] As an embodiment of the present invention, the dynamic simulation of the assembly equipment based on the assembly equipment parameters includes: constructing a physical model of the assembly equipment. In the physical model, after defining the motion constraint relationships between the components of the assembly equipment, external loads and driving forces are applied to the physical model to obtain a preliminary setup model. The time range, time step size, and integration algorithm of the preliminary setup model are set to obtain a target dynamic model. The target dynamic model is used to perform dynamic simulation on the assembly equipment.

[0056] Among them, the external load refers to the forces acting on the equipment and its operating elements other than the driving force of the equipment itself during the process of assembling storage chips by the assembly equipment. The driving force refers to the force or torque that causes the assembly equipment to move according to a predetermined assembly path and motion requirements, and it is the active power source for the equipment to work normally. The time range refers to the time period from the set start time to the end time of the simulation during the dynamic simulation process, and this time period covers the entire or part of the working process of the assembly equipment. The time step size refers to the step size of dividing the time range into multiple discrete time intervals during the dynamic simulation process. The integration algorithm refers to the mathematical method used by the dynamic simulation software to solve the dynamic equation, such as the Euler method.

[0057] Optionally, the physical model can be created by professional 3D modeling software (such as SolidWorks, etc.). The motion constraint relationships can be set by operating on the connection parts of the physical model in the interface of the dynamic simulation software. For a rotary joint, set its rotational degrees of freedom and angle range; for a translational joint, specify the translational direction and stroke range. For example, in a robotic arm model, define the rotation type (such as pitch, yaw, etc.) and the allowable rotation angle interval of each joint to define it. The external load can be added to the model according to the actual force conditions during the assembly process for the preliminary setup model. For example, for a robotic arm, consider the component gravity as a load and apply it to the end effector; for a conveyor belt, consider the component weight and friction as loads and apply them to the conveyor belt. At the same time, determine the magnitude and direction of the driving force according to the assembly equipment parameters. For example, add motor torque at the robotic arm joints and add motor rotational torque at the conveyor belt rollers to obtain it.

[0058] Furthermore, in the embodiment of the present invention, by configuring the assembly parameters of the assembly equipment based on the dynamic simulation results, the target assembly equipment obtained can ensure that the assembly equipment finally put into use can efficiently, stably, and accurately complete the assembly task of storage chips.

[0059] Optionally, the target assembly equipment can be obtained by inputting the motion parameters during the simulated operation of the assembly equipment into the equipment and setting it up.

[0060] S4. Input the to-be-assembled memory chip and the packaging component into an assembly station to obtain a pre-assembled part, calculate the pose deviation of the pre-assembled part, perform pose adjustment on the pre-assembled part based on the pose deviation to obtain a target assembled part, and according to the target assembly equipment, use the target assembly path to perform chip packaging on the target assembled part to obtain a preliminary packaged chip.

[0061] In the embodiment of the present invention, by inputting the to-be-assembled memory chip and the packaging component into the assembly station to obtain a pre-assembled part, the physical location of the assembly work can be clarified, ensuring that all required components can be concentrated in a convenient operation space, laying a foundation for carrying out the assembly operation orderly and efficiently, which is a necessary prerequisite for realizing the packaging of the memory chip.

[0062] Optionally, the process of inputting the to-be-assembled memory chip and the packaging component into the assembly station to obtain a pre-assembled part is as follows: Use an automated guided vehicle (AGV) or a conveyor belt system to transport the to-be-assembled memory chip and the packaging component from a warehouse or a station of the previous process to a designated assembly station, and then in the assembly station, through a vision recognition system or a mechanical positioning device, place the memory chip and the packaging component at a predetermined position.

[0063] In the embodiment of the present invention, by calculating the pose deviation of the pre-assembled part, the difference between the current actual position and pose of the pre-assembled part (i.e., the combination of the to-be-assembled memory chip and the packaging component) and the position and pose in the ideal state can be determined, so as to facilitate position adjustment.

[0064] As an embodiment of the present invention, calculating the pose deviation of the pre-assembled part includes: setting a high-precision three-dimensional coordinate system in the assembly station corresponding to the pre-assembled part, constructing the preferred position and preferred pose parameters of the pre-assembled part by using the preset assembly requirements and the target assembly path, performing vision positioning on the pre-assembled part to obtain positioning parameters, constructing the preferred coordinates of the pre-assembled part in the three-dimensional coordinate system by using the preferred position and the preferred pose parameters, constructing the real-time coordinates of the pre-assembled part in the three-dimensional coordinate system by using the positioning parameters, and calculating the pose deviation of the pre-assembled part based on the preferred coordinates and the real-time coordinates.

[0065] Optionally, the three-dimensional coordinate system can be obtained by selecting a fixed position of the assembly station as the origin, such as the center of the robotic arm base or a corner of the assembly platform, and then using a laser measurement and calibration tool to accurately determine the directions and unit lengths of the x, y, and z axes to ensure that it meets the required accuracy requirements, such as using high-precision linear guides and angle measuring instruments to accurately calibrate and mark the x, y, and z axes. The preferred position can store the design specifications of the chip and packaging components and the target assembly path information, and determine, for example, the coordinates of the chip center and pin positions in three-dimensional space; the preferred attitude parameters can determine the required attitude parameters of the parts according to the assembly process requirements, such as the angular relationship between the plane of the storage chip and the coordinate axes, obtained through theoretical calculations or extracted from the virtual assembly model. The positioning parameters can be obtained by using a vision sensor to perform visual positioning on the pre-assembled parts and then extracting the parameters generated by the positioning. The preferred coordinates can be obtained by representing the preset ideal position and attitude information in the established three-dimensional coordinate system to obtain information such as the coordinates and rotation angles of the pre-assembled parts on the x, y, and z axes in the ideal state. The real-time coordinates can be obtained by accurately expressing the positioning parameters obtained by visual positioning, that is, the converted actual physical position information, in the same three-dimensional coordinate system. The pose deviation can be obtained by subtracting the coordinate values of the preferred coordinates and the real-time coordinates on the x, y, and z axes respectively.

[0066] In an embodiment of the present invention, by performing pose adjustment on the pre-assembled parts based on the pose deviation, the target assembled parts can correct the position and pose of the pre-assembled parts to make them as close as possible to the ideal state to meet the high-precision requirements of chip packaging.

[0067] Optionally, the process of performing pose adjustment on the pre-assembled parts based on the pose deviation to obtain the target assembled parts is as follows: Use precise motion control equipment (such as a high-precision multi-axis robotic arm or an electric translation stage), and determine the displacement and rotation amounts that need to be adjusted according to the calculated pose deviation information. For example, if the pose deviation shows that the pre-assembled parts are offset by a certain distance in the x-axis direction, control the robotic arm or translation stage to move accordingly in the x-axis direction; for the attitude deviation, control the joint angles of the robotic arm to perform rotational adjustment to achieve.

[0068] In an embodiment of the present invention, by using the target assembly equipment according to the target assembly path to perform chip packaging on the target assembled parts, the preliminary packaged chip can perform actual packaging operations on the target assembled parts after pose adjustment, and combine the storage chip and the packaging components together in a predetermined manner to form a preliminarily packaged chip.

[0069] As an embodiment of the present invention, the target assembly device encapsulates the target assembly parts using the target assembly path to obtain a preliminary encapsulated chip, including: initializing the device of the target assembly device to obtain an initialized device, loading the target assembly path into the initialized device to obtain a ready device, performing surface treatment and pre-linking on the target assembly parts to obtain ready assembly parts, and encapsulating the ready assembly parts using the ready device to obtain a preliminary encapsulated chip.

[0070] Optionally, the initialized device can be obtained by starting the target assembly device, including turning on the power supply, checking whether the hardware connection of the device is normal, and then performing self-checks on each subsystem of the device, such as checking the joint movement range of the robotic arm, checking the functions of the heating element and the welding head of the welding device, calibrating the sensor, etc., to ensure that the device is in a normal operable state. The ready device is obtained by inputting the target assembly path information (including parameters such as movement trajectory, action sequence, speed, acceleration, etc.) required for chip assembly into the device through the control system of the device. The ready assembly parts can be obtained by performing surface treatment on the target assembly parts, such as cleaning the surfaces of the memory chip and the packaging components to remove contaminants and oxides that may affect the packaging quality, and then performing a pre-linking operation to preliminarily align and fix the memory chip and the substrate, and temporary fixing jigs or adhesives can be used to ensure that they do not shift during the subsequent packaging process.

[0071] S5. Perform electrical performance tests on the preliminary encapsulated chip. When the results of the electrical performance tests are normal, perform encapsulation enhancement processing on the preliminary encapsulated chip to obtain a preliminarily processed chip, perform non-destructive testing on the preliminarily processed chip, classify the quality of the preliminarily processed chip based on the test results of the non-destructive testing to obtain a quality-classified chip, and perform integrated packaging on the quality-classified chip to obtain a target encapsulated chip.

[0072] Through the electrical performance tests on the preliminary encapsulated chip in the embodiment of the present invention, it can be ensured that the electrical performance of the encapsulated chip meets the design requirements and can work normally.

[0073] Optionally, the process of performing electrical performance tests on the preliminary encapsulated chip is as follows: Prepare test equipment such as a semiconductor parameter analyzer and an oscilloscope and calibrate them. Install the preliminary encapsulated chip in a test socket and connect the test probes to the corresponding pins. Perform tests such as conductivity, I-V characteristics, signal transmission, and power supply performance, analyze the data and compare it with the specifications, and judge whether the electrical performance is qualified.

[0074] In the embodiment of the present invention, when the electrical performance test result is normal, the preliminary packaged chip is subjected to packaging enhancement treatment to obtain a preliminarily processed chip, which can enhance the firmness and protection ability of the packaging, prevent the influence of the external environment (such as moisture, dust, mechanical vibration, etc.) on the internal circuit of the chip, extend the service life of the chip, enhance the stability and durability of the chip in different application scenarios, and ensure that the chip will not fail due to packaging damage during subsequent use and storage.

[0075] Among them, "when the electrical performance test result is normal" means that after the electrical performance test, all electrical indexes of the preliminary packaged chip meet the established design standards and quality requirements. Specifically, it includes no short circuit or open circuit between pins, normal I-V characteristic curve, qualified signal transmission parameters, power supply performance within the specified range, etc.

[0076] Optionally, the preliminarily processed chip can be realized by hot pressing and curing the preliminary packaged chip.

[0077] In the embodiment of the present invention, by performing non-destructive testing on the preliminarily processed chip, it is possible to detect microscopic defects such as voids, delamination, and cracks that are invisible to the naked eye inside the package, and at the same time observe whether the positions of the internal components of the chip are shifted.

[0078] As an implementation of the present invention, the non-destructive testing of the preliminarily processed chip includes: collecting the X-ray image of the preliminarily processed chip, performing image enhancement on the X-ray image to obtain an enhanced image, using an edge detection algorithm to perform edge detection on the enhanced image to identify the surface defect contour of the preliminarily processed chip, analyzing the quantitative characteristics of the surface defect contour to perform surface flaw detection on the preliminarily processed chip, using the enhanced image to identify the circuit wiring characteristics of the preliminarily processed chip, and after detecting the circuit integrity of the preliminarily processed chip using the circuit wiring characteristics, completing the non-destructive testing of the preliminarily processed chip.

[0079] Optionally, the X-ray image can be acquired using a high-precision X-ray imaging device. The enhanced image can be obtained by importing the acquired X-ray image into image processing software. By adjusting basic parameters such as contrast and brightness to highlight image details. Filtering techniques can also be employed, such as median filtering to remove noise, making the image clearer. The surface defect contour can be obtained by using a suitable edge detection algorithm, such as the Canny edge detection algorithm, setting algorithm parameters such as thresholds, and processing the enhanced image to identify regions with drastic gray level changes in the image, which may be the edges of chip surface defects, thereby outlining the surface defect contour. The process of analyzing the quantitative features of the surface defect contour to detect the surface flaw degree of the preliminarily processed chip is as follows: measuring quantitative features such as the length, area, and shape of the surface defect contour. By comparing with pre-set standard flaw features or calculating the flaw degree level using a mathematical model to determine whether the chip surface flaws are within an acceptable range and evaluate the surface quality. The circuit wiring features can be obtained by using an image recognition algorithm to distinguish features such as the path and connection points of the circuit wiring in the enhanced image.

[0080] Furthermore, in the embodiment of the present invention, by performing quality classification on the preliminarily processed chip based on the detection results of the non-destructive testing, the quality classification chip obtained can perform different processes on the chip according to different quality levels, ensuring that only chips meeting the quality requirements will enter the final integrated packaging process, improving resource utilization efficiency, reducing costs, and at the same time providing chip selections with different quality levels for different users or different application scenarios.

[0081] Optionally, the process of performing quality classification on the preliminarily processed chip based on the detection results of the non-destructive testing to obtain the quality classification chip is as follows: First, set different quality standards according to the surface flaw degree and circuit integrity of the chip in the non-destructive testing results; then, compare the detection results with these standards, classify chips without obvious flaws and with complete circuits as high-quality products, those with certain problems but not affecting the main functions as second-class products, and those with serious defects as defective products; finally, make corresponding marks on the chips to complete the quality classification.

[0082] Even further, in the embodiment of the present invention, by performing integrated packaging on the quality classification chip, the target packaging chip obtained can complete the final packaging process of the chip, integrate multiple functional modules together, facilitate user use, improve the functionality and applicability of the chip, meet the integration requirements of different systems, and finally form a complete target packaging chip, providing high-quality core components for the production of electronic products.

[0083] As an embodiment of the present invention, integrating and packaging the quality classification chip to obtain a target packaged chip includes: configuring a packaging platform for the quality classification chip, performing packaging deployment on the target packaged chip in the packaging platform to obtain a deployed chip, coating the deployed chip with a material to obtain a coated chip, dispensing glue on the coated chip to obtain a glue-dispensed chip, and injecting a housing for the glue-dispensed chip to obtain the target packaged chip.

[0084] Optionally, the packaging platform can be obtained by debugging and calibrating equipment such as a packaging mold, a glue dispenser, a chip mounter, a wire bonder, and a soldering device. The deployed chip can be obtained by placing the selected chips in a packaging mold or on a substrate according to a predetermined layout and design, then precisely mounting the chips to the designated positions using a chip mounter, and then bonding the pins or pads of the chips to external circuits or pins using a wire bonder. Coating the deployed chip with a material can be performed using a spin coater, dispensing glue on the coated chip can be implemented using a glue dispenser, and injecting a housing for the glue-dispensed chip can be operated using an injection molding machine.

[0085] Embodiment 2: As Figure 2 shown, it is a functional module diagram of a high-density assembly system for a storage chip using a modular integrated packaging technology of the present invention.

[0086] The high-density assembly system 200 for a storage chip using the modular integrated packaging technology of the present invention can be installed in an electronic device. According to the functions achieved, the high-density assembly system for a storage chip using the modular integrated packaging technology can include an assembly model construction module 201, a path testing module 202, a device parameter configuration module 203, a chip preliminary packaging module 204, and a chip integrated packaging module 205. The modules of the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0087] In the embodiments of the present invention, the functions of each module / unit are as follows: The assembly model construction module 201 is used to obtain the storage chips to be assembled and packaging components, perform high-precision scanning on the storage chips to be assembled and the packaging components to obtain corresponding geometric shape data, and construct an assembly model of the storage chips to be assembled based on the geometric shape data; The path testing module 202 is used to define assembly constraints for the to-be-assembled memory chip to obtain an assembly relationship. Based on the assembly relationship, search for an optimal assembly path for the to-be-assembled memory chip. Based on the optimal assembly path, construct an assembly space for the to-be-assembled memory chip, divide the assembly space to obtain multiple small regional spaces, perform an assembly collision test on the to-be-assembled memory chip in the small regional spaces, adjust the assembly path based on the test results of the assembly collision test to obtain an adjusted path, perform a path test on the adjusted path, and obtain a target assembly path when the test results of the path test are excellent. The device parameter configuration module 203 is used to query the assembly path parameters of the target assembly path to construct the assembly device parameters of the assembly device corresponding to the to-be-assembled memory chip. Based on the assembly device parameters, perform a dynamic simulation on the assembly device, and configure the assembly parameters of the assembly device based on the dynamic simulation results to obtain a target assembly device. The chip preliminary packaging module 204 is used to input the to-be-assembled memory chip and the packaging components to an assembly station to obtain pre-assembled parts, calculate the pose deviation of the pre-assembled parts, adjust the pose of the pre-assembled parts based on the pose deviation to obtain target assembled parts, and perform chip packaging on the target assembled parts using the target assembly path according to the target assembly device to obtain a preliminarily packaged chip. The chip integrated packaging module 205 is used to perform an electrical performance test on the preliminarily packaged chip. When the electrical performance test results are normal, perform a packaging enhancement process on the preliminarily packaged chip to obtain a preliminarily processed chip, perform a non-destructive test on the preliminarily processed chip, classify the quality of the preliminarily processed chip based on the test results of the non-destructive test to obtain a quality classified chip, and perform integrated packaging on the quality classified chip to obtain a target packaged chip.

[0088] Specifically, in the embodiment of the present invention, the modular integrated packaging technology used in each module of the high-density assembly system 200 for memory chips adopts the same technical means as those Figure 1 described in the modular integrated packaging technology for the high-density assembly method of memory chips, and can produce the same technical effects, which will not be elaborated here.

[0089] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high-density assembly method for memory chips using modular integrated packaging technology, characterized in that: The method comprises: Acquire a memory chip to be assembled and a packaging component, perform high-precision scanning on the memory chip to be assembled and the packaging component to acquire corresponding geometric shape data, and construct an assembly model of the memory chip to be assembled based on the geometric shape data; Defining assembly constraints on the memory chip to be assembled to obtain an assembly relationship, searching for an assembly preferred path for the memory chip to be assembled based on the assembly relationship, constructing an assembly space for the memory chip to be assembled based on the assembly preferred path, dividing the assembly space to obtain a plurality of small area spaces, performing an assembly collision test on the memory chip to be assembled in the small area spaces, adjusting the preferred assembly path based on a test result of the assembly collision test to obtain an adjusted path, performing a path test on the adjusted path, and obtaining a target assembly path when the test result of the path test is excellent; Querying the assembly path parameters of the target assembly path to construct assembly equipment parameters of the assembly equipment corresponding to the memory chip to be assembled, performing dynamic simulation on the assembly equipment based on the assembly equipment parameters, and configuring assembly parameters of the assembly equipment based on the dynamic simulation results to obtain the target assembly equipment; Input the memory chip to be assembled and the packaging component to an assembly station to obtain a pre-assembled part, calculate the posture deviation of the pre-assembled part, adjust the posture of the pre-assembled part based on the posture deviation to obtain a target assembly part, and perform chip packaging on the target assembly part using the target assembly path according to the target assembly equipment to obtain a preliminary packaged chip; Perform an electrical performance test on the preliminary packaged chip, and when the electrical performance test result is normal, perform packaging enhancement processing on the preliminary packaged chip to obtain a preliminary processed chip, perform non-destructive testing on the preliminary processed chip, and perform quality classification on the preliminary processed chip based on the test result of the non-destructive testing to obtain a quality classified chip, and perform integrated packaging on the quality classified chip to obtain a target packaged chip.

2. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The step of defining assembly constraints on the memory chip to be assembled to obtain an assembly relationship includes: Identifying component features and interface functions of the memory chip to be assembled; Based on the component features, the memory chip to be assembled is subjected to component fitting constraints and component constraints on itself to obtain a position constraint relationship; Based on the interface function, electrical connection constraints and mechanical connection constraints are performed on the memory chip to be assembled to obtain a link constraint relationship; Querying the component structure of the memory chip to be assembled; Based on the component structure, constructing assembly sequence constraints of the memory chip to be assembled; Based on the position constraint relationship, the link constraint relationship and the assembly order constraint, assembly constraints are defined for the storage chip to be assembled to obtain an assembly relationship.

3. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The step of searching for an optimal assembly path for the memory chip to be assembled based on the assembly relationship includes: Constructing an initial assembly path of the memory chip to be assembled; Using the assembly relationship, performing path screening on the initial assembly path to obtain a screening path; Performing a pheromone search on the screening path to obtain a search pheromone; The search pheromone is updated using the following formula to obtain the updated pheromone: Among them, PM represents the update pheromone, e represents the attenuation coefficient of the search pheromone, represents the search pheromone concentration from path i to path j at time t, represents the newly added pheromone concentration, and T represents the time when the search for pheromones begins; Based on the update pheromone, the probability value of each path in the screening path being selected is calculated, and based on the probability value, an assembly path of the memory chip to be assembled is selected to obtain an assembly preferred path.

4. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 3, characterized in that: The step of calculating the probability value of each path in the screening path being selected based on the updated pheromone comprises: querying the pheromone concentration of the updated pheromone; Based on the pheromone concentration, the probability value of each path in the screening path being selected is calculated using the following formula: Among them, p represents the probability value, represents the pheromone concentration, represents the pheromone importance factor, represents the heuristic information importance factor, represents the set of next paths that can be selected at the current node k, represents the heuristic information, that is, the attraction from node k to node j, Represents the comprehensive attractiveness of the path from node k to node j.

5. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The step of performing an assembly collision test on the memory chip to be assembled in the small area space comprises: Querying the size information of the small area space to construct an accurate test space for the memory chip to be assembled; Constructing collision detection rules for the memory chip to be assembled; querying the preferred assembly path of the memory chip to be assembled to perform assembly simulation on the memory chip to be assembled; During the assembly simulation process, the collision detection rule is used to perform collision detection on the memory chip to be assembled; After evaluating the detection result of the collision detection, an assembly collision test of the memory chip to be assembled is performed.

6. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The performing dynamic simulation on the assembly equipment based on the assembly equipment parameters comprises: constructing a physical model of the assembly device; In the physical model, after defining the motion constraint relationship between the components of the assembly equipment, external loads and driving forces are applied to the physical model to obtain a preliminary setting model; Setting the time range, time step and integration algorithm of the preliminary setting model to obtain a target dynamic model; The target dynamic model is used to perform dynamic simulation on the assembly equipment.

7. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The calculating the position and posture deviation of the pre-assembled parts comprises: Setting a high-precision three-dimensional coordinate system in the assembly station corresponding to the pre-assembled parts; Using the preset assembly requirements and the target assembly path, constructing the preferred position and preferred posture parameters of the pre-assembled parts; Performing visual positioning on the pre-assembled parts to obtain positioning parameters; constructing the preferred coordinates of the preassembled part in the three-dimensional coordinate system using the preferred position and the preferred posture parameters; constructing real-time coordinates of the preassembled parts in the three-dimensional coordinate system using the positioning parameters; Based on the preferred coordinates and the real-time coordinates, the position and posture deviation of the pre-assembled part is calculated.

8. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The step of packaging the target assembly parts into chips using the target assembly path according to the target assembly equipment to obtain preliminary packaged chips includes: Initializing the target assembly device to obtain an initialized device; Loading the target assembly path into the initialization device to obtain a prepared device; Performing surface treatment and pre-linking on the target assembly parts to obtain prepared assembly parts; The prepared assembly parts are packaged using the prepared equipment to obtain preliminary packaged chips.

9. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The performing nondestructive testing on the preliminary processing chip comprises: Acquiring an X-ray image of the preliminary processing chip; Performing image enhancement on the X-ray image to obtain an enhanced image; Performing edge detection on the enhanced image using an edge detection algorithm to identify the surface defect contour of the preliminarily processed chip; Analyzing the quantitative characteristics of the surface defect profile to perform surface flaw detection on the preliminarily processed chip; using the enhanced image to identify circuit wiring features of the preliminary processing chip; After the circuit integrity of the preliminary processing chip is detected by using the circuit wiring characteristics, the non-destructive detection of the preliminary processing chip is completed.

10. The high-density assembly method for memory chips using modular integrated packaging technology as claimed in claim 1, characterized in that: The step of integrating and packaging the quality classification chips to obtain target packaged chips includes: Configuring a packaging platform for the quality classification chip; Performing packaging and deployment on the target packaged chip in the packaging platform to obtain a deployed chip; coating the deployment chip with a material to obtain a coated chip; Dispensing glue on the coated chip to obtain a glue-dispensed chip; The glue-dispensing chip is subjected to shell injection molding to obtain a target packaged chip.

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