Electronic packaging, manufacturing method thereof and conductive structure

Abstract

The present invention relates to an electronic package, a manufacturing method thereof, and a conductive structure. The electronic package includes a first substrate configured with a first conductive structure and a second substrate configured with a second conductive structure. The first conductive structure has a first conductive layer, a bump body, and a metal auxiliary layer formed in sequence on the first substrate, and the second conductive structure has a metal column, a second conductive layer, a metal layer, and a solder layer formed in sequence on the second substrate. The solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, through the design of the bump body and the metal auxiliary layer, the IMC can be fully reacted after the solder layer is reflowed, so that the volume of the conductive structures will not continue to shrink, thereby effectively avoiding the problem of the conductive structures being fragmented.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, in particular to an electronic packaging component and its manufacturing method and conductive structure. Background Art

[0002] Flip-chip technology, with its advantages of reducing chip packaging area and shortening signal transmission paths, is now widely used in the chip packaging field. Examples include chip scale packages (CSP), direct chip attach packages (DCA), and multi-chip modules (MCM), as well as chip stacking technologies that integrate chips into three-dimensional integrated circuits (3D ICs).

[0003] During the flip-chip packaging process, the significant difference in the coefficient of thermal expansion (CTE) between the chip and the package substrate prevents the bumps on the chip's periphery from forming a good bond with the corresponding contacts on the package substrate, causing the bumps to easily peel off the package substrate. Furthermore, as the density of integrated circuits increases, the mismatch in CTE between the chip and the package substrate leads to increasingly severe thermal stress and warpage. This results in a decrease in the reliability of the electrical connection between the chip and the package substrate, potentially causing reliability testing failures.

[0004] To solve the above problems, the industry has developed a process that uses a semiconductor substrate as an interposer. This process adds a silicon interposer between a package substrate and a semiconductor chip, so that the silicon interposer is close to the material of the semiconductor chip to avoid the problem caused by the mismatch of thermal expansion coefficients. Specifically, Figure 1The semiconductor package 1 shown provides a silicon interposer (TSI) 10, which has a die side 10b and a transfer side 10a opposite to each other, and a plurality of conductive through-silicon vias (TSVs) 100 connecting the die side 10b and the transfer side 10a, and a circuit redistribution structure (RDL) 11 on the die side 10b, so that a plurality of electrode pads 60 with small pitches of the semiconductor chip 6 are electrically connected to the circuit redistribution structure 11 via a plurality of solder bumps 61, and then the solder bumps 61 are coated with a primer 62, and the conductive silicon vias 100 are electrically connected to a plurality of solder pads 70 with large pitches of the packaging substrate 7 via a plurality of conductive elements 17 such as solder bumps, and then a packaging glue 8 is formed on the packaging substrate 7 to cover the semiconductor chip 6 and the silicon interposer 10.

[0005] However, between the silicon interposer 10 and the package substrate 7 of the conventional semiconductor package 1, after the conductive elements 17 are reflowed, the solder material has not yet completely reacted to form an intermetallic compound (IMC) and immediately formed the encapsulation colloid 8. At this time, the residual thermal stress generated by the reflow process is concentrated in the conductive elements 17, causing the continuous reaction of the IMC to reduce the volume of the conductive elements 17, thereby generating voids in the conductive elements 17 (IMC reaction is incomplete) and cracking the conductive elements 17 (e.g., cracking). Figure 1 The stress concentration point k) shown in the figure may cause the fracture to extend to the circuits to which it is connected (such as the circuits of the package substrate 7 or the conductive silicon vias 100), thereby reducing the reliability of the semiconductor package 1 and the yield of the product.

[0006] In addition, the same problem may also occur on the solder bump 61 between the semiconductor chip 6 and the circuit redistribution structure 11, causing cracks to appear between the solder bump 61 and the circuit redistribution structure 11, such as Figure 1 The stress concentration point k shown may even cause the fracture to extend to the circuits it is connected to (such as the circuit redistribution structure 11 or the electrode pads 60 of the semiconductor chip 6 ), thereby reducing the reliability of the semiconductor package 1 and the yield of the product.

[0007] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0008] In view of the above-mentioned various defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof and a conductive structure, which can effectively avoid the problem of the conductive structure being broken.

[0009] The conductive structure of the present invention includes: a first conductive layer; a bump body formed on a local surface of the first conductive layer; and a metal auxiliary layer formed on the first conductive layer and / or the bump body.

[0010] In the aforementioned conductive structure, the first conductive layer is a nickel layer.

[0011] In the aforementioned conductive structure, the bump body is a copper bump.

[0012] In the aforementioned conductive structure, the metal auxiliary layer is a gold layer.

[0013] The present invention also provides an electronic package, comprising: a first substrate, which is provided with a plurality of first pads, and allows a plurality of the aforementioned conductive structures to be bonded to the first pads via the first conductive layer; a second substrate, which has a plurality of second pads; and a plurality of second conductive structures, which are formed on the second pads, and the second conductive structures are sequentially formed with metal columns, a second conductive layer, a metal layer and a solder layer on the second pads, so that the solder layer of the second substrate is bonded to the protruding block body of the conductive structure on the first substrate and the metal auxiliary layer, so that the first substrate and the second substrate are stacked.

[0014] In the aforementioned conductive structure, the first pad is a copper pad.

[0015] In the aforementioned electronic package, the metal pillar is a copper pillar.

[0016] In the aforementioned electronic package, the second conductive layer is a nickel layer.

[0017] In the aforementioned electronic package, the metal layer is a copper layer.

[0018] In the aforementioned electronic package, the ratio of the sum of the volume of the bump body and the volume of the metal layer to the volume of the solder layer is 1:1.6-2.1.

[0019] In the aforementioned electronic package, the bump body and the metal layer are not in contact with each other. For example, the distance between the bump body and the metal layer is at most 12 microns.

[0020] The present invention also provides a method for manufacturing an electronic package, comprising: providing the aforementioned electronic package; and reflowing the solder layer so that the solder layer, the bump body and the metal layer form a reinforcing body, so that the reinforcing body, the first conductive layer, the second conductive layer and the metal column form a third conductive structure.

[0021] In the above-mentioned preparation method, the reinforcement comprises a first compound contacting the first conductive layer and a second compound contacting the second conductive layer. For example, the first compound is nickel tetratin, and the second compound is copper pentatin or nickel pentatin.

[0022] The aforementioned manufacturing method further includes forming an insulating layer between the first substrate and the second substrate to cover the third conductive structure.

[0023] As can be seen from the above, in the electronic package, its manufacturing method, and conductive structure of the present invention, the design of the bump body is mainly to provide sufficient copper material for the IMC reaction, and the design of the metal auxiliary layer is to increase the adhesion of the solder layer, causing the solder material to shrink laterally. Therefore, compared with the existing technology, after reflow, the IMC is completely reacted, and the volume of the third conductive structure will not continue to shrink, thereby effectively avoiding the generation of bubbles in the reinforcement body and the fragmentation of the third conductive structure. The reliability of the electronic package and the product yield are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0025] Figures 2A to 2D It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0026] Figure 2D 'for Figure 2D A cross-sectional view of another embodiment of the present invention.

[0027] Figures 3A to 3E for Figure 2A Partial top view of different embodiments.

[0028] Figures 4A to 4C for Figure 2A Partial cross-sectional views of different embodiments.

[0029] Figures 4D to 4E for Figure 2A Partial side views of different embodiments.

[0030] Description of Reference Numerals

[0031] 1 Semiconductor Package

[0032] 10 Silicon interposer

[0033] 10a Transfer side

[0034] 10b Chip side

[0035] 100 Conductive Silicon Vias

[0036] 11 Line Rerouting Structure

[0037] 17 Conductive elements

[0038] 2,2',2” electronic enclosures

[0039] 2a First conductive structure

[0040] 2b Second conductive structure

[0041] 2c Third conductive structure

[0042] 20 Enhanced Body

[0043] 20a First compound

[0044] 20b Second compound

[0045] 21 First substrate

[0046] 210 First pad

[0047] 22 Second substrate

[0048] 220 Second pad

[0049] 22a first conductive layer

[0050] 22b second conductive layer

[0051] 23 bump body

[0052] 24 Metal auxiliary layer

[0053] 25 Metal Pillar

[0054] 26 Metal Layer

[0055] 27 Solder layer

[0056] 28 Insulation layer

[0057] 6 Semiconductor Chips

[0058] 60 electrode pads

[0059] 61 solder bumps

[0060] 62 Primer

[0061] 7 Package substrate

[0062] 70 solder pads

[0063] 8 Encapsulation colloid

[0064] k stress concentration point

[0065] F,F' action direction

[0066] V,V1,V2 volume

[0067] t Separation distance

[0068] D width. DETAILED DESCRIPTION

[0069] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0070] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "first", "second", "upper", and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0071] Figures 2A to 2D It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present invention.

[0072] like Figure 2A As shown, a first substrate 21 and a second substrate 22 are provided. The first substrate 21 has at least a first pad portion 210 , and the second substrate 22 has at least a second pad portion 220 .

[0073] In this embodiment, the first substrate 21 and the second substrate 22 are substrate structures and / or electronic components. For example, the substrate structure is a package substrate having a core layer and a circuit structure, or a coreless circuit structure. The circuit structure forms a circuit layer (not shown) on a dielectric material, such as a fan-out redistribution layer (RDL). The electronic components are active components, passive components, or a combination thereof. The active components are, for example, semiconductor chips, while the passive components are, for example, resistors, capacitors, and inductors. Specifically, the dielectric material is polybenzoxazole (PBO), polyimide (PI), or prepreg (PP), and the electronic component is a semiconductor chip having an active surface and an inactive surface opposite the active surface. The active surface has a plurality of electrode pads (e.g., first pads 210 or second pads 220) electrically connected to the circuit layer of the substrate structure (e.g., first pads 210 or second pads 220) via a plurality of first conductive structures 2a and a plurality of second conductive structures 2b in a flip-chip manner. An under-bump metallurgy (UBM) (not shown) may be formed between the pads and the conductive structures. It should be understood that the substrate structure may also be other carrier units for carrying electronic components such as chips, such as a lead frame or a silicon interposer, and is not limited to the above.

[0074] In addition, in this embodiment, a substrate structure is used as the first substrate 21 and an electronic component is used as the second substrate 22 . However, in other embodiments, any flip-chip stacked substrate can be used without particular limitation.

[0075] In addition, the first conductive structure 2a is formed with a first conductive layer 22a, a bump body 23 and a metal auxiliary layer 24 in sequence on a first pad portion 210 such as a copper pad. The first conductive layer 22a substantially covers the first pad portion 210, and the bump body 23 is only formed on a partial top surface of the first conductive layer 22a. For example, the first conductive layer 22a is a nickel layer, the bump body 23 is a copper bump, and the metal auxiliary layer 24 is a gold layer. Specifically, the shape of the bump body 23 can be adjusted as needed (e.g., Figures 3A to 3E As shown), but it cannot completely cover the top surface of the first conductive layer 22a, and the metal auxiliary layer 24 can be formed on the first conductive layer 22a and / or the bump body 23 as required, as shown Figure 2A As shown, the first conductive layer 22a and the bump 23 are completely covered. Figures 4A to 4E The arrangement shown is not particularly limited.

[0076] Furthermore, the second conductive structure 2b is formed on the second pad portion 220, such as a copper electrode pad, in sequence, comprising a metal pillar 25, a second conductive layer 22b, a metal layer 26, and a solder layer 27. For example, the second conductive layer 22b is a nickel layer, the metal pillar 25 is a copper pillar, and the metal layer 26 is a copper layer. Specifically, the second conductive structure 2b is a bump structure suitable for flip-chip manufacturing, and the solder layer 27 covers the metal layer 26.

[0077] like Figure 2B As shown, a flip chip bonding operation is performed to cover the bump body 23 and the metal auxiliary layer 24 with the solder layer 27 of the second conductive structure 2b to form an electronic package 2".

[0078] In this embodiment, the solder layer 27 contacts the first conductive layer 22 a. For example, the solder layer 27 covers the entire first conductive layer 22 a.

[0079] In addition, the ratio of the sum of the volume V2 of the bump body 23 and the volume V1 of the metal layer 26 to the volume V of the solder layer 27 is 1:1.6-2.1 (if the sum of V2+V1 is 1 unit volume, then V is 1.6 to 2.1 unit volumes). Figure 2A As shown, it is beneficial for the subsequent complete reaction to form an intermetallic compound (IMC).

[0080] In addition, the bump 23 and the metal layer 26 are not in contact with each other. For example, the spacing distance t between the bump 23 and the metal layer 26 is at most 12 micrometers (μm), and after experiments, it is found that the spacing distance t is preferably 5-12 μm.

[0081] like Figure 2C As shown, a flip chip reflow operation is performed to reflow the solder layer 27 so that the solder layer 27 and the bump body 23 and the metal layer 26 therein form a reinforcement body 20, so that the reinforcement body 20, the first conductive layer 22a, the second conductive layer 22b and the metal pillar 25 form a third conductive structure 2c.

[0082] In this embodiment, the reinforcement 20 includes two interfacial metal co-compounds (IMCs), one of which contacts the first compound 20a of the first conductive layer 22a, and the other contacts the second compound 20b of the second conductive layer 22b. For example, the first compound 20a is nickel tetratin (Ni3Sn4), and the second compound 20b is copper pentatin (Cu6Sn5) or nickel pentatin (Ni6Sn5). Specifically, during the reflow of the solder layer 27, the gold material (metal auxiliary layer 24) is expanded (e.g., Figure 2BThe direction of action F) is shown, causing the copper bump (bump body 23) to move laterally (as shown in FIG. Figure 2B The direction of action F) is formed by the reaction of the solder material (solder layer 27) and the lateral contraction (such as Figure 2C The first pad portion 210 of the first substrate 21 and the second pad portion 220 of the second substrate 22 are electrically connected to each other via the third conductive structure 2c.

[0083] In addition, the metal auxiliary layer 24 remains outside the reinforcement body 20 after reflow and is removed with a cleaning solution.

[0084] like Figure 2D As shown, in the subsequent flip-chip packaging operation, an insulating layer 28 may be formed between the first substrate 21 and the second substrate 22 to cover the conductive structure 2 c , thereby completing the manufacture of another electronic package 2 .

[0085] In this embodiment, the insulating layer 28 is formed of a primer, polyimide (PI), dry film, an encapsulant such as epoxy, a molding compound, or other suitable materials. For example, the insulating layer 28 can be formed by methods such as filling, liquid compound, injection, lamination, or compression molding.

[0086] In addition, in other embodiments, the first substrate 21 may be removed according to the requirements of packaging specifications, such as wafer-level packaging or chip-scale packaging (CSP). Figure 2D 'The electronic package shown.

[0087] Therefore, in the manufacturing method of the present invention, the design of the bump body 23 is mainly to provide sufficient copper material for the IMC reaction, and the design of the metal auxiliary layer 24 is to increase the adhesion of the solder layer 27, so that the solder material produces lateral shrinkage (such as Figure 2C Therefore, compared with the prior art, when the insulating layer 28 is subsequently formed, the IMC has completely reacted, so the volume of the third conductive structure 2c will not continue to shrink, thereby effectively avoiding the problems of bubbles (Void) generated in the reinforcement 20 and cracks (Crack) of the third conductive structure 2c, and even the problem of the cracks extending to the circuits to which they are connected (such as the first pad 210 or the second pad 220), thereby effectively improving the reliability of the electronic package 2 and the product yield.

[0088] The present invention provides a first conductive structure 2a, comprising: a first conductive layer 22a formed on a first pad 210, a bump 23 formed only on a partial surface of the first conductive layer 22a, and a metal auxiliary layer 24 formed on the first conductive layer 22a and / or the bump 23.

[0089] In one embodiment, the first pad 210 is a copper pad.

[0090] In one embodiment, the first conductive layer 22a is a nickel layer.

[0091] In one embodiment, the bump body 23 is a copper bump.

[0092] In one embodiment, the metal auxiliary layer 24 is a gold layer.

[0093] The present invention also provides an electronic package 2 ″, comprising: a first substrate 21 having a first conductive structure 2 a, a second substrate 22 having a second pad portion 220 , and a second conductive structure 2 b formed on the second pad portion 220 .

[0094] The first substrate 21 is configured with the first pad portion 210 to combine with the first conductive structure 2 a.

[0095] The second conductive structure 2b is formed with a metal column 25, a second conductive layer 22b, a metal layer 26 and a solder layer 27 in sequence on the second pad 220, so that the solder layer 27 is combined with the bump body 23 of the first conductive structure 2a and the metal auxiliary layer 24, so that the first substrate 21 and the second substrate 22 are stacked.

[0096] In one embodiment, the metal pillar 25 is a copper pillar.

[0097] In one embodiment, the second conductive layer 22b is a nickel layer.

[0098] In one embodiment, the metal layer 26 is a copper layer.

[0099] In one embodiment, the ratio of the sum of the volume V2 of the bump 23 and the volume V1 of the metal layer 26 to the volume V of the solder layer 27 is 1:1.6-2.1.

[0100] In one embodiment, the bump 23 and the metal layer 26 are not in contact with each other. For example, the spacing distance t between the bump 23 and the metal layer 26 is at most 12 micrometers (ie, t≦12).

[0101] In summary, the electronic package and its manufacturing method and the first conductive structure of the present invention, through the design of the bump body and the metal auxiliary layer, are designed so that the IMC is completely reacted after the solder layer is reflowed. Therefore, the volume of the third conductive structure will not continue to shrink, thereby effectively avoiding problems such as the generation of bubbles in the reinforcement and the fragmentation of the third conductive structure. Therefore, the first conductive structure of the present invention can effectively improve the reliability of the electronic package and the product yield.

[0102] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. An electronic package, characterized in that: include: A first substrate is provided with a plurality of first pads; a second substrate having a plurality of second pad portions; a plurality of first conductive structures formed on the first pad portion, wherein the first conductive structure comprises a first conductive layer, a bump body, and a metal auxiliary layer sequentially formed on the first pad portion, the bump body being directly formed on a portion of the top surface of the first conductive layer and not completely covering the top surface of the first conductive layer, and the metal auxiliary layer being formed on the bump body and / or on the first conductive layer exposed from the bump body; and a plurality of second conductive structures formed on the second pad portion, wherein the second conductive structures are sequentially formed with a metal column, a second conductive layer, a metal layer, and a solder layer on the second pad portion, so that the solder layer of the second substrate is combined with the bump body and the metal auxiliary layer of the first conductive structure on the first substrate, thereby stacking the first substrate and the second substrate; The ratio of the sum of the volume of the bump body and the volume of the metal layer to the volume of the solder layer is 1:1.6-2.

1.

2. The electronic package according to claim 1, wherein: The first pad is a copper pad.

3. The electronic package according to claim 1, wherein: The metal pillar is a copper pillar.

4. The electronic package according to claim 1, wherein: The first conductive layer and the second conductive layer are nickel layers.

5. The electronic package according to claim 1, wherein: The metal layer is a copper layer.

6. The electronic package according to claim 1, wherein: The bump body and the metal layer are not in contact with each other.

7. The electronic package according to claim 6, wherein: The distance between the bump body and the metal layer is at most 12 micrometers.

8. A method for manufacturing an electronic package, characterized in that: include: Providing an electronic package according to claim 1; as well as The solder layer is reflowed to form a reinforcement body with the solder layer, the bump body and the metal layer, so that the reinforcement body, the first conductive layer, the second conductive layer and the metal column form a third conductive structure.

9. The method for manufacturing an electronic package according to claim 8, wherein: The reinforcement includes a first compound contacting the first conductive layer and a second compound contacting the second conductive layer.

10. The method for manufacturing an electronic package according to claim 9, wherein: The first compound is nickel tetratin.

11. The method for manufacturing an electronic package according to claim 9, wherein: The second compound is hexacopper pentatin or hexanickel pentatin.

12. The method for manufacturing an electronic package according to claim 8, wherein: The manufacturing method further includes forming an insulating layer between the first substrate and the second substrate to cover the third conductive structure.

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