Printed circuit board and electronic component package comprising the same

Abstract

The present disclosure provides a printed circuit board and an electronic package including the same. The printed circuit board includes a first insulating layer having at least one recess in one surface thereof, a first wiring layer embedded in one surface of the first insulating layer, and a first via layer including a first via penetrating at least a portion of the first insulating layer, one surface of the first via being outwardly exposed from a lower surface of each of the at least one recess.

Claims

1. A printed circuit board, comprising: A first insulating layer has a plurality of recesses located in a surface of the first insulating layer; A first wiring layer is embedded in one surface of the first insulating layer; The first via layer includes a plurality of first vias, each penetrating at least a portion of the first insulating layer, and one surface of each of the plurality of first vias is exposed outward from the lower surface of a corresponding one of the plurality of recesses; as well as A plurality of first electrical connection metal bumps, each first electrical connection metal bump being disposed in a corresponding one of the plurality of recesses and connected to a corresponding one of the plurality of first vias.

2. The printed circuit board of claim 1, wherein, The first via layer further includes a second via that penetrates at least a portion of the first insulating layer, and the second via tapers in a direction opposite to the taper direction of each of the plurality of first vias.

3. The printed circuit board as claimed in claim 2, further comprising: The second wiring layer is disposed on the other surface of the first insulating layer; A second insulating layer is disposed on the other surface of the first insulating layer to embed the second wiring layer in one surface of the second insulating layer; The third wiring layer is disposed on the other surface of the second insulating layer; as well as The second via layer penetrates at least a portion of the second insulating layer and electrically connects the second wiring layer and the third wiring layer to each other. In each of the second and third wiring layers, at least one of the line width, pitch, and spacing is greater than at least one of the corresponding line width, pitch, and spacing in the first wiring layer.

4. The printed circuit board of claim 3, further comprising: The fourth wiring layer is configured to protrude from one surface of the first insulating layer. The second via electrically connects the second wiring layer and the fourth wiring layer to each other.

5. The printed circuit board of claim 4, further comprising: A first passivation layer is disposed on one surface of the first insulating layer and has a plurality of first openings that at least partially expose the first wiring layer, the plurality of recesses and the fourth wiring layer, respectively. as well as A second passivation layer is disposed on the other surface of the second insulating layer and has a plurality of second openings that at least partially expose the third wiring layer.

6. The printed circuit board of claim 5, further comprising a second electrical connection metal bump disposed in at least some of the plurality of first openings for electrical connection to the fourth wiring layer.

7. The printed circuit board of claim 1, wherein, The first wiring layer includes a first circuit pattern and a second circuit pattern, wherein at least one of the line width, pitch, and spacing of the second circuit pattern is greater than at least one of the corresponding line width, pitch, and spacing of the first circuit pattern.

8. The printed circuit board of claim 7, further comprising: The second wiring layer is disposed on the other surface of the first insulating layer. The first via layer further includes a second via, the second via penetrating at least a portion of the first insulating layer and gradually tapering in the same direction as each of the plurality of first vias. The second via electrically connects the second wiring layer and the second circuit pattern to each other.

9. The printed circuit board as claimed in claim 8, wherein, In the horizontal direction, the area of ​​the surface of each of the plurality of first through holes is smaller than the cross-sectional area of ​​the lower surface of each of the plurality of recesses.

10. The printed circuit board as claimed in claim 2, wherein, The height of each of the plurality of first vias is different from the height of the second via.

11. The printed circuit board of claim 10, wherein, The height of each of the plurality of first vias is less than the height of the second via.

12. The printed circuit board of claim 8, wherein, The second via directly contacts the second wiring layer and the second circuit pattern.

13. An electronic component package, comprising: A first substrate includes a first insulating layer and a first via layer. The first insulating layer is divided into a first region and a second region, and the first insulating layer has a plurality of recesses in one surface of the first region. The first via layer includes a plurality of first vias, each penetrating at least a portion of the first region, and one surface of each of the plurality of first vias is exposed outwardly from the lower surface of a corresponding one of the plurality of recesses. An electronic component is disposed on the first region of the first insulating layer; The second substrate is disposed on one surface of the first substrate and electrically connected to the first substrate; as well as A plurality of first electrical connection metals, each first electrical connection metal being disposed in a corresponding one of the plurality of recesses to electrically connect the plurality of first vias and the electronic components to each other.

14. The electronic component package of claim 13, wherein, The first substrate further includes a first wiring layer disposed on one surface of the first insulating layer.

15. The electronic component package of claim 14, further comprising a second electrical connection metal disposed on the first wiring layer in the second region of the first insulating layer to electrically connect the first wiring layer and the second substrate to each other.

16. The electronic component package of claim 15, wherein, The first via layer further includes a second via that penetrates at least a portion of the second region of the first insulating layer and tapers in a direction opposite to the taper direction of each of the plurality of first vias.

17. The electronic component package of claim 16, wherein, The first wiring layer disposed in the first region of the first insulating layer is embedded from the one surface of the first insulating layer, and The first wiring layer, disposed in the second region of the first insulating layer, protrudes from one surface of the first insulating layer.

18. The electronic component package of claim 17, wherein, The first substrate further includes a second wiring layer disposed on another surface of the first insulating layer. Each of the plurality of first vias is connected in contact with both the second wiring layer and a corresponding one of the plurality of first electrical connection metals, and The second via is in contact with both the second wiring layer and the first wiring layer disposed in the second region of the first insulating layer.

19. The electronic component package of claim 15, wherein, At least one of the line width, pitch, and spacing of the first wiring layer disposed in the first region of the first insulating layer is smaller than at least one of the corresponding line width, pitch, and spacing of the first wiring layer disposed in the second region of the first insulating layer.

20. The electronic component package of claim 13, wherein, The electronic component is located between the second substrate and the lower surface of each of the plurality of recesses.

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