Semiconductor device including contact plug

Abstract

A semiconductor device includes a lower circuit structure having a first lower conductive pattern. An intermediate wiring structure is disposed on the lower circuit structure and includes a horizontal wiring. The intermediate circuit structure is disposed on the intermediate wiring structure and includes a stacked structure of alternating wiring layers and insulating layers. A channel structure extends to the inside of the stacked structure and contacts the horizontal wiring. A contact plug that contacts the first lower conductive pattern and the horizontal wiring is disposed in the intermediate wiring structure. The lowermost end of the channel structure is relatively farther from the top surface of the substrate than the bottom surface of the horizontal wiring. The uppermost end of the contact plug is relatively farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and the uppermost end of the contact plug is disposed relatively closer to the top surface of the substrate than the lowermost end of each of the wiring layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This U.S. nonprovisional patent application claims priority to Korean Patent Application No. 10-2020-0047878 filed on April 21, 2020, in the Korean Intellectual Property Office (KIPO), the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present inventive concept generally relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a contact plug and a method of manufacturing the same. Background Art

[0004] The continuous demand for increased integration density has driven the development of three-dimensional or vertical integrated semiconductor devices. Such semiconductor devices generally include a lower circuit structure formed on a stacked substrate and a stacked structure vertically disposed on the lower circuit structure. In this regard, the stacked structure has become increasingly complex and taller (i.e., vertical thickness). As a result, the aspect ratio of the through hole that passes through the stacked structure in whole or in part to connect to the lower circuit structure increases. Unfortunately, the formation of high aspect ratio through holes requires a more complex set of manufacturing processes. Summary of the invention

[0005] Embodiments of the inventive concept provide semiconductor devices including vias that provide excellent electrical characteristics while methods of manufacturing the semiconductor devices are relatively simple.

[0006] In one embodiment of the inventive concept, a semiconductor device includes: a lower circuit structure disposed on a substrate, the lower circuit structure including a first lower conductive pattern; an intermediate wiring structure disposed on the lower circuit structure, the intermediate wiring structure including a horizontal wiring; an intermediate circuit structure disposed on the intermediate wiring structure, the intermediate circuit structure including a stacked structure having wiring layers and insulating layers stacked alternately; a channel structure extending to the inside of the stacked structure to contact the horizontal wiring; and a contact plug extending to the inside of the intermediate wiring structure to contact the first lower conductive pattern and the horizontal wiring. The lowermost end of the channel structure is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, the uppermost end of the contact plug is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and the uppermost end of the contact plug is disposed closer to the top surface of the substrate than the lowermost end of each of the wiring layers.

[0007] In another embodiment of the inventive concept, a semiconductor device includes: a lower circuit structure disposed on a substrate, the lower circuit structure including a lower conductive pattern; an intermediate wiring structure disposed on the lower circuit structure, the intermediate wiring structure including a horizontal wiring; an intermediate circuit structure disposed on the intermediate wiring structure, the intermediate circuit structure including a stacked structure, the stacked structure including wiring layers and insulating layers stacked alternately; channel structures, which extend to the inside of the stacked structure to contact the horizontal wiring; relay plugs, which extend to the inside of the intermediate wiring structure to contact the lower conductive pattern; vias, which are disposed on the relay plugs to extend to the inside of the intermediate circuit structure; and cell contact plugs, which extend to the inside of the intermediate wiring structure to contact the wiring layer. The lowermost end of each of the channel structures is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, the uppermost end of the relay plug is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and the uppermost end of the relay plug is disposed closer to the top surface of the substrate than the lowermost end of each of the wiring layers.

[0008] In another embodiment of the present invention, a semiconductor device includes: a lower circuit structure arranged on a substrate, the lower circuit structure including a first lower conductive pattern and a second lower conductive pattern; an intermediate wiring structure arranged on the lower circuit structure, the intermediate wiring structure including a horizontal wiring; an intermediate circuit structure arranged on the intermediate wiring structure, the intermediate circuit structure including a stacked structure, the stacked structure including wiring layers and insulating layers stacked alternately; a channel structure, which extends to the interior of the stacked structure to contact the horizontal wiring; a contact plug, which extends to the interior of the intermediate wiring structure to contact the first lower conductive pattern and the horizontal wiring; a relay plug, which extends to the interior of the intermediate wiring structure to contact the second lower conductive pattern; a through hole, which is arranged on the relay plug and extends to the interior of the intermediate circuit structure; a unit contact plug, which extends to the interior of the intermediate wiring structure to contact the wiring layer; and an upper wiring structure arranged on the intermediate circuit structure, the upper wiring structure including a bit line connected to the channel structure and an upper wiring connected to the through hole. The uppermost ends of the contact plug and the relay plug are substantially coplanar, are farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and are arranged closer to the top surface of the substrate than the lowermost end of each of the wiring layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 and Fig.25 are cross-sectional views illustrating various semiconductor devices according to embodiments of the inventive concept, respectively.

[0010] Fig.26 , Fig. 27 , Fig.28 , Fig.29 and Fig.30 are related cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0011] Throughout the written description and the accompanying drawings, the same reference numerals and designations are used to represent the same or similar elements and / or features. Throughout the written description, certain geometric terms may be used to emphasize the relative relationships between elements, components and / or features of a particular embodiment of the present invention. Those skilled in the art will recognize that such geometric terms are relative in nature, arbitrary in their descriptive relationship and / or refer to one or more aspects of the illustrated embodiments. For example, geometric terms may include: height / width; vertical / horizontal; top / bottom; higher / lower; closer / further; thicker / thinner; proximal / distal; above / below; below / above; upper / middle / lower; center / side; surrounding; overlying / underlying, etc.

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept; Figure 2 It further shows Figure 1 an enlarged view of portion 11 and portion 15; Figure 3 It further shows Figure 2 an enlarged view of a portion 36; Figure 4 It further shows Figure 2 an enlarged view of a portion 37; Figure 5 It further shows Figure 2 an enlarged view of portion 38 of ; and Figure 6 It further shows Figure 1 An enlarged view of portion 12. Figure 7 , Figure 8 , Fig. 9 and Fig.10are cross-sectional views illustrating various semiconductor devices according to embodiments of the inventive concept. Fig.11 It further shows Figure 1 An enlarged view of portion 13. Fig.12 , Fig.13 , Fig.14 and Fig.15 are cross-sectional views illustrating various semiconductor devices according to embodiments of the inventive concept. Fig.16 It further shows Figure 1 An enlarged view of portion 14. Fig.17 , Fig.18 and Fig.19 are cross-sectional views illustrating various semiconductor devices according to embodiments of the inventive concept.

[0013] Semiconductor devices according to embodiments of the inventive concept may include nonvolatile memories such as vertical NAND (VNAND) or three-dimensional (3D) flash memories. Certain semiconductor devices according to embodiments of the inventive concept may have a cell-on-periphery (COP) structure.

[0014] Reference Figure 1 , a semiconductor device according to an embodiment of the present invention may include: a substrate 51, which includes first to fifth regions, namely 11, 12, 13, 14 and 15; a lower circuit structure I on the substrate 51; an intermediate wiring structure II on the lower circuit structure I; an intermediate circuit structure III on the intermediate wiring structure II; and an upper wiring structure IV on the intermediate circuit structure III. Here, the first region 11 and the fifth region 15 may correspond to corresponding unit regions, and the second region 12, the third region 13 and the fourth region 14 may correspond to corresponding extension regions. In the illustrated Figure 1 In the example, the second region 12 , the third region 13 , and the fourth region 14 have side surface continuity with the first region 11 and / or the fifth region 15 .

[0015] The semiconductor device according to an embodiment of the inventive concept may further include an isolation pattern 89 , a channel structure 99 , contact plugs 171 , 172 , and 173 (hereinafter, “ 171 to 173 ”), relay plugs 181 and 182 , a via 285 , and a cell contact plug 287 .

[0016] The lower circuit structure I may include an isolation layer 53, an impurity region 55, a transistor 57, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The second lower insulating layer 63 may correspond to a capping layer or an etching stop layer. The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connecting electrode layer 73G, a connecting mold layer 73M, a support 75, a second intermediate insulating layer 76, a third intermediate insulating layer 77, a first buried insulating pattern 78, and a second buried insulating pattern 79. The connecting electrode layer 73G and the connecting mold layer 73M may be configured to connect the wiring layers 73G and 73M.

[0017] The intermediate circuit structure III may include a stacked structure 85 and an interlayer insulating layer 86. The stacked structure 85 may include wiring layers 81G and 81M and an insulating layer 83 that are repeatedly and alternately stacked. The wiring layers 81G and 81M may include an electrode layer 81G and a mold layer 81M. The upper wiring structure IV may include a first upper insulating layer 103, a second upper insulating layer 105, a bit line plug 107, a bit line 108, an upper plug 112, and an upper wiring 113.

[0018] The contact plugs 171 to 173 may include a first contact plug 171, a second contact plug 172, and a third contact plug 173. The relay plugs 181 and 182 may include a first relay plug 181 and a second relay plug 182. The channel structure 99 may extend to the inside of the stack structure 85 and may be connected to the horizontal wiring 71. The lowermost end of each channel structure 99 may be relatively farther from the top surface of the substrate 51 than the bottom surface of the horizontal wiring 71. The uppermost end of each contact plug 171 to 173 may be relatively farther from the top surface of the substrate 51 than the bottom surface of the horizontal wiring 71, and the uppermost end of each contact plug 171 to 173 may be set to be relatively closer to the top surface of the substrate 51 than the lowermost end of each wiring layer 81G and 81M.

[0019] In an embodiment, the horizontal wiring 71 may correspond to a source line or a common source line (CSL). At least one of the electrode layers 81G (e.g., one adjacent to the lowermost end of the stacked structure 85) and at least one of the electrode layers 81G (e.g., one adjacent to the uppermost end of the stacked structure 85) may correspond to a gate-induced drain leakage (GIDL) control line, respectively. Some electrode layers 81G may each correspond to a word line or a pseudo word line. At least one of the electrode layers 81G (e.g., one adjacent to the lowermost end of the stacked structure 85 and disposed between the GIDL control line and the word line) may correspond to a ground selection line (GSL). At least one of the electrode layers 81G (e.g., one adjacent to the uppermost end of the stacked structure 85 and disposed between the GIDL control line and the word line) may correspond to a string selection line (SSL).

[0020] Reference Figure 2, a semiconductor device according to an embodiment of the inventive concept may include: a substrate 51 including a first region 11 and a fifth region 15; a lower circuit structure I on the substrate 51; an intermediate wiring structure II on the lower circuit structure I; an intermediate circuit structure III on the intermediate wiring structure II; an upper wiring structure IV on the intermediate circuit structure III; an isolation pattern 89; and a channel structure 99. In an embodiment, the first region 15 may be adjacent to the first region 11. The fifth region 15 may be a cross-sectional view taken along a direction intersecting the first region 11.

[0021] The lower circuit structure I may include an isolation layer 53, an impurity region 55, a transistor 57, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connecting electrode layer 73G, and a support 75. The intermediate circuit structure III may include a stacked structure 85, which includes electrode layers 81G and insulating layers 83 that are repeatedly and alternately stacked. The electrode layer 81G may correspond to some portions of the wiring layer (e.g., Figure 1 The upper wiring structure IV may include a first upper insulating layer 103, a second upper insulating layer 105, a bit line plug 107 and a bit line 108.

[0022] The bit line plug 107 may pass through the second upper insulating layer 105 and the first upper insulating layer 103 to connect the channel structure 99. The bit line 108 may be disposed on the second upper insulating layer 105. The bit line 108 may directly contact the bit line plug 107. The isolation pattern 89 may pass through the first upper insulating layer 103, the intermediate circuit structure III, the support member 75, and the connection electrode layer 73G, thereby extending to the inside of the horizontal wiring 71.

[0023] Reference Figure 3 , the channel structure 99 may include a core pattern 97, a channel layer 96 surrounding the outside of the core pattern 97, an information storage pattern 95 at least partially surrounding the outside of the channel layer 96, and a bit line pad 98 on the channel layer 96. The information storage pattern 95 may include a tunnel insulating layer 91 surrounding the outside of the channel layer 96, a charge storage layer 92 surrounding the outside of the tunnel insulating layer 91, and a blocking layer 93 surrounding the outside of the charge storage layer 92. The channel structure 99 may pass through the electrode layer 81G and the insulating layer 83. The bit line plug 107 may pass through the first upper insulating layer 103 and may contact the bit line pad 98 of the channel structure 99.

[0024] The tunnel insulating layer 91 may include an insulating layer such as silicon oxide. The charge storage layer 92 may include an insulating layer such as silicon nitride. The blocking layer 93 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or a combination thereof. The channel layer 96 may include polysilicon, amorphous silicon, monocrystalline silicon, or a combination thereof. The core pattern 97 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, polysilicon, or a combination thereof. The bit line pad 98 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof.

[0025] Reference Figure 4 The electrode layer 81G and the insulating layer 83 may be repeatedly and alternately stacked. The channel structure 99 may pass through the electrode layer 81G and the insulating layer 83.

[0026] Reference Figure 5 , the connection electrode layer 73G may be disposed between the horizontal wiring 71 and the support member 75. The insulating layer 83 may be disposed on the support member 75. The channel structure 99 may pass through the insulating layer 83 and the support member 75, thereby extending to the inside of the horizontal wiring 71. The connection electrode layer 73G may pass through the side surface of the information storage pattern 95 to directly contact the side surface of the channel layer 96. The lowermost end of the channel structure 99 may be disposed at a level higher than the bottom surface of the horizontal wiring 71. The channel layer 96 may be electrically connected to the horizontal wiring 71 via the connection electrode layer 73G.

[0027] Reference Figure 6 , a semiconductor device according to an embodiment of the present invention may include: a substrate 51 including a second region 12; a lower circuit structure I on the substrate 51; an intermediate wiring structure II on the lower circuit structure I; an intermediate circuit structure III on the intermediate wiring structure II; an upper wiring structure IV on the intermediate circuit structure III; a first contact plug 171; a second contact plug 172; a first relay plug 181; a through hole 285; and a cell contact plug 287. In the illustrated Figure 6 In the example of Figure 1 11) has side surface continuity.

[0028] The lower circuit structure I may include an isolation layer 53, an impurity region 55, a transistor 57, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support 75, a second intermediate insulating layer 76, a third intermediate insulating layer 77, and a first buried insulating pattern 78.

[0029] The connection electrode layer 73G and the connection mold layer 73M may be configured to form connection wiring layers 73G and 73M. The connection mold layer 73M may be arranged at substantially the same level as the connection electrode layer 73G. The connection mold layer 73M may have substantially the same thickness as the connection electrode layer 73G. The connection mold layer 73M may include a lower mold layer 73L, an upper mold layer 73U on the lower mold layer 73L, and an intermediate mold layer 73C between the lower mold layer 73L and the upper mold layer 73U. The intermediate mold layer 73C may include a material having an etching selectivity relative to the lower mold layer 73L and the upper mold layer 73U. For example, each of the lower mold layer 73L and the upper mold layer 73U may include silicon oxide. The intermediate mold layer 73C may include silicon nitride.

[0030] A portion of the support 75 may pass through the connection wiring layers 73G and 73M to directly contact the top surface of the horizontal wiring 71. The support 75 may directly contact side surfaces of the connection electrode layer 73G and the connection mold layer 73M. A first buried insulating pattern 78 may be disposed on the support 75.

[0031] The first contact plugs 171 may pass through the support member 75, the connection mold layer 73M, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive patterns 61. The second contact plugs 172 may pass through the first intermediate insulating layer 68 and the second lower insulating layer 63 to directly and respectively contact the lower conductive patterns 61. The second contact plugs 172 may directly contact the bottom surface of the horizontal wiring 71.

[0032] The first relay plug 181 may pass through the third intermediate insulating layer 77, the second intermediate insulating layer 76, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive pattern 61. Top surfaces of the first contact plug 171, the first relay plug 181, the support member 75, the third intermediate insulating layer 77, and the first buried insulating pattern 78 may be substantially coplanar with each other.

[0033] The intermediate circuit structure III may include a stacked structure 85 and an interlayer insulating layer 86. The stacked structure 85 may include electrode layers 81G and insulating layers 83 that are repeatedly and alternately stacked. The electrode layer 81G may correspond to some portions of the wiring layer (eg, Figure 1 81G and 81M). The interlayer insulating layer 86 may have side surface continuity with the stacked structure 85. Here, the side surface of the stacked structure 85 may have a step shape. The interlayer insulating layer 86 may at least partially cover the top surface of the stacked structure 85.

[0034] The upper wiring structure IV may include a first upper insulating layer 103, a second upper insulating layer 105, upper plugs 112, and upper wirings 113. The upper wirings 113 may be disposed on the second upper insulating layer 105. The upper wirings 113 may directly contact a corresponding one of the upper plugs 112.

[0035] The through hole 285 may pass through the first upper insulating layer 103 and the interlayer insulating layer 86 to directly contact the first relay plug 181. The cell contact plug 287 may pass through the first upper insulating layer 103 and the interlayer insulating layer 86 to directly and respectively contact the electrode layer 81G. Top surfaces of the through hole 285, the cell contact plug 287, and the first upper insulating layer 103 may be substantially coplanar with each other.

[0036] At least one upper plug 112 selected from the upper plugs 112 may pass through the second insulating layer 105 to directly contact the through hole 285. Some of the upper plugs 112 may pass through the second upper insulating layer 105 to directly contact one of the cell contact plugs 287.

[0037] Reference Figure 7 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51, a first contact plug 171, and a first relay plug 181, the substrate 51 including the sixth region 16. Here, the second contact plug (eg, Figure 1 172). The sixth region 16 may be adjacent to the second region (e.g., Figure 1 12), or may be combined with a second zone (e.g., Figure 1 The sixth region 16 may correspond to an extension region.

[0038] Reference Figure 8 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51, a first contact plug 171, a second contact plug 172, and a through hole 285, the substrate 51 including the seventh region 17. The through hole 285 may pass through the first upper insulating layer 103, the interlayer insulating layer 86, the third intermediate insulating layer 77, the second intermediate insulating layer 76, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive pattern 61. Here, the first relay plug (e.g., Figure 1 The seventh region 17 may be adjacent to the second region (eg, Figure 1 12), or may be combined with a second zone (e.g., Figure 1 The seventh region 17 may correspond to an extension region.

[0039] Reference Fig. 9 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51, a second contact plug 172, and a first relay plug 181, the substrate 51 including the eighth region 18. Here, the first contact plug (eg, Figure 1 171). The eighth region 18 may be adjacent to the second region (eg, Figure 1 12), or may be combined with a second zone (e.g., Figure 1 The eighth region 18 may correspond to an extension region.

[0040] Reference Fig.10 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51, a first contact plug 171, a second contact plug 172, and a first relay plug 181, the substrate 51 including a ninth region 19. The ninth region 19 may be adjacent to the second region (eg, Figure 1 12), or may be combined with a second zone (e.g., Figure 1 The ninth region 19 may correspond to an extension region.

[0041] A portion of the support member 75 may directly contact the top surface of the horizontal wiring 71. The first buried insulating pattern 78 may be disposed on the support member 75. The support member 75 may directly contact the top surface and side surface of the connection electrode layer 73G. The top surface of the first buried insulating pattern 78 may be substantially coplanar with the uppermost end of the support member 75.

[0042] The first contact plug 171 may pass through the first buried insulating pattern 78, the support 75, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact one lower conductive pattern 61 selected from the lower conductive patterns 61. The first relay plug 181 may pass through the third intermediate insulating layer 77, the second intermediate insulating layer 76, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact another lower conductive pattern 61 selected from the lower conductive patterns 61. The uppermost end of the first contact plug 171, the uppermost end of the first relay plug 181, the uppermost end of the support 75, the top surface of the first buried insulating pattern 78, and the top surface of the third intermediate insulating layer 77 may be substantially coplanar with each other.

[0043] Reference Fig.11 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a third region 13), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, an isolation pattern 89, and a third contact plug 173. In the illustrated Fig.11 In the embodiment of the present invention, the third region 13 may be formed along the second region (eg, Figure 1 12) is a cross-sectional view taken in the direction of intersection.

[0044] The lower circuit structure I may include an isolation layer 53, an impurity region 55, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The second lower insulating layer 63 may correspond to a capping layer or an etch stop layer.

[0045] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connecting electrode layer 73G, a connecting mold layer 73M, a support member 75, and a first buried insulating pattern 78. The connecting electrode layer 73G and the connecting mold layer 73M may be configured to connect the wiring layers 73G and 73M. A portion of the support member 75 may pass through the connecting wiring layers 73G and 73M and may directly contact the top surface of the horizontal wiring 71. In an embodiment, a portion of the support member 75 may pass through the area between the connecting electrode layer 73G and the connecting mold layer 73M to directly contact the top surface of the horizontal wiring 71. A portion of the support member 75 may directly contact the side surfaces of the connecting electrode layer 73G and the connecting mold layer 73M. A portion of the support member 75 may directly contact the side surfaces of the lower mold layer 73L, the middle mold layer 73C, and the upper mold layer 73U.

[0046] The intermediate circuit structure III may include a stacked structure 85 and an interlayer insulating layer 86. The stacked structure 85 may include wiring layers 81G and 81M and an insulating layer 83 that are repeatedly and alternately stacked. The wiring layers 81G and 81M may include an electrode layer 81G and a mold layer 81M. Each of the mold layers 81M may have a side surface continuity with one of the electrode layers 81G. Each of the mold layers 81M may have substantially the same thickness as a corresponding one of the electrode layers 81G. The interlayer insulating layer 86 may be disposed on the stacked structure 85. The upper wiring structure IV may include a first upper insulating layer 103 and a second upper insulating layer 105.

[0047] The third contact plug 173 may pass through the support member 75, the connection mold layer 73M, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63, and may directly contact one lower conductive pattern 61 selected from the lower conductive patterns 61. Top surfaces of the third contact plug 173, the support member 75, and the first buried insulating layer 78 may be substantially coplanar with each other.

[0048] Reference Fig.12 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 and a fourth contact plug 174, the substrate 51 including a tenth region 20. The tenth region 20 may be adjacent to the second region (eg, Figure 1 12) or the third zone (e.g. Figure 1 13), or may be combined with a second zone (e.g., Figure 1 12) or the third zone (e.g. Figure 1 The tenth region 20 may correspond to an extension region.

[0049] A portion of the support member 75 may directly contact the top surface of the horizontal wiring 71. The first buried insulating pattern 78 may be disposed on the support member 75. The support member 75 may directly contact the top surface and the side surface of the connection electrode layer 73G. The top surface of the first buried insulating pattern 78 may be substantially coplanar with the uppermost end of the support member 75. The fourth contact plug 174 may pass through the first buried insulating pattern 78, the support member 75, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63, and may directly contact one of the lower conductive patterns 61 selected from the lower conductive patterns 61. The uppermost end of the fourth contact plug 174, the uppermost end of the support member 75, and the top surface of the first buried insulating pattern 78 may be substantially coplanar with each other.

[0050] Reference Fig.13 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 and a fifth contact plug 175, the substrate 51 including an eleventh region 21. The eleventh region 21 may be adjacent to the first region ( Figure 1 11) or the fifth zone (e.g. Figure 1 15), or may be associated with the first zone (e.g., Figure 1 11) or the fifth zone (e.g. Figure 1 15). The eleventh region 21 may correspond to the cell region. The intermediate circuit structure III may include a stacked structure 85, and the stacked structure 85 includes electrode layers 81G and insulating layers 83 that are repeatedly and alternately stacked. The electrode layer 81G may correspond to some parts of the wiring layer (for example, Figure 1 81G and 81M).

[0051] A portion of the support member 75 may directly contact the top surface of the horizontal wiring 71. The first buried insulating pattern 78 may be disposed on the support member 75. The support member 75 may directly contact the top surface and the side surface of the connection electrode layer 73G. The top surface of the first buried insulating pattern 78 may be substantially coplanar with the uppermost end of the support member 75. The fifth contact plug 175 may pass through the first buried insulating pattern 78, the support member 75, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact one of the lower conductive patterns 61 selected from the lower conductive patterns 61. The uppermost end of the fifth contact plug 175, the uppermost end of the support member 75, and the top surface of the first buried insulating pattern 78 may be substantially coplanar with each other.

[0052] Reference Fig.14 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a twelfth region 22) and a sixth contact plug 176. The twelfth region 22 may be adjacent to the first region (eg, Figure 1 11) or the fifth zone (e.g. Figure 1 15), or may be associated with the first zone (e.g., Figure 111) or the fifth zone (e.g. Figure 1 The twelfth region 22 may correspond to the unit region.

[0053] The connection electrode layer 73G may be disposed between the support member 75 and the horizontal wiring 71. The sixth contact plug 176 may pass through the support member 75, the connection electrode layer 73G, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact one of the lower conductive patterns 61 selected from the lower conductive patterns 61. The uppermost end of the sixth contact plug 176 and the uppermost end of the support member 75 may be substantially coplanar with each other. The side surfaces of the support member 75, the connection electrode layer 73G, and the horizontal wiring 71 may directly contact the side surface of the sixth contact plug 176.

[0054] Reference Fig.15 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a thirteenth region 23) and a seventh contact plug 177. The thirteenth region 23 may be adjacent to the first region (eg, Figure 1 11) or the fifth zone (e.g. Figure 1 15), or may be associated with the first zone (e.g., Figure 1 11) or the fifth zone (e.g. Figure 1 The twelfth region 22 may correspond to the cell region. The connection electrode layer 73G may extend to the inside of the seventh contact plug 177. The connection electrode layer 73G may pass through the side surface of the seventh contact plug 177 and may enter the inside of the seventh contact plug 177.

[0055] Reference Fig.16 , a semiconductor device according to an embodiment of the present invention may include a substrate 51 (including a fourth region 14), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, an isolation pattern 89, a second relay plug 182, and a through hole 285. In the illustrated Fig.16 In the embodiment of the present invention, the fourth region 14 may be adjacent to the second region (eg, Figure 1 12) or the third zone (e.g. Figure 1 13), or may be combined with a second zone (e.g., Figure 1 12) or the third zone (e.g. Figure 1 The fourth area 14 may be arranged along the same direction as the second area ( Figure 1 12) is a cross-sectional view taken in the direction of intersection.

[0056] The lower circuit structure I may include an isolation layer 53, an impurity region 55, a transistor 57, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support member 75, a first buried insulating pattern 78, and a second buried insulating pattern 79. The connection electrode layer 73G and the connection mold layer 73M may be configured to connect the wiring layers 73G and 73M.

[0057] The intermediate circuit structure III may include a stacked structure 85 and an interlayer insulating layer 86. The stacked structure 85 may include wiring layers 81G and 81M and an insulating layer 83 that are repeatedly and alternately stacked. The wiring layers 81G and 81M may include an electrode layer 81G and a mold layer 81M. The upper wiring structure IV may include a first upper insulating layer 103, a second upper insulating layer 105, an upper plug 112, and an upper wiring 113.

[0058] The second buried insulating layer 79 may pass through the support member 75, the connection mold layer 73M, and the horizontal wiring 71 to contact the first intermediate insulating layer 68. The second relay plug 182 may pass through the second buried insulating layer 79, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive pattern 61. Top surfaces of the second relay plug 182, the second buried insulating layer 79, and the support member 75 may be substantially coplanar with each other.

[0059] The through hole 285 may pass through the first upper insulating layer 103, the interlayer insulating layer 86, the mold layer 81M, and the insulating layer 83 to directly contact the second relay plug 182. The upper plug 112 may pass through the second upper insulating layer 105 to directly contact the through hole 285. The upper wiring 113 may be disposed on the second upper insulating layer 105. The upper wiring 113 may directly contact the upper plug 112.

[0060] Reference Fig.17 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a fourteenth region 24) and a third relay plug 183. The fourteenth region 24 may be adjacent to the second region (eg, Figure 1 12) or the fourth zone (e.g. Figure 1 14), or may be combined with a second zone (e.g., Figure 1 12) or the fourth zone (e.g. Figure 1 The fourteenth region 24 may correspond to an extension region.

[0061] A portion of the support member 75 may directly contact the top surface of the horizontal wiring 71. The first buried insulation pattern 78 may be disposed on the support member 75. The second buried insulation pattern 79 may pass through the first buried insulation pattern 78, the support member 75, and the horizontal wiring 71. The third relay plug 183 may pass through the second buried insulation pattern 79, the first intermediate insulation layer 68, and the second lower insulation layer 63 to directly contact one of the lower conductive patterns 61 selected from the lower conductive patterns 61. The uppermost end of the third relay plug 183, the top surface of the first buried insulation pattern 78, and the top surface of the second buried insulation pattern 79 may be substantially coplanar with each other.

[0062] Reference Fig.18 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a fifteenth region 25) and a fourth relay plug 184. The fifteenth region 25 may be adjacent to the second region (eg, Figure 1 12) or the fourth zone (e.g. Figure 1 14), or may be combined with a second zone (e.g., Figure 1 12) or the fourth zone (e.g. Figure 1 The fifteenth region 25 may correspond to an extension region.

[0063] The connection electrode layer 73G may be disposed between the support member 75 and the horizontal wiring 71. The second buried insulating layer 79 may pass through the support member 75, the connection electrode layer 73G, and the horizontal wiring 71. The fourth relay plug 184 may pass through the second buried insulating pattern 79, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact one lower conductive pattern 61 selected from the lower conductive patterns 61. The uppermost end of the fourth relay plug 184, the top surface of the second buried insulating pattern 79, and the top surface of the support member 75 may be substantially coplanar with each other.

[0064] Reference Fig.19 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a sixteenth region 26) and a through hole 285. The sixteenth region 26 may be adjacent to the second region (eg, Figure 1 12) or the fourth zone (e.g. Figure 1 14), or may be combined with a second zone (e.g., Figure 1 12) or the fourth zone (e.g. Figure 1 The sixteenth region 26 may correspond to an extension region.

[0065] The through hole 285 may pass through the first upper insulating layer 103, the interlayer insulating layer 86, the mold layer 81M, the insulating layer 83, the second buried insulating pattern 79, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive pattern 61. Here, the second relay plug (e.g., Figure 1182).

[0066] Fig. 20 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. Fig.21 It further shows Fig. 20 An enlarged view of part 27, Fig. 22 It further shows Fig. 20 an enlarged view of portion 28 of ; and Fig.23 It further shows Fig. 20 An enlarged view of portion 29.

[0067] Reference Fig. 20 , a semiconductor device according to an embodiment of the present invention may include: a substrate 51 including a first region 11, a seventeenth region 27, an eighteenth region 28, and a nineteenth region 29; a lower circuit structure I on the substrate 51; an intermediate wiring structure II on the lower circuit structure I; an intermediate circuit structure III on the intermediate wiring structure II; an upper wiring structure IV on the intermediate circuit structure III; an isolation pattern 89; a channel structure 99; contact plugs 172, 178, and 179; relay plugs 185 and 186; a through hole 285; and a cell contact plug 287. In the illustrated Fig. 20 In the embodiment of the present invention, the first region 11 may correspond to the cell region, and each of the seventeenth region 27, the eighteenth region 28, and the nineteenth region 29 may correspond to the extension region. Each of the seventeenth region 27, the eighteenth region 28, and the nineteenth region 29 may have side surface continuity with the first region 11.

[0068] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support 75, a second intermediate insulating layer 76, a third intermediate insulating layer 77, a first buried insulating pattern 78, and second buried insulating patterns 79L and 79U. The connection electrode layer 73G and the connection mold layer 73M may be configured to connect the wiring layers 73G and 73M.

[0069] The second buried insulating patterns 79L and 79U may include a lower buried insulating pattern 79L and an upper buried insulating pattern 79U. The contact plugs 172, 178, and 179 may include a second contact plug 172, an eighth contact plug 178, and a ninth contact plug 179. The contact plugs 185 and 186 may include a fifth relay plug 185 and a sixth relay plug 186. Top surfaces of the horizontal wiring 71, the eighth contact plug 178, the ninth contact plug 179, the fifth relay plug 185, and the sixth relay plug 186 may be substantially coplanar with each other.

[0070] Reference Fig.21, the semiconductor device according to the embodiment of the present invention may include a substrate 51 (including the seventeenth region 27), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, a second contact plug 172, an eighth contact plug 178, a fifth relay plug 185, a through hole 285, and a cell contact plug 287. In the illustrated Fig.21 In the embodiment of FIG. 1 , the seventeenth region 27 may have side surface continuity with the first region 11 .

[0071] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support 75, a second intermediate insulating layer 76, a third intermediate insulating layer 77, and a first buried insulating pattern 78. The connection electrode layer 73G and the connection mold layer 73M may be configured to connect the wiring layers 73G and 73M.

[0072] The eighth contact plug 178 may pass through the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly and respectively contact the lower conductive patterns 61. The fifth relay plug 185 may pass through the second intermediate insulating layer 76, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact at least one of the lower conductive patterns 61.

[0073] Top surfaces of the horizontal wiring 71 , the eighth contact plug 178 , and the fifth relay plug 185 may be substantially coplanar with each other. The via 285 may pass through the first upper insulating layer 103 , the interlayer insulating layer 86 , and the third intermediate insulating layer 77 , and may directly contact the fifth relay plug 185 .

[0074] Reference Fig. 22 , the semiconductor device according to the embodiment of the present invention may include a substrate 51 (including the eighteenth region 28), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, an isolation pattern 89, and a ninth contact plug 179. In the illustrated Fig. 22 In the embodiment of the present invention, the eighteenth region 28 may be formed along the seventeenth region (eg, Fig. 20 27) is a cross-sectional view taken in the direction of intersection.

[0075] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support 75, and a first buried insulating pattern 78. The connection electrode layer 73G and the connection mold layer 73M may configure the connection wiring layers 73G and 73M. The ninth contact plug 179 may pass through the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63, and may directly contact at least a corresponding one of the lower conductive patterns 61. The bottom surface of the connection mold layer 73M may contact the top surface of the ninth contact plug 179. The top surfaces of the ninth contact plug 179 and the horizontal wiring 71 may be substantially coplanar with each other.

[0076] Reference Fig.23 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 51 (including a nineteenth region 29), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, an isolation pattern 89, a sixth relay plug 186, and a through hole 285. In an embodiment, the nineteenth region 29 may be adjacent to the seventeenth region (e.g., Fig. 20 27) or the 18th District (e.g. Fig. 20 28), or can be combined with the seventeenth zone (e.g. Fig. 20 27) or the 18th District (e.g. Fig. 20 The nineteenth region 29 may be arranged similarly to the seventeenth region (e.g., Fig. 20 27) is a cross-sectional view taken in the direction of intersection.

[0077] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connecting electrode layer 73G, a connecting mold layer 73M, a support 75, a first buried insulating pattern 78, and second buried insulating patterns 79L and 79U. The connecting electrode layer 73G and the connecting mold layer 73M may configure the connecting wiring layers 73G and 73M. The second buried insulating patterns 79L and 79U may include a lower buried insulating pattern 79L and an upper buried insulating pattern 79U. The upper buried insulating pattern 79U may be disposed on the lower buried insulating pattern 79L. The upper buried insulating pattern 79U may pass through the support 75 and the connecting mold layer 73M.

[0078] The sixth relay plug 186 may pass through the lower buried insulating pattern 79L, the first intermediate insulating layer 68, and the second lower insulating layer 63 to directly contact a corresponding one of the lower conductive patterns 61. Top surfaces of the sixth relay plug 186, the lower buried insulating pattern 79L, and the horizontal wiring 71 may be substantially coplanar with each other. The through hole 285 may pass through the first upper insulating layer 103, the interlayer insulating layer 86, the mold layer 81M, the insulating layer 83, and the upper buried insulating pattern 79U to directly contact the sixth relay plug 186.

[0079] Fig.24 and Fig.25 are cross-sectional views respectively illustrating semiconductor devices according to embodiments of the inventive concept.

[0080] Reference Fig.24 , a semiconductor device according to an embodiment of the present invention may include a substrate 51 (including first to fourth regions 11 to 14 and a sixteenth region 26), a lower circuit structure I on the substrate 51, an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, an upper wiring structure IV on the intermediate circuit structure III, an isolation pattern 89, a channel structure 99, contact plugs 171 to 173, relay plugs 181 and 182, a through hole 285, and a cell contact plug 287.

[0081] In the shown Fig.24 In the embodiment of FIG. 1 , the sixteenth region 26 may be adjacent to the fourth region 14, or may be configured similarly to the fourth region 14. The sixteenth region 26 may have the same configuration as previously described. Fig.19 A configuration similar to the one described.

[0082] Reference Fig.25 , a semiconductor device according to an embodiment of the present invention may include: a substrate 51, which includes a first region 11, a seventeenth region 27, an eighteenth region 28, a nineteenth region 29 and a twentieth region 30; a lower circuit structure I on the substrate 51; an intermediate wiring structure II on the lower circuit structure I; an intermediate circuit structure III on the intermediate wiring structure II; an upper wiring structure IV on the intermediate circuit structure III; an isolation pattern 89; a channel structure 99; contact plugs 172, 178 and 179; relay plugs 185 and 186; a through hole 285; and a cell contact plug 287.

[0083] In the shown Fig.25 In the embodiment of the present invention, the first region 11 may correspond to the unit region, and each of the seventeenth region 27, the eighteenth region 28, the nineteenth region 29 and the twentieth region 30 may correspond to the extension region. Each of the seventeenth region 27, the eighteenth region 28, the nineteenth region 29 and the twenty-third region 30 may have side surface continuity with the first region 11. The seventeenth region 27, the eighteenth region 28 and the nineteenth region 29 may be respectively as previously described with reference to Fig. 20 , Fig.21 , Fig. 22 and Fig.23 Configure as described.

[0084] In the twentieth region 30, the through hole 285 may pass through the first upper insulating layer 103, the interlayer insulating layer 86, the mold layer 81M, the insulating layer 83, the upper buried insulating pattern 79U, the lower buried insulating pattern 79L, the first intermediate insulating layer 68 and the second lower insulating layer 63 to directly and respectively contact the lower conductive pattern 61.

[0085] Fig.26 , Fig. 27 , Fig.28 , Fig.29 and Fig.30 2 is a related cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0086] Reference Fig.26 , a lower circuit structure I may be formed on the substrate 51 including the first region 11 to the fifth region 15. The lower circuit structure I may include an isolation layer 53, an impurity region 55, a transistor 57, a first lower insulating layer 59, a lower conductive pattern 61, and a second lower insulating layer 63. The second lower insulating layer 63 may correspond to a capping layer or an etch stop layer.

[0087] The substrate 51 may include a semiconductor substrate such as a silicon wafer. The isolation layer 53 may include an insulating layer formed by using a shallow trench isolation (STI) process. The impurity region 55 may be formed in the substrate 51 by using at least one of an N-type impurity and / or a P-type impurity.

[0088] Transistor 57 may be formed in and / or on substrate 51 using various well-known processes. For example, transistor 57 may include a fin field effect transistor (finFET), such as The transistor 57 may include a multi-bridge channel transistor, a nanowire transistor, a vertical transistor, a recessed channel transistor, a 3D transistor, a planar transistor, or a combination thereof. The transistor 57 may include some impurity regions 55 that serve as drain regions or source regions, respectively.

[0089] A first lower insulating layer 59 covering the transistor 57 and the isolation layer 53 may be formed on the substrate 51. A lower conductive pattern 61 may be formed in the first lower insulating layer 59. The lower conductive pattern 61 may include horizontal wirings and vertical wirings having various shapes. Some of the lower conductive patterns 61 may directly contact the impurity region 55. The transistor 57 and the lower conductive pattern 61 may be variously configured as one or more peripheral circuits. A second lower insulating layer 63 may be formed on the first lower insulating layer 59 and the lower conductive pattern 61.

[0090] Here, each of the isolation layer 53 and the first lower insulating layer 59 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. The second lower insulating layer 63 may include a material different from that of the first lower insulating layer 59. The second lower insulating layer 63 may include silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. The lower conductive pattern 61 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof.

[0091] Reference Fig. 27, a first intermediate insulating layer 68 may be formed on the lower circuit structure I. The first intermediate insulating layer 68 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. A second contact plug 172 may be formed through the first intermediate insulating layer 68 and the second lower insulating layer 63 to contact one of the lower conductive patterns 61. The process of forming the second contact plug 172 may include a thin film formation process and a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. The top surfaces of the first intermediate insulating layer 68 and the second contact plug 172 may be exposed at substantially the same plane. The second contact plug 172 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. For example, the second contact plug 172 may include tungsten (W), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), platinum (Pt), or a combination thereof.

[0092] Reference Fig.28 , a horizontal wiring 71 and a second intermediate insulating layer 76 may be formed on the first intermediate insulating layer 68 and the second contact plug 172. The process of forming the horizontal wiring 71 and the second intermediate insulating layer 76 may include a plurality of thin film forming processes, patterning processes, and planarization processes. The top surfaces of the horizontal wiring 71 and the second intermediate insulating layer 76 may be exposed at substantially the same plane. The bottom surface of the horizontal wiring 71 may directly contact the top surface of the second contact plug 172. The horizontal wiring 71 may include a single layer or multiple layers. The horizontal wiring 71 may include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, polysilicon, or a combination thereof. For example, the horizontal wiring 71 may include a doped polysilicon layer.

[0093] A connection mold layer 73M, a support member 75, and a third intermediate insulating layer 77 may be formed on the horizontal wiring 71 and the second intermediate insulating layer 76. The connection mold layer 73M may include a material having an etching selectivity with respect to the horizontal wiring 71 and the support member 75. The connection mold layer 73M may include the Figure 6 For example, the connection molding layer 73M may include a lower molding layer 73L, an upper molding layer 73U on the lower molding layer 73L, and an intermediate molding layer 73C between the lower molding layer 73L and the upper molding layer 73U.

[0094] The support member 75 may cover the connection mold layer 73M. Some portions of the support member 75 may pass through the connection mold layer 73M to directly contact the top surface of the horizontal wiring 71. The support member 75 may directly contact the top surface and the side surface of the connection mold layer 73M. The third intermediate insulating layer 77 may contact the side surface of the support member 75 and the side surface of the connection mold layer 73M. A first buried insulating pattern 78 may be formed on the support member 75. A second buried insulating pattern 79 may be formed passing through the support member 75, the connection mold layer 73M and the horizontal wiring 71. The third intermediate insulating layer 77 and the first buried insulating pattern 78 may include the same material and are formed at the same time. In a specific embodiment, the third intermediate insulating layer 77 may be omitted.

[0095] The process of forming the connection mold layer 73M, the support member 75, the third intermediate insulating layer 77, the first buried insulating pattern 78 and the second buried insulating pattern 79 may include a plurality of thin film forming processes, patterning processes and / or planarization processes. The planarization process may include a CMP process, an etch-back process or a combination thereof. The top surfaces of the support member 75, the third intermediate insulating layer 77, the first buried insulating pattern 78 and the second buried insulating pattern 79 may be exposed at substantially the same plane. Each of the second intermediate insulating layer 76, the third intermediate insulating layer 77, the first buried insulating pattern 78 and the second buried insulating pattern 79 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric or a combination thereof. In an embodiment, the support member 75 may include a polysilicon layer.

[0096] Reference Fig.29 , a first contact plug 171, a third contact plug 173, a first relay plug 181, and a second relay plug 182 may be formed. The first contact plug 171, the second contact plug 172, and the third contact plug 173 may be configured differently as contact plugs 171 to 173. The first relay plug 181 and the second relay plug 182 may be configured differently as relay plugs 181 and 182. The process of forming the first contact plug 171, the third contact plug 173, the first relay plug 181, and the second relay plug 182 may include a patterning process, a thin film forming process, and a planarization process. The planarization process may include a CMP process, an etch-back process, or a combination thereof. Top surfaces of the support 75 , the third intermediate insulating layer 77 , the first buried insulating pattern 78 , the second buried insulating pattern 79 , the first contact plug 171 , the third contact plug 173 , the first relay plug 181 , and the second relay plug 182 may be exposed at substantially the same plane.

[0097] Each of the first contact plug 171, the third contact plug 173, the first relay plug 181, and the second relay plug 182 may include a metal, a metal nitride, a metal silicide, a metal oxide, a conductive carbon, polysilicon, or a combination thereof. For example, each of the first contact plug 171, the third contact plug 173, the first relay plug 181, and the second relay plug 182 may include W, WN, Ru, Ti, TiN, Ta, TaN, Co, Pt, or a combination thereof. The first relay plug 181 and the second relay plug 182 may include the same material as that of the first contact plug 171 and the third contact plug 173, and may be formed at the same time.

[0098] Each of the first contact plug 171 and the third contact plug 173 may pass through the support member 75, the connection mold layer 73M, the horizontal wiring 71, the first intermediate insulating layer 68, and the second lower insulating layer 63 to contact a corresponding one of the lower conductive patterns 61. Each of the first contact plug 171 and the third contact plug 173 may directly contact the support member 75, the connection mold layer 73M, and the horizontal wiring 71. The first relay plug 181 may pass through the third intermediate insulating layer 77, the second intermediate insulating layer 76, the first intermediate insulating layer 68, and the second lower insulating layer 63 to contact a corresponding one of the lower conductive patterns 61. The second relay plug 182 may pass through the second buried insulating pattern 79, the first intermediate insulating layer 68, and the second lower insulating layer 63 to contact a corresponding one of the conductive patterns 61.

[0099] Reference Fig.30 , an intermediate wiring structure II on the lower circuit structure I, an intermediate circuit structure III on the intermediate wiring structure II, a first upper insulating layer 103 on the intermediate circuit structure III, a second upper insulating layer 105, a bit line plug 107, an upper plug 112, an isolation pattern 89, a channel structure 99, a through hole 285, and a cell contact plug 287 can be formed. The connection mold layer 73M can be partially replaced to form a connection electrode layer 73G.

[0100] The intermediate wiring structure II may include a first intermediate insulating layer 68, a horizontal wiring 71, a connection electrode layer 73G, a connection mold layer 73M, a support 75, a second intermediate insulating layer 76, a third intermediate insulating layer 77, a first buried insulating pattern 78, and a second buried insulating pattern 79. The intermediate circuit structure III may include a stacked structure 85 and an interlayer insulating layer 86. The stacked structure 85 may include wiring layers 81G and 81M and an insulating layer 83 that are repeatedly and alternately stacked. The wiring layers 81G and 81M may include an electrode layer 81G and a mold layer 81M.

[0101] The process of forming the through hole 285 and the cell contact plug 287 may include a patterning process and a thin film forming process. The through hole 285 and the cell contact plug 287 may include the same material and, therefore, may be formed at the same time. According to a specific embodiment of the inventive concept, the first relay plug 181 and the second relay plug 182 may include the same material as the first contact plug 171 and the third contact plug 173 and, therefore, may be formed at the same time. Therefore, the complexity and difficulty level of the process required to form the through hole 285 may be significantly reduced relative to the first relay plug 181 and the second relay plug 182.

[0102] Return to reference Figure 1 , a bit line 108 and an upper wiring 113 may be formed on the second upper insulating layer 105. The first upper insulating layer 103, the second upper insulating layer 105, the bit line plug 107, the bit line 108, the upper plug 112 and the upper wiring 113 may be configured differently to form an upper wiring structure IV.

[0103] Each of the connection electrode layer 73G, the electrode layer 81G, the bit line plug 107, the bit line 108, the upper plug 112, the upper wiring 113, the through hole 285 and the cell contact plug 287 may include metal, metal nitride, metal silicide, metal oxide, conductive carbon, polysilicon or a combination thereof. Each of the insulating layer 83, the mold layer 81M, the interlayer insulating layer 86, the isolation pattern 89, the first upper insulating layer 103 and the second upper insulating layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric or a combination thereof. In a specific embodiment, the mold layer 81M may include silicon nitride.

[0104] According to the embodiments of the present invention, various contact plugs, relay plugs, through-holes and cell contact plugs can be provided. However, the complexity and difficulty level associated with the process required to form the through-hole can be significantly reduced. Therefore, the semiconductor device according to the embodiments of the present invention exhibits excellent electrical characteristics while being manufactured using a simplified series of processes.

[0105] Embodiments of the inventive concept have been described with reference to the accompanying drawings, but those skilled in the art will recognize that many changes and modifications are possible to the illustrated embodiments without removing them from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: A lower circuit structure is disposed on the substrate, wherein the lower circuit structure comprises a first lower conductive pattern; an intermediate wiring structure, which is disposed on the lower circuit structure, the intermediate wiring structure comprising horizontal wiring; an intermediate circuit structure disposed on the intermediate wiring structure, the intermediate circuit structure comprising a stacked structure having wiring layers and insulating layers stacked alternately; a channel structure extending to the interior of the stack structure to contact the horizontal wiring; as well as a contact plug extending to the inside of the intermediate wiring structure to contact the first lower conductive pattern and the horizontal wiring, wherein the lowermost end of the channel structure is further away from the top surface of the substrate than the bottom surface of the horizontal wiring, The uppermost end of the contact plug is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and The uppermost end of the contact plug is disposed closer to the top surface of the substrate than the lowermost end of each of the wiring layers, Wherein, the intermediate wiring structure further includes: a support member located on the horizontal wiring; and a connecting wiring layer located between the horizontal wiring and the support member, The uppermost end of the contact plug is substantially coplanar with the uppermost end of the support member.

2. The semiconductor device according to claim 1, wherein The contact plug passes through the horizontal wiring, and top surfaces of the contact plug and the horizontal wiring are substantially coplanar.

3. The semiconductor device according to claim 1, wherein The connection wiring layer includes a connection electrode layer and a connection mold layer provided at substantially the same level as the connection electrode layer, and The contact plug passes through both the support member and the horizontal wiring, and passes through at least one of the connection mold layer and the connection electrode layer.

4. The semiconductor device according to claim 3, wherein: The connecting molding layer includes a lower molding layer, an upper molding layer on the lower molding layer, and an intermediate molding layer between the lower molding layer and the upper molding layer. The lower molding layer and the upper molding layer include silicon oxide, The middle mold layer includes silicon nitride, and The contact plug contacts side surfaces of the lower mold layer, the middle mold layer, and the upper mold layer.

5. The semiconductor device according to claim 3, wherein: A portion of the support directly contacts the horizontal wiring, The intermediate wiring structure further includes a first buried insulating pattern disposed on the portion of the support, and The contact plug passes through the first buried insulating pattern, the support, and the horizontal wiring.

6. The semiconductor device according to claim 1, further comprising: A through hole extends into the interior of the middle circuit structure, wherein the lower circuit structure further includes a second lower conductive pattern connected to the through hole.

7. The semiconductor device according to claim 6, further comprising: a cell contact plug extending into the interior of the intermediate circuit structure, The wiring layer includes an electrode layer and a mold layer, each of the mold layers is disposed at substantially the same level as a corresponding one of the electrode layers, and each of the cell contact plugs contacts a corresponding one of the electrode layers.

8. The semiconductor device according to claim 7, wherein: The uppermost ends of the through-hole and the cell contact plug are substantially coplanar.

9. The semiconductor device according to claim 6, further comprising: A relay plug is disposed between the second lower conductive pattern and the through hole and extends to an interior of the intermediate wiring structure.

10. The semiconductor device according to claim 9, wherein The uppermost end of the relay plug is substantially coplanar with the uppermost end of the contact plug.

11. The semiconductor device according to claim 9, wherein The relay plug includes the same material as the contact plug.

12. The semiconductor device according to claim 9, wherein: The intermediate wiring structure further includes a second buried insulating pattern passing through the horizontal wiring, and The relay plug passes through the second buried insulating pattern.

13. The semiconductor device according to claim 9, wherein: Top surfaces of the relay plug and the horizontal wiring are substantially coplanar.

14. The semiconductor device according to claim 9, wherein The intermediate wiring structure includes a support on the horizontal wiring, a connection wiring layer between the horizontal wiring and the support, and a second buried insulation pattern passing through the support, the connection wiring layer and the horizontal wiring, and The relay plug passes through the second buried insulating pattern.

15. The semiconductor device according to claim 14, wherein: Top surfaces of the relay plug, the second buried insulation pattern, and the support are substantially coplanar.

16. A semiconductor device comprising: A lower circuit structure is disposed on the substrate, wherein the lower circuit structure comprises a lower conductive pattern; an intermediate wiring structure, which is disposed on the lower circuit structure, the intermediate wiring structure comprising horizontal wiring; an intermediate circuit structure disposed on the intermediate wiring structure, the intermediate circuit structure comprising a stacked structure including wiring layers and insulating layers stacked alternately; Channel structures respectively extending into the interior of the stacked structures to contact the horizontal wirings; a relay plug extending to the interior of the intermediate wiring structure to contact the lower conductive pattern; a through hole, which is provided on the relay plug to extend to the interior of the intermediate circuit structure; as well as cell contact plugs, each extending into the interior of the intermediate wiring structure to contact the wiring layer, wherein the lowermost end of each of the channel structures is further away from the top surface of the substrate than the bottom surface of the horizontal wiring, The uppermost end of the relay plug is farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and The uppermost end of the relay plug is disposed closer to the top surface of the substrate than the lowermost end of each of the wiring layers.

17. The semiconductor device according to claim 16, wherein: The intermediate wiring structure includes a connection mold layer on the horizontal wiring, a support member on the connection mold layer, and a buried insulation pattern passing through the support member and the connection mold layer, The relay plug passes through the buried insulating pattern, and Top surfaces of the relay plug, the buried insulation pattern, and the support are substantially coplanar.

18. The semiconductor device according to claim 16, wherein: The uppermost end of the relay plug is substantially coplanar with the uppermost end of the horizontal wiring.

19. A semiconductor device comprising: A lower circuit structure, which is disposed on the substrate, the lower circuit structure comprising a first lower conductive pattern and a second lower conductive pattern; an intermediate wiring structure, which is disposed on the lower circuit structure, the intermediate wiring structure comprising horizontal wiring; an intermediate circuit structure disposed on the intermediate wiring structure, the intermediate circuit structure comprising a stacked structure including wiring layers and insulating layers stacked alternately; Channel structures respectively extending into the interior of the stacked structures to contact the horizontal wirings; a contact plug extending to the interior of the intermediate wiring structure to contact the first lower conductive pattern and the horizontal wiring; a relay plug extending to the interior of the intermediate wiring structure to contact the second lower conductive pattern; a through hole, which is disposed on the relay plug and extends to the interior of the intermediate circuit structure; cell contact plugs, which respectively extend into the interior of the intermediate wiring structure to contact the wiring layer; as well as an upper wiring structure disposed on the intermediate circuit structure, the upper wiring structure comprising a bit line connected to the channel structure and an upper wiring connected to the through hole, The uppermost ends of the contact plug and the relay plug are substantially coplanar. The uppermost ends of the contact plug and the relay plug are farther from the top surface of the substrate than the bottom surface of the horizontal wiring, and The uppermost ends of the contact plug and the relay plug are disposed closer to the top surface of the substrate than the lowermost end of each of the wiring layers.

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