Avalanche protection transistor using bottom breakdown current path and method of forming the same

Abstract

An avalanche protection field effect transistor includes in a semiconductor substrate: a main semiconductor layer and a doped main contact region having a first conductivity type of doping; and a source region and a drain region having a second conductivity type of doping. A buried first conductivity type well may be located in the semiconductor substrate. The buried first conductivity type well is located below the drain region and has an area overlap with the drain region in a plan view, and is spaced apart from the drain region in a vertical direction, and has a higher atomic concentration of dopants of the first conductivity type than the main semiconductor layer. The configuration of the field effect transistor induces more than 90% of the impact ionization charge to flow from the source region, through the buried first conductivity type well, and impinge on the bottom surface of the drain region during avalanche breakdown. A method for forming a semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to an avalanche protection transistor using a bottom breakdown current path and a method for forming the same. Background Art

[0002] For power applications such as automotive applications and voltage regulator modules (VRM) applications, parasitic voltages in the power loop or inductive circuits can cause significant voltage spikes and / or ringing. The device can enter avalanche mode during the switching cycle and may suffer performance degradation due to damage caused by the charge avalanche at the structural level. To prevent the device from suffering such damage during avalanche breakdown, the power device needs to be robust under unclamped inductive switching (UIS) events. To maintain circuit performance and prevent functional failure of the power semiconductor device during its lifetime, a high single pulse avalanche energy (E A A) is required. AS ) and high repetitive avalanche energy (E AR ). Summary of the Invention

[0003] An embodiment of the present invention provides a field effect transistor, comprising: a main semiconductor layer, located in a semiconductor substrate and having a first conductivity type of doping; a source region and a drain region, formed in an upper portion of the semiconductor substrate, having a second conductivity type of doping opposite to the first conductivity type, and spaced apart laterally by a channel region; a doped main contact region, formed in an upper portion of the semiconductor substrate, having a first conductivity type of doping, and spaced apart from the source region; and a buried first conductivity type well, located in the semiconductor substrate, below the drain region and having an area overlap with the drain region in a plan view, spaced apart from the drain region in a vertical direction, and having a higher atomic concentration of dopants of the first conductivity type than the main semiconductor layer.

[0004] An embodiment of the present invention provides a semiconductor chip comprising at least one avalanche protection field-effect transistor (APFET) located in a semiconductor substrate. Each of the at least one APEFET includes: a bulk semiconductor layer located in the semiconductor substrate and having a first conductivity type dopant; a source region and a drain region formed in an upper portion of the semiconductor substrate, having a second conductivity type dopant opposite to the first conductivity type, and laterally separated by a channel region; and a buried first conductivity type well located in the semiconductor substrate, below the drain region and overlapping with the drain region in plan view, vertically separated from the drain region, and having a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer. Each of the at least one APEFET has the following configuration: during avalanche breakdown, more than 90% of the impact ionization charge flows from the source region, passes through the buried first conductivity type well, and impinges on a horizontal surface of a pn junction, which is the bottom surface of the drain region, and less than 10% of the impact ionization charge impinges on a sidewall surface of the pn junction.

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a bulk semiconductor layer having a doping type of a first conductivity type; doping a surface region of the semiconductor substrate into a doped bulk contact region having a doping type of the first conductivity type; depositing a gate dielectric layer and a gate electrode layer and patterning the gate dielectric layer and the gate electrode layer to form a gate stack structure comprising a gate dielectric and a gate electrode on the semiconductor substrate; implanting a dopant of a second conductivity type opposite to the first conductivity type in an upper portion of the semiconductor substrate, wherein a source region and a drain region are formed, the source region and the drain region being laterally separated by a channel region located below the gate stack structure; and implanting a dopant of the first conductivity type before, between, or after processing steps for forming the gate stack structure, the source region, the drain region, and the doped bulk contact region, thereby forming a buried first conductivity type well located in the semiconductor substrate, wherein the buried first conductivity type well has an area overlap with the drain region in a plan view, is vertically separated from the drain region, and has a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming a shallow trench isolation structure according to an embodiment of the present disclosure.

[0008] Figure 1B is a vertical cross-sectional view of the first exemplary structure after forming a buried first conductivity type well and a buried second conductivity type well according to an embodiment of the present disclosure.

[0009] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming at least one source-side first conductivity type well, at least one doped body contact region, and a drain extension region according to an embodiment of the present disclosure.

[0010] Figure 1D is a vertical cross-sectional view of the first exemplary structure after forming at least one gate stack structure according to an embodiment of the present disclosure.

[0011] Figure 1E is a vertical cross-sectional view of the first exemplary structure after forming at least one source extension region according to an embodiment of the present disclosure.

[0012] Figure 1F is a vertical cross-sectional view of the first exemplary structure after forming dielectric gate spacers, at least one deep source region, and a deep drain region according to an embodiment of the present disclosure.

[0013] Figure 1G is a vertical cross-sectional view of the first exemplary structure after forming a contact-level dielectric layer, various metal-semiconductor alloy portions, and various contact via structures according to an embodiment of the present disclosure.

[0014] Figure 1H is Figure 1G A perspective top view of a first configuration of a first exemplary structure at a processing step.

[0015] Figure 1I is Figure 1G A perspective top view of a second configuration of the first exemplary structure at a processing step.

[0016] Figure 2A is a vertical cross-sectional view of a second exemplary structure according to an embodiment of the present disclosure.

[0017] Figure 2B yes Figure 2A A perspective top view of a second exemplary structure.

[0018] Figure 3 is a vertical cross-sectional view of a third exemplary structure according to an embodiment of the present disclosure.

[0019] Figure 4 is a vertical cross-sectional view of a fourth exemplary structure according to an embodiment of the present disclosure.

[0020] Figure 5AIt is a vertical cross-sectional view of the fifth exemplary structure after forming a shallow trench isolation structure, a buried first conductivity type well and a buried second conductivity type well, at least one source side first conductivity type well, at least one doped body contact region and a drain extension region according to an embodiment of the present disclosure.

[0021] Figure 5B is a vertical cross-sectional view of the fifth exemplary structure after forming a contact-level dielectric layer, various metal-semiconductor alloy portions, and various contact via structures according to an embodiment of the present disclosure.

[0022] Figure 6 is a vertical cross-sectional view of a sixth exemplary structure according to an embodiment of the present disclosure.

[0023] Figure 7 is a vertical cross-sectional view of a seventh exemplary structure according to an embodiment of the present disclosure.

[0024] Figure 8 is a vertical cross-sectional view of an eighth exemplary structure according to an embodiment of the present disclosure.

[0025] Figure 9A It is a vertical cross-sectional view of the ninth exemplary structure after forming a shallow trench isolation structure, a buried first conductivity type well, a buried second conductivity type well, at least one source side first conductivity type well, at least one doped body contact region, a drain extension region, at least one gate electrode and at least one source extension region according to an embodiment of the present disclosure.

[0026] Figure 9B is a vertical cross-sectional view of the ninth exemplary structure after forming a buried first conductivity type well and a buried second conductivity type well according to an embodiment of the present disclosure.

[0027] Figure 9C is a vertical cross-sectional view of the ninth exemplary structure after forming at least one source extension region, a dielectric gate spacer, at least one deep source region, and a deep drain region according to an embodiment of the present disclosure.

[0028] Figure 9D is a vertical cross-sectional view of the ninth exemplary structure after forming a contact-level dielectric layer, various metal-semiconductor alloy portions, and various contact via structures according to an embodiment of the present disclosure.

[0029] Figure 10 is a vertical cross-sectional view of a tenth exemplary structure according to an embodiment of the present disclosure.

[0030] Figure 11 is a vertical cross-sectional view of an eleventh exemplary structure according to an embodiment of the present disclosure.

[0031] Figure 12is a vertical cross-sectional view of a twelfth exemplary structure according to an embodiment of the present disclosure.

[0032] Figure 13 is a vertical cross-sectional view of a thirteenth exemplary structure according to an embodiment of the present disclosure.

[0033] Figure 14 is a vertical cross-sectional view of a fourteenth exemplary structure according to an embodiment of the present disclosure.

[0034] Figure 15 is a vertical cross-sectional view of a fifteenth exemplary structure according to an embodiment of the present disclosure.

[0035] Figure 16 is a vertical cross-sectional view of a sixteenth exemplary structure according to an embodiment of the present disclosure.

[0036] Figure 17 is a vertical cross-sectional view of an exemplary structure after forming a metal interconnect structure, a dielectric material layer, a bonding pad, and a passivation dielectric layer according to an embodiment of the present disclosure.

[0037] Figure 18 is a top view of a semiconductor chip incorporating any of the above exemplary structures according to an embodiment of the present disclosure.

[0038] Figure 19 is a graph of voltage-current during avalanche breakdown of a test sample embodying an exemplary structure of the present disclosure and a comparative exemplary test sample.

[0039] Figure 20A is a first flow chart illustrating steps for forming the avalanche protection field effect transistor of the present disclosure according to an embodiment of the present disclosure.

[0040] Figure 20B is a second flow chart illustrating steps for forming the avalanche protection field effect transistor of the present disclosure according to an embodiment of the present disclosure.

[0041] Figure 20C is a third flow chart illustrating steps for forming the avalanche protection field effect transistor of the present disclosure according to an embodiment of the present disclosure.

[0042] Figure 20D is a fourth flow chart illustrating steps for forming the avalanche protection field effect transistor of the present disclosure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed "above" or "on" a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0045] The present disclosure relates generally to semiconductor devices, and more particularly to avalanche protection transistors using a bottom breakdown current path and methods of forming the same.

[0046] In power applications of semiconductor devices, parasitic inductance can cause high voltage overshoots and lead to degradation of on-current in semiconductor devices. For example, a reduction of about 10% in on-current is typically observed under 100 hours of stress under voltage overshoot conditions. The reason for the degradation of on-current may be due to impact ionization at the drain side edge of the gate dielectric during a charge carrier avalanche event. Embodiments of the present disclosure provide semiconductor structures that can inherently protect the gate dielectric from avalanche breakdown. The semiconductor structures of embodiments of the present disclosure can provide excellent reliability under high voltage, high current and / or high-speed switching conditions without performance degradation or with minimal performance degradation.

[0047] For example, a buried doped well can be formed within a field effect transistor (FET) by ion implanting electrical dopants of the same conductivity type as the bulk region of the field effect transistor. Such a field effect transistor with a buried doped well can have a configuration that induces breakdown at the bottom of the drain region without inducing breakdown at the sidewalls of the drain region. The buried doped well functions similarly to a Zener diode. The drain region forms a pn junction with an underlying semiconductor material portion overlying the buried doped well. The underlying semiconductor material portion can be a bulk semiconductor layer or a buried well extension region.

[0048] The avalanche breakdown path provided at the bottom of the drain region can increase the single pulse avalanche energy (E AS ) and repetitive avalanche energy (E AR ). The buried doped well can be formed by global bottom breakdown implantation or by local bottom breakdown implantation. Various aspects of the embodiments of the present disclosure are described in detail below.

[0049] refer to Figure 1A , illustrating a first exemplary structure according to an embodiment of the present disclosure, the first exemplary structure comprising a semiconductor substrate 8. At least an upper portion of the semiconductor substrate 8 comprises a layer of semiconductor material having a doping of a first conductivity type, which is subsequently used to form a body region of the field effect transistor and is referred to herein as a body semiconductor layer 709. The semiconductor substrate 8 may be a bulk substrate entirely comprising semiconductor material, such as a commercially available single crystal silicon substrate having a thickness in the range of 500 microns to 1 mm.

[0050] Shallow trenches may be formed through the front surface (i.e., top surface) of semiconductor substrate 8. For example, a photoresist layer may be applied over the front surface of semiconductor substrate 8 and patterned photolithographically to cover each device region. The device region may be a corresponding portion of bulk semiconductor layer 709 that may subsequently be used to form a semiconductor device (e.g., a field-effect transistor). An etching process (e.g., a reactive ion etching process) may be performed to recess unmasked portions of semiconductor substrate 8, thereby forming shallow trenches that protrude downward from a horizontal plane including the top surface of semiconductor substrate 8. The shallow trenches may laterally surround an upper portion of semiconductor substrate 8 where a corresponding semiconductor device may subsequently be formed. At least one dielectric material (e.g., silicon oxide) may be deposited in the shallow trenches. Excess portions of the at least one dielectric material may be removed from above the horizontal plane including the top surface of semiconductor substrate 8. For example, a chemical mechanical planarization (CMP) process may be used to remove the excess portions of the at least one dielectric material. The remaining portion of the at least one dielectric material filling the shallow trench constitutes shallow trench isolation structure 720. The depth of shallow trench isolation structure 720 may be in the range of 80 nm to 800 nm (eg, 160 nm to 400 nm), although lesser and greater depths may also be used.

[0051] The bulk semiconductor layer 709 may be doped with a first conductivity type, which may be p-type or n-type. The bulk semiconductor layer 709 may have the same doping level as the initial semiconductor substrate provided, or may have a different doping level, which may be adjusted by implanting a dopant of the first conductivity type or by epitaxially depositing a doped semiconductor material. In one embodiment, the bulk semiconductor layer 709 may have a uniform dopant concentration throughout. In an illustrative example, the bulk semiconductor layer 709 may include an atomic concentration of 1.0×10 14 / cm 3 to 3.0×10 17 / cm 3 (e.g. 1.0×10 15 / cm 3 to 1.0×10 17 / cm 3 ) range of a first conductivity type dopant.

[0052] refer to Figure 1B, a buried first conductivity type well 711 and a buried second conductivity type well 712 can be formed by performing an ion implantation process. The buried first conductivity type well 711 can be formed by a first blanket ion implantation process (i.e., implantation without using an implantation mask). The first blanket ion implantation process can implant the first conductivity type dopant to an implantation depth located at a depth approximately at the bottom surface of the shallow trench isolation structure 720. Due to the randomness of the depth of the implanted first conductivity type dopant, the buried first conductivity type well 711 can be formed with a finite thickness. This finite thickness can be in the range of 20 nm to 600 nm (e.g., 40 nm to 300 nm). The interface between the buried first conductivity type well 711 and the main semiconductor layer 709 can be defined as a contour line, at which the atomic concentration of the first conductivity type dopant is 200% of the average atomic concentration of the first conductivity type dopant in the main semiconductor layer 709 before the first blanket ion implantation process. The planar interface between the bulk semiconductor layer 709 and the buried first conductivity type well 711 can be in the range of 200 nm to 2,000 nm, although smaller and larger depths can also be used. The average atomic concentration of the first conductivity type dopant in the buried first conductivity type well 711 can be in the range of 1.0×10 17 / cm 3 to 1.0×10 19 / cm 3 (e.g. 3.0×10 17 / cm 3 to 3.0×10 18 / cm 3 The average atomic concentration of the dopant of the first conductivity type in the buried first conductivity type well 711 may be high enough to provide sufficient conductivity for charge carriers during avalanche breakdown, and low enough to prevent premature breakdown at low voltages occurring during normal operation of the field effect transistor.

[0053] The top surface of the buried first conductivity type well 711 may be located above a horizontal plane including the bottom surface of the shallow trench isolation structure 720. In this embodiment, each bulk semiconductor layer 709 may be laterally confined within the sidewalls of the corresponding shallow trench isolation structure 720, and may be vertically confined between the top surface of the buried first conductivity type well 711 and the front surface (i.e., top surface) of the semiconductor substrate 8. Initially, Figure 1AThe remaining portion of the bulk semiconductor layer 709 provided at the processing step and now located below the buried first conductivity type well 711 is not subsequently used as the body region of the field effect transistor and, as such, is hereinafter referred to as the substrate semiconductor layer 719. The substrate semiconductor layer 719 may have the same atomic concentration of dopants of the first conductivity type as the bulk semiconductor layer 709. In one embodiment, the buried first conductivity type well 711 may be formed as a single continuous layer that extends continuously below all device regions and below all shallow trench isolation structures 720. In addition, the bottom surface of the buried first conductivity type well 711 may be formed above a horizontal plane including the bottom surface of the shallow trench isolation structure 720, and a plurality of separate buried first conductivity type wells 711 may be formed. In this embodiment, each buried first conductivity type well 711 may be laterally surrounded by a corresponding shallow trench isolation structure 720 and may laterally contact the corresponding shallow trench isolation structure 720.

[0054] The buried second conductivity type well 712 can be formed by a second blanket ion implantation process, which can be performed after or before the first blanket ion implantation process. The second blanket ion implantation process can implant the second conductivity type dopant to an implantation depth that can be below the depth of the bottom surface of the shallow trench isolation structure 720. Due to the randomness of the depth of the implanted second conductivity type dopant, the buried second conductivity type well 712 can be formed with a finite thickness. This finite thickness can be in the range of 20nm to 600nm (for example, 40nm to 300nm). A pn ​​junction can be formed between the buried second conductivity type well 712 and each of the buried first conductivity type well 711 and the substrate semiconductor layer 719. The average atomic concentration of the second conductivity type dopant in the buried second conductivity type well 712 can be in the range of 1.0×10 17 / cm 3 to 1.0×10 19 / cm 3 (e.g. 3.0×10 17 / cm 3 to 3.0×10 18 / cm 3 The average atomic concentration of the second conductivity type dopant in the buried second conductivity type well 712 may be high enough to provide sufficient conductivity for charge carriers to serve as an auxiliary conduction path during avalanche breakdown, and low enough to prevent the buried second conductivity type well 712 from serving as a conduction path at low voltages occurring during normal operation of the field effect transistor.

[0055] While the process of forming the first exemplary structure is described using an embodiment in which a buried first conductivity type well 711 and a buried second conductivity type well 712 are formed sequentially, embodiments in which at least one of the ion implantation processes for forming the buried first conductivity type well 711 and / or the buried second conductivity type well 712 can be performed in parallel or simultaneous processing steps are expressly contemplated herein. Generally speaking, the buried first conductivity type well 711 and / or the buried second conductivity type well 712 can be formed before, between, or after the processing steps used to form the gate stack structure, source region, drain region, and doped body contact region. In embodiments in which the buried first conductivity type well 711 is formed as a continuous layer over the entire area of ​​the semiconductor substrate 8, the buried first conductivity type well 711 can overlap in area with each of the gate stack structure, source region, drain region, and doped body contact region to be formed subsequently. Regarding the electrical dopant species, boron or indium can be used as a p-type dopant during the ion implantation process, and phosphorus, arsenic, and / or antimony can be used as an n-type dopant.

[0056] refer to Figure 1C , a first shielded ion implantation process can be used to implant dopants of the first conductivity type into at least one surface region of the main semiconductor layer 709 to form at least one doped main contact region 731. Each of the at least one doped main contact region 731 can be a heavily doped semiconductor region having a dopant of the first conductivity type and can be used to provide electrical contact with the main semiconductor layer 709. In one embodiment, the at least one doped main contact region 731 can be formed adjacent to the shallow trench isolation structure 720. The at least one doped main contact region 731 can be heavily doped to provide high electrical conductivity. For example, the at least one doped main contact region 731 can include an average atomic concentration of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The depth of the flat bottom surface of each doped body contact region 731 can be in the range of 50 nm to 200 nm, although smaller and larger depths can also be used. The at least one doped body contact region 731 can be vertically spaced apart from the buried first conductivity type well 711.

[0057] A second shielded ion implantation process may be used to implant additional dopants of the first conductivity type into the bulk semiconductor layer 709 to form at least one source-side first conductivity type well 721. The ion implantation energy of the second shielded ion implantation process may be selected such that each source-side first conductivity type well 721 extends vertically from the front surface of the semiconductor substrate 8 (i.e., the top surface of the bulk semiconductor layer 709) to the top surface of the buried first conductivity type well 711. In one embodiment, the at least one source-side first conductivity type well 721 may vertically connect the buried first conductivity type well 711 to the corresponding doped body contact region 731. In one embodiment, the at least one source-side first conductivity type well 721 may be formed adjacent to the shallow trench isolation structure 720. The at least one source-side first conductivity type well 721 may have a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709. The at least one source-side first conductivity type well 721 may be doped to a level that provides a sufficient resistivity level to enable the at least one source-side first conductivity type well 721 to function as a conductive path during avalanche breakdown, but insufficient to function as a conductive path during normal operation of the field effect transistor. For example, the at least one source-side first conductivity type well 721 may include an average atomic concentration of 1.0×10 18 / cm 3 to 5.0×10 19 / cm 3 In one embodiment, each doped body contact region 731 may contact a combination of a source-side first conductivity type well 721 and a shallow trench isolation structure 720 and may be laterally bounded by the combination of the source-side first conductivity type well 721 and the shallow trench isolation structure 720.

[0058] A third shielded ion implantation process can be used to implant dopants of the second conductivity type into the surface region of the bulk semiconductor layer 709 to form a drain extension region 736. The drain extension region 736 can be a region doped with the second conductivity type and located below the end of the gate dielectric, serving as a drain region. The drain extension region 736 can determine the voltage-current characteristics of the field-effect transistor by determining the location of the pn junction on the drain side of the field-effect transistor. Furthermore, the atomic concentration of the dopant of the second conductivity type in the drain extension region 736 determines the electric field profile on the drain side during operation of the field-effect transistor. In one embodiment, the field-effect transistor can be designed to have an asymmetric extension profile between the source and drain sides, and the overlap area between the drain extension region 736 and the gate dielectric to be formed later can be greater than the overlap area between the source extension region and the gate dielectric. The atomic concentration of the dopant of the second conductivity type in the drain extension region 736 can be lower than the atomic concentration of the dopant of the second conductivity in the deep source and deep drain regions to be formed later. For example, drain extension region 736 may include an average atomic concentration of 1.0×10 18 / cm 3 to 1.0×10 20 / cm 3 The drain extension region 736 may include a dopant of the second conductivity type in the range of 10 nm to 20 nm. The depth of the bottom surface of the drain extension region 736 may be in the range of 20 nm to 100 nm, although smaller and larger depths may also be used. The drain extension region 736 may be laterally separated from the source-side first conductivity type well 721 by a surface portion of the bulk semiconductor layer 709 in which a semiconductor channel will subsequently be formed.

[0059] refer to Figure 1D , a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer may be deposited to sequentially form the gate dielectric layer, the gate electrode layer, and the gate cap dielectric layer over the front surface of the semiconductor substrate 8. A photoresist layer 759 may be applied over the gate cap dielectric layer and patterned photolithographically into a gate pattern, which may extend across a corresponding portion of the bulk semiconductor layer 709. For example, each lithographically patterned portion of the photoresist layer 759 may overlie a portion of the bulk semiconductor layer 709 that extends to the front surface of the semiconductor substrate 8. Thus, a process for patterning the gate dielectric layer, the gate electrode layer, and the gate cap dielectric layer may be achieved.

[0060] An anisotropic etching process may be performed to transfer the pattern in the photoresist layer 759 to the gate cap dielectric layer, the gate electrode layer, and the gate dielectric layer. A stack of gate dielectrics 752, gate electrodes 754, and gate cap dielectrics 758 may be formed. Each gate dielectric 752 includes a patterned portion of the gate dielectric layer. Each gate electrode 754 includes a patterned portion of the gate electrode layer. Each gate cap dielectric includes a patterned portion of the gate cap dielectric layer. Subsequently, the photoresist layer 759 may be removed, for example, by ashing. Each gate electrode 754 may overlie a portion of a corresponding drain extension region in the drain extension region 736 and may overlie a peripheral portion of a corresponding source-side first conductivity type well in the source-side first conductivity type well 721.

[0061] refer to Figure 1E At least one source extension region 734 may be formed by implanting dopants through a shielded ion implantation process. The combination of the patterned photoresist layer 757, the gate electrode 754, and the gate cap dielectric 758 may be used as a composite implantation mask. Dopants of the second conductivity type may be implanted into portions of the source-side first conductivity type well 721 that are not shielded by the photoresist layer 757, the gate electrode 754, or the gate cap dielectric 758 to form at least one source extension region 734. Each source extension region 734 may include an average atomic concentration of 5.0×10 18 / cm 3 to 1.0×10 21 / cm 3 The source extension region 734 may have a dopant of the second conductivity type in the range of 10 nm to 20 nm. The depth of the bottom surface of each source extension region 734 may be in the range of 20 nm to 100 nm, but smaller and larger depths may also be used. The source extension region 734 may have the same dopant concentration as the drain extension region 736 or may have a higher dopant concentration than the drain extension region 736. Each source extension region 734 may be laterally separated from the drain extension region 736 by a surface portion of the bulk semiconductor layer 709 and a surface portion of the source-side first conductivity type well 721, which may form a channel region 735. Each channel region 735 may be a semiconductor channel of a field effect transistor. Subsequently, the photoresist layer 757 may be removed, for example, by ashing.

[0062] refer to Figure 1F , a dielectric gate spacer 756 may be formed on the stack of gate dielectric 752, gate electrode 754, and gate cap dielectric 758. For example, a dielectric material layer may be conformally deposited and anisotropically etched to form dielectric gate spacer 756. Each set of gate dielectric 752, gate electrode 754, gate cap dielectric 758, and at least one dielectric gate spacer 756 forms a gate stack structure (752, 754, 758, 756).

[0063] A photoresist layer 755 may be applied over the semiconductor substrate 8 and the gate stack structures (752, 754, 758, 756), and the photoresist layer 755 may be patterned to form openings through the photoresist layer 755. The openings through the photoresist layer 755 may be formed around the gate stack structures (752, 754, 758, 756) such that outer edges of the dielectric gate spacers 756 are physically exposed within the openings through the photoresist layer 755. The photoresist layer 755 covers the doped body contact regions 731.

[0064] Dopants of the second conductivity type may be implanted into surface portions of the semiconductor substrate 8 that are not shielded by the photoresist layer 755 or the gate stack structure 750 including the elements (752, 754, 758, 756). The surface portion of the semiconductor substrate 8 implanted with dopants of the second conductivity type includes at least one deep source region 732 and a deep drain region 738. The at least one deep source region 732 and the deep drain region 738 may be heavily doped with dopants of the second conductivity type to provide high conductivity. The atomic concentration of the dopant of the second conductivity type in the implanted region may be higher than the atomic concentration of the dopant of the second conductivity type in the source extension region 734 and the drain extension region 736. For example, the at least one deep source region 732 and the deep drain region 738 may include an average atomic concentration of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 (e.g. 1.0×10 20 / cm 3 to 1.0×10 21 / cm 3 ) range. Subsequently, the photoresist layer 755 can be removed, for example, by ashing. The bottom surface of the at least one deep source region 732 and the bottom surface of the deep drain region 738 can have a depth in the range of 100 nm to 1,600 nm (e.g., 200 nm to 800 nm), although smaller and larger depths can also be used.

[0065] Each combination of the deep source region 732 and the source extension region 734 constitutes a source region (732, 734). Each combination of the deep drain region 738 and the drain extension region 736 constitutes a drain region (736, 738). The source regions (732, 734) and the drain regions (736, 738) may be laterally separated by a channel region 735 located below the corresponding gate stack structure (752, 754, 758, 756). In one embodiment, the source-side first conductivity type well 721 may laterally surround the source regions (732, 734) and may form a pn junction with the source regions (732, 734). In one embodiment, the channel region 735 may be located below the gate dielectric 752 and may laterally extend through an upper portion of the source-side first conductivity type well 721 and through an upper portion of the bulk semiconductor layer 709.

[0066] In one embodiment, the source region (732, 734) and the drain region (736, 738) of the field effect transistor may have asymmetric extensions, such that the overlap of the drain extension region 736 with the gate electrode 754 in a plan view is greater than the overlap of the source extension region 734 with the gate electrode 754 in a plan view. A plan view refers to a view along a direction perpendicular to the front surface of the semiconductor substrate 8.

[0067] refer to Figure 1G 、 Figure 1H and Figure 1I A contact-level dielectric layer 770 may be formed on the semiconductor substrate 8 and the gate stack structure ( 752 , 754 , 758 , 756 ). Figure 1G is a vertical cross-sectional view of a first configuration of the first exemplary structure, Figure 1H is a partial perspective top view of a first configuration of the first exemplary structure, Figure 1H The contact level dielectric layer 770 is not shown, and Figure 1I is a partial perspective top view of a second configuration of the first exemplary structure, Figure 1I The contact-level dielectric layer 770 is not shown. Figure 1H and Figure 1I The two configurations described in Figure 1G Each top view is a plan view in which, in addition to omitting the contact-level dielectric layer 770, underlying structural elements that are obscured by overlying structural elements are not shown.

[0068] The contact-level dielectric layer 770 may include a dielectric material (e.g., silicon oxide or organosilicate glass) and may be formed by a conformal deposition process or a non-conformal deposition process. The top surface of the contact-level dielectric layer 770 may be planarized, for example, by a chemical mechanical planarization process. A via cavity may be formed through the contact-level dielectric layer 770 over each of the doped body contact region 731, the source regions 732, 734, and the drain regions 736, 738.

[0069] A metal layer may be deposited in the via cavity and react with underlying semiconductor material portions of the doped body contact region 731, the source regions 732, 734, and the drain regions 736, 738 to form various metal-semiconductor alloy portions 741, 742, 748. The metal-semiconductor alloy portions 741, 742, 748 may include at least one body-contact metal-semiconductor alloy portion 741, at least one source-contact metal-semiconductor alloy portion 742, and a drain-contact metal-semiconductor alloy portion 748. Unreacted portions of the metal layer may be removed, for example, by a wet etching process that selectively removes material of the metal layer relative to the metal-semiconductor alloy material of the metal-semiconductor alloy portions 741, 742, 748. In one embodiment, the metal-semiconductor alloy portions 741, 742, 748 may include a metal silicide material, such as nickel silicide, titanium silicide, tungsten silicide, or the like. Other suitable materials are within the scope of this disclosure.

[0070] At least one conductive material may be deposited in the remaining volume of the via cavity. For example, a metal liner material (e.g., TiN, TaN, or WN) may be deposited in the remaining volume of the via cavity, and then a conductive fill material (e.g., tungsten) may be deposited. Excess portions of the at least one conductive material may be removed from a level above the top surface of the contact-level dielectric layer 770. The remaining portions of the at least one conductive material filling the via cavity constitute contact via structures (771, 772, 778). The contact via structures (771, 772, 778) may include: at least one body contact via structure 771 contacting a corresponding body contact metal semiconductor alloy portion 741; at least one source contact via structure 772 contacting a corresponding source contact metal semiconductor alloy portion 742; and a drain contact via structure 778 contacting the drain contact metal semiconductor alloy portion 748.

[0071] The drain regions (736, 738) form a pn junction with the bulk semiconductor layer 709. The buried first conductivity type well 711 may overlap with the entire drain regions (736, 738) in a plan view and may be vertically separated from the drain regions (736, 738) by a lateral extension of the bulk semiconductor layer 709. The buried first conductivity type well 711 may have a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709.

[0072] The buried first conductivity type well 711 can be formed by performing an ion implantation process before forming the gate stack structure (752, 754, 758, 756), and can overlap in plan view with the entire source region (732, 734), the drain region (736, 738), and the doped body contact region 731. If the ion implantation process is performed before forming the gate stack structure (752, 754, 758, 756), the entire top surface of the buried first conductivity type well 711 can be flat, and the entire bottom surface of the buried first conductivity type well 711 can be flat (i.e., located in a horizontal plane).

[0073] In one embodiment, the shallow trench isolation structure 720 may laterally surround the source region (732, 734), the drain region (736, 738), and the doped body contact region 731. In one embodiment, the entire closed perimeter of the interface between the top surface of the buried first conductivity type well 711 and the bulk semiconductor layer 709 continuously contacts the sidewalls of the shallow trench isolation structure 720.

[0074] In general, the field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of the impact ionization charge flows from the source region (732, 734), passes through the buried first conductivity type well 711, and impinges on the horizontal surface of the pn junction, which is the bottom surface of the drain region (736, 738). The drain region (736, 738) may include a drain extension region 736 and a deep drain region 738 having a greater depth than the drain extension region 736. In one embodiment, the field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of the impact ionization charge flows from the source region (732, 734), passes through the buried first conductivity type well 711, and impinges on the horizontal surface of the pn junction, which is the bottom surface of the deep drain region 738. The bottom surface of deep drain region 738 may be located at a greater depth than the bottom surface of drain extension region 736. Less than 10% (may be less than 5%, and / or less than 2%, and / or less than 1%) of the charges may impinge on sidewall surfaces of the pn junction between drain regions (736, 738) above the bottommost surface of the drain regions (736, 738), which is the bottom surface of deep drain region 738.

[0075] refer to Figure 2A and Figure 2B The second exemplary structure according to an embodiment of the present disclosure can be derived from the first exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. Specifically, the doped body contact region 731, the source regions (732, 734), and the drain regions (736, 738) can be arranged with a uniform width throughout the horizontal direction, which is the lateral separation distance between the two parallel portions of the shallow trench isolation structure 720. The second exemplary structure is an alternative configuration to the first exemplary structure.

[0076] refer to Figure 3 , a third exemplary structure according to an embodiment of the present disclosure can be derived from the first exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the top surface of the substrate semiconductor layer 719. The third exemplary structure is an alternative configuration to the first exemplary structure and / or the second exemplary structure.

[0077] refer to Figure 4, a fourth exemplary structure according to an embodiment of the present disclosure can be derived from the second exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the top surface of the substrate semiconductor layer 719. In addition, the fourth exemplary structure can be derived from the third exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731.

[0078] Generally speaking, the buried first conductivity type well 711 can be formed within the semiconductor substrate 8 by implanting a first conductivity type dopant before, between, or after the processing steps for forming the gate stack structures (752, 754, 758, 756), the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. Furthermore, the lateral extent of each of the buried first conductivity type well 711 and the buried second conductivity type well 712 can be limited by using a patterned photoresist layer as an implantation mask during the ion implantation process for forming the buried first conductivity type well 711 and the buried second conductivity type well 712. The fourth exemplary structure is an alternative configuration to any of the first to third exemplary structures.

[0079] refer to Figure 5A , illustrating a fifth exemplary structure according to an embodiment of the present disclosure. The lateral extent of each of the buried first conductive type well 711 and the buried second conductive type well 712 can be limited from Figure 1C The fifth exemplary structure is derived from the first exemplary structure. A patterned ion implantation mask layer (e.g., a patterned photoresist layer) can be used during the ion implantation process for forming the buried first conductivity type well 711 and the buried second conductivity type well 712. In one embodiment, the lateral extent of the buried first conductivity type well 711 can be selected so that the buried first conductivity type well 711 has an area overlap with the drain region (736, 738) in a plan view and has no area overlap with the doped body contact region 731. In one embodiment, the buried first conductivity type well 711 can have an area overlap with the entire drain region (736, 738) in a plan view. In one embodiment, the ion implantation process for forming the buried first conductivity type well 711 and the buried second conductivity type well 712 can be performed using the same ion implantation mask. The ion implantation process for forming the buried first conductivity type well 711 and the buried second conductivity type well 712 can be performed at any processing step before forming the gate electrode 754. In this embodiment, each of the buried first conductivity type well 711 and the buried second conductivity type well 712 may have a respective horizontal top surface and a respective horizontal bottom surface.

[0080] In one embodiment, the lateral extent of the buried first conductivity type well 711 can be selected so that the source-side first conductivity type well 721 connects the doped body contact region 731 and the buried first conductivity type well 711. The buried second conductivity type well 712 can be located below the buried first conductivity type well 711 and can form a pn junction with the buried first conductivity type well 711.

[0081] refer to Figure 5B , feasible Figure 1D to Figure 1I The process steps are as follows: a gate stack structure (752, 754, 758, 756), at least one source region (732, 734), a drain region (736, 738), a contact-level dielectric layer 770, a metal-semiconductor alloy portion (741, 742, 748), and a contact via structure (771, 772, 778). The drain region (736, 738) forms a pn junction with the bulk semiconductor layer 709. The source-side first conductivity type well 721 laterally surrounds the source region (732, 734) and forms a pn junction with the source region (732, 734). The channel region 735 is located below the gate dielectric 752 and extends laterally through the upper portion of the source-side first conductivity type well 721 and through the upper portion of the bulk semiconductor layer 709. The buried first conductivity type well 711 may have an area overlap with the entire area of ​​the drain region ( 736 , 738 ) in a plan view, and may not overlap with the area of ​​the doped body contact region 731 in a plan view.

[0082] The field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of impact ionization charges flow from the source regions (732, 734), pass through the buried first conductivity type well 711, and impinge on a horizontal surface of the pn junction, which is the bottom surface of the drain regions (736, 738). The drain regions (736, 738) may include a drain extension region 736 and a deep drain region 738 having a greater depth than the drain extension region 736. In one embodiment, the field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of impact ionization charges flow from the source regions (732, 734), pass through the buried first conductivity type well 711, and impinge on a horizontal surface of the pn junction, which is the bottom surface of the deep drain region 738. The bottom surface of deep drain region 738 may be located at a greater depth than the bottom surface of drain extension region 736. Less than 10% (may be less than 5%, and / or less than 2%, and / or less than 1%) of the charges may impinge on the sidewall surfaces of the pn junction between drain regions (736, 738) above the bottommost surface of the drain regions (736, 738), which is the bottom surface of deep drain region 738. The fifth exemplary structure is an alternative configuration of any one of the first to fourth exemplary structures.

[0083] refer to Figure 6 The sixth exemplary structure according to an embodiment of the present disclosure can be derived from the fifth exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. Specifically, the doped body contact region 731, the source regions (732, 734), and the drain regions (736, 738) can be arranged with a uniform width throughout the horizontal direction, which is the lateral separation distance between the two parallel portions of the shallow trench isolation structure 720. The sixth exemplary structure is an alternative configuration to any of the first to fifth exemplary structures.

[0084] refer to Figure 7 The seventh exemplary structure according to an embodiment of the present disclosure can be derived from the fifth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the horizontal surface of the bulk semiconductor layer 709. The seventh exemplary structure is an alternative configuration to any of the first to sixth exemplary structures.

[0085] refer to Figure 8The eighth exemplary structure according to an embodiment of the present disclosure can be derived from the sixth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the top surface of the substrate semiconductor layer 719. Furthermore, the eighth exemplary structure can be derived from the seventh exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. The eighth exemplary structure is an alternative configuration to any of the first to seventh exemplary structures.

[0086] refer to Figure 9A , which can be omitted Figure 1B The processing steps from Figure 1E The first exemplary structure of derives a ninth exemplary structure according to an embodiment of the present disclosure. In other words, Figure 1B The buried first conductivity type well 711 and the buried second conductivity type well 712 are not formed in the processing step.

[0087] refer to Figure 9B A photoresist layer 767 may be formed over the semiconductor substrate 8 and the gate electrode 754, and the photoresist layer 767 may be patterned photolithographically to form openings between the gate electrodes 754 or between the gate electrode 754 and the shallow trench isolation structure 720. Dopants of the first conductivity type may be implanted into portions of the bulk semiconductor layer 709 not shielded by the photoresist layer 767 or the gate electrode 754 to form a buried first conductivity type well 711. The buried first conductivity type well 711 may have a lateral extent limited by the lateral distance between the two gate electrodes 754 or by the lateral distance between the gate electrode 754 and the shallow trench isolation structure 720. The depth and material composition of the buried first conductivity type well 711 may be the same as in the first exemplary structure. Dopants of the second conductivity type may be implanted into portions of the bulk semiconductor layer 709 not shielded by the photoresist layer 767 or the gate electrode 754 to form a buried second conductivity type well 712. The buried second conductivity type well 712 can have a lateral extent limited by the lateral distance between the two gate electrodes 754 or by the lateral distance between the gate electrode 754 and the shallow trench isolation structure 720. The depth and material composition of the buried second conductivity type well 712 can be the same as in the first exemplary structure. The buried second conductivity type well 712 is located below the buried first conductivity type well 711 and forms a pn junction with the buried first conductivity type well 711. Each source-side first conductivity type well 721 can be laterally separated from the buried first conductivity type well 711 by a portion of the bulk semiconductor layer 709 located below the gate dielectric 752.

[0088] refer to Figure 9C , feasible Figure 1F and Figure 1G to Figure 1I The processing steps are as follows to form a dielectric gate spacer 756, at least one deep source region 732, and a deep drain region 738. The drain regions (736, 738) form a pn junction with the main semiconductor layer 709. The buried first conductivity type well 711 has an area overlap with the drain regions (736, 738) in a plan view and has no area overlap with the doped body contact region 731. In one embodiment, the buried first conductivity type well 711 may have an area overlap with the entire drain regions (736, 738) in a plan view and has no area overlap with the doped body contact region 731 or with at least one source region (732, 734). The source-side first conductivity type well 721 laterally surrounds the source regions (732, 734) and forms a pn junction with the source regions (732, 734). The channel region 735 is located below the gate dielectric 752 and extends laterally through an upper portion of the source-side first conductivity type well 721 and through an upper portion of the bulk semiconductor layer 709 .

[0089] refer to Figure 9D , feasible Figure 1G to Figure 1I The processing steps are to form the contact level dielectric layer 770, the metal semiconductor alloy portion (741, 742, 748) and the contact through-hole structure (771, 772, 778).

[0090] The field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of impact ionization charges flow from the source regions (732, 734), pass through the buried first conductivity type well 711, and impinge on a horizontal surface of the pn junction, which is the bottom surface of the drain regions (736, 738). The drain regions (736, 738) may include a drain extension region 736 and a deep drain region 738 having a greater depth than the drain extension region 736. In one embodiment, the field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of impact ionization charges flow from the source regions (732, 734), pass through the buried first conductivity type well 711, and impinge on a horizontal surface of the pn junction, which is the bottom surface of the deep drain region 738. The bottom surface of deep drain region 738 may be located at a greater depth than the bottom surface of drain extension region 736. Less than 10% (may be less than 5%, and / or less than 2%, and / or less than 1%) of the charges may impinge on the sidewall surfaces of the pn junction between drain regions (736, 738) above the bottommost surface of the drain regions (736, 738), which is the bottom surface of deep drain region 738. The ninth exemplary structure is an alternative configuration of any one of the first to eighth exemplary structures.

[0091] refer to Figure 10 The tenth exemplary structure according to an embodiment of the present disclosure can be derived from the ninth exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. Specifically, the doped body contact region 731, the source regions (732, 734), and the drain regions (736, 738) can be arranged with a uniform width throughout the horizontal direction, which is the lateral separation distance between the two parallel portions of the shallow trench isolation structure 720. In this case, the buried first conductivity type well 711 and the buried second conductivity type well 712 can be located below the drain regions (736, 738) and extend to the region below the sidewalls of the shallow trench isolation structure 720. The tenth exemplary structure is an alternative configuration of any of the first to ninth exemplary structures.

[0092] refer to Figure 11 The eleventh exemplary structure according to an embodiment of the present disclosure can be derived from the ninth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the horizontal surface of the bulk semiconductor layer 709. The eleventh exemplary structure is an alternative configuration to any of the first to tenth exemplary structures.

[0093] refer to Figure 12 The twelfth exemplary structure according to an embodiment of the present disclosure can be derived from the tenth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the underlying portion of the bulk semiconductor layer 709. Furthermore, the twelfth exemplary structure can be derived from the eleventh exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped bulk contact region 731. The twelfth exemplary structure is an alternative configuration to any of the first to eleventh exemplary structures.

[0094] refer to Figure 13 , the thirteenth exemplary structure according to an embodiment of the present disclosure can be derived from the ninth exemplary structure by forming a drain-side first conductivity type well 723. The drain-side first conductivity type well 723 can be formed using the same ion implantation mask as the drain extension region 736. For example, the first conductivity type dopant can be implanted while the ion implantation mask (e.g., a patterned photoresist layer) used to form the drain extension region 736 is present on the front surface of the semiconductor substrate 8. The energy of the ion implantation process for forming the drain-side first conductivity type well 723 is selected so that the drain-side first conductivity type well 723 extends continuously from below the bottom surface of the drain region (736, 738) to the top surface of the buried first conductivity type well 711.

[0095] The dose of the ion implantation process for forming the drain-side first conductivity type well 723 may be selected so that the average dopant concentration in the drain-side first conductivity type well 723 is between 1.0×10 16 / cm 3 to 3.0×10 18 / cm 3 range. The average atomic concentration of the first conductivity type dopant in the drain-side first conductivity type well 723 is higher than the atomic concentration of the first conductivity type dopant in the main semiconductor layer 709. The average dopant concentration of the first conductivity type dopant in the drain-side first conductivity type well 723 is selected to serve as a conduction path for high-energy charge carriers during avalanche breakdown conditions and not to serve as a conduction path for low-energy charge carriers during normal operation of the field effect transistor. The drain-side first conductivity type well 723 overlies the buried first conductivity type well 711 and contacts the buried first conductivity type well 711 and has a lower atomic concentration of the first conductivity type dopant than the buried first conductivity type well 711. The source-side first conductivity type well 721 may be laterally spaced apart from the buried first conductivity type well 711 and the drain-side first conductivity type well 723 by a portion of the main semiconductor layer 709 located below the gate dielectric 752. In an alternative embodiment, Figure 9B The drain-side first conductivity type well 723 is formed at the processing step using the patterned photoresist layer 767 as an ion implantation mask layer.

[0096] The field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of the impact ionization charge flows from the source region (732, 734), passes through the buried first conductivity type well 711, and impinges on a horizontal surface of the pn junction, which is the bottom surface of the drain region (736, 738). The drain region (736, 738) may include a drain extension region 736 and a deep drain region 738 having a greater depth than the drain extension region 736. In one embodiment, the field effect transistor may have a configuration such that during avalanche breakdown, more than 90% (may be more than 95%, and / or more than 98%, and / or more than 99%) of the impact ionization charge flows from the source region (732, 734), passes through the buried first conductivity type well 711, and impinges on a horizontal surface of the pn junction, which is the bottom surface of the deep drain region 738. The bottom surface of deep drain region 738 may be located at a greater depth than the bottom surface of drain extension region 736. Less than 10% (may be less than 5%, and / or less than 2%, and / or less than 1%) of the charges may impinge on the sidewall surfaces of the pn junction between drain regions (736, 738) above the bottommost surface of the drain regions (736, 738), which is the bottom surface of deep drain region 738. The thirteenth exemplary structure is an alternative configuration of any one of the first to twelfth exemplary structures.

[0097] refer to Figure 14 The fourteenth exemplary structure according to an embodiment of the present disclosure can be derived from the thirteenth exemplary structure by changing the layout of the source regions (732, 734), the drain regions (736, 738), and the doped body contact region 731. Specifically, the doped body contact region 731, the source regions (732, 734), and the drain regions (736, 738) can be arranged with a uniform width throughout the horizontal direction, which is the lateral separation distance between the two parallel portions of the shallow trench isolation structure 720. In this case, the buried first conductivity type well 711 and the buried second conductivity type well 712 can be located below the drain regions (736, 738) and extend to the region below the sidewalls of the shallow trench isolation structure 720. The fourteenth exemplary structure is an alternative configuration of any of the first to thirteenth exemplary structures.

[0098] refer to Figure 15 The fifteenth exemplary structure according to an embodiment of the present disclosure can be derived from the thirteenth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the horizontal surface of the bulk semiconductor layer 709. The fifteenth exemplary structure is an alternative configuration to any of the first to fourteenth exemplary structures.

[0099] refer to Figure 16 , the sixteenth exemplary structure according to an embodiment of the present disclosure can be derived from the fourteenth exemplary structure by omitting the formation of the buried second conductivity type well 712. In this case, the horizontal bottom surface of the buried first conductivity type well 711 can contact the horizontal surface of the bulk semiconductor layer 709. The sixteenth exemplary structure is an alternative configuration to any of the first to fifteenth exemplary structures.

[0100] In general, each of the various exemplary structures described above can include a field effect transistor. The field effect transistor can include: a bulk semiconductor layer 709 located in a semiconductor substrate 8 and having a first conductivity type doping; source regions (732, 734) and drain regions (736, 738) formed in an upper portion of the semiconductor substrate 8, having a second conductivity type doping opposite to the first conductivity type, and spaced laterally apart by a channel region 735; a doped body contact region 731 formed in an upper portion of the semiconductor substrate 8, having a first conductivity type doping and spaced apart from the source regions (732, 734); and a buried first conductivity type well 711 located in the semiconductor substrate 8, below the drain regions (736, 738), overlapping in area with the drain regions (736, 738) in a plan view, spaced apart in a vertical direction from the drain regions (736, 738), and having a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709.

[0101] In one embodiment, the source-side first conductivity type well 721 may be located within the semiconductor substrate 8 and may have a higher concentration of first conductivity type dopants than the bulk semiconductor layer 709. In one embodiment, the source-side first conductivity type well 721 connects the doped body contact region 731 and the buried first conductivity type well 711. In one embodiment, the source-side first conductivity type well 721 laterally surrounds the source regions (732, 734) and forms a pn junction with the source regions (732, 734); and the channel region 735 located below the gate dielectric 752 laterally extends through the upper portion of the source-side first conductivity type well 721 and through the upper portion of the bulk semiconductor layer 709.

[0102] In one embodiment, the source-side first conductivity type well 721 is laterally spaced apart from the buried first conductivity type well 711 by a portion of the bulk semiconductor layer 709 underlying the gate dielectric 752 .

[0103] In one embodiment, the source regions (732, 734) and the drain regions (736, 738) have asymmetric extension regions such that the drain extension region 736 overlaps a larger area with the gate electrode 754 in a plan view than the source extension region 734 overlaps an area with the gate electrode 754 in a plan view.

[0104] In one embodiment, the drain region (736, 738) forms a pn junction with the main semiconductor layer 709 or the drain-side first conductivity type well 723, and the drain-side first conductivity type well 723 overlies the buried first conductivity type well 711 and has a lower atomic concentration of the first conductivity type dopant than the buried first conductivity type well 711.

[0105] In one embodiment, the field effect transistor has the following configuration: during avalanche breakdown, more than 90% of the impact ionization charge flows from the source region (732, 734), passes through the buried first conductivity type well 711, and impinges on the horizontal surface of the pn junction, which is the bottom surface of the drain region (736, 738) (which is the bottommost surface), and less than 10% of the charge impinges on the sidewall surface of the pn junction.

[0106] In one embodiment, the buried first conductivity type well 711 has an area overlap with the entire area of ​​the source region ( 732 , 734 ), the drain region ( 736 , 738 ), and the doped body contact region 731 in a plan view.

[0107] In one embodiment, the shallow trench isolation structure 720 may laterally surround the source regions 732 and 734, the drain regions 736 and 738, and the doped body contact region 731. The entire closed perimeter of the interface between the top surface of the buried first conductivity type well 711 and the bulk semiconductor layer 709 continuously contacts the sidewalls of the shallow trench isolation structure 720.

[0108] In one embodiment, the buried first conductivity type well 711 has an area overlap with the entire area of ​​the drain region ( 736 , 738 ) in plan view and does not overlap with the area of ​​the doped body contact region 731 in plan view.

[0109] In one embodiment, the buried second conductivity type well 712 may be located below the buried first conductivity type well 711 and may form a pn junction with the buried first conductivity type well 711 .

[0110] Additional metal interconnect structures may be formed in the dielectric material layer over any of the exemplary structures described above.

[0111] refer to Figure 17, illustrating an exemplary structure according to an embodiment of the present disclosure, which can be derived from any of the above exemplary structures by forming a metal interconnect structure (812, 822, 882, 892), which is formed in a dielectric material layer (810, 820, 880, 890) located above each field effect transistor 800. Each field effect transistor 800 is an avalanche protection field effect transistor, that is, a field effect transistor configured to provide device protection in the event of an avalanche breakdown event. Specifically, during an avalanche breakdown event, the gate dielectric 752 of each avalanche protection field effect transistor is protected from impacting charge carriers by inducing charge carriers to pass through the buried first conductivity type well 711 and reach the bottommost surface of the drain region (736, 738), which is the bottom surface of the deep drain region 738.

[0112] The metal interconnect structures (812, 822, 882, 892) may include: a first metal line 812 formed in a first line-level dielectric layer 810; a second integrated line and via structure 822 formed in a second line-level dielectric layer 820; an additional integrated line and via structure (not shown) formed in an additional line-level dielectric layer (not shown); a terminal integrated line and via structure 882 formed in a terminal line-level dielectric layer 880; and a bonding pad 892 formed in a bonding pad-level dielectric layer 890. A passivation dielectric layer 898 including an opening overlying the bonding pad 892 may be formed on the bonding pad-level dielectric layer 890.

[0113] refer to Figure 18 , indicating the incorporation Figure 17 The semiconductor chip 900 may include: Figure 17 Each of the plurality of field effect transistors 800 in the semiconductor chip 900 may be an avalanche protection field effect transistor.

[0114] In general, the semiconductor chip 900 may include at least one avalanche protection field effect transistor 800 located in a semiconductor substrate 8. Each of the at least one avalanche protection field effect transistor 800 includes: a bulk semiconductor layer 709 located in the semiconductor substrate 8 and having a first conductivity type of doping; a source region (732, 734) and a drain region (736, 738) formed in an upper portion of the semiconductor substrate 8, having a second conductivity type opposite to the first conductivity type, and laterally spaced apart by a channel region 735; and a buried first conductivity type well 711 located in the semiconductor substrate 8, below the drain region (736, 738), overlapping with the drain region (736, 738) in a plan view, spaced apart from the drain region (736, 738) in a vertical direction (by a lateral extension of the bulk semiconductor layer 709 or by a drain-side first conductivity type well 723), and having a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709. Each of the at least one avalanche protection field effect transistor 800 has the following configuration: during avalanche breakdown, more than 90% of the impact ionization charge is induced to flow from the source region (732, 734), pass through the buried first conductivity type well 711, and impinge on the horizontal surface of the pn junction, the bottom surface of the horizontal surface drain region (736, 738), and less than 10% of the charge impinges on the sidewall surface of the pn junction.

[0115] In one embodiment, each of the at least one avalanche protection field effect transistor 800 includes a doped body contact region 731 formed in an upper portion of the semiconductor substrate 8, having a first conductivity type of doping and spaced apart from the source region (732, 734). In one embodiment, each of the at least one avalanche protection field effect transistor 800 includes a source-side first conductivity type well 721 located within the semiconductor substrate 8 and having a higher atomic concentration of a dopant of the first conductivity type than the bulk semiconductor layer 709.

[0116] In one embodiment, the source-side first conductivity type well 721 connects the doped body contact region 731 in each of the at least one avalanche protection field effect transistor 800 and the buried first conductivity type well 711. In one embodiment, each of the at least one avalanche protection field effect transistor 800 includes a buried second conductivity type well 712, which is located below the buried first conductivity type well 711 of the corresponding avalanche protection field effect transistor 800 and forms a pn junction with the buried first conductivity type well 711 of the corresponding avalanche protection field effect transistor 800.

[0117] refer to Figure 19, illustrating voltage-current curves during avalanche breakdown of a test sample embodying an exemplary structure of the present disclosure and a comparative exemplary test sample. Curve 1910 represents a current-voltage curve during avalanche breakdown of the comparative exemplary test sample, which is obtained by removing the buried first conductivity type well 711 and the source side first conductivity type well 721 from the source side. Figure 4 The second exemplary structure is derived. Curves 1920 and 1930 represent the embodiment Figure 4 Current-voltage curve during avalanche breakdown of an exemplary test sample of the second exemplary structure, Figure 4 The buried first conductivity type well 711 and the source-side first conductivity type well 721 of the second exemplary structure have different implantation conditions. The presence of the buried first conductivity type well 711 and the source-side first conductivity type well 721 reduces the breakdown voltage by approximately 10%. However, when the buried first conductivity type well 711 and the source-side first conductivity type well 721 are present in the field-effect transistor, the magnitude of the current during avalanche breakdown increases by 2.5 to 4.0 times. Therefore, the field-effect transistor of the embodiments of the present disclosure provides enhanced protection against avalanche breakdown.

[0118] According to an embodiment of the present disclosure, the device transmission line pulse snapback current is improved by using the bottom avalanche breakdown structure of the embodiment of the present disclosure. The transmission line pulse (TLP) measurement method is a measurement method for characterizing the electrostatic discharge (ESD) performance of a device under stress. A short pulse width and a fast rise time are used to emulate the pulse condition during an electrostatic discharge event. Curves 1920 and 1930 show that the embodiment of the present disclosure can improve the ESD performance of the field effect transistor and improve the non-clamped inductive switching performance. It is believed that further improvements can be made by optimizing the energy and dose of the implantation process for forming the buried first conductive type well 711.

[0119] FIG. 20A to FIG. 20D 1 is a flow chart of steps for forming an avalanche protection field effect transistor according to an embodiment of the present disclosure. The processing sequence in the flow chart differs from each other in the timing of performing the processing step 2090, in which a buried first conductivity type well 711 is formed in the semiconductor substrate 8.

[0120] Generally speaking, various embodiments of the present disclosure describe methods for forming a semiconductor structure. Referring to step 2010, a semiconductor substrate 8 including a bulk semiconductor layer 709 doped with a first conductivity type may be provided, for example Figure 1AReferring to step 2020, a doped body contact region 731 having a doping of the first conductivity type may be formed in the surface region of the semiconductor substrate 8, for example Figure 1C 、 Figure 2A and Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9A 、 Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 、 Figure 15 and Figure 16 Referring to step 2030, a gate stack structure (752, 754, 758, 756) including a gate dielectric 752 and a gate electrode 754 may be formed on the semiconductor substrate 8, for example Figure 1D 、 Figure 2A and Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9A 、 Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 、 Figure 15 and Figure 16 Referring to step 2040, source regions (732, 734) and drain regions (736, 738) may be formed in the upper portion of the semiconductor substrate 8 by implanting dopants of a second conductivity type opposite to the first conductivity type, for example Figure 1F 、 Figure 2A and Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9A 、 Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 、 Figure 15 and Figure 16 The source regions (732, 734) and the drain regions (736, 738) may be laterally separated by a channel region 735 located below the gate stack structure (752, 754, 758, 756). Figure 20A Between step 2010 and step 2020 described in Figure 20B Between step 2020 and step 2030 described in Figure 20C Between step 2030 and step 2040 described in or Figure 20D Step 2090 is performed after step 2040 described in . At step 2090, a buried first conductivity type well 711 may be formed in the semiconductor substrate 8 by implanting dopants of the first conductivity type before, between, or after the processing steps for forming the gate stack structure (752, 754, 758, 756), the source region (732, 734), the drain region (736, 738), and the doped body contact region 731. For example, Figure 1B 、 Figure 1C 、 Figure 2A and Figure 2B 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10 、 Figure 11 、 Figure 13 、 Figure 14 、 Figure 15 and Figure 16 The buried first conductivity type well 711 is formed in any of the processing steps described in the foregoing, but is not limited to any of the processing steps. The buried first conductivity type well 711 has an area overlap with the drain region (736, 738) in a plan view, is spaced apart from the drain region (736, 738) in a vertical direction, and has a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709.

[0121] Generally speaking, the bottom portion of the pn junction between the drain region (736, 738) and the underlying p-doped semiconductor material (which may constitute a lateral extension of the bulk semiconductor layer 709 or the drain-side first conductivity type well 723) breaks down during an avalanche breakdown condition, while the sidewall portion of the pn junction does not break down. In this configuration, the hot spot of impact ionization does not occur at the sidewall portion of the pn junction but rather at the bottom surface of the pn junction. Because the bottom surface of the pn junction is vertically separated from the gate dielectric 752, permanent damage to the gate dielectric 752 can be avoided in the avalanche protection field effect transistor 800 of the present disclosure.

[0122] In general, the comprehensive bottom breakdown implantation process used to form the first exemplary structure to the fourth exemplary structure is simple and effective. The additional implantation below the gate stack structure (752, 754, 758, 756) can change the potential profile distribution, which means that the bottom breakdown implantation optimization will also affect the electric field at the gate edge and can limit the improvement of the device's unclamped inductive switching (UIS) capability. According to an embodiment of the present disclosure, a local bottom breakdown implantation can be used to form any one of the fifth exemplary structure to the sixteenth exemplary structure. The local bottom breakdown implantation can be deep or shallow. The resulting breakdown value can be much lower than or slightly lower than the device surface breakdown value. The depth, lateral amplitude and dopant concentration distribution profile of the buried first conductive type well 711 can be optimized based on the application. In some embodiments, the local bottom avalanche breakdown provided by the buried first conductive type well 711 with limited lateral extension can improve the repetitive avalanche energy (E AR ) capability and / or single pulse avalanche energy (E AS )ability.

[0123] Various embodiments of the present disclosure provide an avalanche protection field effect transistor having excellent device characteristics during avalanche breakdown by using a buried first conductivity type well 711 as a conductive path during avalanche breakdown of the field effect transistor and by inducing impact ionization at the bottommost surface of the drain region (736, 738) rather than at the sidewalls of the drain region (736, 738). The buried first conductivity type well 711 can replace the channel region 735 formed below the gate structure 750 to provide a conductive path for charge carriers under avalanche conditions. By providing an alternative conductive path, various embodiments can significantly improve the avalanche durability of the device. Damage that may occur at the gate edge during avalanche conditions in conventional devices can be moved away from the gate edge in embodiment devices including the buried first conductivity type well 711.

[0124] Various embodiments described above may include a field effect transistor. The field effect transistor may include: a bulk semiconductor layer 709 located in a semiconductor substrate 8 and having a first conductivity type doping; a source region (732, 734) and a drain region (736, 738) formed in an upper portion of the semiconductor substrate 8 and having a second conductivity type doping opposite to the first conductivity type and spaced laterally apart by a channel region 735; a doped bulk contact region 731 formed in an upper portion of the semiconductor substrate 8 and having a first conductivity type doping and spaced apart from the source region (732, 734); and a buried first conductivity type well 711 located in the semiconductor substrate 8, below the drain region (736, 738), overlapping in area with the drain region (736, 738) in a plan view, spaced apart in a vertical direction from the drain region (736, 738), and having a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709.

[0125] In other embodiments, the semiconductor chip 900 may include at least one avalanche protection field effect transistor 800 located in the semiconductor substrate 8. Each of the at least one avalanche protection field effect transistor 800 includes: a bulk semiconductor layer 709 located in the semiconductor substrate 8 and having a first conductivity type of doping; a source region (732, 734) and a drain region (736, 738) formed in an upper portion of the semiconductor substrate 8, having a second conductivity type opposite to the first conductivity type and laterally spaced apart by a channel region 735; and a buried first conductivity type well 711 located in the semiconductor substrate 8, below the drain region (736, 738), overlapping with the drain region (736, 738) in a plan view, spaced apart from the drain region (736, 738) in a vertical direction (by a lateral extension of the bulk semiconductor layer 709 or by a drain-side first conductivity type well 723), and having a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer 709. Each of the at least one avalanche protection field effect transistor 800 has the following configuration: during avalanche breakdown, more than 90% of the impact ionization charge is induced to flow from the source region (732, 734), pass through the buried first conductivity type well 711, and impinge on the horizontal surface of the pn junction, the bottom surface of the horizontal surface drain region (736, 738), and less than 10% of the charge impinges on the sidewall surface of the pn junction.

[0126] In other embodiments, a method of forming a semiconductor structure may be provided. The method may include providing a semiconductor substrate 8 including a bulk semiconductor layer 709 having a doping type of a first conductivity type. The method may include forming a doped bulk contact region 731 having a doping type of the first conductivity type in a surface region of the semiconductor substrate 8. The method may include forming a gate stack structure 750 (752, 754, 756, 758) including a gate dielectric 752 and a gate electrode 754 above the semiconductor substrate 8. The method may include forming a source region (732, 734) and a drain region (736, 738) in an upper portion of the semiconductor substrate 8 by implanting dopants of a second conductivity type opposite to the first conductivity type, wherein the source region (732, 734) and the drain region (736, 738) are laterally separated by a channel region (735) below the gate stack structure 750 (752, 754, 756, 758). The method may include an operation of forming a buried first conductive type well 711 in the semiconductor substrate 8 by implanting first conductive type dopants before, between or after the processing steps for forming the gate stack structure 750, the source region (732, 734), the drain region (736, 738) and the doped main contact region 731, wherein the buried first conductive type well 711 has an area overlap with the drain region (732, 734) in a plan view, is spaced apart from the drain region (732, 734) in a vertical direction, and has an atomic concentration of the first conductive type dopant higher than that of the main semiconductor layer 709.

[0127] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A field effect transistor comprising: a main semiconductor layer located in the semiconductor substrate and having a doping of a first conductivity type; a source region and a drain region formed in an upper portion of the semiconductor substrate, having a second conductivity type opposite to the first conductivity type and laterally spaced apart by a channel region; a doped body contact region formed in the upper portion of the semiconductor substrate, having doping of the first conductivity type and spaced apart from the source region; a buried first conductivity type well located in the semiconductor substrate, located below the drain region and overlapping in area with the drain region in a plan view, spaced apart from the drain region in a vertical direction, and having a higher atomic concentration of dopants of the first conductivity type than that of the bulk semiconductor layer; as well as a source-side first conductivity type well located in the semiconductor substrate, wherein the source-side first conductivity type well directly contacts the source region to provide a first pn junction, a periphery of the first pn junction is completely located within the top surface of the semiconductor substrate, and the source-side first conductivity type well is in direct contact with the bulk semiconductor layer along an interface extending from the top surface of the semiconductor substrate to the top surface of the buried first conductivity type well, and the source-side first conductivity type well has a higher atomic concentration of dopants of the first conductivity type than the bulk semiconductor layer, The channel region located below the gate dielectric extends laterally through an upper portion of the source-side first conductivity type well and through an upper portion of the bulk semiconductor layer. 2 . The field effect transistor of claim 1 , wherein the source-side first conductivity type well connects the doped body contact region and the buried first conductivity type well. 3 . The field effect transistor of claim 1 , wherein the source-side first conductivity type well is laterally spaced apart from the buried first conductivity type well by a portion of the bulk semiconductor layer below the gate dielectric.

4. The field effect transistor according to claim 1, wherein the source region and the drain region have asymmetric extension regions, so that the area overlapped by the drain extension region with the gate electrode in the plan view is larger than the area overlapped by the source extension region with the gate electrode in the plan view.

5. The field effect transistor according to claim 1 , wherein the drain region forms a second pn junction with the main semiconductor layer or the drain-side first conductivity type well, and the drain-side first conductivity type well is overlying the buried first conductivity type well and has a lower atomic concentration of the first conductivity type dopant than the buried first conductivity type well.

6. The field effect transistor of claim 5 , wherein the field effect transistor has a configuration such that during avalanche breakdown, more than 90% of impact ionization charges flow from the source region, pass through the buried first conductivity type well, and impinge on a horizontal surface of the second pn junction that is a bottom surface of the drain region, and less than 10% of the impact ionization charges impinge on sidewall surfaces of the second pn junction. 7 . The field effect transistor of claim 1 , wherein the buried first conductivity type well has an area overlap with the entire areas of the source region, the drain region, and the doped body contact region in the plan view.

8. The field effect transistor according to claim 1 further includes a shallow trench isolation structure that laterally surrounds the source region, the drain region and the doped body contact region, wherein the entire closed perimeter of the interface between the top surface of the buried first conductive type well and the body semiconductor layer continuously contacts the sidewall of the shallow trench isolation structure. 9 . The field effect transistor of claim 1 , wherein the buried first conductivity type well has an area overlap with an entire area of ​​the drain region in the plan view and does not overlap with an area of ​​the doped body contact region in the plan view. 10 . The field effect transistor according to claim 1 , further comprising a buried second conductivity type well, the buried second conductivity type well being located below the buried first conductivity type well and forming an additional pn junction with the buried first conductivity type well.

11. A semiconductor chip comprising at least one avalanche protection field effect transistor (APFET) located in a semiconductor substrate, wherein each of the at least one APT comprises: a main semiconductor layer, located in the semiconductor substrate and having a doping layer of a first conductivity type; a source region and a drain region formed in an upper portion of the semiconductor substrate, having a second conductivity type opposite to the first conductivity type and laterally spaced apart by a channel region; a buried first conductivity type well located in the semiconductor substrate, located below the drain region and overlapping in area with the drain region in a plan view, spaced apart from the drain region in a vertical direction, and having a higher atomic concentration of dopants of the first conductivity type than that of the bulk semiconductor layer; as well as a source-side first conductivity type well located in the semiconductor substrate, wherein the source-side first conductivity type well directly contacts the source region to provide a first pn junction, a periphery of the first pn junction is completely located within the top surface of the semiconductor substrate, and the source-side first conductivity type well is in direct contact with the bulk semiconductor layer along an interface extending from the top surface of the semiconductor substrate to the top surface of the buried first conductivity type well, and the source-side first conductivity type well has a higher atomic concentration of dopants of the first conductivity type than the bulk semiconductor layer, wherein the drain region forms a second pn junction with the main semiconductor layer, wherein each of the at least one avalanche protection field effect transistor has a configuration such that during avalanche breakdown, more than 90% of impact ionization charges flow from the source region, pass through the buried first conductivity type well, and impinge on a horizontal surface of the second pn junction, the horizontal surface being a bottom surface of the drain region, and less than 10% of the impact ionization charges impinge on sidewall surfaces of the second pn junction, The channel region located below the gate dielectric extends laterally through an upper portion of the source-side first conductivity type well and through an upper portion of the bulk semiconductor layer.

12. The semiconductor chip according to claim 11, wherein each of the at least one avalanche protection field effect transistor comprises a doped body contact region formed in the upper portion of the semiconductor substrate, having doping of the first conductivity type and spaced apart from the source region. 13 . The semiconductor chip according to claim 12 , wherein the source-side first conductivity type well of each of the at least one avalanche protection field effect transistor has a higher atomic concentration of dopants of the first conductivity type than the bulk semiconductor layer. 14 . The semiconductor chip according to claim 13 , wherein the source-side first conductivity type well connects the doped body contact region and the buried first conductivity type well in each of the at least one avalanche protection field effect transistor.

15. A semiconductor chip according to claim 11, wherein each of the at least one avalanche protection field effect transistor includes a buried second conductivity type well, which is located below the buried first conductivity type well of the corresponding avalanche protection field effect transistor and forms an additional pn junction with the buried first conductivity type well.

16. A method of forming a semiconductor structure, comprising: Providing a semiconductor substrate comprising a bulk semiconductor layer doped with a first conductivity type; doping a surface region of the semiconductor substrate into a doped body contact region having the first conductivity type; Depositing a gate dielectric layer and a gate electrode layer and patterning the gate dielectric layer and the gate electrode layer to form a gate stack structure including a gate dielectric and a gate electrode on the semiconductor substrate; implanting dopants of a second conductivity type opposite to the first conductivity type in an upper portion of the semiconductor substrate, wherein a source region and a drain region are formed, the source region and the drain region being laterally separated by a channel region located below the gate stack structure; implanting dopants of the first conductivity type before, during, or after the processing steps for forming the gate stack structure, the source region, the drain region, and the doped body contact region, thereby forming a buried well of the first conductivity type within the semiconductor substrate, wherein the buried first conductivity type well has an area overlap with the drain region in a plan view, is spaced apart from the drain region in a vertical direction, and has a higher atomic concentration of the first conductivity type dopant than the bulk semiconductor layer; as well as forming a source-side first conductivity type well in the semiconductor substrate, wherein the source-side first conductivity type well directly contacts the source region to provide a first pn junction, a periphery of the first pn junction is completely located within the top surface of the semiconductor substrate, and the source-side first conductivity type well is in direct contact with the bulk semiconductor layer along an interface extending from the top surface of the semiconductor substrate to the top surface of the buried first conductivity type well, and the source-side first conductivity type well has a higher atomic concentration of dopants of the first conductivity type than the bulk semiconductor layer, The channel region below the gate dielectric laterally extends through an upper portion of the source-side first conductivity type well and through an upper portion of the bulk semiconductor layer.

17. A method for forming a semiconductor structure according to claim 16, wherein the buried first conductive type well is formed by performing an ion implantation process before forming the gate stack structure, and has an area overlap with the entire source region, the drain region and the doped body contact region in the plan view.

18. The method for forming a semiconductor structure according to claim 16, wherein the buried first conductive type well is formed by performing an ion implantation process after forming the gate electrode, and has an area overlap with the drain region and has no area overlap with the doped body contact region in the plan view.

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