Semiconductor system including transmitter and receiver

Abstract

A transmitter including an encoder and a transmission interface circuit is disclosed. The encoder receives data bits and generates conversion bits based on the number of data bits, the number of conversion bits being greater than the number of data bits. The encoder detects a risk pattern of the conversion bits to generate detection data, and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, the number of code bits being equal to the number of conversion bits.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0048118 filed on April 21, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts described herein relate to a transceiver, and more particularly, to a transmitter that transmits a signal to a channel, a receiver that receives a signal from the channel, and / or a semiconductor system including the transmitter and the receiver. Background Art

[0004] In a high-speed parallel data interface, data bits can be sent in parallel through channels. When sending signals through channels such as coaxial cables or printed circuit board (PCB) traces, data may transition. This transition affects adjacent channels, causing crosstalk that hinders data transmission in adjacent channels.

[0005] In particular, as semiconductor devices and systems are highly integrated, the distance between channels may decrease, and the influence of crosstalk may increase. Therefore, it is necessary to reduce the influence of crosstalk between channels. Summary of the invention

[0006] Example embodiments of the inventive concepts provide a transmitter that transmits a signal to a channel, a receiver that receives a signal from the channel, and / or a semiconductor system including the transmitter and the receiver, thereby reducing crosstalk between channels.

[0007] According to some example embodiments, a transmitter that outputs a transmission signal to a channel in parallel includes an encoder and a transmission interface circuit. The encoder receives data bits having a target logic value, generates conversion bits based on the number of data bits, the number of conversion bits being greater than the number of data bits, detects a risk pattern of the conversion bits to generate detection data, and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, the number of code bits being equal to the number of conversion bits. The transmission interface circuit converts the code bits into a transmission signal.

[0008] According to some example embodiments, a receiver that receives a receive signal from a channel in parallel includes a receive interface circuit and a decoder. The receive interface circuit converts the receive signal into a code bit. The decoder generates detection data based on a pattern of the code bit, converts at least a portion of the code bit into a risk pattern based on the detection data to generate a conversion bit, and converts the conversion bit into a data bit, the number of data bits being less than the number of conversion bits. The conversion bits corresponding to four channels arranged sequentially, respectively, have three or more conversion bits having a target logic value in the risk pattern.

[0009] According to some example embodiments, a semiconductor system includes a transmitter, a channel unit, and a receiver. The transmitter generates conversion bits based on the number of data bits each having a target logic value among the data bits, the number of conversion bits being greater than the number of data bits, and converting the risk pattern into a replacement pattern to generate code bits when the conversion bit has a risk pattern. The channel unit includes channels, the number of channels being equal to the number of code bits, and is configured to receive a signal generated based on the code bits. The receiver receives the signal through the channel unit, converts the signal into code bits, and converts the code bits into data bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram of a semiconductor system according to some example embodiments of the inventive concept.

[0012] Figure 2 yes Figure 1 An exemplary block diagram of an encoder.

[0013] Figure 3 Is used to describe Figure 1 and Figure 2 Illustration of the transition and crosstalk described in .

[0014] Figure 4 Is used to describe Figure 2 An illustration of how an encoder converts data bits into conversion bits.

[0015] Figure 5 and Figure 6 yes Figure 2 0026] An exemplary logic circuit diagram of a portion of a first conversion circuit.

[0016] Figure 7 and Figure 8 yes Figure 2 An exemplary logic circuit diagram of a portion of a pattern detection circuit.

[0017] Fig. 9 yes Figure 2 An exemplary logic circuit diagram of a second conversion circuit.

[0018] Fig.10 yes Figure 2 An exemplary logic circuit diagram of a portion of a third conversion circuit.

[0019] Fig.11 yes Figure 1 An exemplary block diagram of a decoder of .

[0020] Fig.12 yes Fig.11 0026] An exemplary logic circuit diagram of a portion of a first conversion circuit.

[0021] Fig.13 yes Fig.11 An exemplary logic circuit diagram of a detection bit generation circuit.

[0022] Fig.14 yes Fig.11 An exemplary logic circuit diagram of a second conversion circuit.

[0023] Fig.15 yes Fig.11 An exemplary logic circuit diagram of a third conversion circuit.

[0024] Fig.16 It is shown in Figure 1 Block diagram of a system corresponding to one channel in a semiconductor system of FIG.

[0025] Figures 17 to 20 The reference is applied Figures 1 to 16 An exemplary diagram of an electronic device of an encoder and a decoder is described. DETAILED DESCRIPTION

[0026] Hereinafter, example embodiments of the inventive concept will be described in detail and clearly with reference to the accompanying drawings so that those having ordinary skill in the art can implement the example embodiments of the inventive concept.

[0027] Figure 1 is a block diagram of a semiconductor system according to some example embodiments of the inventive concept. Figure 1 , the semiconductor system 100 includes a transmitter 110, a receiver 120 and / or a channel 130. The semiconductor system 100 may transmit data or signals in parallel through the channel 130.

[0028] The transmitter 110, the receiver 120 or other components and subcomponents (e.g., the encoder 111, the decoder 121, etc.) may include: a processing circuit system such as hardware including a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, more specifically, the processing circuit system may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0029] The transmitter 110 may transmit signals to the channels 130 in parallel. The transmitter 110 may generate signals to be transmitted based on data bits. When the signals are output to the channels 130 in parallel, a transition may occur at the channels 130 due to the signals. For example, in the case where a transition occurs at a channel adjacent to a target channel, signal transmission of the target channel may be hindered. This phenomenon may be referred to as "crosstalk". In order to reduce the occurrence of crosstalk, the transmitter 110 may include an encoder 111.

[0030] The encoder 111 may receive data bits and may encode the data bits into code bits. When the logic value of the transmission bit is "1", a transition of the transmission bit may occur, thereby affecting adjacent channels. Therefore, the encoder 111 may generate code bits based on the number of bits having a logic value of "1" among the data bits and the pattern of the logic value "1" at the data bits. The number of code bits may be more than the number of data bits. However, a pattern causing crosstalk may not be found at the code bits. The transmitter 110 may convert the code bits into a transmission signal and may output the transmission signal to the channel 130. The encoder 111 will be described more fully later.

[0031] The receiver 120 may receive signals from the channels 130 in parallel. The receiver 120 may convert the received signals into code bits. The receiver 120 may restore the code bits into data bits. To this end, the receiver 120 may include a decoder 121. The decoder 121 may receive the code bits and may decode the code bits into data bits. The decoder 121 will be described more fully later.

[0032] The channel 130 may be a path that physically or electrically connects the transmitter 110 and the receiver 120. For example, the channel 130 may be implemented using a trace of a printed circuit board (PCB) or a coaxial cable. When a signal is transmitted through the channel 130, the signal may cause a transition. For example, when a signal corresponding to a logic value "1" is transmitted through the channel 130, a rising edge or a falling edge may be caused. In some example embodiments, crosstalk may occur at a channel adjacent to the channel where the transition occurs. According to the inventive concept, the signal received by the channel 130 may be generated based on code bits for reducing crosstalk. The encoding / decoding for reducing crosstalk will be described below.

[0033] Figure 2 yes Figure 1 An exemplary block diagram of an encoder. Figure 2 The encoder 111 may encode 8 data bits D[7:0] into 10 code bits C[9:0]. In some example embodiments, Figure 1 The number of channels 130 may be "10". Figure 2 , the encoder 111 may include a first mapper 112 and a second mapper 115 .

[0034] The first mapper 112 may generate conversion bits S[9:0] and detection bits T1 and T2 based on data bits D[7:0]. The first mapper 112 may include a first conversion circuit 113 for generating conversion bits S[9:0] and a pattern detection circuit 114 for generating detection bits T1 and T2.

[0035] The first conversion circuit 113 may generate the conversion bits S[9:0] based on the number of bits each having a target logic value (e.g., logic value "1") that causes a transition among the data bits D[7:0]. The first conversion circuit 113 may generate the first portion of conversion bits S[9:5] based on the number of target logic values ​​included in the first portion of data bits D[7:4] of the data bits D[7:0]. The first conversion circuit 113 may generate the second portion of conversion bits S[4:0] based on the number of target logic values ​​included in the second portion of data bits D[3:0] of the data bits D[7:0].

[0036] When the number of 1s included in the first portion of data bits D[7:4] is greater than half of the total number of the first portion of data bits D[7:4], that is, "3" or greater, the first conversion circuit 113 may invert the logic value of the first portion of data bits D[7:4]. Therefore, the number of 1s may be reduced. S[8:5] in the first portion of conversion bits S[9:5] may be equal to D[7:4] or an inverted version of D[7:4]. S[9] in the first portion of conversion bits S[9:5] may be an added bit indicating whether D[7:4] is inverted.

[0037] When the number of 1s included in the second portion of data bits D[3:0] is greater than half of the total number of the second portion of data bits D[3:0], that is, "3" or greater, the first conversion circuit 113 may invert the logic value of the second portion of data bits D[3:0]. Therefore, the number of 1s may be reduced. S[4:1] in the second portion of conversion bits S[4:0] may be equal to D[3:0] or an inverted version of D[3:0]. S[0] in the second portion of conversion bits S[4:0] may be an additional bit indicating whether D[3:0] is inverted.

[0038] The pattern detection circuit 114 may detect a risk pattern included in the conversion bits S[9:0] to generate a first detection bit T1 and a second detection bit T2. Here, when extracting four sequentially arranged bits from the conversion bits S[9:0], the risk pattern may be defined by a pattern including three or more 1s. For example, "1101", "1011", "1110", "0111", etc. may be defined as a risk pattern. In other words, the three or more 1s do not need to be sequential, and only three or more 1s are required among the four sequentially arranged conversion bits S[9:0].

[0039] As a result of detecting whether the number of 1s included in the first partial data bits D[7:4] is "2" and whether the risk pattern exists in the conversion bits S[9:0], the pattern detection circuit 114 may generate a first detection bit T1. When the number of 1s included in the first partial data bits D[7:4] is "2", the logic value "1" is not negated in the data conversion operation of the first conversion circuit 113. However, the risk pattern may be found when the first partial data bits D[7:4] and the second partial data bits D[3:0] are arranged. For example, when D[7:0]="00101100", the first detection bit T1 may indicate whether the risk pattern is not found at the first partial data bits D[7:4], but the risk pattern is found at the conversion bits S[9:0].

[0040] Likewise, as a result of detecting whether the number of 1s included in the second partial data bits D[3:0] is "2" and whether the risk pattern exists in the conversion bits S[9:0], the pattern detection circuit 114 may generate a second detection bit T2. The risk pattern may not exist in the second partial data bits D[3:0], but the risk pattern may be found when the first partial data bits D[7:4] and the second partial data bits D[3:0] are arranged. For example, when D[7:0]="00110100", the second detection bit T2 may indicate whether the risk pattern is not found at the second partial data bits D[3:0], but the risk pattern is found at the conversion bits S[9:0].

[0041] The second mapper 115 may generate code bits C[9:0] by removing the risk pattern present in the conversion bits S[9:0] based on the first detection bit T1 and the second detection bit T2. The second mapper 115 may include a second conversion circuit 116 for generating a replacement pattern to replace the risk pattern and a third conversion circuit 117 for generating code bits C[9:0].

[0042] The second conversion circuit 116 may generate a replacement bit E[8:1] based on the conversion bit S[9:0]. The second conversion circuit 116 may generate the replacement bit E[8:1] using S[8:1] in the conversion bit S[9:0]. When there is a risk pattern in the conversion bit S[9:0], the replacement bit E[8:1] converted by the second conversion circuit 116 may not have a risk pattern. Therefore, the number of bits each having a logic value of "1" among the four bits sequentially arranged in the replacement bit E[8:1] is less than "3". This pattern is defined as a replacement pattern.

[0043] The second conversion circuit 116 may generate a third detection bit T3 based on the first detection bit T1 and the second detection bit T2. The third detection bit T3 may indicate whether a risk pattern is found at the conversion bit S[9:0]. For example, the third detection bit T3 may be generated based on a NOR operation of the first detection bit T1 and the second detection bit T2.

[0044] The third conversion circuit 117 may generate code bits C[9:0] based on the third detection bit T3, the conversion bit S[9:0], and the replacement bit E[8:1]. When the third detection bit T3 indicates that there is a risk pattern in the conversion bit S[9:0], S[8:1] in the conversion bit S[9:0] may be replaced by the replacement bit E[8:1]. The code bit C[9:0] may include the replacement bit E[8:1]. Alternatively, when the third detection bit T3 indicates that the risk pattern does not exist in the conversion bit S[9:0], the code bit C[9:0] may be the same as the conversion bit S[9:0]. Therefore, the code bit C[9:0] may not include a risk pattern that causes a transition.

[0045] Figure 3 Is used to describe Figure 1 and Figure 2 Schematic diagram of the transition and crosstalk described in . Figure 3 ,In the transition item, the rising arrow indicates the rising edge, and the falling arrow indicates the falling edge.

[0046] The transition item indicates the status of the three channels adjacent to each other. When the logic value of the bit is "0", the Figure 1 When the logic value of a bit is "1", the signal to be sent to Figure 1 A transition such as a rising edge or a falling edge may occur at the signal of channel 130 .

[0047] The crosstalk caused by the transitions occurring at the channels (hereinafter referred to as the "first channel" and the "second channel") placed on the opposite sides of the center channel (hereinafter referred to as the "reference channel") will be described. When the transitions do not occur at the first channel and the second channel, the crosstalk does not occur. When the transitions occur at one of the first channel and the second channel, the crosstalk occurs. When the same type of transitions occur at the first channel and the second channel, severe crosstalk occurs. When different types of transitions occur at the first channel and the second channel, the crosstalk is canceled.

[0048] The encoder 111 according to some example embodiments may make three adjacent bits not have a logic value of "1", thereby reducing crosstalk according to parallel data transmission. In addition, the encoder 111 according to some example embodiments may remove a risk pattern in which three or more of four adjacent bits have a logic value of "1", thereby reducing crosstalk according to parallel data transmission.

[0049] Figure 4 Is used to describe Figure 2 An illustration of how the encoder converts data bits into conversion bits. Figure 4 , 8 data bits D[7:0] may be converted into 10 conversion bits S[9:0]. Data bits D[7:0] may be divided into first part data bits D[7:4] and second part data bits D[3:0]. The first part data bits D[7:4] may be converted into first part conversion bits S[9:5], and the second part data bits D[3:0] may be converted into second part conversion bits S[4:0].

[0050] When the number of 1s included in the first partial data bits D[7:4] is "3" or more, the first conversion circuit 113 may invert the logic value of the first partial data bits D[7:4]. This inversion may occur at S[8:5], and may be marked by an added bit such as S[9] to indicate whether the inversion has been performed. Similarly, when the number of 1s included in the second partial data bits D[3:0] is "3" or more, the logic value of the second partial data bits D[3:0] may be inverted. This inversion may occur at S[4:1], and may be marked by an added bit such as S[0] to indicate whether the inversion has been performed.

[0051] according to Figure 4 In the conversion scheme shown, the number of 1s included in the first portion of conversion bits S[9:5] may be less than "3", and the number of 1s included in the second portion of conversion bits S[4:0] may be less than "3". However, when the first portion of conversion bits S[9:5] and the second portion of conversion bits S[4:0] are linked, a risk pattern may be generated. As described above, the risk pattern may be removed by the second mapper 115.

[0052] Figure 5 yes Figure 2 0026] An exemplary logic circuit diagram of a portion of a first conversion circuit. Figure 5 The first conversion circuit 113a shown in FIG. 1 can be understood as converting the first part of the data bits D[7:4] into the first part of the conversion bits S[9:5] (refer to Figure 4 Description) logic circuit. Figure 5 , the first conversion circuit 113a may include first to ninth gates G1 to G9.

[0053] The first gate G1 performs a NOR operation on D[6] and D[7]. The second gate G2 performs a NOR operation on the output of the first gate G1, the inverted version of D[4], and the inverted version of D[5]. The third gate G3 performs a NOR operation on D[4] and D[5]. The fourth gate G4 performs a NOR operation on the output of the third gate G3, the inverted version of D[6], and the inverted version of D[7]. The fifth gate G5 performs a NAND operation on the output of the second gate G2 and the output of the fourth gate G4.

[0054] The sixth gate G6 performs an XNOR operation on S[9] and D[7] to output S[8]. The seventh gate G7 performs an XNOR operation on S[9] and D[6] to output S[7]. The eighth gate G8 performs an XNOR operation on S[9] and D[5] to output S[6]. The ninth gate G9 performs an XNOR operation on S[9] and D[4] to output S[5]. As a result, the first partial conversion bits S[9:5] are output.

[0055] Figure 6 yes Figure 2 0026] An exemplary logic circuit diagram of a portion of a first conversion circuit. Figure 6 The first conversion circuit 113b shown in FIG. 1 can be understood as converting the second part of the data bits D[0:3] into the second part of the conversion bits S[4:0] (refer to Figure 4 Description) logic circuit. Figure 6 , the first conversion circuit 113b may include first to ninth gates G1 to G9.

[0056] Figure 6 The first gate G1 to the ninth gate G9 correspond to Figure 5 The first gate G1 to the ninth gate G9, and Figure 6 The connection structure and Figure 5 Substantially the same. Figure 5 D[4:7] is replaced by D[0:3], and thus, the second partial conversion bits S[4:0] are output.

[0057] Figure 7 yes Figure 2 An exemplary logic circuit diagram of a portion of a pattern detection circuit. Figure 7 The pattern detection circuit 114a shown in FIG. 1 can be understood as a logic circuit that generates a first detection bit T1 based on the data bits D[7:0]. Figure 7 , the pattern detection circuit 114 a may include first to twenty-fourth gates G1 to G24 .

[0058] The first gate G1 performs a NAND operation on the inverted version of D[0], the inverted version of D[1], and D[2]. When D[0], D[1], and D[2] are "0", "0", and "1" respectively, the first gate G1 outputs "0"; otherwise, the first gate G1 outputs "1".

[0059] The second gate G2 performs a NAND operation on the inverted versions of D[4], D[5], and D[7]. When D[4], D[5], and D[7] are "1", "1", and "0", respectively, the second gate G2 outputs "0"; otherwise, the second gate G2 outputs "1".

[0060] The third gate G3 performs a NAND operation on the inverted versions of D[2] and D[3]. When D[2] and D[3] are "1" and "0" respectively, the third gate G3 outputs "0"; otherwise, the third gate G3 outputs "1".

[0061] The fourth gate G4 performs a NAND operation on the inverted version of D[2] and D[3]. When D[2] and D[3] are "0" and "1" respectively, the fourth gate G4 outputs "0"; otherwise, the fourth gate G4 outputs "1".

[0062] The fifth gate G5 performs a NAND operation on the inverted version of D[1], the inverted version of D[2], and D[3]. When D[1], D[2], and D[3] are "0", "0", and "1" respectively, the fifth gate G5 outputs "0"; otherwise, the fifth gate G5 outputs "1".

[0063] The sixth gate G6 performs a NAND operation on the inverted versions of D[4], D[6], and D[7]. When D[4], D[6], and D[7] are "1", "1", and "0", respectively, the sixth gate G6 outputs "0"; otherwise, the sixth gate G6 outputs "1".

[0064] The seventh gate G7 performs a NAND operation on the inverted version of D[0], the inverted version of D[2], and D[3]. When D[0], D[2], and D[3] are "0", "0", and "1" respectively, the seventh gate G7 outputs "0"; otherwise, the seventh gate G7 outputs "1".

[0065] The eighth gate G8 performs a NAND operation on the inverted version of D[3] and the inverted version of D[5]. When D[3] and D[5] are "0" and "0" respectively, the eighth gate G8 outputs "0"; otherwise, the eighth gate G8 outputs "1".

[0066] The ninth gate G9 performs a NAND operation on D[0], D[1], and D[2]. When D[0], D[1], and D[2] are "1", "1", and "1" respectively, the ninth gate G9 outputs "0"; otherwise, the ninth gate G9 outputs "1".

[0067] The tenth gate G10 performs a NAND operation on the inverted versions of D[5], D[6], and D[7]. When D[5], D[6], and D[7] are "1", "1", and "0", respectively, the tenth gate G10 outputs "0"; otherwise, the tenth gate G10 outputs "1".

[0068] The eleventh gate G11 performs a NAND operation on the inverted version of D[3] and the inverted version of D[4]. When D[3] and D[4] are "0" and "0" respectively, the eleventh gate G11 outputs "0"; otherwise, the eleventh gate G11 outputs "1".

[0069] The twelfth gate G12 performs a NOR operation on the output of the first gate G1, D[6], and the output of the second gate G2. When D[0:2] and D[4:7] are "001" and "1100" respectively, the twelfth gate G12 outputs "1"; otherwise, the twelfth gate G12 outputs "0".

[0070] The thirteenth gate G13 performs a NOR operation on the output of the second gate G2, D[6] and the output of the third gate G3. When D[2:7] is "101100", the thirteenth gate G13 outputs "1"; otherwise, the thirteenth gate G13 outputs "0".

[0071] The fourteenth gate G14 performs a NOR operation on the output of the second gate G2, D[6] and the output of the fourth gate G4. When D[2:7] is "011100", the fourteenth gate G14 outputs "1"; otherwise, the fourteenth gate G14 outputs "0".

[0072] The fifteenth gate G15 performs a NOR operation on the output of the fifth gate G5, D[5] and the output of the sixth gate G6. When D[1:7] is "0011010", the fifteenth gate G15 outputs "1"; otherwise, the fifteenth gate G15 outputs "0".

[0073] The sixteenth gate G16 performs a NOR operation on the output of the sixth gate G6, D[5] and the output of the seventh gate G7. When D[0] and D[2:7] are "0" and "011010" respectively, the sixteenth gate G16 outputs "1"; otherwise, the sixteenth gate G16 outputs "0".

[0074] The seventeenth gate G17 performs a NOR operation on the output of the sixth gate G6, the output of the eighth gate G8 and the output of the ninth gate G9. When D[0:7] is "11101010", the seventeenth gate G17 outputs "1"; otherwise, the seventeenth gate G17 outputs "0".

[0075] The eighteenth gate G18 performs a NOR operation on the output of the seventh gate G7, D[4] and the output of the tenth gate G10. When D[0] and D[2:7] are "0" and "010110" respectively, the eighteenth gate G18 outputs "1"; otherwise, the eighteenth gate G18 outputs "0".

[0076] The nineteenth gate G19 performs a NOR operation on the output of the fifth gate G5, D[4], and the output of the tenth gate G10. When D[1:7] is "0010110", the nineteenth gate G19 outputs "1", otherwise, the nineteenth gate G19 outputs "0".

[0077] The twentieth gate G20 performs a NOR operation on the output of the tenth gate G10, the output of the ninth gate G9, and the output of the eleventh gate G11. When D[0:7] is "11100110", the twentieth gate G20 outputs "1", otherwise, the twentieth gate G20 outputs "0".

[0078] The 21st gate G21 performs a NOR operation on the output of the 12th gate G12, the output of the 13th gate G13 and the output of the 14th gate G14. When D[0:7] is "001X1100", "XX101100" or "XX011100" (X represents "0" or "1"), the 21st gate G21 outputs "0".

[0079] The 22nd gate G22 performs a NOR operation on the output of the 15th gate G15, the output of the 16th gate G16 and the output of the 17th gate G17. When D[0:7] is "X0011010", "0X011010" or "11101010" (X represents "0" or "1"), the 22nd gate G22 outputs "0".

[0080] The twenty-third gate G23 performs a NOR operation on the output of the eighteenth gate G18, the output of the nineteenth gate G19, and the output of the twentieth gate G20. When D[0:7] is "X010110", "X0010110", or "11100110" (X represents "0" or "1"), the twenty-third gate G23 outputs "0".

[0081] The twenty-fourth gate G24 performs a NAND operation on the output of the twenty-first gate G21, the output of the twenty-second gate G22, and the output of the twenty-third gate G23 to output the first detection bit T1. When D[0:7] corresponds to "001X1100", "XX101100", "XX011100", "X0011010", "0X011010", "11101010" (S[1:8]="00011010"), "0X010110", "X0010110" or "11100110" (S[1:8]="00010110") (X represents "0" or "1"), the twenty-fourth gate G24 outputs "1"; when D[0:7] does not correspond to the above 9 patterns, the twenty-fourth gate G24 outputs "0". That is, the first detection bit T1 may be a result of detecting a pattern in which the number of 1s included in the first partial data bits D[7:4] is '2' in a state in which the conversion bits S[9:0] have a risk pattern.

[0082] Figure 8 yes Figure 2 An exemplary logic circuit diagram of a portion of a pattern detection circuit. Figure 8 The pattern detection circuit 114b shown in FIG. 1 can be understood as a logic circuit that generates a second detection bit T2 based on the data bit D[7:0]. Figure 8 , the pattern detection circuit 114 b may include first to twenty-first gates G1 to G21 .

[0083] The first gate G1 performs a NAND operation on the inverted version of D[0], D[2], and D[3]. When D[0], D[2], and D[3] are "0", "1", and "1" respectively, the first gate G1 outputs "0"; otherwise, the first gate G1 outputs "1".

[0084] The second gate G2 performs a NAND operation on the inverted versions of D[4] and D[5]. When D[4] and D[5] are "1" and "0" respectively, the second gate G2 outputs "0"; otherwise, the second gate G2 outputs "1".

[0085] The third gate G3 performs a NAND operation on the inverted version of D[4] and D[5]. When D[4] and D[5] are "0" and "1" respectively, the third gate G3 outputs "0"; otherwise, the third gate G3 outputs "1".

[0086] The fourth gate G4 performs a NAND operation on the inverted version of D[0], D[1], and D[3]. When D[0], D[1], and D[3] are "0", "1", and "1" respectively, the fourth gate G4 outputs "0"; otherwise, the fourth gate G4 outputs "1".

[0087] The fifth gate G5 performs a NAND operation on the inverted version of D[2] and the inverted version of D[6]. When D[2] and D[6] are "0" and "0" respectively, the fifth gate G5 outputs "0"; otherwise, the fifth gate G5 outputs "1".

[0088] The sixth gate G6 performs a NAND operation on the inverted version of D[2], D[6], and D[7]. When D[2], D[6], and D[7] are "0", "1", and "1" respectively, the sixth gate G6 outputs "0"; otherwise, the sixth gate G6 outputs "1".

[0089] The seventh gate G7 performs a NAND operation on the inverted version of D[3] and the inverted version of D[6]. When D[3] and D[6] are "0" and "0" respectively, the seventh gate G7 outputs "0"; otherwise, the seventh gate G7 outputs "1".

[0090] The eighth gate G8 performs a NAND operation on the inverted version of D[3] and the inverted version of D[7]. When D[3] and D[7] are "0" and "0" respectively, the eighth gate G8 outputs "0"; otherwise, the eighth gate G8 outputs "1".

[0091] The ninth gate G9 performs a NAND operation on the inverted version of D[0], D[1], and D[2]. When D[0], D[1], and D[2] are "0", "1", and "1" respectively, the ninth gate G9 outputs "0"; otherwise, the ninth gate G9 outputs "1".

[0092] The tenth gate G10 performs a NAND operation on the inverted version of D[3], D[6], and D[7]. When D[3], D[6], and D[7] are "0", "1", and "1" respectively, the tenth gate G10 outputs "0"; otherwise, the tenth gate G10 outputs "1".

[0093] The eleventh gate G11 performs a NOR operation on the output of the first gate G1, D[1], and the output of the second gate G2. When D[0:5] is "001110", the eleventh gate G11 outputs "1", otherwise, the eleventh gate G11 outputs "0".

[0094] The twelfth gate G12 performs a NOR operation on the output of the first gate G1, D[1] and the output of the third gate G3. When D[0:5] is "001101", the twelfth gate G12 outputs "1"; otherwise, the twelfth gate G12 outputs "0".

[0095] The thirteenth gate G13 performs a NOR operation on the output of the fourth gate G4, the output of the second gate G2, and the output of the fifth gate G5. When D[0:6] is "0101100", the thirteenth gate G13 outputs "1", otherwise, the thirteenth gate G13 outputs "0".

[0096] The fourteenth gate G14 performs a NOR operation on the output of the fourth gate G4, the output of the third gate G3 and the output of the sixth gate G6. When D[0:7] is "01010111", the fourteenth gate G14 outputs "1"; otherwise, the fourteenth gate G14 outputs "0".

[0097] The fifteenth gate G15 performs a NOR operation on the output of the second gate G2, the output of the seventh gate G7, and the output of the ninth gate G9. When D[0:6] is "0110100", the fifteenth gate G15 outputs "1", otherwise, the fifteenth gate G15 outputs "0".

[0098] The sixteenth gate G16 performs a NOR operation on the output of the second gate G2, the output of the eighth gate G8, and the output of the ninth gate G9. When D[0:5] is "011010" and D[7] is "0", the sixteenth gate G16 outputs "1"; otherwise, the sixteenth gate G16 outputs "0".

[0099] The seventeenth gate G17 performs a NOR operation on the output of the ninth gate G9, the output of the third gate G3, and the output of the tenth gate G10. When D[0:7] is "01100111", the seventeenth gate G17 outputs "1", otherwise, the seventeenth gate G17 outputs "0".

[0100] The eighteenth gate G18 performs a NOR operation on the output of the eleventh gate G11 and the output of the twelfth gate G12. When D[0:7] is "001110XX" or "01010111" (X represents "0" or "1"), the eighteenth gate G18 outputs "0".

[0101] The nineteenth gate G19 performs a NOR operation on the output of the thirteenth gate G13 and the output of the fourteenth gate G14. When D[0:7] is "0101100X" or "001101XX" (X represents "0" or "1"), the nineteenth gate G19 outputs "0".

[0102] The twentieth gate G20 performs a NOR operation on the output of the fifteenth gate G15, the output of the sixteenth gate G16, and the output of the seventeenth gate G17. When D[0:7] is "0110100X", "011010X0", or "01100111" (X represents "0" or "1"), the twentieth gate G20 outputs "0".

[0103] The 21st gate G21 performs a NAND operation on the output of the 18th gate G18, the output of the 19th gate G19, and the output of the 20th gate G20 to output the second detection bit T2. When D[0:7] corresponds to "001110XX", "001101XX", "0101100X", "01010111" (S[1:8]="01011000"), "0110100X", "011010X0" or "01100111" (S[1:8]="01101000") (X represents "0" or "1"), the 21st gate G21 outputs "1"; when D[0:7] does not correspond to the above 7 patterns, the 21st gate G21 outputs "0". That is, the second detection bit T2 may be a result of detecting a pattern in which the number of 1s included in the second partial data bits D[3:0] is '2' in a state in which the conversion bits S[9:0] have a risk pattern.

[0104] Fig. 9 yes Figure 2 0026] An exemplary logic circuit diagram of a portion of a second conversion circuit. Fig. 9 The second conversion circuit 116 shown in FIG. 1 can be understood as a logic circuit that generates replacement bits E[8:1] and third detection bits T3 based on the conversion bits S[9:0] and the first detection bits T1 and the second detection bits T2. Fig. 9 , the second conversion circuit 116 may include a first gate G1 to a twenty-third gate G23.

[0105] The first gate G1 performs a NAND operation on S[5] and S[6]. When S[5] and S[6] are "1" and "1" respectively, the first gate G1 outputs "0"; otherwise, the first gate G1 outputs "1".

[0106] The second gate G2 performs a NAND operation on S[3] and S[7]. When S[3] and S[7] are "1" and "1" respectively, the second gate G2 outputs "0"; otherwise, the second gate G2 outputs "1".

[0107] The third gate G3 performs a NAND operation on the inverted version of S[3] and the inverted version of S[5]. When S[3] and S[5] are "0" and "0" respectively, the third gate G3 outputs "0"; otherwise, the third gate G3 outputs "1".

[0108] The fourth gate G4 performs a NAND operation on the inverted version of S[3] and S[7]. When S[3] and S[7] are "0" and "1" respectively, the fourth gate G4 outputs "0"; otherwise, the fourth gate G4 outputs "1".

[0109] The fifth gate G5 performs a NAND operation on the inverted version of S[4] and S[6]. When S[4] and S[6] are "0" and "1" respectively, the fifth gate G5 outputs "0"; otherwise, the fifth gate G5 outputs "1".

[0110] The sixth gate G6 performs a NAND operation on S[4], S[5], and S[6]. When S[4], S[5], and S[6] are "1", "1", and "1" respectively, the sixth gate G6 outputs "0", otherwise, the sixth gate G6 outputs "1".

[0111] The seventh gate G7 performs a NAND operation on the inverted version of S[3], the inverted version of S[6], and S[7]. When S[3], S[6], and S[7] are "0", "0", and "1" respectively, the seventh gate G7 outputs "0"; otherwise, the seventh gate G7 outputs "1".

[0112] The eighth gate G8 performs a NAND operation on the inverted version of S[3], the inverted version of S[6], and the inverted version of S[7]. When S[3], S[6], and S[7] are "0", "0", and "0" respectively, the eighth gate G8 outputs "0"; otherwise, the eighth gate G8 outputs "1".

[0113] The ninth gate G9 performs a NAND operation on the inverted version of S[2], S[3], and S[6]. When S[2], S[3], and S[6] are "0", "1", and "0" respectively, the ninth gate G9 outputs "0"; otherwise, the ninth gate G9 outputs "1".

[0114] The tenth gate G10 performs a NAND operation on S[3], S[4], and S[6]. When S[3], S[4], and S[6] are "1", "1", and "1" respectively, the tenth gate G10 outputs "0"; otherwise, the tenth gate G10 outputs "1".

[0115] The eleventh gate G11 performs a NAND operation on the inverted version of S[4] and the inverted version of S[6]. When S[4] and S[6] are "0" and "0" respectively, the eleventh gate G11 outputs "0"; otherwise, the eleventh gate G11 outputs "1".

[0116] The twelfth gate G12 performs a NAND operation on S[2] and S[7]. When S[2] and S[7] are "1" and "1" respectively, the twelfth gate G12 outputs "0"; otherwise, the twelfth gate G12 outputs "1".

[0117] The thirteenth gate G13 performs a NAND operation on S[2] and S[6]. When S[2] and S[6] are "1" and "1" respectively, the thirteenth gate G13 outputs "0"; otherwise, the thirteenth gate G13 outputs "1".

[0118] The fourteenth gate G14 performs a NAND operation on the inverted versions of S[3] and S[5]. When S[3] and S[5] are "1" and "0" respectively, the fourteenth gate G14 outputs "0"; otherwise, the fourteenth gate G14 outputs "1".

[0119] The fifteenth gate G15 performs a NOR operation on the first detection bit T1 and the second detection bit T2 to output a third detection bit T3. When the first detection bit T1 and the second detection bit T2 are "0" and "0" respectively, the fifteenth gate G15 outputs "1"; otherwise, the fifteenth gate G15 outputs "0". That is, when D[0:7] corresponds to "001X1100", "XX101100", "XX011100", "X0011010", "0X011010", "11101010", "0X010110", "X0010110", "11100110", "001110XX", "001101XX", "0101100X", "01010111", "0110100X", "011010X0", or "01100111" (X represents "0" or "1"), the third detection bit T3 may have a logic value of "0", and when D[0:7] does not correspond to the above pattern, the third detection bit T3 may have a logic value of "1". The above pattern is defined as the above risk pattern.

[0120] The sixteenth gate G16 performs a NAND operation on the output of the first gate G1 and the inverted version of S[8] to output E[8]. When S[8] is "1" or S[5] and S[6] are "1" and "1" respectively, E[8] is "1".

[0121] The seventeenth gate G17 performs a NAND operation on the output of the second gate G2 and the output of the third gate G3 to output E[7]. When S[3] and S[7] are "1" and "1" respectively or S[3] and S[5] are "0" and "0" respectively, E[7] is "1".

[0122] The eighteenth gate G18 performs a NAND operation on the output of the fourth gate G4 and the output of the fifth gate G5 to output E[6]. When S[3] and S[7] are "0" and "1" respectively or S[4] and S[6] are "0" and "1" respectively, E[6] is "1".

[0123] The nineteenth gate G19 performs a NAND operation on the output of the sixth gate G6 and the output of the seventh gate G7 to output E[5]. When S[4], S[5], and S[6] are "1", "1", and "1" respectively, or S[3], S[6], and S[7] are "0", "0", and "1" respectively, E[5] is "1".

[0124] The twentieth gate G20 performs a NAND operation on the output of the eighth gate G8 and the output of the ninth gate G9 to output E[4]. When S[3], S[6], and S[7] are "0", "0", and "0" respectively, or S[2], S[3], and S[6] are "0", "1", and "0" respectively, E[4] is "1".

[0125] The twenty-first gate G21 performs a NAND operation on the output of the eighth gate G8, the output of the tenth gate G10, and the output of the eleventh gate G11 to output E[3]. When S[3], S[6], and S[7] are "0", "0", and "0", respectively, when S[3], S[4], and S[6] are "1", "1", and "1", or when S[4] and S[6] are "0" and "0", respectively, E[3] is "1".

[0126] The 22nd gate G22 performs a NAND operation on the output of the 11th gate G11, the output of the 12th gate G12, and the output of the 13th gate G13 to output E[2]. When S[4] and S[6] are "0" and "0", respectively, when S[2] and S[7] are "1" and "1", respectively, or when S[2] and S[6] are "0" and "0", respectively, E[2] is "1".

[0127] The twenty-third gate G23 performs a NAND operation on the output of the ninth gate G9, S[1], and the output of the fourteenth gate G14 to output E[1]. When S[3], S[6], and S[7] are "0", "0", and "0", respectively, when S[1] is "0", or when S[3] and S[5] are "1" and "0", respectively, E[1] is "1".

[0128] When the conversion bit S[9:0] has a risk pattern, the replacement bit E[8:1] generated by the second conversion circuit 116 is converted to not have a risk pattern. For example, when S[8:1] is "00101100", the replacement bit E[8:1] is "01000101"; when S[8:1] is "00111100", the replacement bit E[8:1] is "10010101". That is, when the conversion bit S[9:0] has a risk pattern, the replacement bit E[8:1] can be generated so that the logic value "1" is dispersed between the bits.

[0129] Fig.10 yes Figure 2 An exemplary logic circuit diagram of a portion of a third conversion circuit. Fig.10 The third conversion circuit 117 shown in FIG. 1 can be understood as a logic circuit that generates code bits C[9:0] to be output to the channel 130 based on the conversion bits S[9:0], the replacement bits E[8:1], and the first detection bits T1, the second detection bits T2, and the third detection bits T3. Fig.10 , the third conversion circuit 117 may include a first gate G1 to a twenty-sixth gate G26.

[0130] The first gate G1 performs an XNOR operation on the first detection bit T1 and S[9] to generate C[9]. When the logic value of the first detection bit T1 is different from the logic value of S[9], C[9] is "0". When the data bit D[0:7] corresponds to "001X1100", "XX101100", "XX011100", "X0011010", "0X011010", "11101010", "0X010110", "X0010110", or "11100110" (X represents "0" or "1"), the first detection bit T1 is "1"; otherwise, the first detection bit T1 is "0". Therefore, when D[0:7] has the above pattern, C[9] is the same as S[9]. In some example embodiments, since two bits in the first portion of data bits D[7:4] are "1", S[9] is "0" and C[9] is "0". When D[0:7] does not have the above pattern, C[9] corresponds to the inverted version of S[9].

[0131] The second gate G2, the third gate G3, and the nineteenth gate G19 generate C[8]. The second gate G2 performs a NOR operation on S[8] and the inverted version of the third detection bit T3. The third gate G3 performs a NOR operation on E[8] and the third detection bit T3. The nineteenth gate G19 performs a NOR operation on the output of the second gate G2 and the output of the third gate G3. As a result, when the third detection bit T3 is "1", that is, when there is no risk pattern, C[8] is the same as S[8]. When the third detection bit T3 is "0", that is, when there is a risk pattern, C[8] is the same as E[8].

[0132] The fourth gate G4, the fifth gate G5, and the twentieth gate G20 generate C[7], and the configurations of the fourth gate G4, the fifth gate G5, and the twentieth gate G20 are substantially the same as the configurations of the second gate G2, the third gate G3, and the nineteenth gate G19. As a result, when the third detection bit T3 is "1", C[7] is the same as S[7]. When the third detection bit T3 is "0", C[7] is the same as E[7].

[0133] The sixth gate G6, the seventh gate G7 and the twenty-first gate G21 generate C[6]. As a result, when the third detection bit T3 is "1", C[6] is the same as S[6]. When the third detection bit T3 is "0", C[6] is the same as E[6].

[0134] The eighth gate G8, the ninth gate G9 and the twenty-second gate G22 generate C[5]. As a result, when the third detection bit T3 is "1", C[5] is the same as S[5]. When the third detection bit T3 is "0", C[5] is the same as E[5].

[0135] The tenth gate G10, the eleventh gate G11 and the twenty-third gate G23 generate C[4]. As a result, when the third detection bit T3 is "1", C[4] is the same as S[4]. When the third detection bit T3 is "0", C[4] is the same as E[4].

[0136] The twelfth gate G12, the thirteenth gate G13 and the twenty-fourth gate G24 generate C[3]. As a result, when the third detection bit T3 is "1", C[3] is the same as S[3]. When the third detection bit T3 is "0", C[3] is the same as E[3].

[0137] The fourteenth gate G14, the fifteenth gate G15 and the twenty-fifth gate G25 generate C[2]. As a result, when the third detection bit T3 is "1", C[2] is the same as S[2]. When the third detection bit T3 is "0", C[2] is the same as E[2].

[0138] The sixteenth gate G16, the seventeenth gate G17 and the twenty-sixth gate G26 generate C[1]. As a result, when the third detection bit T3 is "1", C[1] is the same as S[1]. When the third detection bit T3 is "0", C[1] is the same as E[1].

[0139] The eighteenth gate G18 performs an XNOR operation on the second detection bit T2 and S[0] to generate C[0]. When the logic value of the second detection bit T2 is different from the logic value of S[0], C[0] is "0". When the data bit D[0:7] corresponds to "001110XX", "001101XX", "0101100X", "01010111", "0110100X", "011010X0" or "01100111" (X represents "0" or "1"), the second detection bit T2 is "1"; otherwise, the second detection bit T2 is "0". Therefore, when D[0:7] has the above pattern, C[0] is the same as S[0]. In some example embodiments, since two bits in the second portion of the data bits D[3:0] are "1", S[0] is "0" and C[0] is "0". When D[0:7] does not have the above pattern, C[0] corresponds to the inverted version of S[0].

[0140] Fig.11 yes Figure 1 An exemplary block diagram of a decoder of . Fig.11The decoder 121 may decode the 10 code bits C[9:0] into 8 data bits D[7:0]. In some example embodiments, Figure 1 The number of channels 130 may be "10". Fig.11 , the decoder 121 includes a first demapper 122 and a second demapper 125 .

[0141] The first demapper 122 may generate replacement bits DE[8:1] and detection bits Ta and Tb based on code bits C[9:0]. The first demapper 122 may include a first conversion circuit 123 for generating replacement bits DE[8:1] and a detection bit generation circuit 124 for generating detection bits Ta and Tb.

[0142] The first conversion circuit 123 may generate replacement bits DE[8:1] based on the code bits C[9:0]. When there is a risk pattern in the conversion bits S[9:0], the risk pattern is converted into a replacement pattern by the encoder 111. In some example embodiments, the decoder 121 needs to convert the replacement pattern into a risk pattern again. The first conversion circuit 123 may generate replacement bits DE[8:1] so that the code bits C[9:0] generated by the replacement pattern are converted into conversion bits S[9:0].

[0143] The detection bit generation circuit 124 may generate a first detection bit Ta and a second detection bit Tb based on the pattern of the code bit C[9:0]. The detection bit generation circuit 124 may generate the first detection bit Ta based on the pattern of C[9:5] in the code bit C[9:0]. The detection bit generation circuit 124 may generate the second detection bit Tb based on the pattern of C[4:0] in the code bit C[9:0]. The first detection bit Ta and the second detection bit Tb may be used to determine whether the code bit C[9:0] corresponds to the result of replacing the risk pattern at the encoder 111.

[0144] The second demapper 125 may generate data bits D[7:0] based on the code bits C[9:0], the replacement bits DE[8:1], and the first detection bits Ta and the second detection bits Tb. The second demapper 125 may include a second conversion circuit 126 for generating conversion bits S[9:0] and a third conversion circuit 127 for generating data bits D[7:0].

[0145] The second conversion circuit 126 may generate conversion bits S[9:0] based on the code bits C[9:0], the replacement bits DE[8:1], and the first detection bits Ta and the second detection bits Tb. When the first detection bits Ta and the second detection bits Tb indicate that the code bits C[9:0] correspond to the result of replacing the risk pattern with the replacement pattern at the encoder 111, in order to restore the data bits D[7:0], the second conversion circuit 126 may convert the replacement pattern into the risk pattern. When the first detection bits Ta and the second detection bits Tb indicate that the code bits C[9:0] do not correspond to the result of replacing the risk pattern at the encoder 111, the second conversion circuit 126 may not apply the replacement bits DE[8:1] to the conversion bits S[9:0].

[0146] The third conversion circuit 127 may convert the conversion bits S[9:0] into data bits D[7:0]. The third conversion circuit 127 may convert S[8:5] into first part of data bits D[7:4] based on S[9] in the conversion bits S[9:0]. The third conversion circuit 127 may convert S[4:1] into second part of data bits D[3:0] based on S[0] in the conversion bits S[9:0].

[0147] Fig.12 yes Fig.11 0026] An exemplary logic circuit diagram of a portion of a first conversion circuit.

[0148] Fig.12 The first conversion circuit 123 shown in FIG. 1 can be understood as a logic circuit that generates the first replacement bit to the eighth replacement bit DE[8:1] based on the code bit C[9:0] received from the channel 130. The code bit C[9:0] corresponds to the code bit C[9:0] described above. Fig.12 , the first conversion circuit 123 may include first to eighteenth gates G1 to G18.

[0149] The first gate G1 performs a NOR operation on C[5], C[6], and C[8] to generate DE[8]. When C[8], C[6], and C[5] are "0", "0", and "0", respectively, DE[8] is "1".

[0150] The second gate G2 and the thirteenth gate G13 generate DE[7]. The second gate G2 performs a NAND operation on the inverted version of C[8] and C[6]. The thirteenth gate G13 performs a NAND operation on the output of the second gate G2 and the inverted version of C[7]. When C[8] and C[6] are "0" and "1" respectively or C[7] is "1", DE[7] is "1".

[0151] The third gate G3, the fourth gate G4 and the fourteenth gate G14 generate DE[6]. The third gate G3 performs a NAND operation on C[1] and C[3]. The fourth gate G4 performs an XNOR operation on C[5] and C[6]. The fourteenth gate G14 performs a NAND operation on the output of the third gate G3 and the output of the fourth gate G4. When C[3] and C[1] are "1" and "1" respectively or C[5] and C[6] are different, DE[6] is "1".

[0152] The fifth gate G5, the sixth gate G6, and the fifteenth gate G15 generate DE[5]. The fifth gate G5 performs a NAND operation on the inverted version of C[7] and the inverted version of C[3]. The sixth gate G6 performs a NAND operation on the inverted version of C[6] and the inverted version of C[1]. The fifteenth gate G15 performs a NAND operation on the output of the fifth gate G5, the inverted version of C[4], and the output of the sixth gate G6. When C[7] and C[3] are "0" and "0" respectively, C[4] is "1", or C[6] and C[1] are "0" and "0" respectively, DE[5] is "1".

[0153] The seventh gate G7, the eighth gate G8, and the sixteenth gate G16 generate DE[4]. The seventh gate G7 performs a NAND operation on the inverted version of C[8] and the inverted version of C[3]. The eighth gate G8 performs a NAND operation on the inverted version of C[6] and the inverted version of C[2]. The sixteenth gate G16 performs a NAND operation on the output of the seventh gate G7, the inverted version of C[5], and the output of the eighth gate G8. When C[8] and C[3] are "0" and "0" respectively, C[5] is "1", or C[6] and C[2] are "0" and "0" respectively, DE[4] is "1".

[0154] The ninth gate G9, the tenth gate G10, and the seventeenth gate G17 generate DE[3]. The ninth gate G9 performs a NAND operation on C[8] and C[6]. The tenth gate G10 performs an XNOR operation on C[4] and C[3]. The seventeenth gate G17 performs a NAND operation on the output of the ninth gate G9 and the output of the tenth gate G10. When C[8] and C[6] are "1" and "1" respectively or C[4] and C[3] are different, DE[3] is "1".

[0155] The eleventh gate G11 and the eighteenth gate G18 generate DE[2]. The eleventh gate G11 performs a NAND operation on the inverted version of C[1] and C[4]. The eighteenth gate G18 performs a NAND operation on the output of the eleventh gate G11 and the inverted version of C[2]. When C[1] and C[4] are "0" and "1" respectively or C[2] is "1", DE[2] is "1".

[0156] The twelfth gate G12 performs a NOR operation on C[1], C[3], and C[4] to generate DE[1]. When C[1], C[3], and C[4] are "0", "0", and "0", respectively, DE[1] is "1".

[0157] Fig.13 yes Fig.11 An exemplary logic circuit diagram of a detection bit generation circuit. Fig.13 The detection bit generation circuit 124 shown in FIG. 1 can be understood as a logic circuit that generates a first detection bit Ta and a second detection bit Tb based on the code bits C[9:0] received from the channel 130. Fig.13 , the detection bit generation circuit 124 may include first to tenth gates G1 to G10.

[0158] The first gate G1, the second gate G2, the fifth gate G5, the sixth gate G6 and the ninth gate G9 generate the first detection bit Ta. The first gate G1 performs a NOR operation on C[7] and C[5]. The second gate G2 performs a NOR operation on C[6] and C[5]. The fifth gate G5 performs a NOR operation on the inverted version of C[6], the output of the first gate G1 and the inverted version of C[9]. The sixth gate G6 performs a NOR operation on the inverted version of C[8], the output of the second gate G2 and the inverted version of C[9]. The ninth gate G9 performs a NAND operation on the output of the fifth gate G5 and the output of the sixth gate G6. When C[5] and C[7] are "0" and "0" respectively, C[6] is "0", C[8] is "0", or C[9] is "0", the first detection bit Ta is "1".

[0159] The third gate G3, the fourth gate G4, the seventh gate G7, the eighth gate G8 and the tenth gate G10 generate the second detection bit Tb. The third gate G3 performs a NOR operation on C[4] and C[2]. The fourth gate G4 performs a NOR operation on C[4] and C[3]. The seventh gate G7 performs a NOR operation on the inverted version of C[3], the output of the third gate G3 and the inverted version of C[1]. The eighth gate G8 performs a NOR operation on the inverted version of C[1], the output of the fourth gate G4 and the inverted version of C[0]. The tenth gate G10 performs a NAND operation on the output of the seventh gate G7 and the output of the eighth gate G8. When C[2] and C[4] are "0" and "0" respectively, C[3] is "0", C[1] is "0", or C[0] is "0", the second detection bit Tb is "1".

[0160] Fig.14 yes Fig.11 An exemplary logic circuit diagram of a second conversion circuit. Fig.14The second conversion circuit 126 shown in FIG. 1 can be understood as a logic circuit that generates a conversion bit S[9:0] based on the code bit C[9:0], the replacement bit DE[8:1], and the first detection bit Ta and the second detection bit Tb. The conversion bit S[9:0] corresponds to the above-mentioned conversion bit S[9:0]. Fig.14 , the second conversion circuit 126 may include first to thirtieth gates G1 to G30.

[0161] The first gate G1 performs an XNOR operation on the first detection bit Ta and C[9] to generate S[9]. When the first detection bit Ta and C[9] are different, S[9] is "0"; when the first detection bit Ta and C[9] are the same, S[9] is "1".

[0162] The second gate G2, the third gate G3, and the fifteenth gate G15 generate S[8]. The second gate G2 performs a NOR operation on C[8] and the inverted version of the first detection bit Ta. The third gate G3 performs a NOR operation on DE[8] and the first detection bit Ta. The fifteenth gate G15 performs a NOR operation on the output of the second gate G2 and the output of the third gate G3. When the first detection bit Ta is "1", S[8] is the same as C[8]. When the first detection bit Ta is "0", S[8] is the same as DE[8].

[0163] The fourth gate G4, the fifth gate G5 and the sixteenth gate G16 generate S[7]. The fourth gate G4 performs a NOR operation on C[7] and the inverted version of the first detection bit Ta. The fifth gate G5 performs a NOR operation on DE[7] and the first detection bit Ta. The sixteenth gate G16 performs a NOR operation on the output of the fourth gate G4 and the output of the fifth gate G5. When the first detection bit Ta is "1", S[7] is the same as C[7]. When the first detection bit Ta is "0", S[7] is the same as DE[7].

[0164] The sixth gate G6, the seventeenth gate G17, the eighteenth gate G18 and the twenty-seventh gate G27 generate S[6]. The sixth gate G6 performs a NAND operation on the first detection bit Ta and the second detection bit Tb. The seventeenth gate G17 performs a NOR operation on the output of the sixth gate G6 and C[6]. The eighteenth gate G18 performs a NOR operation on the inverted version of the output of the sixth gate G6 and DE[6]. The twenty-seventh gate G27 performs a NOR operation on the output of the seventeenth gate G17 and the output of the eighteenth gate G18. When the first detection bit Ta and the second detection bit Tb are "1" and "1" respectively, S[6] is the same as C[6]; otherwise, S[6] is the same as DE[6].

[0165] The seventh gate G7, the nineteenth gate G19, the twentieth gate G20 and the twenty-eighth gate G28 generate S[5]. The seventh gate G7 performs a NAND operation on the first detection bit Ta and the second detection bit Tb. The nineteenth gate G19 performs a NOR operation on the output of the seventh gate G7 and C[5]. The twentieth gate G20 performs a NOR operation on the inverted version of the output of the seventh gate G7 and DE[5]. The twenty-eighth gate G28 performs a NOR operation on the output of the nineteenth gate G19 and the output of the twentieth gate G20. When the first detection bit Ta and the second detection bit Tb are "1" and "1" respectively, S[5] is the same as C[5]; otherwise, S[5] is the same as DE[5].

[0166] The eighth gate G8, the twenty-first gate G21, the twenty-second gate G22, and the twenty-ninth gate G29 generate S[4]. The eighth gate G8 performs a NAND operation on the first detection bit Ta and the second detection bit Tb. The twenty-first gate G21 performs a NOR operation on the output of the eighth gate G8 and C[4]. The twenty-second gate G22 performs a NOR operation on the inverted version of the output of the eighth gate G8 and DE[4]. The twenty-ninth gate G29 performs a NOR operation on the output of the twenty-first gate G21 and the output of the twenty-second gate G22. When the first detection bit Ta and the second detection bit Tb are "1" and "1" respectively, S[4] is the same as C[4]; otherwise, S[4] is the same as DE[4].

[0167] The ninth gate G9, the twenty-third gate G23, the twenty-fourth gate G24, and the thirtieth gate G30 generate S[3]. The ninth gate G9 performs a NAND operation on the first detection bit Ta and the second detection bit Tb. The twenty-third gate G23 performs a NOR operation on the output of the ninth gate G9 and C[3]. The twenty-fourth gate G24 performs a NOR operation on the inverted version of the output of the ninth gate G9 and DE[3]. The thirtieth gate G30 performs a NOR operation on the output of the twenty-third gate G23 and the output of the twenty-fourth gate G24. When the first detection bit Ta and the second detection bit Tb are "1" and "1" respectively, S[3] is the same as C[3]; otherwise, S[3] is the same as DE[3].

[0168] The tenth gate G10, the eleventh gate G11, and the twenty-fifth gate G25 generate S[2]. The tenth gate G10 performs a NOR operation on C[2] and the inverted version of the second detection bit Tb. The eleventh gate G11 performs a NOR operation on DE[2] and the second detection bit Tb. The twenty-fifth gate G25 performs a NOR operation on the output of the tenth gate G10 and the output of the eleventh gate G11. When the second detection bit Tb is "1", S[2] is the same as C[2]. When the second detection bit Tb is "0", S[2] is the same as DE[2].

[0169] The twelfth gate G12, the thirteenth gate G13 and the twenty-sixth gate G26 generate S[1]. The twelfth gate G12 performs a NOR operation on C[1] and the inverted version of the second detection bit Tb. The thirteenth gate G13 performs a NOR operation on DE[1] and the second detection bit Tb. The twenty-sixth gate G26 performs a NOR operation on the output of the twelfth gate G12 and the output of the thirteenth gate G13. When the second detection bit Tb is "1", S[1] is the same as C[1]. When the second detection bit Tb is "0", S[1] is the same as DE[1].

[0170] The fourteenth gate G14 performs an XNOR operation on the second detection bit Tb and C[0] to generate S[0]. When the second detection bit Tb and C[0] are different, S[0] is "0"; when the second detection bit Tb and C[0] are the same, S[0] is "1".

[0171] Fig.15 yes Fig.11 An exemplary logic circuit diagram of a third conversion circuit. Fig.15 The third conversion circuit 127 shown in FIG. 1 can be understood as a logic circuit that generates data bits D[7:0] based on conversion bits S[9:0]. Data bits D[7:0] correspond to the above-mentioned data bits D[7:0]. Fig.15 , the third conversion circuit 127 may include first to eighth gates G1 to G8.

[0172] The first gate G1 performs an XOR operation on S[9] and S[8] to generate D[7]. The second gate G2 performs an XOR operation on S[9] and S[7] to generate D[6]. The third gate G3 performs an XOR operation on S[9] and S[6] to generate D[5]. The fourth gate G4 performs an XOR operation on S[9] and S[5] to generate D[4]. Therefore, when S[9] is "1", S[8:5] is inverted; when S[9] is "0", S[8:5] is not inverted.

[0173] The fifth gate G5 performs an XOR operation on S[0] and S[4] to generate D[3]. The sixth gate G6 performs an XOR operation on S[0] and S[3] to generate D[2]. The seventh gate G7 performs an XOR operation on S[0] and S[2] to generate D[1]. The eighth gate G8 performs an XOR operation on S[0] and S[1] to generate D[0]. Therefore, when S[0] is "1", S[4:1] is inverted; when S[0] is "0", S[4:1] is not inverted.

[0174] Fig.16 It is shown Figure 1 A block diagram of a system corresponding to one channel in a semiconductor system. Fig.16, the semiconductor system 200 includes an encoder 211, a transmission interface circuit 218, a decoder 221, a reception interface circuit 228 and a channel 230. The encoder 211 corresponds to Figure 1 and Figure 2 The encoder 111 and the decoder 221 correspond to Figure 1 and Fig.11 Decoder 121.

[0175] As described above, the encoder 211 can convert the data bits D[7:0] into code bits C[9:0]. The code bits C[9:0] are converted into a transmit signal VT[9:0] to be transmitted to the channel 230 through the transmit interface circuit 218. The channel 230 can receive one of the transmit signals VT[9:0], and the remaining transmit signals are received by other channels arranged in parallel. Similarly, the transmit interface circuit 218 converts one of the code bits C[9:0] into a transmit signal, and the remaining code bits are converted by other transmit interface circuits arranged in parallel.

[0176] The transmission interface circuit 218 may include an XOR gate GT, a delay 219, and a transmission driver TD. A transition that occurs when the logic value of the code bit C[9:0] is "1" may be detected by the XOR gate GT and the delay 219. Based on the detection of the transition, the XOR gate GT may output a transmission bit W[9:0] corresponding to the code bit C[9:0] to the transmission driver TD. The transmission driver TD may convert the transmission bit W[9:0] into a transmission signal VT[9:0] that can be transmitted through the channel 230.

[0177] The receiving interface circuit 228 converts the receiving signal VR[9:0] received through the channel 230 into a code bit C[9:0]. The receiving interface circuit 228 may include an XOR gate GT, a delay 229, and a receiving driver RD. The receiving driver RD may convert the receiving signal VR[9:0] into a receiving bit Z[9:0] as a digital signal. A transition occurring when the logic value of the receiving bit Z[9:0] is "1" may be detected by the XOR gate GT and the delay 219. Based on the detection of the transition, the XOR gate GT may output the code bit C[9:0] to the decoder 221. As described above, the decoder 221 converts the code bit C[9:0] into a data bit D[7:0].

[0178] Fig.17 The reference is applied Figures 1 to 16 1000 is an exemplary diagram of an electronic device that includes an encoder and a decoder described herein. The electronic device 1000 may be referred to as a “computing system”, “memory system”, “electronic system” or “communication system”. The electronic device 1000 may include a memory module 1100 and a memory controller 1300. Although Fig.17Although not shown in the figure, the electronic device 1000 may further include a substrate provided with the memory module 1100 and the memory controller 1300 and a socket in which the memory module 1100 is mounted.

[0179] The memory module 1100 may include a memory device 1200. In the electronic device 1000, the number of the memory modules 1100 and the number of the memory devices 1200 attached to one memory module 1100 are not limited to Fig.17 . The memory module 1100 may be a dual in-line memory module (DIMM) that complies with the JEDEC (Joint Electron Device Engineering Council) standard. The memory module 1100 may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM), or any other memory module (e.g., a single in-line memory module (SIMM)).

[0180] The memory device 1200 may be various DRAM devices such as double data rate synchronous dynamic random access memory (DDRSDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, graphic double data rate synchronous graphic random access memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, etc. The memory device 1200 may be a memory device in which DRAM dies are stacked, such as high bandwidth memory (HBM), HBM2, HBM3, etc. The memory device 1200 may include a static random access memory (SRAM) device, a thyristor RAM (TRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive RAM (RRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), etc. The type of the memory device 1200 is not limited to the above types, and the memory device 1200 may include any device capable of storing data.

[0181] A plurality of paths for transmitting a command signal CMD / address signal ADD and a data input / output signal DQ may be inserted between the memory module 1100 and the memory controller 1300. The plurality of paths may correspond to Figure 1 Channel 130.

[0182] The memory device 1200 may include at least one of the above-mentioned transmitter 110 or the receiver 120. For example, the memory device 1200 may receive a command signal CMD / address signal ADD transmitted through a plurality of paths from the memory controller 1300 using the receiver 120. For example, the memory device 1200 may transmit or receive a data input / output signal DQ through a plurality of paths using at least one of the transmitter 110 or the receiver 120.

[0183] The memory controller 1300 may further include at least one of the transmitter 110 or the receiver 120 described above. For example, the memory controller 1300 may transmit a command signal CMD / address signal ADD to a plurality of paths using the transmitter 110. For example, the memory controller 1300 may transmit or receive a data input / output signal DQ through a plurality of paths using at least one of the transmitter 110 or the receiver 120.

[0184] Fig.18 The reference is applied Figures 1 to 16 An exemplary diagram of an electronic device of an encoder and a decoder is described. The electronic device 2000 may include a memory device 2200 , a system on chip (SoC) 2300 , and a substrate 2400 .

[0185] The memory device 2200 may include memory dies 2210 and 2220 and a buffer die 2230 stacked in a vertical direction. The memory device 2200 may be a high bandwidth memory (HBM) device providing high bandwidth. The memory device 2200 may be disposed on one surface of the substrate 2400, and solder balls or bumps may be disposed on one surface of the memory device 2200. The memory device 2200 and the substrate 2400 may be electrically interconnected through the solder balls or bumps.

[0186] The through silicon vias TSV may provide a physical path or an electrical path between the memory dies 2210 and 2220 and the buffer die 2230. For example, the through silicon vias TSV may be arranged in a matrix form, and the positions where the through silicon vias TSV are arranged are not limited to Fig.18 .

[0187] The memory die 2210 may include a first region 2211 and a second region 2212. Fig.17 The components of the described memory device 1200 may be disposed in the first region 2211. Through silicon vias TSV may be disposed in the second region 2212, and a circuit for transmitting or receiving a signal through the through silicon vias TSV may be disposed in the second region 2212. For example, at least one of the above-described transmitter 110 or receiver 120 may be disposed in the second region 2212. The memory die 2220 may be implemented to be substantially the same as the memory die 2210.

[0188] The buffer die 2230 (referred to as a "core die" or a "logic die") may include a first area 2231 and a second area 2232. In order to transmit a command CMD, an address ADD, and a data input / output signal DQ transmitted through an input / output path, at least one of the transmitter 110 or the receiver 120 described above may be disposed in the first area 2231. In addition, referring to Fig.17 The components of the described memory device 1200 may be disposed in the first region 2231. Through silicon vias TSV may be disposed in the second region 2232, and a circuit for transmitting or receiving a signal through the through silicon vias TSV may be disposed in the second region 2232.

[0189] The SoC 2300 may be disposed on one surface of the substrate 2400, and solder balls or bumps may be disposed on one surface of the SoC 2300. The SoC 2300 and the substrate 2400 may be electrically interconnected through the solder balls or bumps. The SoC 2300 may include Fig.17 The SoC 2300 may include components of the memory controller 1300 , a processor, an on-chip memory, etc. In order to transmit or receive a data input / output signal DQ through an input / output path, the SoC 2300 may include at least one of the transmitter 110 or the receiver 120 described above.

[0190] The substrate 2400 may provide an input / output path between the SoC 2300 and the memory device 2200. For example, the substrate 2400 may include a printed circuit board, a flexible circuit board, a ceramic substrate, or an interposer. In the case where the substrate 2400 is an interposer, the substrate 2400 may be implemented using a silicon wafer. A plurality of input / output paths may be implemented within the substrate 2400.

[0191] Fig.19 The reference is applied Figures 1 to 16 3000 is an exemplary diagram of an electronic device of an encoder and a decoder described in the present invention. The electronic device 3000 can be implemented using an electronic device that can use or support an interface proposed by the Mobile Industry Processor Interface (MIPI) Alliance. For example, the electronic device 3000 can be (but is not limited to) one of a server, a computer, a smart phone, a tablet, a personal digital assistant (PDA), a digital camera, a portable multimedia player (PMP), a wearable device, an Internet of Things (IoT) device, a mobile device, etc.

[0192] The electronic device 3000 may include a SoC 3100 and a memory device 3200. The SoC 3100 may include a processor 3110, an on-chip memory 3120, and a memory controller 3130. The SoC 3100 may be referred to as an "application processor". The processor 3110 may execute various programs stored in the on-chip memory 3120 and may control the memory controller 3130. The memory controller 3130 may include Fig.17 The memory device 3200 may include components of the memory controller 1300. Fig.17 The memory controller 3130 may transmit a command CMD, an address ADD, and a data input / output signal DQ to the memory device 3200. The memory device 3200 may transmit a data input / output signal DQ to the memory controller 3130.

[0193] The electronic device 3000 may further include a display 3400 that communicates with the SoC 3100. The SoC 3100 may communicate with a DSI device 3410 in accordance with a display serial interface (DSI). An optical deserializer DES may be implemented in the DSI device 3410. The electronic device 3000 may further include an image sensor 3500 that communicates with the SoC 3100. The SoC 3100 may communicate with a CSI device 3510 in accordance with a camera serial interface (CSI). An optical serializer SER may be implemented in the CSI device 3510.

[0194] The electronic device 3000 may further include a radio frequency (RF) chip 3600 that communicates with the SoC 3100. The RF chip 3600 may include a physical layer 3610, a DigRF slave 3620, and an antenna 3630. For example, the physical layer 3610 and the SoC 3100 may exchange data with each other in accordance with a DigRF interface proposed by the MIPI Alliance.

[0195] The electronic device 3000 may further include an embedded / card storage unit 3700. The embedded / card storage unit 3700 may store data provided from the SoC 3100. The electronic device 3000 may communicate with an external system through Worldwide Interoperability for Microwave Access (WiMAX) 3810, a wireless local area network (WLAN) 3820, an ultra-wideband (UWB) 3830, or the like.

[0196] In some example embodiments, in order to exchange data with any other component of the electronic device 3000, each of the components 3100, 3110, 3120, 3130, 3200, 3400, 3410, 3500, 3510, 3600, 3610, 3620, 3630, 3700, 3810, 3820 and 3830 of the electronic device 3000 may include at least one of the above-mentioned transmitter 110 or receiver 120.

[0197] Fig. 20 The reference is applied Figures 1 to 16 An exemplary diagram of an electronic device of an encoder and a decoder is described. The electronic device 4000 may include a first SoC 4100 and a second SoC 4200.

[0198] The first SoC 4100 and the second SoC 4200 may communicate with each other based on the open system interconnection (OSI) 7-layer structure proposed in the international standard organization. For example, each of the first SoC 4100 and the second SoC 4200 may include an application layer AL, a presentation layer PL, a session layer SL, a transport layer TL, a network layer NL, a data link layer DL, and a physical layer PHY.

[0199] The layers of the first SoC 4100 may communicate physically or logically with the corresponding layers of the second SoC 4200. The application layer AL, presentation layer PL, session layer SL, transport layer TL, network layer NL, data link layer DL, and physical layer PHY of the first SoC 4100 may communicate logically or physically with the application layer AL, presentation layer PL, session layer SL, transport layer TL, network layer NL, data link layer DL, and physical layer PHY of the second SoC 4200, respectively.

[0200] In some example embodiments, the physical layer PHY of the first SoC 4100 may include a receiver 4110. The receiver 4110 may be the above-described receiver 120. The physical layer PHY of the second SoC 4200 may include a transmitter 4210 that transmits a transmission signal via a channel 4300. The transmitter 4210 may be the above-described transmitter 110.

[0201] According to a transmitter that transmits a signal to a channel, a receiver that receives a signal from a channel, and a semiconductor system including the transmitter and the receiver, the signal can be encoded or decoded so that the transition of parallel signals is reduced. Therefore, crosstalk between channels can be reduced.

[0202] While some example embodiments have been described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of some example embodiments as set forth in the appended claims.

Claims

1. A transmitter for sending signals to channel parallel outputs, comprising: The encoder is configured as: receiving a data bit having a target logic value, generating a toggle bit based on the number of data bits, the number of toggle bits being greater than the number of data bits, detecting a risk pattern of the transition bits to generate detection data, and converting the risk pattern into a replacement pattern based on the detection data to generate code bits, the number of the code bits being equal to the number of the conversion bits; as well as The transmission interface circuit is configured to convert the code bits into the transmission signal.

2. The transmitter according to claim 1, wherein: The encoder is configured as: generating a first portion of the conversion bits based on the number of first bits having the target logic value among the first portion of the data bits; and A second portion of the conversion bits is generated based on the number of second bits having the target logic value among the second portion of the data bits.

3. The transmitter according to claim 2, wherein: The encoder is configured as: Based on the number of the first bits being greater than half of the total number of the first portion of data bits, negating the logic value of the first portion of data bits to generate the first portion of conversion bits; and Based on the number of the second bits being greater than half of the total number of the second portion of data bits, logic values ​​of the second portion of data bits are inverted to generate the second portion of conversion bits.

4. The transmitter according to claim 3, wherein: The number of data bits is 8, The number of conversion bits is 10, The number of channels is 10, The number of the first part of data bits is 4, The number of the second part of data bits is 4, The number of the first part conversion bits is 5, and The number of the second part conversion bits is 5; wherein 4 bits in the first part of conversion bits correspond to the first part of data bits respectively, and the remaining bits other than the 4 bits in the first part of conversion bits indicate whether the first part of data bits are inverted; and The four bits in the second part of conversion bits correspond to the second part of data bits respectively, and the remaining bits other than the four bits in the second part of conversion bits indicate whether the second part of data bits are inverted.

5. The transmitter according to claim 1, wherein: In the risk pattern, the number of bits having the target logic value among the bits respectively corresponding to the four channels arranged sequentially in the conversion bits is 3 or more.

6. The transmitter according to claim 5, wherein: The encoder is configured as: detecting a first pattern of transition bits based on the data bits; generating a first detection bit of the detection data, the first detection bit having a logic value depending on whether the first pattern is detected; detecting a second pattern of the transition bits based on the data bits; and generating a second detection bit of the detection data, the second detection bit having a logic value based on whether the second pattern is detected, wherein the first pattern has the risk pattern, and two of the first part of the conversion bits have the target logic value in the first pattern, and The second pattern has the risk pattern, and two of the second part of the conversion bits have the target logic value in the second pattern.

7. The transmitter according to claim 1, wherein: The encoder generates replacement bits corresponding to the data bits respectively based on bits among the conversion bits corresponding to the data bits respectively, wherein, based on the conversion bit having the risk pattern, the replacement bit is generated to have the replacement pattern, and In the replacement pattern, the number of bits having the target logic value among the bits in the replacement bits respectively corresponding to four channels arranged sequentially is less than three.

8. The transmitter according to claim 7, wherein: The encoder is configured as: generating detection data having a first logic value based on the presence of the risk pattern in the conversion bit; and generating detection data having a second logic value based on the absence of the risk pattern in the conversion bit, wherein, based on the detection data having the first logic value, some of the code bits are the replacement bits, and Wherein, based on the detection data having the second logic value, the code bit is the conversion bit.

9. A receiver for receiving signals from channels in parallel, comprising: a receiving interface circuit configured to convert the received signal into code bits; as well as The decoder is configured as: generating detection data based on the pattern of code bits; converting at least a portion of the code bits into a risk pattern based on the detection data to generate conversion bits; and converting the conversion bits into data bits, the number of the data bits being less than the number of the conversion bits, Among them, in the risk pattern, the number of bits having a target logic value among the bits in the conversion bits respectively corresponding to four channels arranged sequentially is 3 or more.

10. The receiver according to claim 9, wherein: Two of the code bits have logic values ​​depending on whether the data bit or the transition bit has the risk pattern, and The decoder is configured to generate a replacement bit based on a pattern of different code bits from the two code bits, and determine whether to convert the different code bits into the replacement bit based on the detection data.

11. The receiver according to claim 9, wherein: The decoder is configured to: generating a first detection bit having a logic value depending on whether the first portion of data bits of the code bits have a target pattern; and generating a second detection bit having a logic value depending on whether the second part of the data bits of the code bits have the target pattern, and The detection data includes the first detection bit and the second detection bit.

12. The receiver according to claim 11, wherein: The decoder is configured to: switching a pattern of some of the first portion of data bits and some of the second portion of data bits based on the first detection bit; and The patterns of some of the second portion of data bits and some of the first portion of data bits are switched based on the second detection bit.

13. The receiver according to claim 9, wherein: The decoder is configured to: generating a first portion of data bits of the data bits by determining whether to invert remaining conversion bits in the first portion of conversion bits based on a first conversion bit in the first portion of conversion bits; and A second portion of data bits of the data bits is generated by determining whether to invert the remaining transition bits of the second portion of transition bits based on a second transition bit of the second portion of transition bits.

14. A semiconductor system comprising: a transmitter configured to generate conversion bits based on the number of data bits each having a target logic value among the data bits, the number of conversion bits being greater than the number of the data bits, and convert the risk pattern into a replacement pattern to generate code bits when the conversion bits have a risk pattern; as well as a channel unit, comprising channels, the number of the channels being equal to the number of the code bits, and configured to receive a signal generated based on the code bits; as well as A receiver is configured to receive the signal through the channel unit, convert the signal into the code bits, and convert the code bits into the data bits.

15. The semiconductor system according to claim 14, wherein: The transmitter comprises: an encoder configured to generate the code bits based on the data bits so that the number of bits having the target logic value among the bits in the code bits respectively corresponding to four channels arranged sequentially is less than 3; and The transmission interface circuit is configured to convert the code bits into a transmission signal.

16. The semiconductor system according to claim 14, wherein: The transmitter is configured as: generating a first portion of conversion bits of the conversion bits based on the number of first bits having the target logic value among a first portion of data bits corresponding to half of the data bits; and A second portion of the conversion bits is generated based on the number of second bits having the target logic value among a second portion of the data bits corresponding to the remaining half of the data bits.

17. The semiconductor system according to claim 14, wherein: The transmitter is configured as: detecting the risk pattern of the transition bits to generate detection data; and The risk pattern is converted to the replacement pattern based on the detection data.

18. The semiconductor system according to claim 14, wherein: The receiver comprises: a receiving interface circuit configured to convert the signal received from the channel unit into the code bits; and A decoder is configured to generate detection data based on the pattern of the code bits, convert the code bits into the conversion bits based on the detection data, and convert the conversion bits into the data bits.

19. The semiconductor system according to claim 14, wherein: The receiver is configured to: determining, based on the pattern of the code bits, whether the code bits are converted to the replacement pattern; and Based on the code bits being converted into the replacement pattern, the conversion bits are generated by converting the replacement pattern into the risk pattern.

20. The semiconductor system according to claim 14, wherein: The number of channels is 10, The number of conversion bits is 10, and The number of data bits is 8.

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