imaging device

Abstract

An imaging device in which freedom of layout is improved is provided. The imaging device includes a first semiconductor substrate including a sensor pixel for performing photoelectric conversion, and a second semiconductor substrate including a readout circuit for outputting a pixel signal based on a charge output from the sensor pixel. The second semiconductor substrate is laminated on one surface side of the first semiconductor substrate to constitute a laminate. The second semiconductor substrate includes a first surface facing the first semiconductor substrate and a second surface located on an opposite side of the first surface. A first transistor included in the readout circuit is provided in the first surface, and a second transistor included in the readout circuit is provided in the second surface.

Description

TECHNICAL FIELD

[0001] The present application relates to an imaging device. BACKGROUND

[0002] Generally, reduction in area of each pixel of an imaging device having a two-dimensional configuration has been achieved by introducing microfabrication and increasing packaging density. In recent years, an imaging device having a three-dimensional configuration has been developed to achieve reduction in size of the imaging device and increase in pixel density of the imaging device (see, for example, Patent Literature 1). Such an imaging device having a three-dimensional configuration includes a first semiconductor substrate having a plurality of sensor pixels and a second semiconductor substrate having a readout circuit for readout processing of a signal obtained by a corresponding one of the pixels. The second semiconductor substrate is laminated on one surface side of the first semiconductor substrate.

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: JP 2010-245506 A SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] The readout circuit includes a selection transistor for selection among the sensor pixels, an amplification transistor for amplifying the signal obtained by the sensor pixel, and a reset transistor for resetting the signal obtained by the sensor pixel. The arrangement and size of the transistors included in the readout circuit (hereinafter referred to as layout) affect the performance of the imaging device. Therefore, it is desirable to improve the degree of freedom of the layout.

[0008] The present application has been made in view of the above circumstances, and an object of the present application is to provide an imaging device capable of improving the degree of freedom of its layout.

[0009] SOLUTION TO PROBLEM

[0010] The imaging device according to an aspect of the present application includes a first semiconductor substrate including a sensor pixel configured to perform photoelectric conversion, and a second semiconductor substrate including a readout circuit configured to output a pixel signal based on a charge output from the sensor pixel. The second semiconductor substrate is laminated on one surface side of the first semiconductor substrate to constitute a laminate. The second semiconductor substrate includes a first surface facing the first semiconductor substrate and a second surface located on the opposite side of the first surface. A first transistor included in the readout circuit is provided in the first surface, and a second transistor included in the readout circuit is provided in the second surface.

[0011] Compared with a case where the transistors included in the readout circuit are provided on only one side of the second semiconductor substrate, the area of the arrangement region allocated to the transistors can be made larger, and thus the degree of freedom of the layout of the readout circuit is improved. For example, the amplification transistor can be provided in the first surface of the second semiconductor substrate, and the selection transistor and the reset transistor can be provided in the second surface of the second semiconductor substrate. This configuration can maximize the area of the amplification transistor, and thus random noise occurring in the imaging device is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a schematic view showing a configuration example of an imaging device according to a first embodiment of the present application.

[0013] Figure 2 is a circuit diagram showing a configuration example of a pixel unit according to the first embodiment of the present application.

[0014] Figure 3 is a cross-sectional view in a depth direction showing a configuration example of a pixel unit according to the first embodiment of the present application.

[0015] Figure 4A is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the first embodiment of the present application.

[0016] Figure 4B is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the first embodiment of the present application.

[0017] Figure 4C is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the first embodiment of the present application.

[0018] Figure 5 is a cross-sectional view in a horizontal direction showing a layout example of a plurality of pixel units.

[0019] Figure 6 is a cross-sectional view in a horizontal direction showing a layout example of a plurality of pixel units.

[0020] Figure 7 is a cross-sectional view in a horizontal direction showing a layout example of a plurality of pixel units.

[0021] Figure 8 is a cross-sectional view showing a manufacturing method of an imaging device according to the first embodiment of the present application.

[0022] Figure 9 is a cross-sectional view showing a manufacturing method of an imaging device according to the first embodiment of the present application.

[0023] Figure 10is a cross-sectional view showing a manufacturing method of an imaging device according to the first embodiment of the present application.

[0024] Figure 11 is a cross-sectional view showing a manufacturing method of an imaging device according to the first embodiment of the present application.

[0025] Figure 12 is a cross-sectional view in a thickness direction showing a configuration example of an imaging device according to the second embodiment of the present application.

[0026] Figure 13A is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the second embodiment of the present application.

[0027] Figure 13B is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the second embodiment of the present application.

[0028] Figure 13C is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the second embodiment of the present application.

[0029] Figure 13D is a cross-sectional view in a horizontal direction showing a configuration example of a pixel unit according to the second embodiment of the present application.

[0030] Figure 14 is a cross-sectional view showing a manufacturing method of an imaging device according to the second embodiment of the present application.

[0031] Figure 15 is a cross-sectional view showing a manufacturing method of an imaging device according to the second embodiment of the present application.

[0032] Figure 16 is a cross-sectional view showing a manufacturing method of an imaging device according to the second embodiment of the present application.

[0033] Figure 17 is a cross-sectional view showing a manufacturing method of an imaging device according to the second embodiment of the present application. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In the drawings which are referred to in the following description, the same or similar parts or symbols are denoted by the same or similar reference numerals and symbols. However, it should be noted that the drawings are merely schematic and the relationship of thickness to planar dimensions and the thickness ratio between layers and the like can differ from reality. Therefore, specific thicknesses and dimensions and the like should be determined in consideration of the following description. Furthermore, it goes without saying that parts which differ in size relationship or size ratio between the drawings can be included in the drawings.

[0035] In the following description, the definition of directions such as up and down is merely a definition for the convenience of explanation, and does not limit the technical idea of the present application. For example, it goes without saying that when an object is rotated by 90 degrees and observed, up and down are converted into left and right and are read, and when an object is rotated by 180 degrees and observed, up and down are reversed and are read.

[0036] Further, there are cases where the terms "X-axis direction", "Y-axis direction", and "Z-axis direction" are used for explanation. For example, the Z-axis direction is parallel to the thickness direction of the laminate to be described later. The X-axis direction and the Y-axis direction are directions orthogonal to the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. In the following description, the direction parallel to the X-axis direction and the Y-axis direction is also referred to as the horizontal direction. Further, in the following description, the term "plan view" means viewing from the Z-axis direction.

[0037] (First Embodiment)

[0038] Figure 1 is a schematic view showing a configuration example of an imaging device 1 according to the first embodiment of the present application. The imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 is an imaging device having a three-dimensional configuration constituted by laminating the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are laminated in this order.

[0039] The first substrate 10 is such that a first semiconductor substrate 11 includes a plurality of sensor pixels 12 for performing photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix form in a pixel region 13 of the first substrate 10. The second substrate 20 is such that a second semiconductor substrate 21 includes a readout circuit 22 for outputting a pixel signal based on a charge output from the sensor pixels 12, one circuit for every four sensor pixels 12. The second substrate 20 includes a plurality of pixel drive lines 23 extending in a row direction and a plurality of vertical signal lines 24 extending in a column direction.

[0040] The third substrate 30 is such that a third semiconductor substrate 31 includes a logic circuit 32 for processing a pixel signal. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout of each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low resistance region containing a silicide such as CoSi2or NiSi or the like can be formed on the surface of an impurity diffusion region in contact with a source electrode and a drain electrode, and the silicide is formed by using a Self Aligned Silicide process.

[0041] For example, the vertical drive circuit 33 selects the plurality of sensor pixels 12 in units of rows in sequence. For example, the column signal processing circuit 34 performs a correlated double sampling (CDS) process on a pixel signal output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 performs the CDS process, thereby extracting a signal level of the pixel signal and holding pixel data corresponding to an amount of light received by a corresponding one of the sensor pixels 12. For example, the horizontal drive circuit 35 outputs the pixel data held in the column signal processing circuit 34 to the outside in sequence. For example, the system control circuit 36 controls driving of all blocks (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0042] Figure 2 is a circuit diagram showing a configuration example of a pixel unit PU according to the first embodiment of the present application. As Figure 2 indicated, in the imaging device 1, four sensor pixels 12 are electrically connected to one readout circuit 22 to constitute one pixel unit PU. The four sensor pixels 12 share one readout circuit 22, and outputs from each of the four sensor pixels 12 are output to the shared readout circuit 22.

[0043] The sensor pixels 12 include components that are common to each other. In Figure 2 order to distinguish the components of each sensor pixel 12 from each other, a corresponding identification number (1, 2, 3, or 4) is given to the end of the reference numeral of the components of each sensor pixel 12 (e.g., PD, TG, and FD explained later). Hereinafter, in a case where it is necessary to distinguish the components of each sensor pixel 12 from each other, such a corresponding identification number is given to the end of the reference numeral of the components of each sensor pixel 12. However, in a case where it is not necessary to distinguish the components of each sensor pixel 12 from each other, no identification number is given to the end of the reference numeral of the components of the sensor pixel 12.

[0044] The sensor pixels 12 each include, for example, a photodiode PD (one example of a photoelectric conversion element), a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion portion FD that temporarily holds electric charges output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate electric charges corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion portion FD, and the gate electrode of the transfer transistor TR is electrically connected to the pixel drive line 23. The transfer transistor TR is, for example, a complementary metal oxide semiconductor (CMOS: Complementary Metal Oxide Semiconductor) transistor.

[0045] The floating diffusion portions FD of the respective sensor pixels 12 that share the readout circuit 22 are electrically connected to each other and to an input terminal of the shared readout circuit 22. The readout circuit 22 includes, for example, an amplification transistor AMP (one example of a first transistor), a reset transistor RST, and a selection transistor SEL (one example of a second transistor). Note that the selection transistor SEL can be omitted as needed.

[0046] The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion portion FD, and the drain of the reset transistor RST is electrically connected to both the power supply line VDD and the drain of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate electrode of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate electrode of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0047] When the transfer transistor TR is turned on, the transfer transistor TR transfers the electric charges of the photodiode PD to the floating diffusion portion FD. As will be described later Figure 3 , the gate electrode TG of the transfer transistor TR extends, for example, from the surface of the first semiconductor substrate 11 through the well layer WE to a depth reaching the photodiode PD. The reset transistor RST resets the potential of the floating diffusion portion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion portion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22.

[0048] The amplification transistor AMP generates a voltage signal corresponding to the level of the electric charge held in the floating diffusion section FD as a pixel signal. The amplification transistor AMP is configured as a source follower amplifier to output a pixel signal of a voltage corresponding to the level of the electric charge generated by each photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion section FD and outputs a voltage corresponding to the thus amplified potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0049] Figure 3 is a cross-sectional view in the thickness direction showing a configuration example of the pixel unit PU according to the first embodiment of the present application. Note that, Figure 3 The cross-sectional view shown is merely a schematic view, and is not intended to be a view that strictly and correctly shows the actual structure. Figure 3 The cross-sectional view shown includes some portions in which the positions of the transistors and the impurity diffusion layers in the horizontal direction are intentionally changed for the purpose of easily understanding the explanation of the configuration of the pixel unit PU included in the imaging device 1 by viewing the drawings.

[0050] For example, in Figure 3 , the floating diffusion section FD, the gate electrode TG of the transfer transistor TR, and the well contact layer WEC are provided side by side in the horizontal direction. However, in the actual structure, there is a case in which the floating diffusion section FD, the gate electrode TG, and the well contact layer WEC are provided side by side in a direction perpendicular to the plane of the drawing. In this case, one of the floating diffusion section FD and the well contact layer WEC is provided in front of the plane of the drawing, the other of the floating diffusion section FD and the well contact layer WEC is provided in the rear of the plane of the drawing, and the gate electrode TG is interposed therebetween. The actual structure of the imaging device 1 will be shown more accurately in Figures 4A-4C to be described later.

[0051] As shown in Figure 3 , the imaging device 1 has the second substrate 20 laminated on the front surface 10a (one example of one surface) side of the first substrate 10 to constitute a laminate. On the front surface 10a side of the first substrate 10, the photodiode PD, the transfer transistor TR, and the floating diffusion section FD are provided. The photodiode PD, the transfer transistor TR, and the floating diffusion section FD are provided for each sensor pixel 12.

[0052] The other surface (for example, the rear surface) of the first substrate 10 is a light incident surface. The imaging device 1 is a back-illuminated imaging device in which a color filter and a light-receiving lens are provided on the rear surface thereof. The color filter and the light-receiving lens are provided for each sensor pixel 12.

[0053] The first semiconductor substrate 11 included in the first substrate 10 includes, for example, a silicon substrate. In a portion of the front surface of the first semiconductor substrate 11 and in the vicinity of the portion, a well layer WE of a first conductivity type (for example, p type) is provided. In a region deeper than the well layer WE, a photodiode PD of a second conductivity type (for example, n type) is provided. Further, in the inside of each well layer WE, a well contact layer WEC of p type having a higher concentration than the well layer WE and a floating diffusion FD of n type are provided. The well contact layer WEC is provided in order to reduce contact resistance between the well layer WE and a wiring.

[0054] In the first semiconductor substrate 11, an element isolation layer 16 intended to electrically isolate adjacent sensor pixels 12 from each other is provided. Each element isolation layer 16 has, for example, a shallow trench isolation (STI) structure and extends in the depth direction of the first semiconductor substrate 11. The element isolation layer 16 contains, for example, silicon oxide. Further, in the first semiconductor substrate 11, between the element isolation layer 16 and the photodiode PD, a p type layer 17 and an n type layer 18 are provided. The p type layer 17 is located on the element isolation layer 16 side, and the n type layer 18 is located on the photodiode PD side.

[0055] On the surface side of the first semiconductor substrate 11, an insulating film 15 is provided. The insulating film 15 is, for example, a film formed by laminating any one or two or more of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), and a silicon carbonitride film (SiCN).

[0056] The second semiconductor substrate 21 included in the second substrate 20 includes, for example, a silicon substrate. The second semiconductor substrate 21 has a front surface 21a (one example of a first surface) facing the first substrate 10 and a back surface 21b (one example of a second surface) located on the opposite side of the front surface 21a. In the front surface 21a, an amplification transistor AMP is provided. In the back surface 21b, a selection transistor SEL and a reset transistor RST are provided. Figure 3 In the present embodiment, the front surface 21a is an upper surface, and the back surface 21b is a lower surface. In the front surface 21a, the amplification transistor AMP is provided. In the back surface 21b, the selection transistor SEL and the reset transistor RST are provided.

[0057] The second semiconductor substrate 21 is provided with an element isolation layer 26 and a p type well layer 27. The element isolation layer 26 is provided on the back surface 21b side of the second semiconductor substrate 21 so as to electrically isolate between the selection transistor SEL and the reset transistor RST. The well layer 27 is provided in a range from the back surface 21b to the front surface 21a and an intermediate position between the back surface 21b. The well layer 27 electrically isolates the amplification transistor AMP provided on the front surface 21a side of the second semiconductor substrate 21 from the selection transistor SEL and the reset transistor RST both provided on the back surface 21b side of the second semiconductor substrate 21.

[0058] The second substrate 20 includes an insulating film 25 covering the front surface 21a, rear surface 21b, and side surface of the second semiconductor substrate 21. For example, the insulating film 25 is formed by laminating one or more of SiO, SiN, SiON, and SiCN. The insulating film 15 of the first substrate 10 and the insulating film of the second substrate 20 are bonded to each other to form an interlayer insulating film 51.

[0059] Imaging device 1 includes a plurality of wirings L1 to L10, which are disposed within interlayer insulating film 51 and electrically connected to at least one of the first substrate 10 and the second substrate 20. Figure 2 and Figure 3 As shown, wiring L1 electrically connects the drain AD of the amplifying transistor AMP to the power supply line VDD. Wiring L2 (an example of a second wiring) electrically connects the four floating diffusers FD included in a pixel unit PU to the gate electrode AG of the amplifying transistor AMP. Wiring L3 electrically connects the source AS of the amplifying transistor AMP to the drain SD of the select transistor SEL. Wiring L4 electrically connects the gate electrode SG of the select transistor SEL to pixel drive line 23 (see...). Figure 1 ).

[0060] Wiring L5 electrically connects the source SS of the select transistor SEL to the vertical signal line 24. Wiring L6 electrically connects the drain RD of the reset transistor RST to the power supply line VDD. Wiring L7 electrically connects the gate RG of the reset transistor RST to the pixel drive line 23. Wiring L8 electrically connects the source RS of the reset transistor RST to wiring L2. Wiring L9 (an example of the first wiring) electrically connects the gate TG of the transmit transistor TR to the pixel drive line 23 (see [link to wiring description]). Figure 1 Wiring L10 electrically connects the well contact layer WEC to a reference potential line supplying a reference potential (e.g., ground potential: 0V). In imaging apparatus 1, wiring L2 connects to the rear surface AGb of the gate electrode AG of the amplifying transistor AMP (in...). Figure 3 (Middle, upper surface) side.

[0061] In wirings L1 to L10, the wiring portions extending in the thickness direction of the laminate contain tungsten (W), and the wiring portions extending in a direction orthogonal to the thickness direction of the laminate (e.g., a horizontal direction) contain copper (Cu) or a Cu alloy with Cu as the main component. However, in embodiments of the present invention, the materials of wirings L1 to L10 are not limited to these materials and may include other materials.

[0062] Figures 4A-4C This is a cross-sectional view in the horizontal direction illustrating an example of the construction of a pixel unit PU according to a first embodiment of the present invention. More specifically,Figure 4A A cross-sectional view of the pixel unit PU is shown as horizontally cut at a position sec1. Figure 3 The position sec1 is at the same height as the upper surface of the gate electrode SG of the selection transistor SEL and the upper surface of the gate electrode RG of the reset transistor RST. Figure 4B A cross-sectional view of the pixel unit PU is shown as horizontally cut at a position sec2. Figure 3 The position sec2 is at the same height as the lower surface of the gate electrode AG of the amplification transistor AMP. Figure 4C A cross-sectional view of the pixel unit PU is shown as horizontally cut at a position sec3. Figure 3 The position sec3 is at the same height as the upper surface of the gate electrode TG of the transfer transistor TR.

[0063] Figures 4A-4C The figures are shown respectively for one pixel unit, and in a positional relationship in which the figures overlap each other in the thickness direction of the laminate (e.g., the Z-axis direction). Figure 4A The selection transistor and the reset transistor RST, Figure 4B The amplification transistor AMP, and Figure 4C The four sensor pixels 12 are shown as overlapping each other in the Z-axis direction. As Figure 4A As shown, the transistor group including the selection transistor SEL and the reset transistor RST is located at the center portion of the pixel unit PU in the plan view. The wiring group including the wirings L2, L9, and L10 is located outside the transistor group. The wiring group is arranged to be left-right symmetrical about the transistor group in the plan view.

[0064] As shown, the amplification transistor AMP is located at the center portion of the pixel unit PU in the plan view. In the thickness direction of the laminate, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are in a positional relationship in which they overlap each other. Further, in the plan view, the wiring group including the wirings L2, L9, and L10 is located outside the amplification transistor AMP. The wiring group is arranged to be left-right symmetrical about the amplification transistor AMP in the plan view. Figure 4B As shown, the four sensor pixels 12 included in one pixel unit PU are arranged to be close to each other via the element isolation layer 16. Further, in each of the four sensor pixels 12, the gate electrode TG of the transfer transistor TR is interposed between the floating diffusion FD and the well WE in the plan view. The gate electrode TG separates the floating diffusion FD and the well WE. As

[0065] As shown, the photodiode PD is located below the floating diffusion FD, the well WE, and the gate electrode TG. Figure 4C Figure 3

[0066] ​​Figures 5-7 This is a cross-sectional view in the horizontal direction showing an example layout of multiple pixel units (PUs). More specifically, Figure 5 It shows in Figure 3 The image device 1 is shown as a cross-sectional view of a horizontally cut section at position sec1. Figure 6 It shows in Figure 3 The image device 1 is shown as a cross-sectional view of a horizontally cut section at position sec2. Figure 7 It shows in Figure 3 The cross-sectional view of the first substrate 10, horizontally cut at position sec3 as shown. Figures 5-7 As shown, in imaging device 1, multiple pixel units PU are arranged at fixed intervals in the X-axis and Y-axis directions. The pixel units PU are repeatedly arranged in the X-axis and Y-axis directions.

[0067] Next, the manufacturing method of imaging device 1 will be described. It should be noted that imaging device 1 is manufactured using various equipment such as film deposition equipment (including chemical vapor deposition (CVD) equipment and sputtering equipment), ion implantation equipment, heat treatment equipment, etching equipment, and bonding equipment. In the following text, these devices will be collectively referred to as manufacturing equipment.

[0068] Figures 8-11 This is a cross-sectional view showing a method for manufacturing an imaging device 1 according to a first embodiment of the present invention. Figure 8 As shown, a well layer WE, a device isolation layer 16, a p-type layer 17, an n-type layer 18, a photodiode PD, a gate electrode TG of a transmission transistor TR, a floating diffusion portion FD, and a well contact layer WEC are formed on the front surface 11a side of the first semiconductor substrate 11 using a manufacturing equipment and a CMOS process. Then, an insulating film 15 is formed on the front surface 11a side of the first semiconductor substrate 11 using the manufacturing equipment, and then its surface is planarized. This completes the first substrate 10.

[0069] Before, after, or in parallel with the manufacturing process of the first substrate 10, the manufacturing equipment is installed on the front surface 21a of the second semiconductor substrate 21. Figure 8An amplifying transistor AMP is formed on the upper surface of the second semiconductor substrate 21. For example, the manufacturing apparatus forms the source AS and drain AD of the amplifying transistor AMP on the front surface 21a of the second semiconductor substrate 21. Then, the manufacturing apparatus forms the gate electrode AG of the amplifying transistor AMP on the front surface 21a of the second semiconductor substrate 21. The gate electrode AG is formed in such a way that it covers the drain AD and exposes the source AS. Alternatively, the manufacturing apparatus may form the drain AD and the gate electrode AG, and then form the source AS by using the gate electrode AG as a mask. Next, the manufacturing apparatus forms an insulating film 25 on the front surface 21a side of the second semiconductor substrate 21, and then plans its surface.

[0070] Next, the manufacturing equipment brings the insulating film 25 formed on the second semiconductor substrate 21 and the insulating film 15 formed on the first semiconductor substrate 11 face to face, and then bonds the insulating films 15 and 25 together. The bonding method is, for example, plasma bonding. Through this process, as... Figure 9 As shown, the first semiconductor substrate 11 and the second semiconductor substrate 21 are integrated into a laminate.

[0071] Next, as Figure 10 As shown, the manufacturing equipment uses CMOS technology on the rear surface 21b of the second semiconductor substrate 21. Figure 10 The upper surface of the transistor is formed with an isolation layer 26, a well layer 27, a select transistor SEL, and a reset transistor RST.

[0072] Next, as Figure 11 As shown, the manufacturing apparatus partially removes the second semiconductor substrate 21, thereby exposing the source AS, drain AD, and gate electrode AG of the amplifying transistor AMP. For example, the manufacturing apparatus forms a first mask on the rear surface 21b side of the second semiconductor substrate 21, such that the first mask has a shape that covers both the select transistor SEL and the reset transistor RST, leaving the remaining area open. The first mask includes, for example, a resist mask and a hard mask. Then, the manufacturing apparatus performs dry etching on the portion of the second semiconductor substrate 21 exposed from the first mask, thereby exposing the source AS and drain AD of the amplifying transistor AMP. Thereafter, the manufacturing apparatus removes the first mask from the rear surface 21b side of the second semiconductor substrate 21.

[0073] Next, the manufacturing apparatus forms a second mask on the back surface 21b side of the second semiconductor substrate 21 so that the second mask has a shape that covers the source AS and the drain AD of the amplification transistor AMP and the rest of the regions are open. The second mask includes, for example, a resist mask and a hard mask. Then, for the second semiconductor substrate 21, the manufacturing apparatus performs dry etching on the portions exposed from the second mask. In this dry etching, the insulating film 25 is used as an etching stopper. Through this process, the gate electrode AG of the amplification transistor AMP is exposed from below the second semiconductor substrate 21. Thereafter, the manufacturing apparatus removes the second mask from the back surface 21b side of the second semiconductor substrate 21.

[0074] Next, the manufacturing apparatus forms Figure 3 the wirings L1 to L10 illustrated in FIG. 9. For example, the manufacturing apparatus performs the formation process of the insulating film, the planarization process of the insulating film, the formation process of the contact hole, and the formation process of the wiring on the insulating film and in the contact hole multiple times. As described above, the wiring extending in the vertical direction contains tungsten (W), and the wiring extending in the horizontal direction contains Cu or a Cu alloy. In this way, the imaging device 1 is completed.

[0075] As described above, the imaging device 1 according to the first embodiment of the present application includes the first semiconductor substrate 11 having the sensor pixel for performing photoelectric conversion and the second semiconductor substrate 21 having the readout circuit 22 for outputting a pixel signal based on the charge output from the sensor pixel 12. The second semiconductor substrate 21 is laminated on the front surface 11a side of the first semiconductor substrate 11 to constitute a laminate. The second semiconductor substrate 21 has the front surface 21a facing the first semiconductor substrate 11 and the back surface 21b located on the opposite side of the front surface 21a. The amplification transistor AMP included in the readout circuit 22 is provided in the front surface 21a, and the selection transistor SEL and the reset transistor RST included in the readout circuit 22 are provided in the back surface 21b.

[0076] With this configuration, compared to a case where the transistors included in the readout circuit 22 are provided only on one side of the second semiconductor substrate 21, it is possible to make the area of the arrangement region allocated to the transistors larger, and thus the degree of freedom of the layout of the readout circuit 22 is improved. For example, the amplification transistor AMP is provided in the front surface 21a of the second semiconductor substrate 21, and the selection transistor SEL and the reset transistor RST are provided in the back surface 21b of the second semiconductor substrate 21. With this configuration, in each pixel unit PU, it is possible to maximize the area of the amplification transistor AMP. This maximized area of the amplification transistor AMP makes the random noise occurring in the imaging device decrease.

[0077] (Second Embodiment)

[0078] In the above-described first embodiment, it has been described that the floating diffusion FD is connected to the back surface AGb side of the gate electrode AG of the amplification transistor AMP via the wiring L2. However, in the embodiment of the present application, the connection manner of the floating diffusion FD to the gate electrode AG is not limited to this. For example, the floating diffusion FD can be connected to the front surface AGa side of the gate electrode AG via the wiring L2.

[0079] Figure 12 is a cross-sectional view in the thickness direction showing a configuration example of the imaging device 1A according to the second embodiment of the present application. Note that, as in the case of the Figure 3 described in the first embodiment, Figure 12 the cross-sectional view shown is merely a schematic view, and is not intended to be a view that strictly and correctly shows the actual structure. Figure 12 The cross-sectional view shown includes some portions in which the positions of transistors and impurity diffusion layers in the horizontal direction are intentionally changed for the purpose of easily understanding the configuration of the imaging device 1A by viewing the drawings. The actual structure of the imaging device 1A will be more accurately shown in Figures 13A-13D described later.

[0080] As Figure 12 shown, the imaging device 1A includes the wiring L2 that electrically connects the floating diffusion FD to the gate electrode AG of the amplification transistor AMP. The wiring L2 includes the first wiring portion L21 provided in the first substrate 10 and the second wiring portion L22 provided in the second substrate 20. The first wiring portion L21 is electrically connected to the four floating diffusions FD1 to FD4 included in one pixel unit PU. The second wiring portion L22 is connected to the gate electrode AG of the amplification transistor AMP included in the same pixel unit PU as the four floating diffusions FD1 to FD4. The second wiring portion L22 is connected to the front surface AGa of the gate electrode AG.

[0081] In the first wiring portion L21 and the second wiring portion L22, the wiring portion extending in the Z-axis direction contains tungsten (W). The wiring portion extending in a direction orthogonal to the thickness direction of the laminate (for example, the horizontal direction) contains copper (Cu) or a Cu alloy. The first wiring portion L21 and the second wiring portion L22 are respectively formed into a plate shape that expands in the horizontal direction at the bonding plane between the first substrate 10 and the second substrate 20. Then, at the bonding plane, the first wiring portion L21 and the second wiring portion L22 are integrated by Cu-Cu bonding.

[0082] Figures 13A-13D is a cross-sectional view in the horizontal direction showing a configuration example of the pixel unit PU according to the second embodiment of the present application. More specifically, Figure 13A is shown in Figure 12The image shows a cross-sectional view of the pixel unit PU horizontally cut at position sec1. Figure 13B It shows in Figure 12 The image shows a cross-sectional view of a pixel cell horizontally cut at position sec21. Position sec21 is at the same height as the lower surface of the gate electrode AG of the amplifying transistor AMP. Figure 13C It shows in Figure 12 The image shows a cross-sectional view of the pixel unit PU horizontally cut at position sec22. Position sec22 is the bonding plane between the first substrate 10 and the second substrate 20. Figure 13D It shows in Figure 12 The image shows a cross-sectional view of the pixel unit PU, which is horizontally cut at position sec3.

[0083] Figures 13A-13D The diagrams for each pixel unit are shown, and the positional relationship of these diagrams overlapping each other in the Z-axis direction is shown. Figure 13A The select transistor and reset transistor RST shown are shown. Figure 13B The amplifier transistor AMP shown Figure 13C The plate-shaped wiring L2 shown and Figure 13D The four sensor pixels 12 shown overlap each other in the Z-axis direction. (As shown...) Figure 13A As shown, similarly, in imaging apparatus 1A, a transistor group including a selection transistor SEL and a reset transistor RST is located at the center of pixel unit PU in a plan view. A wiring group including wirings L2, L9, and L10 is located outside the transistor group. The wiring groups are arranged symmetrically on both sides of the transistor group in a plan view.

[0084] As described above, in the imaging apparatus 1A, wiring L2 is not connected to the rear surface AGb of the gate electrode AG of the amplifying transistor AMP, but rather to the front surface AGa. Therefore, as Figure 13A As shown, regarding the multiple wirings L2 in the imaging device 1A, there is no wiring portion connected to the gate electrode AG at position sec1.

[0085] like Figure 13B As shown, even in imaging device 1A, the amplifying transistor AMP is located at the center of pixel unit PU in the plan view. In the plan view, it is connected to sensor pixel 12 (see...). Figure 2 The wiring group of the imaging device 1A is located outside the amplifying transistor AMP. The wiring group includes wirings L2, L9, and L10. In a plan view viewed from the Z-axis, at least a portion of the wiring group is arranged symmetrically around the amplifying transistor AMP. It should be noted that the gate electrode AG of the imaging device 1A is not allocated any area on the rear surface AGb side for connecting to wiring L2 (e.g., as shown in the image). Figure 4BAs shown, the region adjacent to the drain AD in the X-axis direction is thus wider due to this region.

[0086] like Figure 13C As shown, at position sec 22, the second wiring portion L22 of wiring L2 is formed as a plate shape extending in the horizontal direction. Although not shown, at position sec 22, the first wiring portion L21 of wiring L2 is also formed as a plate shape extending in the horizontal direction. For example, at position sec 22, the first wiring portion L21 and the second wiring portion L22 have the same shape and size as each other. Figure 13D As shown, the imaging device 1A at position sec3 is constructed similarly to... Figure 4C The imaging device 1 shown is constructed identically at position sec3.

[0087] Figures 14-17 This is a cross-sectional view showing a method for manufacturing an imaging device 1A according to a second embodiment of the present invention. Figure 14 As shown, using a manufacturing apparatus and a CMOS process, a well layer WE, a device isolation layer 16, a p-type layer 17, an n-type layer 18, a photodiode PD, a gate electrode TG of a transmission transistor TR, a floating diffusion portion FD, and a well contact layer WEC are formed on the front surface 11a side of the first semiconductor substrate 11. Then, an insulating film 15 is formed on the front surface 11a side of the first semiconductor substrate 11. Next, the manufacturing apparatus partially etches the insulating film 15 to form contact holes on the floating diffusion portion FD.

[0088] Next, the manufacturing apparatus forms a first wiring portion L21 extending from the floating diffuser FD through the contact hole to the top of the insulating film 15. The method for forming the first wiring portion L21 is not particularly limited; however, for example, a single-damascene method or a double-damascene method may be included. After forming the insulating film 15, the manufacturing apparatus planarizes the upper surface of the insulating film 15 and the upper surface of the first wiring portion L21. Through planarization, the upper surfaces of the insulating film 15 and the first wiring portion L21 become flush with each other (for example, there is no step between the upper surfaces of the insulating film 15 and the first wiring portion L21). This completes the first substrate 10.

[0089] Before, after, or in parallel with the manufacturing process of the first substrate 10, the manufacturing equipment is installed on the front surface 21a of the second semiconductor substrate 21. Figure 14 An amplifying transistor AMP is formed in the upper surface of the transistor. The method for forming the amplifying transistor AMP is the same as that described in the first embodiment. Figure 8The method is the same. Then, the manufacturing apparatus forms an insulating film 25 on the front surface 21a side of the second semiconductor substrate 21. Then, the manufacturing apparatus partially etches the insulating film 25 to form a contact hole on the front surface AGa of the gate electrode AG of the amplification transistor AMP.

[0090] Then, the manufacturing apparatus forms a wiring (a part of the second wiring portion L22) from the front surface AGa of the gate electrode AG through the contact hole up to the top of the insulating film 25. The method of forming the wiring is not particularly limited, however, for example, can include a single damascene method or a dual damascene method. After forming the insulating film 25, the manufacturing apparatus planarizes both the upper surface of the insulating film 25 and the upper surface of the second wiring portion L22. By planarization, the upper surface of the insulating film 25 and the upper surface of the second wiring portion L22 become flush with each other (for example, a state in which there is no step between the upper surface of the insulating film 25 and the upper surface of the second wiring portion L22).

[0091] Next, the manufacturing apparatus causes the insulating film 25 formed on the second semiconductor substrate 21 and the insulating film 15 formed on the first semiconductor substrate 11 to face each other, and then bonds the insulating films 15 and 25 together, and also bonds the first wiring portion L21 and the second wiring portion L22 together. The bonding method is, for example, plasma bonding. By this process, as shown in FIG. 1, the first semiconductor substrate 11 and the second semiconductor substrate 21 are integrated as a laminate. In addition, the first wiring portion L21 and the second wiring portion L22 are integrated as a wiring L2. Figure 15

[0092] The subsequent processes are the same as in the first embodiment. Next, as shown in FIG. 2, the manufacturing apparatus forms an element isolation layer 26, a well layer 27, a selection transistor SEL, and a reset transistor RST in the upper surface of the rear surface 21b of the second semiconductor substrate 21 by a CMOS process. Next, as shown in FIG. 3, the manufacturing apparatus partially removes the second semiconductor substrate 21, thereby exposing a source electrode AS, a drain electrode AD, and a gate electrode AG of the amplification transistor AMP. Then, the manufacturing apparatus forms the wirings L1, L3 to L10, and the remaining portion of the second wiring portion L22 (for example, a portion higher than the position sec21) shown in FIG. 4. This completes the imaging device 1A. Figure 16 Figure 16 Figure 17 Figure 12

[0093] ​​​​​The imaging device 1A according to the second embodiment of the present application, as in the case of the imaging device 1 according to the first embodiment, can increase the area of the arrangement region assigned to the transistors included in the readout circuit 22. This leads to an increase in the degree of freedom of the layout of the readout circuit 22. For example, the configuration can be such that the amplification transistor AMP is provided in the front surface 21a of the second semiconductor substrate 21 and that the selection transistor SEL and the reset transistor RST are provided in the back surface 21b. This maximizes the area of the amplification transistor AMP, leading to a further reduction in random noise.

[0094] Further, in the imaging device 1A, the wiring L2 is connected to the front surface AGa of the gate electrode AG of the amplification transistor AMP. With this configuration, as compared to the case where the wiring L2 is connected to the back surface AGb of the gate electrode AG, it is possible to reduce the number of wirings L2 that pass through the second semiconductor substrate 21 side. For example, this reduction in the number of wirings L2 that pass through the second semiconductor substrate 21 side allows the size of the pixel unit PU to be proportionally reduced, or alternatively, allows the second semiconductor substrate 21 included in the pixel unit PU to expand in the horizontal direction. In addition, in the wiring L2, it is possible to reduce the wiring length between the floating diffusion portion FD and the gate electrode AG, which leads to a reduction in parasitic capacitance. In this way, the imaging device 1A can contribute to further miniaturization and higher performance of the pixel unit PU.

[0095] (Other Embodiments)

[0096] As described above, although the present application has been described in the form of specific embodiments and modifications, the description and drawings constituting a part of the present application should not be construed as limiting the present application. It should be understood that various alternative embodiments, examples, and operable techniques are obvious to those skilled in the art in light of the present application.

[0097] For example, in the first and second embodiments described above, the configuration in which the amplification transistor AMP is provided in the front surface 21a of the second semiconductor substrate 21 and the selection transistor SEL and the reset transistor RST are provided in the back surface 21b has been described. However, the embodiments of the present application are not limited to this. The selection transistor SEL and the reset transistor RST can be provided in the front surface 21a of the second semiconductor substrate 21, and the amplification transistor AMP can be provided in the back surface 21b. Alternatively, one of the selection transistor SEL and the reset transistor RST and the amplification transistor AMP can be provided in the front surface 21a, and the other of the selection transistor SEL and the reset transistor RST can be provided in the back surface 21b.

[0098] In this way, it is apparent that the present technology includes various embodiments not recited herein. At least one of various omissions, substitutions and changes can be made to the components without departing from the spirit of the above-described embodiments and modifications. Furthermore, the advantageous effects recited in the present specification are merely examples and are not intended to be limiting, and other advantageous effects can be obtained.

[0099] Note that the present application can also include the following configurations.

[0100] (1) An imaging device comprising:

[0101] a first semiconductor substrate including a sensor pixel configured to perform photoelectric conversion; and

[0102] a second semiconductor substrate including a readout circuit configured to output a pixel signal based on a charge output from the sensor pixel, wherein

[0103] the second semiconductor substrate is laminated on one surface side of the first semiconductor substrate to constitute a laminate,

[0104] the second semiconductor substrate includes a first surface facing the first semiconductor substrate and a second surface located on an opposite side of the first surface,

[0105] a first transistor included in the readout circuit is provided in the first surface, and

[0106] a second transistor included in the readout circuit is provided in the second surface.

[0107] (2) The imaging device according to (1), wherein

[0108] the first transistor and the second transistor overlap each other in a thickness direction of the laminate.

[0109] (3) The imaging device according to (1) or (2), wherein

[0110] the sensor pixel includes:

[0111] a photoelectric conversion element,

[0112] a transfer transistor electrically connected to the photoelectric conversion element, and

[0113] a floating diffusion configured to temporarily hold a charge output from the photoelectric conversion element via the transfer transistor,

[0114] the readout circuit includes:

[0115] a reset transistor configured to reset a potential of the floating diffusion to a predetermined potential,

[0116] an amplification transistor configured to generate, as the pixel signal, a voltage signal corresponding to a level of electric charges held in the floating diffusion section, and

[0117] a selection transistor configured to control an output timing of the pixel signal output from the amplification transistor,

[0118] the first transistor is one transistor selected from among the reset transistor, the amplification transistor, and the selection transistor, and

[0119] the second transistor is another transistor other than the one transistor among the reset transistor, the amplification transistor, and the selection transistor.

[0120] (4) The imaging device according to (3), wherein

[0121] the one transistor includes the amplification transistor, and

[0122] the other transistor includes the reset transistor and the selection transistor.

[0123] (5) The imaging device according to (4), wherein

[0124] a plurality of the sensor pixels are electrically connected to one of the readout circuits to constitute one pixel unit, and

[0125] in a plan view seen in a thickness direction of the laminate, the amplification transistor is located at a central portion of the pixel unit.

[0126] (6) The imaging device according to (4) or (5), wherein

[0127] the laminate includes:

[0128] a wiring group electrically connected to the sensor pixels, and

[0129] in a plan view seen in a thickness direction of the laminate, at least a portion of the wiring group is disposed to be left-right symmetrical about the amplification transistor.

[0130] (7) The imaging device according to (6), wherein

[0131] the wiring group includes a first wiring electrically connected to a gate electrode of the transfer transistor, and the first wiring is disposed to be left-right symmetrical about the amplification transistor.

[0132] (8) The imaging device according to any one of (4) to (7), wherein

[0133] The laminate includes:

[0134] A second wiring connected to a surface of a gate electrode of the amplification transistor facing the first semiconductor substrate.

[0135] List of reference numerals

[0136] 1, 1A: Imaging device

[0137] 10: First substrate

[0138] 10a, 11a, 21a: Front surface

[0139] 11: First semiconductor substrate

[0140] 12: Sensor pixel

[0141] 13: Pixel region

[0142] 15, 25: Insulating film

[0143] 16, 26: Element isolation layer

[0144] 17: P-type layer

[0145] 18: N-type layer

[0146] 20: Second substrate

[0147] 21: Second semiconductor substrate

[0148] 21b: Back surface

[0149] 22: Readout circuit

[0150] 23: Pixel drive line

[0151] 24: Vertical signal line

[0152] 27: Well layer

[0153] 30: Third substrate

[0154] 31: Third semiconductor substrate

[0155] 32: Logic circuit

[0156] 33: Vertical drive circuit

[0157] 34: Column signal processing circuit

[0158] 35: Horizontal drive circuit

[0159] 36: System control circuit

[0160] 51: Interlayer insulating film

[0161] AD, RD, SD: Drain

[0162] AG, RG, SG, TG: gate electrode

[0163] AGa: front surface

[0164] AGb: back surface

[0165] AMP: amplification transistor

[0166] AS, RS, SS: source

[0167] FD: floating diffusion

[0168] L1, L2, L3, L4, L5, L6, L7, L8, L9, L10: wiring

[0169] L21: first wiring portion

[0170] L22: second wiring portion

[0171] PD: photodiode

[0172] PU: pixel unit

[0173] RST: reset transistor

[0174] sec1, sec2, sec3, sec21, sec22: position

[0175] SEL: selection transistor

[0176] TR: transfer transistor

[0177] VDD: power supply line

[0178] WE: well layer

[0179] WEC: well contact layer

Claims

1. An imaging device comprising: a first semiconductor substrate including a sensor pixel configured to perform photoelectric conversion; and a second semiconductor substrate including a readout circuit configured to output a pixel signal based on a charge output from the sensor pixel, wherein the second semiconductor substrate is laminated on one surface side of the first semiconductor substrate to constitute a laminate, the second semiconductor substrate includes a first surface facing the first semiconductor substrate and a second surface located on an opposite side of the first surface, a first transistor included in the readout circuit is provided in the first surface, wherein a gate electrode of the first transistor is provided on the first surface, and a second transistor included in the readout circuit is provided in the second surface, wherein a gate electrode of the second transistor is provided on the second surface, wherein the first transistor and the second transistor overlap each other in a thickness direction of the laminate.

2. The imaging device according to claim 1, wherein the sensor pixel includes: a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a floating diffusion configured to temporarily hold a charge output from the photoelectric conversion element via the transfer transistor, the readout circuit includes: a reset transistor configured to reset a potential of the floating diffusion to a predetermined potential, an amplification transistor configured to generate a voltage signal corresponding to a level of the charge held in the floating diffusion as the pixel signal, and a selection transistor configured to control an output timing of the pixel signal output from the amplification transistor, the first transistor is one transistor selected from among the reset transistor, the amplification transistor, and the selection transistor, and the second transistor is another transistor other than the one transistor among the reset transistor, the amplification transistor, and the selection transistor.

3. The imaging device according to claim 2, wherein the one transistor includes the amplification transistor, and the other transistor includes the reset transistor and the selection transistor.

4. The imaging device according to claim 3, wherein a plurality of the sensor pixels are electrically connected to one readout circuit to constitute one pixel unit, and in a plan view seen in the thickness direction of the laminate, the amplification transistor is located at a central portion of the pixel unit.

5. The imaging device according to claim 3, wherein the laminate includes: a wiring group electrically connected to the sensor pixel, and in a plan view seen in the thickness direction of the laminate, at least a part of the wiring group is provided to be left-right symmetrical with the amplification transistor sandwiched therebetween.

6. The imaging device according to claim 5, wherein the wiring group includes a first wiring connected to a gate electrode of the transfer transistor, and the first wiring is provided to be left-right symmetrical with the amplification transistor sandwiched therebetween.

7. The imaging device according to claim 3, wherein the laminate includes: A second wiring connected to a surface of a gate electrode of the amplification transistor facing the first semiconductor substrate.

Images