Radiation-emitting semiconductor chip, radiation-emitting semiconductor component and floodlight

Abstract

A radiation-emitting semiconductor chip (1) is provided, comprising: - mutually separated emitter regions (3) with a radiation exit surface (2), - an epitaxial semiconductor layer sequence (4) comprising active regions (5), wherein each active region (5) is designed for emitting electromagnetic radiation from the corresponding emitter region (3), and - a mounting surface (6) opposite the radiation exit surface (2), wherein the mounting surface (6) comprises a plurality of first solderable contact surfaces (7) and second solderable contact surfaces (8), wherein - each active region (5) can be energized using the first solderable contact surface (7) and the second solderable contact surface (8), respectively, the first solderable contact surface (7) being arranged in an inner region (9) of the mounting surface, and the second solderable contact surface (8) being arranged in an edge region (10) of the mounting surface. In addition, a radiation-emitting semiconductor component (20) and a headlight having such a semiconductor chip (1) are provided.

Description

[0001] A radiation-emitting semiconductor chip is specified. Furthermore, a radiation-emitting semiconductor component and a headlight are specified.

[0002] The technical problem to be solved is to specify a particularly compact radiation-emitting semiconductor chip. In addition, a compact radiation-emitting semiconductor component and a headlight having such a semiconductor component should be specified.

[0003] This object is achieved by a radiation-emitting semiconductor chip having the features of claim 1 , a radiation-emitting semiconductor component having the features of claim 18 , and a headlight having the features of claim 19 .

[0004] Advantageous embodiments of the radiation-emitting semiconductor chip, the semiconductor component and the headlight are the subject matter of the respective dependent claims.

[0005] According to at least one embodiment, the radiation-emitting semiconductor chip comprises a radiation exit surface, which comprises emitter regions separated from each other. The radiation exit surface preferably has a main extension plane. The lateral direction is preferably oriented parallel to the radiation exit surface, and the vertical direction is preferably oriented perpendicular to the lateral direction. The emitter region is preferably part of the radiation exit surface and extends in the lateral direction. In addition, the emitter regions are preferably arranged in a common plane.

[0006] According to one embodiment, the emitter regions are designed in the same way. For example, the emitter regions have the same surface area and / or the same shape.

[0007] The emitter regions are preferably arranged spaced apart from each other in the lateral direction. The emitter regions are preferably arranged in a matrix, i.e. arranged along columns and rows. Preferably, the emitter regions are arranged at grid points of the second regular grid. The second regular grid may preferably be a polygonal grid, such as a hexagonal grid or an orthogonal grid.

[0008] The emitter regions preferably each have a triangular, quadrilateral, hexagonal, circular, oval or elliptical shape. The maximum dimension of each emitter region in a lateral direction is preferably at least 15 micrometers and at most 50 micrometers, particularly preferably between 25 micrometers and at most 35 micrometers.

[0009] In accordance with at least one embodiment, the radiation-emitting semiconductor chip comprises an epitaxial semiconductor layer sequence having active regions, wherein each active region is embodied to emit electromagnetic radiation from a respective emitter region.

[0010] The semiconductor layer sequence is based, for example, on a III-V compound semiconductor material. The III-V compound semiconductor material is, for example, a phosphide, arsenide and / or nitride compound semiconductor material, ie, for example, In x Al y Ga 1-x-y P、In x Al y Ga 1-x-y As and / or In x Al y Ga 1-x-y N, where 0≤x≤1, 0≤y≤1 and x+y≤1.

[0011] The semiconductor layer sequence may contain dopants and additional components. However, for the sake of simplicity, only the basic components of the crystal lattice of the semiconductor layer sequence are described, namely Al, Ga, In, N, As or P, even though these may be partially replaced and / or supplemented with small amounts of other substances.

[0012] The semiconductor layer sequence preferably comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. Preferably, the first semiconductor layer is p-doped and is therefore constructed as p-conducting. Preferably, the second semiconductor layer is n-doped and is therefore constructed as n-conducting. Preferably, the first semiconductor layer and the second semiconductor layer are stacked on each other in a vertical direction.

[0013] Preferably, the active region is arranged between the first semiconductor layer and the second semiconductor layer. Preferably, the active regions each have a pn junction for generating electromagnetic radiation, for example a double heterostructure, a single quantum well structure or a multiple quantum well structure.

[0014] The electromagnetic radiation generated during operation of the active region can be near-ultraviolet radiation, visible light and / or near-infrared radiation. Visible light is, for example, blue, green, yellow or red light.

[0015] A conversion element can be arranged on the emitter region, which conversion element is designed to at least partially convert the electromagnetic radiation of the semiconductor chip into electromagnetic secondary radiation. Preferably, the conversion element converts the electromagnetic radiation of the semiconductor chip into electromagnetic secondary radiation of a different wavelength range. Particularly preferably, the secondary radiation comprises a longer wavelength than the electromagnetic radiation of the semiconductor chip. If the active region generates blue light, for example, the electromagnetic radiation emitted by the radiation-emitting semiconductor chip and the electromagnetic secondary radiation can preferably be mixed to form white mixed light.

[0016] The active regions preferably extend in a lateral direction and are preferably arranged in a common plane. Furthermore, the active regions are preferably arranged separately from one another. In this case, the active regions are preferably arranged spaced apart from one another in a lateral direction. The active regions are preferably arranged in a matrix, i.e. arranged along columns and rows. Preferably, the active regions are arranged at grid points of a third regular grid. The grid points of the third grid on which the active regions are arranged are preferably arranged in a top view at the same positions as the grid points of the second grid on which the emitter regions are arranged.

[0017] The active regions preferably each have a triangular, quadrilateral, hexagonal, circular, oval or elliptical shape. The maximum dimension of each active region in the lateral direction is preferably at least 15 micrometers and at most 50 micrometers, particularly preferably between 25 micrometers and at most 35 micrometers.

[0018] An emitter region is preferably arranged in the vertical direction above each active region. Preferably, in a plan view, each active region completely overlaps with the associated emitter region. The term "associated" indicates that exactly one emitter region is arranged in the vertical direction above exactly one active region. Thus, for example, each active region is associated with exactly one emitter region.

[0019] The size of each active region in the lateral direction preferably predetermines the size of the associated emitter region in the lateral direction. The size of each active region in the lateral direction may be smaller than the size of the associated emitter region in the lateral direction. For example, the beam of electromagnetic radiation of the active region has a propagation component in the lateral direction in addition to the propagation component in the vertical direction. Therefore, the beam at the associated emitter region can be emitted from an area that does not overlap with the active region in a top view.

[0020] According to at least one embodiment, the radiation-emitting semiconductor chip comprises a mounting surface opposite the radiation exit surface, wherein the mounting surface comprises a plurality of first solderable contact surfaces and second solderable contact surfaces. The mounting surface faces an outer surface of the semiconductor layer sequence facing away from the radiation exit surface. The radiation-emitting semiconductor chip can preferably be energized using the mounting surface.

[0021] The first solderable contact surface preferably comprises a metal, in particular a solderable metal, or consists thereof. Furthermore, the second solderable contact surface comprises a further metal, in particular a further solderable metal, or consists thereof. The metal and / or the further metal are / or contain, for example, gold, silver, copper, tin, lead, bismuth and / or antimony. Preferably, the metal and the further metal consist of the same material.

[0022] The first solderable contact surface has an outer surface facing away from the semiconductor layer sequence. In addition, the second solderable contact surface has an outer surface facing away from the semiconductor layer sequence. The outer surface of the first solderable contact surface and / or the outer surface of the second solderable contact surface are preferably freely accessible.

[0023] The outer surface of the first solderable contact surface facing away from the semiconductor layer sequence is preferably arranged in a common plane in a lateral direction. In addition, the outer surface of the second solderable contact surface facing away from the semiconductor layer sequence is preferably arranged in a common plane with the outer surface of the first solderable contact surface. As a result, the radiation-emitting semiconductor chip can preferably be surface mounted.

[0024] According to at least one embodiment, each active region can be electrically connected using the first solderable contact surface and the second solderable contact surface. In the region of the active region, the first semiconductor layer is preferably electrically conductively connected to the first solderable contact surface. In addition, the second semiconductor layer is preferably electrically conductively connected to the second solderable contact surface.

[0025] According to at least one embodiment, the first weldable contact surface is arranged in the inner region of the mounting surface. The inner region of the mounting surface preferably does not extend to the edge of the mounting surface in the lateral direction. That is, the edge region of the mounting surface preferably does not have the first weldable contact surface.

[0026] According to at least one embodiment, the second solderable contact surface is arranged in the edge region of the mounting surface. The edge region of the mounting surface and the inner region of the mounting surface are arranged separately from each other. Therefore, the edge region of the mounting surface and the inner region of the mounting surface preferably do not overlap in a top view. Preferably, the edge region and the inner region form the mounting surface. The edge region and the inner region preferably directly adjoin each other.

[0027] According to a preferred embodiment, the radiation-emitting semiconductor chip comprises: emitter regions separated from each other including a radiation exit surface, an epitaxial semiconductor layer sequence including an active region, wherein each active region is constructed to emit electromagnetic radiation from the corresponding emitter region. In addition, in this embodiment, the radiation-emitting semiconductor chip comprises a mounting surface opposite the radiation exit surface, wherein the mounting surface comprises a plurality of first solderable contact surfaces and second solderable contact surfaces. Finally, in this embodiment of the radiation-emitting semiconductor chip, each active region can be energized using a first solderable contact surface and a second solderable contact surface, wherein the first solderable contact surface is arranged in an inner region of the mounting surface and the second solderable contact surface is arranged in an edge region of the mounting surface.

[0028] According to at least one embodiment, the inner area of ​​the mounting surface does not have a second weldable contact surface. Preferably, the first weldable contact surface and the second weldable contact surface do not overlap in a top view. Furthermore, preferably, in a top view, the second weldable contact surface is not arranged between adjacent first weldable contact surfaces.

[0029] Furthermore, the idea of ​​the radiation-emitting semiconductor chip described here is that the first solderable contact surface is arranged in the inner region of the mounting surface and the second solderable contact surface is arranged in the edge region of the mounting surface. As a result, the distance between directly adjacent first solderable contact surfaces in the lateral direction can advantageously be designed to be relatively small, in particular compared to conventional semiconductor chips in which the first solderable contact surface and the second solderable contact surface are arranged together in the inner region. Due to the small distance between directly adjacent first solderable contact surfaces, the semiconductor chip can have an increased number of active areas compared to conventional semiconductor chips. As a result, such a radiation-emitting semiconductor chip can advantageously be designed to be relatively compact.

[0030] According to at least one embodiment, the first solderable contact surfaces are separated from each other by non-emitting regions. Compared to the emitter region, the non-emitting region emits relatively little radiation or no radiation. The radiation emitted by the non-emitting region is preferably 60% less, particularly preferably 80% less than that of the emitter region.

[0031] The first solderable contact surfaces are preferably arranged spaced apart from each other in the lateral direction. Preferably, in a top view, the non-emitting region is arranged between directly adjacent first solderable contact surfaces. Furthermore, in a top view, the non-emitting region is arranged between directly adjacent emitter regions. The non-emitting region is also preferably arranged between directly adjacent active regions. The non-emitting region and the emitter region preferably completely fill the inner region. Furthermore, the edge region of the mounting surface and the inner region of the mounting surface can be separated from each other by the non-emitting region.

[0032] According to at least one embodiment, the second weldable contact surface completely surrounds the first weldable contact surface. Preferably, the second weldable contact surface is constructed continuously. The second weldable contact surface can be arranged completely in the edge area of ​​the mounting surface. Therefore, the second weldable contact surface preferably completely surrounds the first weldable contact surface in the lateral direction.

[0033] According to at least one embodiment, the first solderable contact surfaces are arranged in a matrix, ie in columns and rows.

[0034] According to at least one embodiment, the first solderable contact surface is arranged at a grid point of the first regular grid. The grid points of the first regular grid at which the first solderable contact surface is arranged are preferably arranged in a top view at the same positions as the grid points of the second grid and / or the third grid at which the emitter region and / or the active region are arranged. Alternatively, it is possible that the grid points of the first regular grid are displaced in one direction in the lateral direction compared to the grid points of the second grid and / or the third grid.

[0035] The first weldable contact surface preferably has a triangular, quadrilateral, hexagonal, circular, egg-shaped or elliptical shape, respectively.

[0036] In a top view, each emitter region and each active region preferably completely overlaps with the associated first solderable contact surface. Furthermore, each first solderable contact surface preferably has a dimension in a lateral direction that is larger than the dimension of the associated emitter region in the lateral direction. Furthermore, each first solderable contact surface preferably has a dimension in a lateral direction that is larger than the dimension of the associated active region in the lateral direction. The term "associated" indicates that exactly one emitter region and exactly one active region are respectively arranged in the vertical direction on exactly one first solderable contact surface. Thus, for example, each of the first solderable contact surfaces is associated with exactly one emitter region and exactly one active region.

[0037] The maximum dimension of each first solderable contact area in the lateral direction is preferably at least 15 micrometers and at most 50 micrometers, particularly preferably between 25 micrometers and at most 35 micrometers.

[0038] According to at least one embodiment, directly adjacent first solderable contact surfaces have a distance of at least 1 micrometer to at most 20 micrometers. Preferably, directly adjacent first solderable contact surfaces have a distance of at least 5 micrometers to at most 15 micrometers.

[0039] According to at least one embodiment, the first solderable contact surface forms at least 60% of the inner area of ​​the mounting surface. Preferably, the first solderable contact surface forms at least 70%, particularly preferably at least 80% of the inner area of ​​the mounting surface. That is, the mounting surface is preferably formed for the most part by the first solderable contact surface. Advantageously, such a semiconductor chip can dissipate heat generated in the semiconductor layer sequence particularly well via the first solderable contact surface. The greater the proportion of the first solderable contact surface on the mounting surface, the better the heat can be dissipated.

[0040] According to at least one embodiment, each active region is conductively connected to the first conductive layer. In this case, each active region is preferably conductively connected to the first solderable contact surface by means of the first conductive layer. In each region of the active region, the first semiconductor layer is preferably conductively contacted to the first conductive layer.

[0041] According to at least one embodiment, each active region is electrically conductively connected to the second conductive layer. Preferably, each active region is electrically conductively connected to the second solderable contact surface by means of the second conductive layer. Furthermore, the second semiconductor layer is preferably in electrically conductive contact with the second conductive layer.

[0042] According to at least one embodiment, the conductive connection layer is arranged on the second conductive layer. The conductive connection layer is preferably arranged on the outer surface of the second conductive layer facing away from the semiconductor layer sequence. Preferably, the conductive connection layer is in conductive contact with the second conductive layer. The conductive connection layer preferably completely covers the outer surface of the second conductive layer facing away from the semiconductor layer sequence. The conductive connection layer may exceed the second conductive layer in the lateral direction. In a top view, the first contact surface and the conductive connection layer may overlap each other in the lateral direction. In addition, the conductive connection layer preferably does not penetrate the active area in the vertical direction.

[0043] The conductive connection layer is preferably in conductive contact with the second solderable contact surface, in particular in the edge region of the mounting surface. The conductive connection layer is preferably formed continuously. In addition, the conductive connection layer preferably completely surrounds each first conductive layer. Thus, preferably, each active area is conductively connected to the second solderable contact surface by means of the second conductive layer and the conductive connection layer.

[0044] According to at least one embodiment, the electrically conductive connection layer is an electrically conductive mirror layer. The electrically conductive mirror layer preferably has a reflectivity of at least 90%, in particular 95% or 99%, for the electromagnetic radiation generated in the active region. The electrically conductive mirror layer contains, for example, at least one of the following metals or consists thereof: silver, aluminum, rhodium, nickel, copper, gold.

[0045] If the conductive mirror layer is gold, the conductive mirror layer preferably has a thickness in the vertical direction of at least 5 nanometers and at most 20 nanometers. It is particularly preferred that the conductive mirror layer has a thickness of at least 7 nanometers and at most 10 nanometers.

[0046] Advantageously, light coupling out of the semiconductor chip may be improved using such an electrically conductive mirror layer.

[0047] According to at least one embodiment, a recess is arranged in the semiconductor layer sequence from the side facing the mounting surface. The non-emitting region is preferably predetermined by the recess in the semiconductor layer sequence. In addition, the recess is preferably constructed continuously. The recess preferably extends along the grid lines of the fourth regular grid. Thus, the non-emitting region preferably extends along the grid lines of the fourth grid. The fourth regular grid can preferably be a polygonal grid, such as a hexagonal grid or an orthogonal grid.

[0048] According to at least one embodiment, the recess completely penetrates the active region. Preferably, the recess completely penetrates the first semiconductor layer sequence and the active region. Preferably, the recess extends into the second semiconductor layer. Preferably, the recess thereby separates the active region and divides it into active regions separated from each other. Therefore, the recess preferably promotes a spacing in the lateral direction of the active region. Thus, the recess preferably also predetermines the lateral size of the non-emitting region in the lateral direction.

[0049] According to at least one embodiment, the second electrically conductive layer is arranged in the recess. The second electrically conductive layer is preferably in direct contact with the second semiconductor layer in the region of the recess.

[0050] According to at least one embodiment, the first insulating layer is arranged between the second conductive layer and the side of the recess. Preferably, the first insulating layer is completely arranged on all sides of the recess. In this case, the first insulating layer is preferably constructed to electrically insulate the second conductive layer from the first semiconductor layer and the active region.

[0051] The first insulation layer is preferably embodied as electrically insulating and comprises, for example, one or more dielectric materials or consists thereof.

[0052] According to at least one embodiment, the first insulating layer is arranged between the electrically conductive connection layer and the outer surface of the semiconductor layer sequence facing the mounting surface. Preferably, the first insulating layer is arranged between the electrically conductive connection layer and the outer surface of the first semiconductor layer facing the mounting surface. In this case, the first insulating layer is preferably designed to insulate the second electrically conductive layer from the outer surface of the first semiconductor layer facing the mounting surface.

[0053] According to at least one embodiment, the second insulating layer is arranged on the electrically conductive connection layer on the outer surface facing the mounting surface. Preferably, the second insulating layer is arranged between the first solderable contact surface and the electrically conductive connection layer. Particularly preferably, the second insulating layer is arranged in a form-fitting manner between the first solderable contact surface and the electrically conductive connection layer. In this case, the second insulating layer is preferably designed to electrically insulate the electrically conductive connection layer from the first solderable contact surface.

[0054] The second insulation layer is preferably embodied as electrically insulating and comprises, for example, one or more dielectric materials or consists thereof.

[0055] According to at least one embodiment, the first weldable contact surfaces can each be controlled individually and separately from one another.

[0056] Furthermore, a radiation-emitting semiconductor component is specified, which comprises a radiation-emitting semiconductor chip described here. Therefore, all features and embodiments disclosed with respect to the radiation-emitting semiconductor chip can also be embodied in connection with the radiation-emitting semiconductor component, and vice versa.

[0057] According to at least one embodiment, the radiation-emitting semiconductor element comprises a further semiconductor chip. The further semiconductor chip preferably has an electronic control element. Furthermore, the further semiconductor chip can have a plurality of electronic control elements. For example, the electronic control element can be associated with one of the active regions, respectively. Alternatively, the electronic control element can be associated with a plurality of the active regions, or the electronic control element can be associated with all active regions. Furthermore, all active regions can be controlled separately from one another by means of a single electronic control element.

[0058] According to at least one embodiment, the first solderable contact surface and the second solderable contact surface are arranged on the further semiconductor chip. The further semiconductor chip preferably has a plurality of connection surfaces. The first solderable contact surface and the second solderable contact surface can be applied directly to the connection surfaces, preferably by means of solder. The first conductive contact surface and the second conductive contact surface are preferably in conductive contact with the connection surfaces. The first solderable contact surface and the second conductive contact surface are preferably firmly mechanically connected to each other, preferably by means of solder.

[0059] According to at least one embodiment, the further semiconductor chip comprises an integrated circuit. One or more electronic control elements are preferably integrated circuits. The integrated circuit is, for example, formed by an integrated circuit loop (English "integrated circuit", referred to as "IC"), or has such an integrated circuit loop. The integrated circuit, for example, comprises a monitoring unit, an analysis unit and / or a control unit. For example, the monitoring unit and the analysis unit respectively check the state of the associated active area. For example, the control unit can control the state of the associated active area, and, for example, turn the active area on or off.

[0060] The invention further provides a headlight comprising a radiation-emitting semiconductor chip as described herein. Therefore, all features and embodiments disclosed with respect to the headlight are also disclosed with respect to the radiation-emitting semiconductor chip, and vice versa.

[0061] In accordance with at least one embodiment, the floodlight comprises a radiation-emitting semiconductor chip.

[0062] With the aid of the radiation-emitting semiconductor chip described here, such a headlight can advantageously be realized in a compact manner.

[0063] A radiation-emitting semiconductor chip, a radiation-emitting semiconductor component and a headlight described here are explained in more detail below with reference to exemplary embodiments and associated figures.

[0064] In the attached figure:

[0065] Figure 1 shows a schematic plan view of a radiation-emitting semiconductor chip according to an exemplary embodiment,

[0066] Figure 2 Shows Figure 1 Schematic diagram of the fragment,

[0067] Figure 3 shows a schematic cross-sectional view of a radiation-emitting semiconductor chip according to an embodiment, and

[0068] Figure 4 A schematic sectional illustration of a radiation-emitting semiconductor component according to a further exemplary embodiment is shown.

[0069] Identical, similar or functionally identical elements are provided with the same reference numerals in the drawings. The figures of the elements shown in the drawings and the ratios to one another are not to be considered to be drawn to scale. Rather, individual elements may be shown exaggeratedly for better display and / or for better understanding.

[0070] according to Figure 1 and Figure 2 The radiation-emitting semiconductor chip of the exemplary embodiment of FIG. 1 has a mounting area 6. The mounting area 6 is opposite the radiation exit area 2 (not shown here). The radiation-emitting semiconductor chip 1 can be supplied with electricity via the mounting area 6.

[0071] The mounting surface 6 comprises a plurality of first weldable contact surfaces 7 and second weldable contact surfaces 8. The first weldable contact surfaces 7 are arranged in a matrix, i.e., arranged along columns and rows. In this embodiment, the first weldable contact surfaces 7 are arranged at the grid points of the first regular grid. Here, the first regular grid is an orthogonal grid, more precisely a quadrilateral grid. The first weldable contact surfaces 7 each have a quadrilateral, in particular a rectangular shape.

[0072] The first weldable contact surfaces 7 are arranged spaced apart from each other in the lateral direction. In addition, the first weldable contact surfaces 7 are separated from each other by non-emitting regions 11. In a top view, the non-emitting regions 11 are arranged between directly adjacent first weldable contact surfaces 7. The non-emitting regions 11 form a fourth regular grid, wherein the non-emitting regions extend along the grid lines of the fourth grid. Here, the fourth regular grid is a quadrilateral grid.

[0073] The first solderable contact surface 7 is arranged completely in the inner region 9 of the mounting surface. In addition, the edge region 10 of the mounting surface is free of the first solderable contact surface 7. The second solderable contact surface 8 is arranged in the edge region 10 of the mounting surface. The edge region 10 of the mounting surface and the inner region 9 of the mounting surface are arranged separately from each other and do not overlap each other in a top view. The edge region 10 of the mounting surface and the inner region 9 of the mounting surface are separated from each other by a non-emitting region 11.

[0074] The second weldable contact surface 8 completely surrounds the first weldable contact surface 7. In this embodiment, the second weldable contact surface 8 is continuously constructed. Therefore, the second weldable contact surface 8 completely surrounds the first weldable contact surface 7 in the lateral direction.

[0075] An outer surface 8a of the second solderable contact area facing away from the semiconductor layer sequence 4 is arranged in a common plane with an outer surface 7a of the first solderable contact area 7 facing away from the semiconductor layer sequence 4. The radiation-emitting semiconductor chip 1 can thus preferably be surface-mounted.

[0076] As per Figure 2 As shown in the fragment of the inner region 9 of the mounting surface, the first solderable contact surface 7 has a lateral dimension B in the lateral direction. The dimension B of the first solderable contact surface is preferably at least 15 micrometers and at most 50 micrometers, particularly preferably between 25 micrometers and at most 35 micrometers.

[0077] Two directly adjacent first solderable contact surfaces 7 have a distance A from one another. Preferably, the distance A is between at least 1 micrometer and at most 20 micrometers, particularly preferably between at least 5 micrometers and at most 15 micrometers.

[0078] With such a distance A and a transverse dimension B, the first weldable contact surface 7 can form at least 60% of the inner region 9 of the mounting surface. Preferably, the first weldable contact surface 7 forms at least 70%, particularly preferably at least 80% of the inner region 9 of the mounting surface. In this embodiment, the mounting surface 9 is mostly formed by the first weldable contact surface 7.

[0079] according to Figure 3 The radiation-emitting semiconductor chip 1 of the exemplary embodiment of FIG. 1 comprises an epitaxial semiconductor layer sequence 4 which includes active regions 5 . Each of the active regions 5 is designed to emit electromagnetic radiation from a respective emitter region 3 .

[0080] The semiconductor layer sequence 4 includes a first semiconductor layer 18 of a first conductivity type and a second semiconductor layer 19 of a second conductivity type. In this embodiment, the first semiconductor layer 18 is p-doped and thus constructed as p-conductive, and in this embodiment, the second semiconductor layer 19 is n-doped and thus constructed as n-conductive. In addition, the active region 5 is arranged between the first semiconductor layer 18 and the second semiconductor layer 19.

[0081] A recess 15 is arranged in the semiconductor layer sequence 4 from the side facing the mounting surface 9. The recess 15 completely penetrates the first semiconductor layer sequence 18 and the active region 5. In addition, the recess 15 extends into the second semiconductor layer 19. Therefore, the recess 15 separates the active region 5 and divides it into active regions 5 separated from each other. Therefore, the recess 15 contributes to the spacing of the active regions 5 in the lateral direction. Therefore, the recess predetermines the size of the emitter region 5 in the lateral direction. The emitter region 3 is arranged above the associated active region 5. The active region 5 completely overlaps with the associated emitter region 3 in a top view.

[0082] The non-emitting regions 11 are predetermined by the recesses 15. The recesses 15 are constructed continuously and extend along the grid lines of the fourth regular grid.

[0083] Furthermore, the second conductive layer 13 is arranged in the recess 15. The second conductive layer 13 is in direct contact with the second semiconductor layer 19 in the region of the recess 15. Here, the first insulating layer 16 is arranged between the second conductive layer 13 and the side surface 15a of the recess. The first insulating layer 15 is configured to electrically insulate the second conductive layer 13 from the first semiconductor layer 18 and the active region 5.

[0084] The electrically conductive connection layer 14 is arranged on the second electrically conductive layer 13. In this case, the electrically conductive connection layer 14 is arranged directly on an outer surface 13a of the second electrically conductive layer facing away from the semiconductor layer sequence 4. The electrically conductive connection layer 14 extends beyond the second electrically conductive layer 13 in a lateral direction.

[0085] The electrically conductive connection layer 14 can be an electrically conductive mirror layer which is preferably designed to reflect the electromagnetic radiation generated in the active region 5 and preferably contains gold.

[0086] The electrically conductive connection layer 14 is in electrically conductive contact with the second contact area 8 in the edge region 10 of the mounting area. The second semiconductor layer 19 is electrically conductively connected to the second contact area 8 via the electrically conductive connection layer 14 and the second electrically conductive layer 13.

[0087] Furthermore, each active region 5 is respectively connected in an electrically conductive manner to the first solderable contact area 7 by means of a first electrically conductive layer 12. In the region of the active region 5, the first semiconductor layer 18 is in electrically conductive contact with the first electrically conductive layer 12.

[0088] Furthermore, a first insulation layer 16 is arranged between the electrically conductive connection layer 14 and an outer surface 4 a of the semiconductor layer sequence facing the mounting area 6 .

[0089] Furthermore, a second insulating layer 17 is arranged on the electrically conductive connecting layer 14 on an outer surface 14a facing the mounting area 6. In this case, the second insulating layer 17 is arranged between the first solderable contact area 7 and the electrically conductive connecting layer 14 in a form-fitting manner.

[0090] according to Figure 4 The radiation-emitting semiconductor element 20 of the exemplary embodiment has a Figure 3 A radiation-emitting semiconductor chip 1 is provided.

[0091] The radiation-emitting semiconductor component further comprises a further semiconductor chip 21. In this case, the further semiconductor chip 21 has an electronic control element as an integrated circuit 22. Furthermore, the state of one, some or all active regions 5 can be controlled via the integrated circuit 22.

[0092] The radiation-emitting semiconductor chip 1 is arranged with its first solderable contact area 7 and its second solderable contact area 7 on a further semiconductor chip 20 .

[0093] according to Figure 3 The radiation-emitting semiconductor chip 1 or Figure 4 The radiation-emitting semiconductor element 20 can be installed in a floodlight.

[0094] This patent application claims the priority of German patent application 10 2019 105 402.8, the disclosure content of which is incorporated herein by reference.

[0095] The invention is not limited to the description of the exemplary embodiments thereof. Rather, the invention comprises individual novel features and individual feature combinations, which in particular include individual combinations of features in the patent claims, even if this feature or this combination itself is not explicitly stated in the patent claims or exemplary embodiments.

[0096] Reference numerals list

[0097] 1 Radiation-emitting semiconductor chip

[0098] 2 Radiation exit surface

[0099] 3 Emitter region

[0100] 4 Semiconductor layer sequence

[0101] 4a Outer surface of the semiconductor layer sequence

[0102] 5 Active area

[0103] 6 Mounting surface

[0104] 7 First weldable contact surface

[0105] 7a Outer surface of the first weldable contact surface

[0106] 8 Second weldable contact surface

[0107] 8a Outer surface of the second weldable contact surface

[0108] 9 Inner area of ​​the mounting surface

[0109] 10 Edge area of ​​the mounting surface

[0110] 11 Non-emitting area

[0111] 12. First conductive layer

[0112] 13. Second conductive layer

[0113] 13a Outer surface of the second conductive layer

[0114] 14 Conductive connection layer

[0115] 14a Outer surface of the conductive connection layer

[0116] 15 concavity

[0117] 15a Side of the concave portion

[0118] 16 First insulation layer

[0119] 17 Second insulation layer

[0120] 18. First semiconductor layer

[0121] 19 Second semiconductor layer

[0122] 20 Radiation-emitting semiconductor components

[0123] 21 Other semiconductor chips

[0124] 22 Integrated Circuits

[0125] A Distance

[0126] B Dimension

Claims

1. A radiation-emitting semiconductor chip (1), comprising: - emitter regions (3) separated from one another comprising the radiation exit surface (2), - an epitaxial semiconductor layer sequence (4) comprising active regions (5), wherein each active region (5) is designed to emit electromagnetic radiation from a respective emitter region (3), and - a mounting surface (6) opposite to the radiation exit surface (2), wherein the mounting surface (6) comprises a plurality of first weldable contact surfaces (7) and second weldable contact surfaces (8), in - each active area (5) can be electrically connected using a first solderable contact surface (7) and a second solderable contact surface (8), respectively, - the first weldable contact surface (7) is arranged in an inner region (9) of the mounting surface, - the second solderable contact surface (8) is arranged in an edge region (10) of the mounting surface, the recess (15) is arranged in the semiconductor layer sequence (4) from the side facing the mounting area (6), - the recess (15) completely penetrates the active area (5), and - a second conductive layer (13) is arranged in said recess (15), - an electrically conductive connecting layer (14) is arranged on the second electrically conductive layer (13), The electrically conductive connecting layer (14) is electrically conductively connected to the second solderable contact surface (8), and The thickness of the electrically conductive connecting layer (14) is at least 5 nanometers and at most 20 nanometers.

2. The radiation-emitting semiconductor chip according to claim 1, in, The inner region (9) of the mounting surface is free of the second solderable contact surface (8).

3. The radiation-emitting semiconductor chip according to claim 1 , in, The first weldable contact surfaces (7) are separated from each other by non-emitting areas (11).

4. The radiation-emitting semiconductor chip according to claim 1 , in, The second weldable contact surface (8) completely surrounds the first weldable contact surface (7).

5. The radiation-emitting semiconductor chip as claimed in claim 1 , in, The first solderable contact surfaces (7) are arranged in columns and rows.

6. The radiation-emitting semiconductor chip as claimed in claim 1 , in, The first weldable contact surfaces (7) are arranged at grid points of the first regular grid.

7. The radiation-emitting semiconductor chip as claimed in claim 1 , in, Directly adjacent first solderable contact surfaces (7) have a distance of at least 1 micrometer to at most 20 micrometers.

8. The radiation-emitting semiconductor chip as claimed in claim 1 , in, The first solderable contact surface (7) has a maximum dimension in a lateral direction of at least 10 micrometers and at most 50 micrometers.

9. The radiation-emitting semiconductor chip as claimed in claim 1 , in, The first weldable contact surface (7) forms at least 60% of the inner area (9) of the mounting surface.

10. The radiation-emitting semiconductor chip as claimed in claim 1, wherein - each active region (5) is respectively electrically conductively connected to the first conductive layer (12), and Each active region (5) is electrically conductively connected to the second electrically conductive layer (13).

11. The radiation-emitting semiconductor chip as claimed in claim 1, in, The electrically conductive connecting layer (14) is an electrically conductive mirror layer.

12. The radiation-emitting semiconductor chip as claimed in claim 1, in, The first insulating layer (16) is arranged between the second conductive layer (13) and the side surface (15a) of the recess.

13. The radiation-emitting semiconductor chip as claimed in claim 12, in, The first insulating layer (16) is arranged between the electrically conductive connecting layer (14) and an outer surface (4a) of the semiconductor layer sequence facing the mounting area.

14. The radiation-emitting semiconductor chip as claimed in claim 1 or 2, in, The second insulating layer (17) is arranged on the electrically conductive connecting layer (14) on an outer surface (14a) facing the mounting surface (6).

15. The radiation-emitting semiconductor chip as claimed in claim 1, in, The first weldable contact surfaces (7) are each controllable individually and separately from one another.

16. A radiation-emitting semiconductor component (20) having a semiconductor chip (1) according to any one of the preceding claims, comprising a further semiconductor chip (21), wherein - the first solderable contact area (7) and the second solderable contact area (8) are arranged on the further semiconductor chip (21), and - the further semiconductor chip (21) comprises an integrated circuit (22).

17. A searchlight, comprising: A radiation-emitting semiconductor chip (1) according to any one of claims 1 to 15.

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