Modular interleaving technology for scalable power electronic converters

Abstract

A power management integrated circuit includes a modular interleaved clock generator, the modular interleaved clock generator including a plurality of interconnected modular elements, each element being configured to generate and output a clock signal, and each element including: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one element of the plurality of elements being in a closed state, except for at least one interleaved controller having the bypass switch in the closed state, the phase port high input or the phase port low input of the remaining elements each receives a voltage, the voltage causing the clock signals output from the remaining active elements to be interleaved to have an interleaved arrangement including the same phase delay.

Description

Technical Field

[0001] The present disclosure relates generally to multi-cell converters, such as multi-level and multi-phase power converters and their interrelationships, and more particularly to scalable interleaved arrangements of multi-cell converters. Background Art

[0002] Modern small electronic components often include modular converters, often referred to as scalable or stackable converters. Modular converter architectures including flying capacitors or multi-phase configurations can implement pulse width modulation (PWM) based on a phase-shifted (PS) carrier to provide uniform power distribution with lower distortion between the units of the converter. A unit can be referred to as the "power part" of the converter and can include a combination of a switching unit (or two power switches), a power switch driver, a storage component such as an inductor or a capacitor, and a PWM signal generator configured to receive a local clock signal. PS-PWM used with multi-unit converters provides additional features such as reduced output ripple and lower switching losses and harmonic pollution, thereby requiring smaller harmonic filters while achieving better harmonic performance than other modulation techniques.

[0003] PS-PWM is typically achieved by interleaving carriers or control signals with equally spaced phase delays. The phase delay depends on the number of cells, or 360° / N, where N is the number of cells. This phase delay can produce an equivalent stepped multi-level output waveform with lower distortion across the cells of a multi-cell converter.

[0004] Figure 1 is a graph 100 showing an example of a PS-PWM implementation of a conventional multilevel converter operating, for example, as a DC / AC inverter. Here, the converter provides three interleaved and phase-shifted triangular carrier signals and three PS-PWM signals (SP1, SP2, SP3) with phase delays of 0°, 120°, and 240°. Due to the interleaved arrangement, the combined signal μ out has a frequency three times greater than that of each PWM signal.

[0005] However, conventional multi-unit systems, etc., cannot be reconfigured during operation. For example, if a unit of the converter is disabled, inoperable, or unable to process the PS-PWM signal during operation, the interleaving arrangement required to generate the PS-PWM signal cannot be modified. For example, if signal SP3 cannot be generated, fixed hardware, such as defined by resistor configuration, processes only signals SP1 and SP2. Because the phase delay is provided by non-configurable hardware, such as defined by resistor values, the phase delay cannot be adjusted regardless of the unavailability of signal SP3. Summary of the Invention

[0006] Aspects of the present disclosure are defined in the following claims.

[0007] In a first aspect, a power management integrated circuit is provided, comprising a modular staggered clock generator, the modular staggered clock generator comprising a plurality of interconnected modular elements, each element being configured to generate and output a clock signal, and each element comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one element of the plurality of elements being in a closed state, except for the at least one element having the bypass switch in the closed state, the phase port high input or the phase port low input of the remaining elements each receives a voltage, the voltage causing the clock signals output from the remaining active elements to be staggered to have a staggered arrangement including the same phase delay.

[0008] In one or more embodiments, the modular staggered clock generator may further include: a resistor ladder comprising a plurality of resistors coupled in series; and a voltage source providing a supply voltage to the resistor ladder, wherein each resistor of the resistor ladder is coupled to an element of the plurality of interconnected elements.

[0009] In one or more embodiments, each resistor of the resistor ladder can be connected in parallel with the bypass switch of the interleaving controller of the plurality of elements to which the resistor ladder is coupled, such that the phase port high input of the interleaving controller is coupled to the resistor ladder on one side of the resistor and the phase port low input of the interleaving controller is coupled to the resistor ladder on the other side of the resistor.

[0010] In one or more embodiments, the power management integrated circuit may further include the phase port high input, the phase port low input, and a direct connection between the bypass switch and the resistor of the resistor ladder coupled to the at least one element among the multiple elements having the bypass switch in the closed state, and the bypass switch and the resistor may be external to the at least one element among the multiple elements or may be integrated with the at least one element among the multiple elements.

[0011] In one or more embodiments, each of the plurality of elements may have a clock signal output constructed and arranged to output the clock signal with a phase delay, the phase delay forming the staggered arrangement in response to a clock source providing an input clock to each clock input.

[0012] In one or more embodiments, when the clock signals of the interleave controllers of the plurality of elements are in phase with the external clock signals previously received by the clock inputs of the plurality of interleave controllers, the interleave controllers of the plurality of elements can be switched from slave interleave controllers to master interleave controllers to output their clock signals from the bidirectional clock input / output interface to other interleave controllers.

[0013] In one or more embodiments, the at least one element of the plurality of elements may have an internal phase-locked loop that generates the clock signal at the same frequency as the clock signal at the clock input.

[0014] In one or more embodiments, the at least one element among the plurality of elements having the bypass switch in the closed state may control the remaining elements to rearrange the clock signal to form the staggered arrangement including the same phase delay.

[0015] In one or more embodiments, the power management integrated circuit may further include an external signal source that generates an enable bypass signal that controls the switching of the bypass switch between the open state and the closed state.

[0016] In one or more embodiments, the phase port high input may form the phase delay of the clock signal.

[0017] In one or more embodiments, the phase port low input may form the phase delay of the clock signal.

[0018] In one or more embodiments, the difference between the phase port high input and the phase port low input may indicate the number of active elements and the value of the relative phase delay.

[0019] In one or more embodiments, one of the elements may include a clock master interleave controller that provides the clock signal to other elements among the multiple elements, and when the clock master interleave controller is in an inactive state, another element among the other elements having a phase low voltage equal to the ground voltage at its phase port low input may automatically send its clock signal to the other element.

[0020] In one or more embodiments, one of the elements may include a master interleave controller that provides the clock signal to the other element, and when the master interleave controller is in an inactive state, another element of the other element having a phase high voltage equal to the ground voltage at its phase port high input may automatically send its clock signal to the other element.

[0021] In a second aspect, an interleaving controller for a clock generator of a power management integrated circuit is provided, comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch being in a closed state, a converter includes a direct connection between the phase port high input, the phase port low input, and the bypass switch to modify an interleaving arrangement, the interleaving arrangement including one or more other interleaving controllers in electronic communication with the interleaving controller.

[0022] In one or more embodiments, the staggered arrangement may include the same phase delay of clocks generated by other staggered controllers.

[0023] In one or more embodiments, the interlace controller may further include a clock signal output constructed and arranged to output a clock signal in response to a signal received at the clock input.

[0024] In one or more embodiments, when the clock signal is in phase with the external clock signal previously received by the clock inputs of the plurality of interleave controllers, the interleave controller may be switched from a slave interleave controller to a master interleave controller to output the clock signal from the clock input to the other interleave controllers.

[0025] In a third aspect, a method of forming a reconfigurable hardware interleaving arrangement for a power management integrated circuit is provided, comprising: outputting a first clock signal to a plurality of slave interleaving controllers; generating a plurality of second clock signals having phase delays relative to the first clock signal; activating a bypass switch of at least one of the slave interleaving controllers; and reconfiguring the interleaving arrangement including the phase delays of the second clock signals in response to activating the bypass switch.

[0026] In one or more embodiments, reconfiguring the hardware interleave arrangement may further include transferring control of one of the plurality of slave interleaves to a master controller of the interleave controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0028] Figure 1 is a graph showing a staggered arrangement of a conventional multilevel converter. Figure 2 is a schematic circuit diagram of a power management integrated circuit (PMIC) including multiple stackable buck controllers, each having interleaved controller (IC) connections.

[0029] Figure 3A and 3B It shows Figure 2 Diagram of a phase delay arrangement of a conventional modular master-slave six (6) phase controller that changes the operating mode depending on the phase selection input voltage.

[0030] Figure 4A and 4B It operates in twelve phases Figure 2 Figure 1.1 shows a diagram of the same conventional controller.

[0031] Figure 5A and 5B is shown operating in ten phases due to unavailable or unneeded slave modules Figure 4A and 4B Diagram of the controller.

[0032] Figure 6A is a block diagram of an IC in a modular converter for generating staggered clocks according to an example embodiment of the present disclosure.

[0033] Figure 6B are shown separately Figure 6A A graph of the waveforms of the IC's input clock and output clock.

[0034] Figure 7A is a schematic circuit diagram of a staggered arrangement with three ICs according to an example embodiment of the present disclosure.

[0035] Figure 7B is Figure 7A 2 is a diagram illustrating the waveform of an interleaved clock signal generated by an interleaved arrangement of FIG.

[0036] Figure 8A is a schematic circuit diagram of a staggered arrangement with four ICs according to an example embodiment of the present disclosure.

[0037] Figure 8B is Figure 8A 2 is a diagram illustrating the waveform of an interleaved clock signal generated by an interleaved arrangement of FIG.

[0038] Figure 8C is a general schematic circuit diagram of a staggered arrangement with any number of ICs according to an example embodiment of the present disclosure.

[0039] Figure 9A is a schematic circuit diagram illustrating dynamic reconfiguration of a staggered arrangement according to an example embodiment of the present disclosure.

[0040] Figure 9B and 10is a schematic circuit diagram illustrating one element sharing its clock with other elements instead of or requiring an external clock according to other example embodiments of the present disclosure.

[0041] Figure 11 is a flowchart representation of a reconfigurable hardware interleaving technique according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Conventional converters may include a combination of master and slave interleave controllers (ICs) stacked together to generate multiple desired phase-shifted clocks for associated converters.

[0043] For example, reference Figure 2 , a power management integrated circuit (PMIC) 10 includes a plurality of stackable buck controller modules 20, 20A, 20C. PMIC 10 may include a processor core, memory, input / output (I / O), and peripheral components (not shown) that receive direct power from ICs 201, 202A, 202B of modules 20, 20A, 20B. PMIC 10 may be implemented in a variety of automotive, industrial, and consumer applications and perform various battery management, voltage regulation, switching, and charging functions.

[0044] ICs 201, 202A, and 202B of modules 20, 20A, and 20B can be configured as either master or slave devices. Thus, all modules are constructed and arranged to include the same IC. Each module is a complete converter in its own right. However, the modules can be stackable, scalable, and modular, as each module can be associated with modules of similar or identical configurations. A characteristic feature of such a configuration is that modules can be removed without affecting other modules.

[0045] Each IC 201, 202A, 202B has an internal clock generator that provides an internal phase-shifted clock CLK 203. In this particular case, each module 20, 20A, 20B has two phases or current outputs or legs that are controlled in an opposite phase manner. For the purposes of this example, module 20 is referred to as the "master" and modules 20A, 20B are referred to as "slaves."

[0046] exist Figure 2In the operating mode of module 20 in FIG, the master IC 201 sends a clock signal (CLKIO) to all slave devices 202A, 202B (typically 202). The master device 201 applies a predetermined current to the resistor network R1, R2 extending between the master device 201 and the slave device 202 to provide a specified voltage to the PHSEL input of IC 201, 202, respectively. The voltage value generated at the PHSEL input is sensed by the internal IC. Therefore, each slave IC 202 delays the local CLK for an appropriate amount of time consistent with the interleaved operating mode of the multi-phase converter. The PHSEL input can be read by an analog-to-digital converter, and the electronics delay the local clock CLK to generate the PS-PWM signal. Therefore, Figure 2 Conventional electronic devices shown and described in are generally limited to producing a strict number of phase delays.

[0047] Figure 3A and 3B It shows Figure 2 FIG10 is a diagram of an interleaved phase delay arrangement of a conventional six-phase controller of a PMIC 10 shown capable of handling voltages that change operating modes depending on the phase selection voltage.

[0048] For example, in a six-phase configuration including a master device 201 and two slave devices 202A, 202B, Figure 3B The points on the circle shown represent equally spaced phase delays for each PWM signal. As described herein, a system-on-chip (SoC) or the like can be an example of a "module," which, as explained above, can include both an IC and a unit. Thus, in some embodiments, an SoC is a converter consisting of a control scheme, a switching unit including two power switches, and, in some cases, filtering elements. Such converters can be scalable, i.e., formed from multiple interoperable modules.

[0049] Similarly, if Figure 4A and 4B The twelve-phase configuration is shown in Figure 4B The points on the circle shown are distributed at equal intervals. However, an additional input is required for twelve-phase operation. Specifically, the slave devices 202C, 202D, and 202E require the auxiliary input AUX to be at a different level, e.g., a different voltage, than the level of the master device 201 and the slave devices 202A and 202B. During hardware construction, the AUX level is defined by the device connection. An AUX level equal to high "H" (e.g., 1.8V-VDD) rather than "L" (e.g., 0-0.8V) adds an additional phase delay of 30° to ensure PS-PWM. And, the auxiliary input AUX provides the additional phase delay to Figure 4A IC200C-E in the circuit is used to distinguish its phase delay from that of the interleaving controllers 201, 202A, and B.

[0050] Figure 5A and 5B is shown to operate in ten (10) phases Figure 4A and 4B As previously mentioned, PS-PWM is usually obtained using control signals with phase delays of the same interval. However, Figure 5A and 5B The controller shows phase delays that are not of equal intervals because the slave device 202E is missing, unused, experiencing a fault, or otherwise unavailable or inoperable. Unequal phase intervals can cause subharmonic oscillations, which typically require an oversized and therefore undesirable output filter to comply with the ripple limit.

[0051] In brief overview, embodiments of the inventive concept provide a method for modular interleaving of stackable multi-cell converters, where optimal interleaving can be achieved across any number of phases and reconfiguration occurs during operation, rather than being defined in hardware such as resistors. In some embodiments, the scalable and reconfigurable interleaving techniques required to generate PS-PWM signals are implemented by local decision-making among the various modular converters associated therewith, specifically, by a common interleaving controller, and not necessarily by a master interleaving controller.

[0052] These local decision-making capabilities allow the common interleave controller to dynamically reconfigure the converters for optimal interleaving when common modules fail or are otherwise inactive or unavailable. Because local decision-making does not need to be performed by the master interleave controller, in some embodiments, the master interleave controller is not required to provide clock signals for the interleaving.

[0053] Figure 6A is an interleaving controller (IC) 600 of a modular converter according to some embodiments. In some embodiments, the interleaving controller 600 is Figure 2 The interleaving controller 600 is a part of the PMIC 10 and can therefore be used in various automotive, consumer or industrial applications, but is not limited thereto. For the reasons described herein, the interleaving controller 600 is about Figure 2 、 3A, 3B, 4A, 4B, 5A, 5B. The interleaving controller 600 may include one or more semiconductor materials connected to form a circuit, or more specifically, a converter unit that may be connected to form a buck converter, etc. or associated with one or more other units forming a multi-unit converter, etc. In some embodiments, the interleaving controller 600, together with other necessary control elements, constitutes a control scheme for the converter. The interleaving controller 600 may be included in a module or other electronic circuit collection that includes one or more units, or more specifically, a switching unit, a converter / inverter, etc. In some embodiments, the interleaving controller 600 is part of a computer motherboard, etc. In some embodiments, the interleaving controller 600 may operate as part of a power converter controller, such as, but not limited to, a buck or boost regulator of a PMIC, etc. In some embodiments, the interleaving controller 600 may be configured and arranged to act as a clock master ("master") or a clock slave ("slave").

[0054] The interleave controller 600 includes a phase port high input (PH_H) 601, a phase port low (PH_L) input 602, a clock (CLKIO) input 611, and a clock (CLK) output 612. In some embodiments, the interleave controller 600 includes an internal phase-locked loop (PLL) that is coupled to the clock signal CLKIO (see Figure 6B ) generates a clock signal CLK at the same frequency, with a period (T) = 1 / f and a time delay V PH_L / V DD T, where V DD is the supply voltage, and VPH_L is the voltage at the phase port low input 602 .

[0055] like Figure 7A and 8A As shown in the schematic diagram, various associations with different component numbers may generate the required number of PSCLK signals. Figure 7A In FIG. 1 , three slave elements 700A, 700B, 700C of an interleaved converter or controller are shown, which can be connected to Figure 6A The elements of the interleaving controller 600 are similar or identical. In some embodiments, the elements 700 are constructed and arranged as a switching unit or unit of a multi-unit converter or the like to provide the desired control of the converter. In addition to showing four slave elements 800A, 800B, 800C, 800D (generally 800), Figure 8A Also similar to Figure 6A In some embodiments, the components 700, 800 are part of a modular interleaved clock generator of a PMIC or the like, for example, Figure 2The PMIC 10 is shown and described.

[0056] Reference again Figure 7A A conductive connector 721, such as a metal line, is coupled to each CLKIO input 711 for transmitting the clock signal EX_CLK to all slave elements 700A-700C (generally 700). Figure 2 As shown in the conventional arrangement of FIG, the clock signal EX_CLK is provided between the slave elements 700 instead of being generated by the master element. In some embodiments, the conductive connector 721 includes a clock resistor R for providing clock termination for the clock signal EX_CLK driving the circuit load. CLK .

[0057] The phase port high input 701 and the phase port low input 702 of each element 700 are coupled to a common voltage supply line 722 or node, such as a metal line. For each element 700, one or more resistors R and a bypass switch 723 can form a voltage loop or a direct connection to connect the phase port high input 701 and the phase port low input 702. The resistor R and the interleaving controller bypass switch 723 can be integrated with respect to the element 700 or external to the element.

[0058] For example, Figure 7B As shown, each element 700 also has a clock output 712 for outputting a clock signal CLK having a predetermined phase relative to the other elements. The clock signals CLK of the elements 700 are interleaved to provide a combined signal having a frequency greater than that of each individual clock signal due to the interleaved arrangement. However, if a failure occurs or if an element 700 in the configuration is unavailable or inoperable due to other problems, the clock signals CLK can be automatically interleaved in a different arrangement so that the unavailable or inoperable element is bypassed and the clock signals CLK output from the remaining elements have the same phase delay.

[0059] In some embodiments, the bypass switch 723 is controlled by an enable bypass signal (EN_BP). The enable bypass signal (EN_BP) can be generated by an external signal source 902 (see Figure 9A ) is provided, the external signal source generating an enable bypass signal (EN_BP) in response to a sensor signal indicating the status of the corresponding slave device 700, for example. For example, the signal source may be in communication with or part of a voltage sensor slave device 700C, which detects that the slave device 700C is receiving a voltage exceeding a threshold value. Here, the voltage sensor may notify the external signal source, which in turn outputs the enable bypass signal EN_BP that closes switch 723, so that the slave device 700C is no longer part of the association with the other slave elements 700A, 700B. Figure 7AThe converter in is automatically reconfigured by a combination of an enable signal (EN_EP) and a resistor ladder to produce interleaved signals that provide the desired equally spaced phase delays, e.g. Figure 7B As shown, the resistor ladder is formed by resistors R connected in series with each other along a voltage supply line 722, but each resistor R is connected in parallel with an interleaving controller bypass switch 723. More specifically, for reconfiguration, the bypass switch 723 connects node 722 directly to ground GND, making the interleaving controller 700C irrelevant to the reconfiguration. Here, the phase port high input 701 and low input 702 of the element 700 are coupled to the voltage supply line 722, so that the voltage loop includes the resistors R of the resistor ladder, where the output voltage, the phase high (PH_H) and phase low (PH_L) voltages at the inputs 701 and 702, respectively, are the supply voltage V DD The PH_H and PH_L voltage pins allow each element 700 to identify the number (N) of active elements, such as modules, and its own position (or ranking) in the chain. The appropriate phase shift can then be calculated and implemented accordingly.

[0060] The phase port low (PH_L) input 702 presents a voltage ratio for selecting the carrier phase delay and produces an interleaved arrangement, i.e., with a number of equals depending on the interleaving controller typically used. Figure 7A The three interleaved controllers shown have control signals with phase delays of the same interval of 360° / N. Figure 7A The interleaved controllers configured in the three interleaved controllers present the following voltages at the phase port low input 702 of the elements 700A, 700B, 700C respectively: [2 / 3, 1 / 3, 0 / 3] V at phases [240°, 120°, 0°] respectively DD .

[0061] refer to Figure 8A , conductive connector 821 is coupled to each CLKIO input 811 of each of the four elements 800A-800D. For each element 800, resistor R and switch 723 can form a voltage loop to connect the phase port high input 801 and the phase port low input 802 controlled by the enable bypass signal (EN_BP). Figure 8A The enable bypass signal (EN_BP) is similar to Figure 7A The enable bypass signal is therefore not repeated in detail for the sake of brevity, as well as the details of the voltage loop of element 800.

[0062] Figure 8A and 8BThe four interleaved controller configurations shown represent the following voltages at the phase port low input 802 of elements 800A, 800B, 800C, and 800D, respectively: [3 / 4, 2 / 4, 1 / 4, 0 / 4] V at phases [270°, 180°, 90°, 0°], respectively. DD . Figure 8B The obtained results are shown in Figure 8A The IC corresponds to the staggered clock signal.

[0063] Embodiments are not limited to two, three, or four interleaving controllers and may include more than four interleaving controllers, where the voltage and phase may be calculated accordingly. Figure 8C Arrangements with a typical number of elements are shown.

[0064] As described above, the features of the multi-cell power converters of various embodiments herein include a reconfigurable hardware interleaving arrangement. Figure 9A and 9B As shown, Figure 8A and 8B The four-mode converter can be dynamically reconfigured as shown. This reconfiguration can produce Figure 7A The circuit shown is an equivalent system.

[0065] like Figure 9A As shown, slave element 800C receives an enable bypass signal (EN_BP) that closes its bypass switch 823. A signal source (not shown) may generate the enable bypass signal (EN_BP) in response to receiving a notification from a sensor or the like indicating that slave element 800C is malfunctioning, damaged, or otherwise unavailable for operation.

[0066] When the bypass switch 823 is closed, the corresponding resistor R C The voltage of is at or about 0 volts. Therefore, there are three elements 800A, 800B, and 800D available for operation. The resistor ladder voltage is also similar to the resistor ladder voltage in a configuration with three interleaved controllers, such as Figure 7A and 7B Specifically, the slave element 800 has [2 / 3, 1 / 3, 1 / 3A and 0 / 3]V DD The PH_L voltages and corresponding phase delays of [2 / 3, 1 / 3, 1 / 3A, 0 / 3]T, where 1 / 3A involves the voltage and phase delay of the bypass element 800C. As a result, the active elements 800A, 800B, 800D are interleaved in the correct manner, i.e., with the same interval phase delay, etc., without the need for Figure 9B Component 800C is shown.

[0067] Reference again Figure 8B, the clock output CLK from the component 800D is in phase with the external clock EX_CLK. In some embodiments, Figure 9B As shown, slave element 800C can operate as a clock master to provide its clock signal CLK to clock slave devices 800A, 800B via its bidirectional CLKIO pin. In such embodiments, the state of the module, i.e., master or slave, can be established by the PH_L voltage at or near ground (0V). In a configuration including a clock master that provides a clock signal to a clock slave device, when the master device is in an inactive state (i.e., bypassed or faulty), the available active interleave controller with a PH_L voltage equal to GND automatically sends its clock signal to the other interleave controllers.

[0068] Figure 10 is a schematic circuit diagram illustrating dynamic reconfiguration of a multi-cell converter according to another example embodiment of the present disclosure. Figure 10 In an alternative arrangement, the PH_H voltage is used to define the phase delay. In other words, Figure 10 Element 1000A is shown. By using PH_H voltage = VDD, element 1000A is established as the master element, which is consistent with Figure 9B Different from the above, it defines the main element 800C as PH_L=GRD. Figure 10 In FIG, the interleaving controller's phase port high (PH_H) input 1001 presents a voltage ratio for selecting the carrier phase delay, rather than the PH_L input 1002. Here, element 1000A, with a PH_H voltage equal to VDD, is configured as a clock master that provides its clock to the converter's other clock slave elements 1000B, 1000C.

[0069] Figure 10 The interleaved controllers of the three interleaved controllers configured in FIG present the following voltages and phases at the phase port high input 1001 of the components 1000A, 1000B, 1000C, respectively (from top to bottom): [3 / 3, 2 / 3, 1 / 3] V at phases [0°, 240°, 120°], respectively. DD .

[0070] Figure 11 is a flowchart representation of a reconfigurable hardware interleaving technique according to an example embodiment of the present disclosure. Figure 1-10 Hardware components that perform the method steps outlined in the flowchart representation.

[0071] At block 1102, a first clock signal is output to a plurality of interleaved controllers of a multi-unit converter, inverter, controller, or other electronic device. In some embodiments, the first clock signal is similar to Figures 7A-9AIn other embodiments, the first clock signal is a clock signal output from one of the interleaving controllers to the other interleaving controllers, for example, similar to the clock signal output from Figure 9B Reconfigured main element 800D or Figure 10 The clock (CLKIO) is output by the clock master element 1000A.

[0072] At block 1104, a plurality of second clock signals are output by other interleaving controllers. In some embodiments, the second clock signal is a clock signal (CLK) output in response to receipt of the first clock signal and has a phase delay relative to the first clock signal, for example, Figures 7A-8B shown.

[0073] At block 1106, a bypass switch at the interleave controller is activated, e.g., Figure 9A Element 800C is shown as bypass switch 823. The bypass switch may be activated by receiving a signal from an external source, an internal sensor of the interleave controller, or other signal source that generates a signal due to a malfunction or detection of an undesirable change in state of a module-operated converter module or the interleave controller.

[0074] At block 1108, the functionally faulty module is removed from the set of operational modules, specifically by forming a voltage loop including an activated bypass switch. In doing so, a reconfiguration operation is performed in which the clock signals of the remaining interleaving controllers have the same phase delay, e.g., to compensate for the different phase intervals caused by the inoperable interleaving controller, e.g., Figure 5A and 5B shown.

[0075] As will be appreciated, the disclosed embodiments include at least the following: In one embodiment, a power management integrated circuit includes a modular interleaved clock generator, the modular interleaved clock generator comprising a plurality of interconnected modular elements, each element being configured to generate and output a clock signal, and each element including: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one element of the plurality of elements being in a closed state, the phase port high input or the phase port low input of the remaining elements, except for the at least one element having the bypass switch in the closed state, each receives a voltage, the voltage causing the clock signals output from the remaining N active elements to have an interleaved arrangement including the same phase delay.

[0076] An alternative embodiment of the power management integrated circuit includes one or any combination of the following features. The modular interleaved clock generator further includes: a resistor ladder comprising a plurality of resistors coupled in series; and a voltage source providing a supply voltage to the resistor ladder, wherein each resistor of the resistor ladder is coupled to an element of a plurality of interconnected elements. Each resistor of the resistor ladder is connected in parallel with a bypass switch of an interleaving controller of the plurality of elements to which the resistor ladder is coupled, such that a phase port high input of the interleaving controller is coupled to the resistor ladder on one side of the resistor and a phase port low input of the interleaving controller is coupled to the resistor ladder on the other side of the resistor. The power management integrated circuit further includes a phase port high input, a phase port low input of at least one element of the plurality of elements having a bypass switch in a closed state, and a direct connection between the bypass switch and the resistors of the resistor ladder coupled to the at least one element of the plurality of elements, wherein the bypass switch and the resistors are external to or integrated with at least one of the plurality of elements. The clock input of an interleave controller of at least one of the plurality of elements operating as a master interleave controller is a bidirectional clock input / output interface responsive to a multiphase controller that is reconfigured to interleave clock signals output from the interleave controllers of the plurality of elements, excluding interleave controllers having bypass switches in a closed state. Each of the plurality of elements has a clock signal output that is constructed and arranged to output a clock signal with a phase delay that forms an interleaved arrangement responsive to a clock source providing an input clock to each clock input. When the clock signal of the interleave controller of the plurality of elements is in phase with an external clock signal previously received by the clock input of the plurality of interleave controllers, the interleave controller of the plurality of elements can be transitioned from a slave interleave controller to a master interleave controller, thereby outputting its clock signal from the bidirectional clock input / output interface to the other interleave controllers. At least one of the plurality of elements has an internal phase-locked loop that generates a clock signal at the same frequency as the clock signal at the clock input. The power management integrated circuit further includes a conductive connector coupled to each of the clock inputs of the interleave controller to provide an external clock signal to each of the interleave controllers. At least one of the plurality of elements having a bypass switch in the closed state controls the remaining elements to rearrange the clock signals to form an interleave arrangement including the same phase delay. The power management integrated circuit further includes an external signal source that generates an enable bypass signal that controls the switching of the bypass switch between an open state and a closed state. A phase port high input forms a phase delay of the clock signal. A phase port low input forms a phase delay of the clock signal.One of the elements includes a clock master interleave controller that provides a clock signal to other elements of the plurality of elements, and wherein when the clock master interleave controller is in an inactive state, another element of the other elements having a phase low voltage equal to a ground voltage at its phase port low input can automatically send its clock signal to the other elements. One of the elements includes a master interleave controller that provides a clock signal to the other elements, and wherein when the master interleave controller is in an inactive state, another element of the other elements having a phase high voltage equal to a ground voltage at its phase port high input can automatically send its clock signal to the other elements.

[0077] In another embodiment, an interleaving controller for a clock generator of a power management integrated circuit includes: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch being in a closed state, the converter includes a direct connection between the phase port high input, the phase port low input, and the bypass switch to modify an interleaving arrangement, the interleaving arrangement including one or more other interleaving controllers in electronic communication with the interleaving controller.

[0078] Alternative embodiments of the interleave controller include one or any combination of the following features. The interleave arrangement includes a common phase delay of clocks generated by other interleave controllers. The interleave controller further includes a clock signal output constructed and arranged to output a clock signal in response to a signal received at a clock input. When the clock signal is in phase with an external clock signal previously received at the clock inputs of the plurality of interleave controllers, the interleave controller can be switched from a slave interleave controller to a master interleave controller to output the clock signal from the clock input to the other interleave controllers.

[0079] In another embodiment, a method of forming a reconfigurable hardware interleave arrangement for a power management integrated circuit includes: outputting a first clock signal to a plurality of slave interleave controllers; generating a plurality of second clock signals having phase delays relative to the first clock signal; activating a bypass switch of at least one slave interleave controller; and reconfiguring the interleave arrangement including the phase delays of the second clock signals in response to activating the bypass switch.

[0080] A power management integrated circuit includes a modular interleaved clock generator, the modular interleaved clock generator including a plurality of interconnected modular elements, each element being configured to generate and output a clock signal, and each element including: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one element of the plurality of elements being in a closed state, except for at least one interleaved controller having the bypass switch in a closed state, the phase port high input or the phase port low input of the remaining elements each receives a voltage, the voltage causing the clock signals output from the remaining active elements to be interleaved to have an interleaved arrangement including the same phase delay.

[0081] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefits, advantages, or solutions to problems described herein with respect to specific embodiments be construed as key, required, or essential features or elements of any or all of the claims.

[0082] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other priority of such elements.

Claims

1. A power management integrated circuit, characterized in that: include: A modular interleaved clock generator comprising: A plurality of interconnected modular elements, each element being configured to generate and output a clock signal, and each element comprising: Phase port high input; Phase port low input; clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one element among the plurality of elements being in a closed state, the phase port high input or the phase port low input of the remaining elements except the at least one element having the bypass switch in the closed state each receives a voltage, the voltage staggering the clock signals output from the remaining active elements to have a staggered arrangement including the same phase delay.

2. The power management integrated circuit according to claim 1, wherein: The modular staggered clock generator additionally comprises: a resistor ladder comprising a plurality of resistors coupled in series; and A voltage source provides a supply voltage to the resistor ladder, wherein each resistor of the resistor ladder is coupled to an element of the plurality of interconnected elements.

3. The power management integrated circuit according to claim 2, wherein: Each resistor of the resistor ladder is connected in parallel with the bypass switch of the interleaving controller of the plurality of elements to which the resistor ladder is coupled such that the phase port high input of the interleaving controller is coupled to the resistor ladder on one side of the resistor and the phase port low input of the interleaving controller is coupled to the resistor ladder on the other side of the resistor.

4. The power management integrated circuit according to claim 2, wherein: Also included is a direct connection between the phase port high input, the phase port low input, and the bypass switch of the at least one element among the plurality of elements having the bypass switch in the closed state and a resistor of the resistor ladder coupled to the at least one element among the plurality of elements, and wherein the bypass switch and the resistor are external to or integrated with the at least one element among the plurality of elements.

5. The power management integrated circuit according to any one of claims 1 to 4, characterized in that: Each of the plurality of elements has a clock signal output constructed and arranged to output the clock signal with a phase delay that forms the staggered arrangement in response to a clock source providing an input clock to each clock input.

6. The power management integrated circuit according to any one of claims 1 to 4, characterized in that: When the clock signals of the interleave controllers of the plurality of elements are in phase with the external clock signals previously received by the clock inputs of the plurality of interleave controllers, the interleave controllers of the plurality of elements are switched from slave interleave controllers to master interleave controllers to output their clock signals from the bidirectional clock input / output interface to other interleave controllers.

7. The power management integrated circuit according to any one of claims 1 to 4, characterized in that: The at least one element of the plurality of elements has an internal phase locked loop that generates the clock signal at the same frequency as the clock signal at the clock input.

8. The power management integrated circuit according to any one of claims 1 to 4, characterized in that: The at least one element of the plurality of elements having the bypass switch in the closed state controls the remaining elements to rearrange the clock signal to form the staggered arrangement including the same phase delay.

9. An interleaving controller for a clock generator of a power management integrated circuit, characterized in that: include: Phase port high input; Phase port low input; Clock input; as well as a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch being in a closed state, the converter includes a direct connection between the phase port high input, the phase port low input, and the bypass switch to modify an interleaving arrangement including one or more other interleaving controllers in electronic communication with the interleaving controller.

10. A method of forming a reconfigurable hardware interleaving arrangement for a power management integrated circuit, characterized in that: include: outputting a first clock signal to a plurality of slave interleaving controllers; generating a plurality of second clock signals having phase delays relative to the first clock signal; activating a bypass switch of at least one of the slave interlace controllers; and reconfiguring the staggered arrangement including the phase delay of the second clock signal in response to activating the bypass switch.

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