Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device with low transistor characteristic variation is provided. The semiconductor device includes the following manufacturing steps: forming first to third insulators; sequentially forming a fourth insulator, a first oxide film, a second oxide film, a third oxide film, a first conductive film, a first insulating film, and a second conductive film on the third insulator; processing the third insulator into an island shape to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer; removing the second conductive layer; forming fifth and sixth insulators on the fourth insulator, the first oxide, the second oxide, the first oxide layer, the first conductive layer, and the first insulating layer; forming a third oxide, a fourth oxide, a first conductive layer, a second conductive layer, a seventh insulator, and an eighth insulator by forming an opening that reaches the second oxide; and forming a fifth oxide, a ninth insulator, and the third conductive layer in the opening, wherein the fifth insulator is formed by bias sputtering.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor chip and a module.

[0002] Note that in this specification and other documents, a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices may also include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. An embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known. In addition, as other materials, oxide semiconductors have attracted attention.

[0005] In oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been discovered (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose a technology for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

[0007] [Prior technical literature]

[0008] [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers,” 2012, volume 43, issue 1, pp. 183-186

[0010] [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics,” 2014, volume 53, number 4S, pp. 04ED18-1-04ED18-10 Summary of the Invention

[0011] Technical problem to be solved by the invention

[0012] One object of one embodiment of the present invention is to provide a semiconductor device with less variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0013] Note that the inclusion of these objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the present invention does not necessarily achieve all of the aforementioned objectives. Furthermore, objectives other than these objectives are readily apparent from the description, drawings, claims, and the like, and such objectives may be inferred from the description, drawings, claims, and the like.

[0014] Means of solving technical problems

[0015] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulator to a third insulator in sequence; forming a fourth insulator, a first oxide film, a second oxide film, a third oxide film, a first conductive film, a first insulating film, and a second conductive film in sequence on the third insulator; processing the first oxide film, the second oxide film, the third oxide film, the first conductive film, the first insulating film, and the second conductive film into an island shape to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer; removing the second conductive layer; forming a first insulator, a first oxide, a second oxide, a first conductive layer, a first insulating layer, and a second conductive layer on the fourth insulator, the first oxide, the second oxide, the first conductive layer, and the ... first conductive layer; removing the second conductive layer; forming a first insulator, a first oxide, a second oxide, a first conductive layer, a first insulating layer, and a second conductive layer on the fourth insulator, the first oxide, the second oxide, the first conductive A fifth insulator is formed on the oxide layer, the first conductive layer, and the first insulating layer; a sixth insulator is formed on the fifth insulator; an opening reaching the second oxide is formed in the first oxide layer, the first conductive layer, the first insulating layer, the fifth insulator, and the sixth insulator; by forming the opening, a third oxide and a fourth oxide are formed from the first oxide layer, a first conductor and a second conductor are formed from the first conductive layer, and a seventh insulator and an eighth insulator are formed from the first insulating layer; a fifth oxide, a ninth insulator on the fifth oxide, and a third conductor on the ninth insulator are formed in the opening, wherein the fifth insulator is formed by a bias sputtering method.

[0016] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulator to a third insulator in sequence; forming a fourth insulator, a first oxide film, a second oxide film, a third oxide film, a first conductive film, a first insulating film, and a second conductive film in sequence on the third insulator; processing the first oxide film, the second oxide film, the third oxide film, the first conductive film, the first insulating film, and the second conductive film into an island shape to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer; removing the second conductive layer; forming a fourth insulator, a first oxide, a second oxide, a first oxide layer, a first insulating layer, and a second conductive layer on the fourth insulator; forming ... conductive layer, a first insulating layer, and a second conductive layer on the fourth insulator; forming a first oxide, a second oxide, a first conductive layer, a first insulating layer, and a second conductive layer on the fourth insulator; forming a first oxide, a second oxide, a first conductive layer, a first insulating layer, and a second conductive layer on the first insulator; forming a first oxide A fifth insulator is formed on a conductive layer and a first insulating layer; an opening reaching the second oxide is formed in the first oxide layer, the first conductive layer, the first insulating layer and the fifth insulator; when forming the opening, a third oxide and a fourth oxide are formed from the first oxide layer, a first conductor and a second conductor are formed from the first conductive layer, and a sixth insulator and a seventh insulator are formed from the first insulating layer; a fifth oxide, an eighth insulator on the fifth oxide, and a third conductor on the eighth insulator are formed in the opening; and a ninth insulator is formed on the fifth insulator, the fifth oxide, the eighth insulator and the third conductor, wherein the ninth insulator is formed by a bias sputtering method.

[0017] In the above-described method for manufacturing a semiconductor device, the first to third insulators are preferably formed continuously under reduced pressure using an apparatus including a plurality of processing chambers.

[0018] In the above method for manufacturing a semiconductor device, the first to third oxide films are preferably formed continuously under reduced pressure using an apparatus including a plurality of processing chambers.

[0019] In the above method for manufacturing a semiconductor device, the first conductive film, the first insulating film, and the second conductive film are preferably formed continuously under reduced pressure using an apparatus including a plurality of processing chambers.

[0020] In the above method for manufacturing a semiconductor device, the first to third insulators, the first to third oxide films, the first conductive film, the first insulating film, the second conductive film, and the fifth oxide are preferably formed by sputtering.

[0021] Effects of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device with less uneven transistor characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the aforementioned effects. Furthermore, effects other than these effects are naturally apparent from the description of the specification, drawings, claims, and the like, and effects other than these effects can be inferred from the description of the specification, drawings, claims, and the like.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A This is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1B to 1D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0026] Figure 2A A diagram illustrating the classification of IGZO crystal structures. Figure 2B It is a diagram illustrating the XRD spectrum of quartz glass. Figure 2C This is a diagram illustrating the XRD spectrum of crystalline IGZO. Figure 2D It is a diagram illustrating the nanobeam electron diffraction pattern of crystalline IGZO.

[0027] Figure 3A This is a top view of a semiconductor device according to one embodiment of the present invention. Figures 3B to 3D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0028] Figure 4A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 4B to 4D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0029] Figure 5A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 5B to 5D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] Figure 6A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 6B to 6D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0031] Figure 7A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 7B to 7D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] Figure 8A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 8B to 8D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] Figure 9A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 9B to 9D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] Figure 10A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10B to FIG. 10D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0035] Figure 11A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 11B to 11D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0036] Figure 12A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 12B to 12D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0037] Figure 13AIt is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 13B to 13D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0038] Figure 14A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 14B to 14D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0039] Figure 15A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 15B to 15D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0040] Figure 16A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 16B to 16D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0041] Figure 17A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 17B to 17D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0042] Figure 18A It is a plan view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 18B to 18D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0043] Figure 19A This is a top view of a semiconductor device according to one embodiment of the present invention. Figures 19B to 19D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0044] Figure 20A This is a top view of a semiconductor device according to one embodiment of the present invention. FIG. 20B to FIG. 20D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0045] Figure 21A and Figure 21B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0046] Figure 22 is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0047] Figure 23 is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0048] Figure 24 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0049] Figure 25A and Figure 25B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0050] Figure 26 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0051] Figure 27 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0052] Figure 28 It is a top view illustrating an apparatus for manufacturing a semiconductor device according to one embodiment of the present invention.

[0053] Figure 29A This is a block diagram showing a configuration example of a storage device according to one embodiment of the present invention. Figure 29B This is a perspective view of a storage device according to one embodiment of the present invention.

[0054] Figures 30A to 30H is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.

[0055] Figure 31 This diagram shows various storage devices in a hierarchical manner.

[0056] Figure 32A and Figure 32B FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention.

[0057] Figure 33A and Figure 33B This is a diagram illustrating an example of an electronic component.

[0058] Figures 34A to 34E is a schematic diagram of a storage device according to one embodiment of the present invention.

[0059] Figures 35A to 35H FIG. 1 is a diagram illustrating an electronic device according to one embodiment of the present invention.

[0060] Figure 36A is a schematic diagram of a sample according to an embodiment. Figure 36B is a graph showing TDS analysis results according to the embodiment.

[0061] Modes for Carrying Out the Invention

[0062] The following describes the embodiments with reference to the accompanying drawings. It should be noted that those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the embodiments described below.

[0063] In the drawings, the size, thickness of a layer, or an area are sometimes exaggerated for obvious reasons. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in the drawings, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a special reference numeral.

[0064] In addition, in particular, in top views (also called plan views) or perspective views, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0065] In addition, in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these numbers do not indicate the order of the steps or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to provide a more detailed description. Furthermore, the ordinal numbers used in this specification and other documents may not match the ordinal numbers used to designate one embodiment of the present invention.

[0066] For convenience, terms such as "upper" and "lower" are used in this specification and other descriptions to describe the positional relationships of components with reference to the accompanying drawings. The positional relationships of the components may vary depending on the orientation in which they are described. Therefore, the terms are not limited to those described in this specification and may be substituted as appropriate depending on the situation.

[0067] For example, in this specification, when it is explicitly stated that "X is connected to Y," this means that: X is electrically connected to Y; X is functionally connected to Y; or X is directly connected to Y. Therefore, connection relationships are not limited to those shown in the drawings or text, and connection relationships other than those shown in the drawings or text are disclosed in the drawings or text. Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0068] In this specification, etc., a transistor refers to a component that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) where a channel is formed. Current can flow between the source and drain through the channel formation region. Note that in this specification, etc., the channel formation region refers to the region where current primarily flows.

[0069] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, etc., the source and drain may be interchanged.

[0070] Note that the channel length refers to, for example, the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap each other in a top view of the transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. In addition, in a transistor, the channel length does not necessarily have the same value in all regions. In other words, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the channel formation region.

[0071] The channel width refers to, for example, the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap in a top view of the transistor, or the length in a direction perpendicular to the channel length direction. In addition, in a transistor, the channel width does not necessarily have the same value in all areas. In other words, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width is any value, maximum value, minimum value, or average value in the channel formation area.

[0072] In this specification, etc., depending on the structure of the transistor, the actual channel width in the region where the channel is formed (hereinafter also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width") may differ. For example, when the gate electrode covers the side of the semiconductor, the effective channel width may be larger than the apparent channel width, and its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, the proportion of the channel formation region formed on the side of the semiconductor may increase. In this case, the effective channel width is larger than the apparent channel width.

[0073] In these situations, it's sometimes difficult to estimate the effective channel width through actual measurement. For example, estimating the effective channel width from the design value requires an assumption: the semiconductor's shape is known. Therefore, accurately measuring the effective channel width is difficult when the semiconductor's shape is uncertain.

[0074] In this specification, when simply referring to "channel width," this may refer to the apparent channel width. Alternatively, when simply referring to "channel width," this may refer to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing cross-sectional TEM images, etc.

[0075] Note that the impurities of a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When impurities are included, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water is sometimes used as an impurity. In addition, for example, when impurities are mixed in, oxygen vacancies (sometimes called V O :oxygen vacancy).

[0076] Note that in this specification and other documents, silicon oxynitride refers to a substance containing more oxygen than nitrogen. Also, silicon nitride oxide refers to a substance containing more nitrogen than oxygen.

[0077] Note that in this specification and other documents, an "insulator" may also be referred to as an "insulating film" or "insulating layer." Furthermore, a "conductor" may also be referred to as a "conductive film" or "conductive layer." Furthermore, a "semiconductor" may also be referred to as a "semiconductor film" or "semiconductor layer."

[0078] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0079] In this specification, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are divided into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS). For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when referred to as an OS transistor, this means a transistor containing a metal oxide or an oxide semiconductor.

[0080] Note that in this specification and other documents, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per channel width of 1 μm is 1×10 -20 Below A, at 85℃, it is 1×10 -18 A or less, or 1×10 -16 A or below.

[0081] (Implementation 1)

[0082] In this embodiment, the Figures 1A to 21B An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention and a method for manufacturing the same will be described.

[0083] <Structural Example 1 of Semiconductor Device>

[0084] use Figures 1A to 1D The structure of a semiconductor device including the transistor 200 will be described. Figures 1A to 1D 2 are a top view and a cross-sectional view of a semiconductor device including the transistor 200 . Figure 1A : is a top view of the semiconductor device. Figures 1B to 1D is a cross-sectional view of the semiconductor device. Figure 1B It is along Figure 1A The cross-sectional view taken along the dot-dash line A1 - A2 in FIG. 1 is equivalent to a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C It is along Figure 1A The cross-sectional view taken along the dashed line A3 - A4 in FIG. 1 is equivalent to a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is Figure 1A A cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. Figure 1A In the top view, some components are omitted for clarity.

[0085] A semiconductor device according to one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on insulator 212, a transistor 200 on insulator 214, an insulator 280 on transistor 200, an insulator 282 on insulator 280, and an insulator 283 on insulator 282. Insulators 212, 214, 280, 282, and 283 serve as interlayer films. Furthermore, the semiconductor device includes a conductor 240 (conductors 240a and 240b) electrically connected to a conductor 242 (conductors 242a and 242b) included in transistor 200 and serving as a plug. Furthermore, the semiconductor device includes an insulator 241 (insulators 241a and 241b) in contact with the side surface of conductor 240 serving as a plug. Furthermore, conductors 246 (conductors 246a and 246b) are provided on the insulator 283 and the conductor 240. The conductors 246 are electrically connected to the conductor 240 and serve as wiring.

[0086] Insulator 241a is disposed so as to contact the inner walls of the openings of insulators 280, 282, 283, and insulators 271a and 272 included in transistor 200. A first conductor of conductor 240a is disposed so as to contact the side surfaces of insulator 241a, and a second conductor of conductor 240a is disposed inside the first conductor. Furthermore, insulator 241b is disposed so as to contact the inner walls of the openings of insulators 271b, 272, 280, 282, and 283. A first conductor of conductor 240b is disposed so as to contact the side surfaces of insulator 241b, and a second conductor of conductor 240b is disposed inside the first conductor. Here, the height of the top surface of conductor 240 can be substantially aligned with the height of the top surface of insulator 283 in the region overlapping with conductor 246. In transistor 200, a first conductor 240 and a second conductor 240 are stacked, but the present invention is not limited to this. For example, conductor 240 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, when a structure has a stacked structure, it is sometimes numbered according to the order in which it was formed to distinguish between them.

[0087] [Transistor 200]

[0088] like Figures 1A to 1DAs shown, transistor 200 includes: an insulator 216 on an insulator 214; a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in insulator 214 or insulator 216; an insulator 222 on insulator 216 and on conductor 205; an insulator 224 on insulator 222; an oxide 230a on insulator 224; an oxide 230b on oxide 230a; an oxide 243 (oxide 243a and oxide 243b) and an oxide 230c on oxide 230b; a conductor 242a on oxide 243a; an insulator 271a on conductor 242a; and an oxide 243b on oxide 243b. Conductor 242b; insulator 271b on conductor 242b; oxide 230d on oxide 230c; insulator 250 on oxide 230d; conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with a portion of oxide 230c; and insulator 272 in contact with a portion of insulator 224, the side of oxide 230a, the side of oxide 230b, the side of oxide 243a, the side of conductor 242a, the side of insulator 271a, the top surface of insulator 271a, the side of insulator 271b and the side of conductor 242b. In addition, the oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, the side surface of the conductor 242b, the side surface of the insulator 271a, the side surface of the insulator 271b, and the side surface of the insulator 272. Figure 1B and Figure 1C As shown, the top surface of conductor 260 is substantially aligned with the top surfaces of insulator 250, oxide 230d, and oxide 230c. Insulator 282 is in contact with the top surfaces of conductor 260, insulator 250, oxide 230d, oxide 230c, and insulator 280.

[0089] Hereinafter, the insulator 271 a and the insulator 271 b may be collectively referred to as the insulator 271 .

[0090] An opening is provided in insulator 280 that reaches oxide 230b. Oxide 230d, oxide 230c, insulator 250, and conductor 260 are arranged within this opening. Furthermore, in the channel length direction of transistor 200, conductor 260, insulator 250, oxide 230d, and oxide 230c are provided between conductor 242a and oxide 243a, and conductor 242b and oxide 243b. Insulator 250 has a region in contact with the side surfaces of conductor 260 and a region in contact with the bottom surface of conductor 260. Furthermore, within the region overlapping with oxide 230b, oxide 230c has a region in contact with oxide 230b, a region overlapping with the side surfaces of conductor 260 via oxide 230d and insulator 250, and a region overlapping with the bottom surface of conductor 260 via oxide 230d and insulator 250.

[0091] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c disposed on the oxide 230b and at least partially in contact with the oxide 230b, and an oxide 230d disposed on the oxide 230c. Providing the oxide 230a below the oxide 230b can suppress the diffusion of impurities from structures formed below the oxide 230a into the oxide 230b. Furthermore, providing the oxide 230d above the oxide 230c can suppress the diffusion of impurities from structures formed above the oxide 230d into the oxide 230c.

[0092] Note that in transistor 200, oxide 230 has a four-layer stacked structure of oxide 230a, oxide 230b, oxide 230c, and oxide 230d, but the present invention is not limited thereto. For example, oxide 230b may be a single layer, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, a three-layer structure of oxide 230a, oxide 230b, and oxide 230c, or a stacked structure of five or more layers. Oxide 230a, oxide 230b, oxide 230c, and oxide 230d may each have a stacked structure.

[0093] Conductor 260 serves as a first gate (also called a top gate) electrode, and conductor 205 serves as a second gate (also called a back gate) electrode. Furthermore, insulator 250 serves as a first gate insulator, and insulator 224 serves as a second gate insulator. Conductor 242a serves as one of a source and a drain, and conductor 242b serves as the other. Furthermore, at least a portion of the region of oxide 230 that overlaps conductor 260 serves as a channel formation region.

[0094] In the transistor 200 , a metal oxide that can function as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide 230 (the oxide 230 a , the oxide 230 b , the oxide 230 c , and the oxide 230 d ) including the channel formation region.

[0095] Furthermore, the band gap of the metal oxide that can be used as a semiconductor is 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.

[0096] As the oxide 230, for example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as the oxide 230.

[0097] Here, it is preferable that the atomic number ratio of In to the element M in the metal oxide used for the oxide 230 b or the oxide 230 c is greater than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230 a or the oxide 230 d .

[0098] In this manner, by disposing the oxide 230 a below the oxide 230 b or the oxide 230 c , it is possible to suppress diffusion of impurities and oxygen from the structure formed below the oxide 230 a into the oxide 230 b or the oxide 230 c .

[0099] Furthermore, by disposing oxide 230d on oxide 230b or oxide 230c, diffusion of impurities from a structure formed above oxide 230d into oxide 230b or oxide 230c can be suppressed. Furthermore, by disposing oxide 230d on oxide 230b or oxide 230c, upward diffusion of oxygen from oxide 230b or oxide 230c can be suppressed.

[0100] Furthermore, since oxides 230a to 230d contain a common element (as a main component) in addition to oxygen, the defect state density at each interface of oxides 230a, 230b, 230c, and 230d can be reduced. In this case, the main carrier path is through oxides 230b and 230c, or their vicinity, such as the interface between oxides 230b and 230c. Since the defect state density at the interface between oxides 230b and 230c can be reduced, the effect of interface scattering on carrier conduction is minimized, resulting in a high on-state current.

[0101] The oxide 230 b and the oxide 230 c are preferably both crystalline. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide 230 b and the oxide 230 c. The oxide 230 d may also be crystalline.

[0102] CAAC-OS has c-axis orientation, with multiple nanocrystals linked in the ab plane, but with a distorted crystal structure. Distortion refers to the difference in lattice alignment between regions where multiple nanocrystals are linked and other regions where the lattice alignment is consistent.

[0103] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and are sometimes non-regular hexagons. In addition, nanocrystals sometimes have lattice arrangements such as pentagons or heptagons in distortion. In addition, in CAAC-OS, it is difficult to observe clear grain boundaries even near the distortion. In other words, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bond distance between atoms due to the substitution of metal elements.

[0104] Note that a crystal structure with clear grain boundaries is called a polycrystal. Grain boundaries are mainly for recombination, and the possibility of carriers being trapped and the on-state current of the transistor decreasing or the field effect mobility decreasing increases. Therefore, CAAC-OS, in which no clear grain boundaries are observed, is a type of crystalline oxide having an appropriate crystal structure in the semiconductor layer of the transistor. In order to form CAAC-OS, a structure containing Zn is preferably adopted. For example, In-Zn oxide and In-Ga-Zn oxide suppress the occurrence of junctions compared to In oxide, so they are preferred.

[0105] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be expressed as an (In, M) layer.

[0106] As described above, CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (such as oxygen vacancies Vo). In particular, by heat-treating the metal oxide after formation at a temperature at which the metal oxide does not undergo polycrystallization (for example, between 400°C and 600°C), CAAC-OS can be given a dense structure with even higher crystallinity. By further increasing the density of CAAC-OS, the diffusion of impurities and oxygen in the CAAC-OS can be further reduced.

[0107] On the other hand, CAAC-OS doesn't easily reveal distinct grain boundaries, making it less likely to cause a drop in electron mobility due to these boundaries. Consequently, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS exhibit heat resistance and high reliability.

[0108] Furthermore, when viewed in a cross-section along the channel length of the transistor, it is preferred that oxide 230b be provided with a groove and oxide 230c be embedded in the groove. In this case, oxide 230c is disposed so as to cover the inner walls (sidewalls and bottom) of the groove. Furthermore, the film thickness of oxide 230c is preferably substantially the same as the depth of the groove.

[0109] With this structure, even if a damaged region is formed on the surface of the oxide 230b corresponding to the bottom of the opening when forming the opening for embedding the conductor 260, the damaged region can be removed. This can suppress electrical characteristic defects of the transistor 200 caused by the damaged region.

[0110] In FIG. 1 and other figures, the side surfaces of the opening (including the groove portion of the oxide 230 b ) in which the conductor 260 is embedded are substantially perpendicular to the surface on which the oxide 230 b is formed, but this embodiment is not limited thereto. For example, the bottom of the opening may be a U-shaped shape with a gently curved surface. In addition, for example, the side surfaces of the opening may be inclined relative to the surface on which the oxide 230 b is formed.

[0111] In addition, if Figure 1C As shown, a curved surface may exist between the side surface and the top surface of the oxide 230b when viewed from a cross section of the channel width of the transistor 200. That is, the ends of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0112] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230 b in the region overlapping with the conductor 242 or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the groove portion of the insulator 250 and the conductor 260 formed in the subsequent process can be improved. In addition, the length of the region without the curved surface can be prevented from being reduced, thereby suppressing the decrease in the on-state current and mobility of the transistor 200. Thus, a semiconductor device with good electrical characteristics can be provided.

[0113] The oxide 230 preferably has a stacked structure of multiple oxide layers having different chemical compositions. Specifically, the atomic ratio of the element M in the metal oxide used for oxide 230a relative to the main component metal element is preferably greater than the atomic ratio of the element M in the metal oxide used for oxide 230b relative to the main component metal element. Furthermore, the atomic ratio of the element M in the metal oxide used for oxide 230a relative to In is preferably greater than the atomic ratio of the element M in the metal oxide used for oxide 230b relative to In. Furthermore, the atomic ratio of the element M in the metal oxide used for oxide 230b relative to In is preferably greater than the atomic ratio of the element M in the metal oxide used for oxide 230a relative to In.

[0114] Note that in order for oxide 230c to become the primary path for carriers, it is preferable that the atomic ratio of indium to the primary metal element in oxide 230c is greater than the atomic ratio of indium to the primary metal element in oxide 230b. Using a metal oxide with a high indium content in the channel formation region can increase the on-state current of the transistor. Therefore, by making the atomic ratio of indium to the primary metal element in oxide 230c greater than the atomic ratio of indium to the primary metal element in oxide 230b, oxide 230c can become the primary path for carriers.

[0115] Furthermore, the conduction band bottom of oxide 230c is preferably further from the vacuum level than the conduction band bottoms of oxides 230a and 230b. In other words, the electron affinity of oxide 230c is preferably greater than that of oxides 230a and 230b. In this case, the primary carrier path is through oxide 230c.

[0116] One parameter used to evaluate transistor reliability is the drift voltage (Vsh), measured during a transistor's +GBT (Gate Bias Temperature) stress test. The drift voltage (Vsh) is defined as the point where the tangent to the transistor's drain current (Id) - gate voltage (Vg) curve, at the steepest point on the curve, intersects the line at Id = 1pA. The change in Vsh is represented by ΔVsh.

[0117] During a +GBT stress test on a transistor, ΔVsh may drift in the negative direction over time. Furthermore, ΔVsh may fluctuate in both the negative and positive directions, but not in the negative direction. Note that in this specification and other documents, this behavior is sometimes referred to as a sawtooth-like behavior of ΔVsh during a +GBT stress test.

[0118] By using a metal oxide that does not contain the element M as a main component or a metal oxide with a small proportion of the element M as the oxide 230 c , for example, ΔVsh can be reduced, a sawtooth behavior of ΔVsh can be suppressed, and transistor reliability can be improved.

[0119] Furthermore, oxide 230b and oxide 230c are preferably crystalline oxides such as CAAC-OS. Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity and few impurities and defects (such as oxygen vacancies). Therefore, oxygen extraction from oxide 230b by the source or drain electrode can be suppressed. Therefore, even during heat treatment, oxygen extraction from oxide 230b can be reduced, and transistor 200 is therefore stable against the high temperatures (so-called thermal budget) encountered during the manufacturing process.

[0120] In addition, CAAC-OS is preferably used as oxide 230c, and the c-axis of the crystals contained in oxide 230c is preferably oriented substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in oxide 230c can be efficiently supplied to oxide 230b.

[0121] The oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230c, and more preferably contains all of the metal elements. For example, it is preferable to use In-M-Zn oxide, In-Zn oxide, or indium oxide as the oxide 230c, and to use In-M-Zn oxide, M-Zn oxide, or an oxide of element M as the oxide 230d. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0122] It is preferred that the conduction band bottom of oxide 230d be closer to the vacuum level than the conduction band bottom of oxide 230c. In other words, the electron affinity of oxide 230d is preferably lower than that of oxide 230c. In this case, a metal oxide that can be used for oxide 230a or oxide 230b is preferably used as oxide 230d. In this case, the main path for carriers is through oxide 230c.

[0123] Furthermore, oxide 230d is preferably a metal oxide that suppresses oxygen diffusion or permeation more than oxide 230c. Providing oxide 230d between insulator 250 and oxide 230c prevents oxygen contained in insulator 280 from diffusing into insulator 250. Thus, oxygen can be efficiently supplied to oxide 230b via oxide 230c.

[0124] Furthermore, when the atomic ratio of In relative to the main metal element in the metal oxide used for oxide 230d is smaller than the atomic ratio of In relative to the main metal element in the metal oxide used for oxide 230c, diffusion of In toward insulator 250 can be suppressed. Since insulator 250 serves as a gate insulator, ingress of In into insulator 250, for example, can lead to poor transistor characteristics. Therefore, by providing oxide 230d between oxide 230c and insulator 250, a highly reliable semiconductor device can be provided.

[0125] Here, the conduction band bottom changes smoothly at the junction of oxide 230a, oxide 230b, oxide 230c, and oxide 230d. In other words, the above situation can also be expressed as the conduction band bottom of the junction of oxide 230a, oxide 230b, oxide 230c, and oxide 230d changing continuously or continuously joining. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 230a and oxide 230b, the interface between oxide 230b and oxide 230c, and the interface between oxide 230c and oxide 230d.

[0126] Specifically, by having oxide 230a and oxide 230b, oxide 230b and oxide 230c, and oxide 230c and oxide 230d contain a common element as a main component in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when oxide 230b is an In-M-Zn oxide, oxide 230a, oxide 230c, and oxide 230d may also be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0127] Specifically, as oxide 230a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto, can be used. Furthermore, as oxide 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto, or an indium oxide can be used as oxide 230c. Note that the composition close thereto falls within a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M. In addition, as the oxide 230d, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, a composition of M:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of element M can be used.

[0128] When forming a metal oxide by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide, but may be the atomic ratio of a sputtering target used for forming the metal oxide.

[0129] By employing the above structure as oxide 230a, oxide 230b, oxide 230c, and oxide 230d, the defect state density at the interface between oxide 230a and oxide 230b, the interface between oxide 230b and oxide 230c, and the interface between oxide 230c and oxide 230d can be reduced. Consequently, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can achieve high on-state current and high frequency characteristics.

[0130] Note that the oxide 230c may be provided in each transistor 200. In other words, the oxide 230c of the transistor 200 may not be in contact with the oxide 230c of the transistor 200 adjacent to the transistor 200. Alternatively, the oxide 230c of the transistor 200 may be separated from the oxide 230c of the transistor 200 adjacent to the transistor 200. In other words, the oxide 230c may not be provided between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0131] When a semiconductor device having the above structure includes multiple transistors 200 arranged in the channel width direction, oxide 230c is independently provided in each transistor 200. Therefore, the generation of parasitic transistors between a transistor 200 and an adjacent transistor 200 can be suppressed, thereby suppressing the generation of the aforementioned leakage path. Consequently, a semiconductor device having excellent electrical characteristics and capable of miniaturization or high integration can be provided.

[0132] For example, when the distance between the side edge of the oxide 230c of the transistor 200 and the side edge of the oxide 230c of the transistor 200 adjacent to the transistor 200, which are opposite to each other in the channel width direction of the transistor 200, is represented by L1, L1 is set to be greater than 0 nm. In addition, when the distance between the side edge of the oxide 230a of the transistor 200 and the side edge of the oxide 230a of the transistor 200 adjacent to the transistor 200, which are opposite to each other in the channel width direction of the transistor 200, is represented by L2, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably greater than 0.1 and less than 0.9, and even more preferably greater than 0.2 and less than 0.8. Alternatively, L2 may be the distance between the side edge of the oxide 230b of the transistor 200 and the side edge of the oxide 230b of the transistor 200 adjacent to the transistor 200.

[0133] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs in a region where the oxide 230c is not provided between the transistor 200 and the transistor 200 adjacent to the transistor 200, the oxide 230c of the transistor 200 and the oxide 230c of the transistor 200 adjacent to the transistor 200 can be separated.

[0134] In addition, by increasing the ratio of L1 to L2 (L1 / L2), the minimum processing dimension width can be ensured even if the interval between the transistor 200 and the transistor 200 adjacent to the transistor 200 is reduced, thereby further miniaturizing or highly integrating the semiconductor device.

[0135] Note that the conductor 260 and the insulator 250 are both shared between adjacent transistors 200. In other words, the conductor 260 of the transistor 200 has a region where it is continuously provided with the conductor 260 of the transistor 200 adjacent to the transistor 200. Furthermore, the insulator 250 of the transistor 200 has a region where it is continuously provided with the insulator 250 of the transistor 200 adjacent to the transistor 200.

[0136] Furthermore, with the above structure, oxide 230d has a region contacting insulator 224 between transistor 200 and an adjacent transistor 200. Oxides 230c and 230d of transistor 200 can also be separated from oxides 230c and 230d of adjacent transistors 200.

[0137] Insulators 212, 214, 271, 272, 282, 283, and 286 are preferably used as blocking insulating films that inhibit the diffusion of impurities such as water and hydrogen from the substrate side or from above transistor 200 into transistor 200. Therefore, insulating materials that inhibit the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (such as copper atoms) are preferably used for insulators 212, 214, 271, 272, 282, 283, and 286 (such as copper atoms) are preferably used. Furthermore, insulating materials that inhibit the diffusion of oxygen (such as oxygen atoms or oxygen molecules) are preferably used (such as oxygen atoms or oxygen molecules).

[0138] In this specification, a barrier insulating film refers to an insulating film having barrier properties. Note that in this specification, barrier properties refer to the ability to suppress the diffusion of the corresponding substance (also referred to as low permeability). Alternatively, barrier properties refer to the ability to capture or immobilize the corresponding substance (also known as gettering).

[0139] For example, it is preferable to use silicon nitride or the like as the insulator 212, the insulator 283, and the insulator 286, and to use aluminum oxide or the like as the insulator 214, the insulator 271, the insulator 272, and the insulator 282. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Alternatively, it can suppress the diffusion of oxygen in the insulator 224 or the like through the insulator 212 and the insulator 214 to the substrate side. Furthermore, it can suppress the diffusion of impurities such as water and hydrogen from the insulator 280, the conductor 246, and the like to the oxide 230. Thus, it is preferable to adopt a structure in which the transistor 200 is surrounded by the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, and the insulator 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0140] In addition, it is sometimes preferable to reduce the resistivity of the insulator 212, the insulator 283, and the insulator 286. For example, by reducing the resistivity of the insulator 212, the insulator 283, and the insulator 286 to approximately 1×10 13Ωcm. In a process using plasma or the like in a semiconductor device manufacturing process, the insulators 212, 283, and 286 may sometimes alleviate charge accumulation on the conductors 205, 242, 260, or 246. The resistivity of the insulators 212, 283, and 286 is 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0141] Furthermore, the dielectric constant of insulator 216 and insulator 280 is preferably lower than that of insulator 214. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance generated between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide having pores can be suitably used as insulator 216 and insulator 280.

[0142] In addition, the insulator 212, the insulator 214, and the insulator 216 are preferably formed by sputtering. The hydrogen concentration in the film of the insulator 212, the insulator 214, and the insulator 216 formed by sputtering is low, so it is preferred. In addition, the insulator 212, the insulator 214, and the insulator 216 are preferably formed continuously in a manner not exposed to the atmospheric environment. By forming in a manner not exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the insulator 212, the insulator 214, and the insulator 216, thereby keeping the interface between the insulator 212 and the insulator 214 and the interface vicinity, and the interface between the insulator 214 and the insulator 216 and the interface vicinity clean, so it is preferred. An apparatus capable of continuously forming a film will be described later.

[0143] Conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without interlocking it with the potential supplied to conductor 260. In particular, by supplying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, when a negative potential is applied to conductor 205, the drain current when the potential supplied to conductor 260 is 0V can be reduced compared to when no negative potential is applied to conductor 205.

[0144] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided so as to be buried in the insulator 214 or the insulator 216.

[0145] In addition, if Figure 1AAs shown in FIG. 1 , the conductor 205 is preferably larger than the region of the oxide 230a and the oxide 230b that does not overlap with the conductor 242a and the conductor 242b. Figure 1C As shown, conductor 205 preferably extends to the area outside the side surfaces of oxide 230a and oxide 230b in the channel width direction. That is, conductor 205 and conductor 260 preferably overlap with an insulator outside the side surfaces of oxide 230a and oxide 230b in the channel width direction. With this structure, the channel formation region of oxide 230 can be electrically surrounded by the electric field of conductor 260, which serves as the first gate electrode, and the electric field of conductor 205, which serves as the second gate electrode. In this specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0146] In this specification, etc., an S-channel transistor refers to a transistor structure in which the channel formation region is surrounded by an electric field generated by one of a pair of gate electrodes and the other. Furthermore, the S-channel structure disclosed in this specification, etc., is different from a fin-type structure and a planar structure. By adopting an S-channel structure, a transistor with improved resistance to short-channel effects can be realized; in other words, a transistor that is less susceptible to short-channel effects can be realized.

[0147] In addition, if Figure 1C As shown, the conductor 205 is extended to serve as wiring. However, the present invention is not limited to this, and a conductor serving as wiring may be provided under the conductor 205. Furthermore, a conductor 205 need not necessarily be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0148] In transistor 200, conductor 205 includes conductor 205a and conductor 205b stacked together, but the present invention is not limited to this. For example, conductor 205 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, when a structure has a stacked structure, it is sometimes numbered according to the order in which it was formed to distinguish between them.

[0149] Here, as the conductor 205a, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0150] By using a conductive material that inhibits oxygen diffusion as the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and thus having a reduced conductivity. As conductive materials that inhibit oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Thus, the conductor 205a can be a single layer or a stack of these conductive materials. For example, the conductor 205a can have a stacked structure of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.

[0151] As the conductor 205b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. In the drawings, the conductor 205b has a single-layer structure, but may also have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive materials may be used.

[0152] Insulator 222 and insulator 224 serve as gate insulators.

[0153] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, compared to the insulator 224, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0154] The insulator 222 preferably uses an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When such a material is used to form the insulator 222, the insulator 222 serves as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inner side of the transistor 200, and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with oxygen contained in the insulator 224 or the oxide 230.

[0155] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0156] Furthermore, as the insulator 222, an insulator comprising a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) may be used in a single layer or a stacked layer. As transistors are miniaturized and highly integrated, problems such as leakage current may occur due to thinning of the gate insulator. Using a high-k material as the insulator used as the gate insulator allows the gate potential during transistor operation to be reduced while maintaining the physical thickness.

[0157] Here, oxygen is preferably removed from the insulator 224 in contact with the oxide 230 by heating. For example, silicon oxide, silicon oxynitride, or the like can be appropriately used as the insulator 224. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0158] Specifically, an oxide material from which some oxygen is released by heating, i.e., an insulating material having an excess oxygen region, is preferably used as the insulator 224. An oxide from which oxygen is released by heating means that the amount of oxygen molecules released by TDS (Thermal Desorption Spectroscopy) is 1.0×10 18 molecules / cm 3 above, preferably 1.0×10 19 molecules / cm 3 More than 2.0×10 19 molecules / cm 3 Above, or 3.0×10 20 molecules / cm 3 The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0159] Alternatively, the insulator having the excess oxygen region and the oxide 230 may be subjected to any one or more of heat treatment, microwave treatment, and RF treatment in a manner that the insulator and the oxide 230 are in contact with each other. By performing such treatment, water or hydrogen in the oxide 230 may be removed. For example, defects (V O H) is broken, in other words, "V O H→V O+H" reaction to achieve dehydrogenation. A portion of the hydrogen generated here is sometimes bonded to oxygen and removed from the oxide 230 or the insulator near the oxide 230 as H2O. In addition, a portion of the hydrogen is sometimes diffused into the conductor 242 or captured by the conductor 242 (also called doping).

[0160] In addition, the above-mentioned microwave treatment preferably uses, for example, a device that generates power for high-density plasma or a device that applies RF power to one side of the substrate. For example, by using a gas containing oxygen and using high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or the insulator near the oxide 230. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the device for performing the microwave treatment, oxygen and argon are used, for example, and the microwave treatment is performed under the condition that the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0161] In addition, in the manufacturing process of the transistor 200, the heat treatment is preferably performed in a state where the surface of the oxide 230 is exposed. The heat treatment is preferably performed at a temperature of, for example, 100°C or higher and 600°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen is supplied to the oxide 230, thereby reducing oxygen vacancies (V O ). The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed under a nitrogen or inert gas atmosphere, and then, in order to replace the oxygen that has been released, the heat treatment may be performed under an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed under an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more, and then, the heat treatment may be continuously performed under a nitrogen or inert gas atmosphere.

[0162] By performing an oxidation treatment on the oxide 230, the supplied oxygen can fill the oxygen vacancies in the oxide 230, in other words, it can promote the "V O +O→null". Furthermore, when the supplied oxygen reacts with the hydrogen remaining in the oxide 230, the hydrogen can be removed as H2O. Thus, the hydrogen remaining in the oxide 230 can be inhibited from recombination with the oxygen vacancies to form V O H.

[0163] Furthermore, the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material, and may be a stacked structure made of different materials.

[0164] The oxide 243 (the oxide 243 a and the oxide 243 b ) may also be provided on the oxide 230 b .

[0165] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of inhibiting oxygen permeation. By disposing the oxide 243, which has a function of inhibiting oxygen permeation, between the conductor 242, which serves as a source electrode or a drain electrode, and the oxide 230b, the resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. By adopting such a structure, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. Alternatively, if the resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0166] A metal oxide containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin is preferably used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Gallium oxide can also be used as oxide 243. In addition, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the atomic ratio of element M relative to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M relative to In in the metal oxide used for oxide 230b. In addition, the thickness of oxide 243 is preferably greater than 0.5 nm and less than 5 nm, more preferably greater than 1 nm and less than 3 nm, and even more preferably greater than 1 nm and less than 2 nm. In addition, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen in oxide 230 can be effectively suppressed. For example, when oxide 243 has a crystalline structure such as hexagonal, the release of oxygen in oxide 230 can sometimes be suppressed.

[0167] Note that the oxide films to be formed as oxide 230a, the oxide films to be formed as oxide 230b, and the oxide films to be formed as oxide 243 are preferably formed continuously without being exposed to the atmosphere. Forming the oxide films without being exposed to the atmosphere prevents impurities or moisture in the atmosphere from adhering to the oxide films to be formed as oxide 230a, the oxide films to be formed as oxide 230b, and the oxide films to be formed as oxide 243. This makes it possible to maintain cleanliness of the interface between the oxide films to be formed as oxide 230a and the oxide films to be formed as oxide 230b, and of the interface between the oxide films to be formed as oxide 230b and the oxide films to be formed as oxide 243, and of the interface between the oxide films to be formed as oxide 230b and the oxide films to be formed as oxide 243. An apparatus capable of continuous film formation will be described later.

[0168] The conductor 242a is provided on the oxide 243a, and the conductor 242b is provided on the oxide 243b. The conductor 242a and the conductor 242b serve as a source electrode and a drain electrode of the transistor 200, respectively.

[0169] As the conductor 242 (conductor 242a and conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferably used. In addition, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0170] When oxide 243 is not provided, conductor 242 is in contact with oxide 230 b or oxide 230 c. Therefore, oxygen in oxide 230 b or oxide 230 c may diffuse into conductor 242, causing conductor 242 to be oxidized. When conductor 242 is oxidized, the conductivity of conductor 242 is likely to decrease. Note that the diffusion of oxygen from oxide 230 b or oxide 230 c into conductor 242 can also be referred to as "conductor 242 absorbing oxygen from oxide 230 b or oxide 230 c."

[0171] In addition, when oxygen in oxide 230b or oxide 230c diffuses into conductors 242a and 242b, a layer may be formed between conductor 242a and oxide 230b, between conductor 242b and oxide 230b, or between conductor 242a and oxide 230c, or between conductor 242b and oxide 230c. Since this layer has a higher oxygen content than conductor 242a or conductor 242b, it is estimated to have insulating properties. In this case, the three-layer structure of conductor 242a or conductor 242b, this layer, and oxide 230b or oxide 230c can be regarded as a three-layer structure composed of metal-insulator-semiconductor, or as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0172] Note that hydrogen contained in oxides 230 b, 230 c, and the like may diffuse into conductors 242 a and 242 b. In particular, by using tantalum nitride as conductors 242 a and 242 b, hydrogen contained in oxides 230 b, 230 c, and the like may easily diffuse into conductors 242 a and 242 b, and this diffused hydrogen may bond with nitrogen contained in conductors 242 a and 242 b. In other words, hydrogen contained in oxides 230 b, 230 c, and the like may be absorbed by conductors 242 a and 242 b.

[0173] Furthermore, a curved surface may exist between the side surfaces and the top surface of the conductor 242. In other words, the ends of the side surfaces and the top surface may be curved. For example, the curved surface may have a radius of curvature of 3 nm to 10 nm, more preferably 5 nm to 6 nm, at the end of the conductor 242. The absence of corners at the end improves film coverage during subsequent film formation steps.

[0174] Insulator 272 is provided to cover the sides of oxide 230a, oxide 230b, oxide 243, conductor 242, and insulator 271, and preferably comprises an insulating film having at least oxygen barrier properties. Therefore, insulator 272 preferably has the function of inhibiting oxygen diffusion. For example, insulator 272 preferably has the function of inhibiting oxygen diffusion further than insulator 280. For example, insulator 272 preferably comprises an oxide of one or both of aluminum and hafnium.

[0175] In particular, the insulator 272 is preferably formed by bias sputtering of aluminum oxide or hafnium oxide in an oxygen-containing atmosphere. Bias sputtering is a method in which sputtering is performed while applying RF power to the substrate. By applying RF power to the substrate, the potential of the substrate becomes negative relative to the plasma potential (called the bias potential), and the positive ions in the plasma are accelerated by this bias potential and injected into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate.

[0176] Thus, by forming aluminum oxide or hafnium oxide in an oxygen-containing atmosphere by bias sputtering, oxygen can be implanted into the insulator 224. Furthermore, the amount of oxygen implanted into the insulator 224 can be controlled by adjusting the RF power applied to the substrate, thereby optimizing the amount of oxygen implanted into the insulator 224.

[0177] Insulator 271 is provided in contact with the top surface of conductor 242 and, like insulator 272, comprises an insulating film having at least oxygen barrier properties. Therefore, insulator 271 preferably has the function of inhibiting oxygen diffusion. For example, insulator 271 preferably has the function of inhibiting oxygen diffusion further than insulator 280. Insulator 271 preferably comprises an oxide of one or both of aluminum and hafnium. Alternatively, insulator 271 may comprise silicon nitride, for example.

[0178] By providing the insulators 271 and 272, the oxides 230a, 230b, 243, and the conductor 242 can be isolated from the insulator 280. Therefore, direct diffusion of oxygen from the insulator 280 into the oxides 230a, 230b, 243, and the conductor 242 can be suppressed. This prevents excessive oxygen from being supplied to the source and drain regions of the oxide 230, thereby reducing the carrier concentration in the source and drain regions. Furthermore, excessive oxidation of the conductor 242, which would increase its resistivity, can be prevented, thereby suppressing a reduction in on-state current.

[0179] Insulator 250 serves as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of oxide 230c. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide with pores can be used as insulator 250. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability.

[0180] Insulator 250, like insulator 224, is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as insulator 250 so that it is aligned with the top surface of oxide 230c, oxygen can be effectively supplied to the channel formation region of oxide 230b, thereby reducing oxygen vacancies in the channel formation region of oxide 230b. Consequently, a transistor can be provided that suppresses fluctuations in electrical characteristics, achieves stable electrical characteristics, and improves reliability. As with insulator 224, the concentration of impurities such as water and hydrogen in insulator 250 is preferably reduced. The thickness of insulator 250 is preferably not less than 1 nm and not more than 20 nm.

[0181] Note that in Figure 1B and Figure 1C , the structure of the insulator 250 is shown as a single layer, but it can also be a stacked structure with two or more layers. When the insulator 250 has a two-layer stacked structure, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen by heating, and the upper layer of the insulator 250 is formed using an insulator that has a function of suppressing the diffusion of oxygen. By having the above structure, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductor 260 caused by the oxygen contained in the lower layer of the insulator 250 can be suppressed. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the above-mentioned insulator 250, and the upper layer of the insulator 250 can be formed using the same material as the insulator 222.

[0182] Note that when silicon oxide or silicon oxynitride is used as the lower layer of insulator 250, a high-k material having a high relative dielectric constant can be used as the upper layer of insulator 250. By providing the gate insulator with a stacked structure of the lower layer of insulator 250 and the upper layer of insulator 250, a stacked structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0183] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used for oxide 230 can be used as the upper layer of insulator 250. In particular, an insulator containing one or both oxides of aluminum and hafnium is preferably used.

[0184] Alternatively, a metal oxide may be provided between insulator 250 and conductor 260. This metal oxide preferably inhibits the diffusion of oxygen from insulator 250 to conductor 260. Providing a metal oxide that inhibits oxygen diffusion suppresses oxygen diffusion from insulator 250 to conductor 260. In other words, a decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, oxidation of conductor 260 caused by oxygen contained in insulator 250 can be suppressed.

[0185] Note that the metal oxide preferably functions as part of the first gate electrode. For example, the metal oxide that can be used for oxide 230 can be used as the metal oxide. In this case, by forming conductor 260a by sputtering, the resistivity of the metal oxide can be reduced, making it a conductor. This conductor can be referred to as an OC (Oxide Conductor) electrode.

[0186] By providing the metal oxide, the on-state current of the transistor 200 can be increased without reducing the influence of the electric field from the conductor 260. In addition, by maintaining the distance between the conductor 260 and the oxide 230 by utilizing the physical thickness of the insulator 250 and the metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a stacked structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the intensity of the electric field applied from the conductor 260 to the oxide 230 can be easily adjusted.

[0187] The conductor 260 is used as the first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. Figure 1B and Figure 1C As shown, the top surface of the conductor 260 is substantially consistent with the top surface of the insulator 250 and the top surface of the oxide 230c. Figure 1B and Figure 1C The middle conductor 260 has a two-layer structure of the conductor 260 a and the conductor 260 b , but may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0188] Here, as the conductor 260a, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0189] Furthermore, when the conductor 260a has the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 250. As a conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0190] Since conductor 260 also functions as wiring, it is preferable to use a highly conductive conductor. For example, conductor 260b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and one of the above conductive materials.

[0191] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill the opening formed in the insulator 280. By forming the conductor 260 in this manner, the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without requiring alignment.

[0192] In addition, if Figure 1C As shown, in the channel width direction of transistor 200, the bottom surface of conductor 260 in the region where conductor 260 does not overlap with oxide 230b is preferably lower than the bottom surface of oxide 230b, with reference to the bottom surface of insulator 222. By adopting a structure in which conductor 260, used as a gate electrode, covers the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, it is easy for the electric field of conductor 260 to act on the entire channel formation region of oxide 230b. As a result, the on-state current and frequency characteristics of transistor 200 can be improved. The difference between the bottom surface height of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 and the bottom surface height of oxide 230b, with reference to the bottom surface of insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0193] Insulator 280 is disposed on insulator 224, oxide 230, conductor 242, and insulator 271. In addition, the top surface of insulator 280 may also be planarized.

[0194] The insulator 280 used as the interlayer film preferably has a low dielectric constant. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance generated between wiring lines. Insulator 280 is preferably formed of the same material as insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with pores are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0195] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulator 280. Furthermore, it is preferable that insulator 280 have a low hydrogen concentration and include an oxygen-excess region or contain excess oxygen. For example, insulator 280 can be formed using the same material as insulator 216. Insulator 280 can also have a structure in which the aforementioned materials are stacked. For example, it can have a stacked structure of a silicon oxide film formed by sputtering and a silicon oxynitride film stacked thereon by chemical vapor deposition (CVD). Furthermore, silicon nitride can be further stacked thereon.

[0196] Insulator 282 or insulator 283 is preferably used as a blocking insulating film to inhibit the diffusion of impurities such as water and hydrogen into insulator 280 from above. Insulator 282 or insulator 283 is preferably used as a blocking insulating film to inhibit oxygen permeation. Insulators 282 and 283 can be made of, for example, aluminum oxide, silicon nitride, or silicon oxynitride. For example, aluminum oxide, which has a high barrier property against oxygen, can be used as insulator 282, and silicon nitride, which has a high barrier property against hydrogen, can be used as insulator 283.

[0197] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0198] When a stacked structure is employed as conductor 240, a conductive material that inhibits the permeation of impurities such as water and hydrogen is preferably used as the conductor in contact with insulators 283, 282, 280, and 271. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. A conductive material that inhibits the permeation of impurities such as water and hydrogen can be used as a single layer or as a stacked layer. Furthermore, impurities such as water and hydrogen contained in the layer above insulator 283 can be prevented from entering oxide 230 through conductors 240a and 240b.

[0199] Insulators 241a and 241b can be made of, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Since insulators 241a and 241b are disposed in contact with insulators 272 and 271, impurities such as water and hydrogen contained in insulators 280 and the like can be prevented from entering oxide 230 through conductors 240a and 240b. Silicon nitride is particularly preferred because it has a high barrier property against hydrogen. Furthermore, oxygen contained in insulator 280 can be prevented from being absorbed by conductors 240a and 240b.

[0200] Conductors 246 (conductors 246a and 246b) serving as wiring can be arranged in contact with the top surfaces of conductors 240a and 240b. Conductors 246 preferably use a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, the conductors can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials. Furthermore, the conductors can be formed so as to be embedded in openings in an insulator.

[0201] Insulator 286 is provided on conductor 246 and insulator 283. Thus, the top surface and side surfaces of conductor 246 are in contact with insulator 286, and the bottom surface of conductor 246 is in contact with insulator 283. In other words, conductor 246 can be surrounded by insulator 283 and insulator 286. This structure suppresses oxygen permeation from the outside, preventing oxidation of conductor 246. It also prevents impurities such as water and hydrogen from diffusing from conductor 246, making it preferable.

[0202] <Materials Constituting Semiconductor Devices>

[0203] Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0204] <<Substrate>>

[0205] As a substrate for forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of materials such as silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include insulating substrates provided with a conductor or semiconductor, semiconductor substrates provided with a conductor or insulator, and conductive substrates provided with a semiconductor or insulator.

[0206] <<Insulator>>

[0207] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0208] For example, as transistors become increasingly miniaturized and highly integrated, problems such as leakage current may arise due to thinner gate insulators. Using a high-k material as the gate insulator allows for lower transistor operating voltages while maintaining the physical thickness. On the other hand, using a material with a low relative dielectric constant as the interlayer insulator reduces parasitic capacitance between wiring lines. Therefore, it is preferable to select the insulator material based on its function.

[0209] Insulators with a relatively high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0210] Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and silicon oxide or resin having pores.

[0211] Furthermore, by surrounding a transistor using a metal oxide with an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0212] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with the oxide 230, oxygen vacancies contained in the oxide 230 can be filled.

[0213] <<Conductor>>

[0214] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, it is preferred to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Alternatively, a semiconductor with high conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0215] Alternatively, multiple conductive layers formed from the above-mentioned materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0216] Furthermore, when an oxide is used in the channel formation region of a transistor, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen is preferably employed as the conductor used as the gate electrode. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. By positioning the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0217] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing the metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal elements and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from external insulators can sometimes be captured.

[0218] <<Metal Oxides>>

[0219] A metal oxide used as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Hereinafter, metal oxides that can be used for the oxide 230 according to the present invention will be described.

[0220] The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. In addition, it preferably also contains aluminum, gallium, yttrium, or tin. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0221] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. Note that the element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that a combination of multiple elements may also be used as the element M.

[0222] In this specification and other documents, metal oxides containing nitrogen may be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0223] [Structure of Metal Oxides]

[0224] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous oxide semiconductors (amorphous-like oxide semiconductors), and amorphous oxide semiconductors.

[0225] In nc-OS, the atomic arrangement in tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) is periodic. Furthermore, in nc-OS, no regularity in crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Consequently, nc-OS can sometimes be indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0226] In addition, when In-Ga-Zn oxide (hereinafter, IGZO), a type of metal oxide containing indium, gallium, and zinc, is the above-mentioned nanocrystal, it may have a stable structure. In particular, since IGZO tends to be difficult to grow in the atmosphere, IGZO formed from small crystals (for example, the above-mentioned nanocrystals) may be structurally more stable than when IGZO is formed from large crystals (here, crystals of several mm or several cm).

[0227] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. It contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0228] Oxide semiconductors (metal oxides) have various structures and properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0229] In addition to the above-mentioned oxide semiconductors, CAC (Cloud-Aligned Composite)-OS can also be used.

[0230] CAC-OS has the function of conductivity in a part of the material, the function of insulation in another part of the material, and the function of semiconductor as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the function of conductivity is to allow electrons (or holes) used as carriers to flow through, and the function of insulation is to prevent electrons used as carriers from flowing through. Through the complementary effects of the functions of conductivity and insulation, CAC-OS or CAC-metal oxide can be given a switching function (open / close function). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0231] CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. In addition, the conductive region and the insulating region are sometimes unevenly distributed in the material. In addition, sometimes the conductive region is observed to be connected in a cloud-like manner with blurred edges.

[0232] In CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0233] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with a narrow gap complements the component with a wide gap, and the carriers flow through the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field-effect mobility can be obtained in the on-state of the transistor.

[0234] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material or a metal matrix composite material.

[0235] In addition, when focusing on the crystal structure, oxide semiconductors may belong to a category different from the above categories. Figure 2A The classification of crystal structures in oxide semiconductors will be described. Figure 2A A diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0236] like Figure 2A As shown, IGZO is roughly divided into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. In addition, "Crystalline" includes CAAC (c-axis-aligned crystalline), NC (nanocrystalline), and CAC (cloud-aligned composite). In addition, the classification of "Crystalline" does not include single crystal, polycrystal, and completely amorphous. "Crystal" includes single crystal and polycrystal.

[0237] in addition, Figure 2A The structure within the bold frame is an intermediate state between "amorphous" and "crystal," representing a novel boundary region (a new crystalline phase). This structure lies at the boundary between amorphous and crystal. In other words, it can be said to be completely different from "crystal" or the energetically unstable "amorphous."

[0238] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) patterns. Figure 2B and Figure 2C The XRD spectra of IGZO (also called crystalline IGZO) using quartz glass and having a crystal structure classified as "Crystalline" are shown. Figure 2B is the XRD spectrum of quartz glass, Figure 2C This is the XRD spectrum of crystalline IGZO. Figure 2C The composition of the crystalline IGZO film shown is approximately In:Ga:Zn=4:2:3 [atomic ratio]. Figure 2C The thickness of the crystalline IGZO shown is 500 nm.

[0239] like Figure 2B As shown by the arrows, the peak shape of the XRD spectrum of quartz glass is roughly bilaterally symmetrical. Figure 2C As shown by the arrow, the peak shape of the XRD spectrum of crystalline IGZO is not bilaterally symmetrical. The peak shape of the XRD spectrum is asymmetrical, which clearly indicates the presence of crystals. In other words, unless the peak shape of the XRD spectrum is bilaterally symmetrical, it cannot be said to be amorphous. Figure 2C In the figure, a crystalline phase (IGZO crystal phase) is shown at or near 2θ=31°. It is speculated that the bilateral asymmetry of the peak shape of the XRD spectrum is due to this crystalline phase (crystal).

[0240] Specifically, in Figure 2C The XRD spectrum of the crystalline IGZO shown in FIG. 1 has a peak at or near 2θ = 34°. In addition, the microcrystal has a peak at or near 2θ = 31°. When evaluating an oxide semiconductor film using an X-ray diffraction pattern, as shown in FIG. Figure 2C As shown in FIG. 1 , the spectrum width at a lower angle than the peak at or near 2θ=34° is broadened. This indicates that the oxide semiconductor film includes microcrystals having a peak at or near 2θ=31°.

[0241] Alternatively, the crystal structure of a film or substrate can be evaluated using a diffraction pattern observed by nanobeam electron diffraction (NBED) (also referred to as a nanobeam electron diffraction pattern). Figure 2D The diffraction pattern of the IGZO film formed under the condition that the substrate temperature is room temperature is shown. Figure 2D The IGZO film shown is formed by sputtering using an oxide target having an atomic ratio of In:Ga:Zn=1:1:1. In nanobeam electron diffraction, electron diffraction was performed with a beam diameter of 1 nm.

[0242] like Figure 2D As shown, the diffraction pattern of the IGZO film formed at room temperature shows a spot-like pattern but no halo pattern. Therefore, it is estimated that the IGZO film formed at room temperature is in an intermediate state between crystalline and amorphous, and it is not possible to conclude that it is amorphous.

[0243] [Impurities]

[0244] Here, the influence of various impurities in the metal oxide will be described.

[0245] When impurities are mixed into an oxide semiconductor, defect energy levels or oxygen vacancies are sometimes formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are easily changed, and sometimes its reliability is reduced. In addition, when the channel formation region has oxygen vacancies, the transistor is likely to have a normally-on characteristic (the characteristic that the channel exists and current flows through the transistor even when a voltage is not applied to the gate electrode).

[0246] The electrical characteristics of transistors using metal oxides vary due to impurities and oxygen vacancies in the metal oxides, and they are prone to exhibiting normally-on characteristics. Furthermore, when the transistor is driven while the metal oxide contains excess oxygen exceeding an appropriate value, the valence of the excess oxygen atoms may change, causing changes in the transistor's electrical characteristics and reducing reliability.

[0247] Therefore, it is preferable to use a metal oxide with a low carrier concentration as the channel formation region in the transistor. In order to reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide is reduced to reduce the defect state density. In this specification, etc., the state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Note that in this specification, etc., the carrier concentration of the metal oxide in the channel formation region is 1×10 16 cm -3 The following situations are defined as high-purity intrinsic.

[0248] In addition, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10 18cm -3 Below, more preferably 1×10 17 cm -3 Below, more preferably 1×10 16 cm -3 Below, more preferably less than 1×10 13 cm -3 , especially preferably less than 1×10 12 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration of the metal oxide in the channel formation region, and it can be set to 1×10 -9 cm -3 .

[0249] Impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. In particular, since hydrogen contained in the metal oxide reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed in the metal oxide. When oxygen vacancies are included in the channel formation region of the metal oxide, the transistor may have a normally-on characteristic. Furthermore, when hydrogen enters the oxygen vacancies in the metal oxide, hydrogen may bond to the oxygen vacancies to form V O H. Hydrogen enters the oxygen vacancy defect (V O H) acts as a donor, sometimes generating electrons as carriers. In addition, some of the hydrogen bonds to oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have normally-on characteristics. In addition, the hydrogen in the metal oxide is easily transferred by heat, electric field, etc., so when the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0250] In one embodiment of the present invention, it is preferred to minimize the V O H and make the oxide 230 high purity intrinsic or substantially high purity intrinsic. In order to obtain such V O To obtain a metal oxide with a very low H, it is important to: remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation); and supply oxygen to the metal oxide to fill oxygen vacancies (sometimes referred to as oxidation). O Metal oxides with significantly reduced impurities such as H are used in the channel formation region of transistors to impart stable electrical characteristics.

[0251] The hydrogen enters the oxygen vacancy defect (V OH) can be used as a donor for metal oxides. However, it is difficult to quantitatively evaluate this defect. Therefore, in metal oxides, the carrier concentration is sometimes used instead of the donor concentration for evaluation. Therefore, in this specification, etc., as a parameter of the metal oxide, the carrier concentration under the assumption that no electric field is applied is sometimes used instead of the donor concentration. In other words, the "carrier concentration" described in this specification, etc. can sometimes also be referred to as the "donor concentration." In addition, the "carrier concentration" described in this specification, etc. can be replaced with "carrier density."

[0252] Therefore, it is preferable to reduce the amount of hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide measured by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0253] Furthermore, these defect levels sometimes include trap levels. Furthermore, charges trapped in metal oxide trap levels take a long time to dissipate, sometimes acting like fixed charges. Consequently, metal oxide transistors with a high trap state density in the channel formation region can sometimes exhibit unstable electrical characteristics.

[0254] In addition, when there are impurities in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region is sometimes reduced. In addition, the crystallinity of the oxide in contact with the channel formation region is sometimes reduced. When the crystallinity of the channel formation region is low, there is a tendency for the stability or reliability of the transistor to decrease. In addition, when the crystallinity of the oxide in contact with the channel formation region is low, an interface energy level is sometimes formed, which causes the stability or reliability of the transistor to decrease.

[0255] Therefore, in order to improve the stability and reliability of the transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0256] Specifically, the concentration of the impurities in the channel formation region and its vicinity measured by SIMS was 1×10 18atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 Or, in the channel formation region of the oxide semiconductor and its vicinity, the concentration of the impurity measured by elemental analysis using EDX is 1.0 atomic % or less. In addition, when an oxide containing element M is used as the oxide semiconductor, in the channel formation region of the oxide semiconductor and its vicinity, the concentration ratio of the impurity to element M is less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the above-mentioned concentration ratio may be the concentration in the same region as the region where the impurity concentration is calculated, or the concentration in the oxide semiconductor.

[0257] Furthermore, since the defect state density of the metal oxide with a reduced impurity concentration is low, the trap state density may also be low.

[0258] Furthermore, in transistors using oxide semiconductors, the presence of impurities and oxygen vacancies in a channel formation region of the oxide semiconductor may reduce the resistance of the oxide semiconductor, and may also easily cause changes in electrical characteristics, thereby reducing reliability.

[0259] For example, the bond energy between silicon and oxygen is greater than that between indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, when silicon is mixed into the oxide semiconductor, oxygen contained in the oxide semiconductor is taken away by silicon, sometimes forming oxygen vacancies near indium or zinc.

[0260] In transistors using an oxide semiconductor for the channel formation region, when a low-resistance region is formed in the channel formation region, leakage current (parasitic channel) is likely to occur between the source and drain electrodes of the transistor in this low-resistance region. Furthermore, this parasitic channel is likely to cause transistor characteristics to deteriorate, such as normally-on, increased leakage current, and fluctuations (drift) in threshold voltage due to stress. Furthermore, when transistor processing accuracy is low, this parasitic channel is non-uniform across transistors, resulting in non-uniform transistor characteristics.

[0261] Therefore, in the channel formation region of the oxide semiconductor and its vicinity, the above-mentioned impurities and oxygen vacancies are preferably reduced as much as possible.

[0262] <<Other semiconductor materials>>

[0263] Semiconductor materials that can be used for oxide 230 are not limited to the above-mentioned metal oxides. Semiconductor materials having a band gap (non-zero-band gap semiconductors) can also be used as oxide 230. For example, single-element semiconductors such as silicon, compound semiconductors such as gallium arsenide, and layered semiconductor materials (also referred to as atomic layer materials, two-dimensional materials, etc.) are preferably used as semiconductor materials. In particular, layered semiconductor materials are preferably used as semiconductor materials.

[0264] Here, in this specification, etc., layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked together by bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per unit layer, that is, high two-dimensional electrical conductivity. By using a material that is a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0265] Examples of layered materials include graphene, silicene, and sulfides. Sulfides are compounds containing sulfur. "Sulfur" is a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and lead. Examples of sulfides include transition metal chalcogenides and Group 13 chalcogenides.

[0266] As the oxide 230, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specifically, examples of the transition metal chalcogenide that can be used for the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0267] <Variation Example 1 of Semiconductor Device>

[0268] The following uses Figures 3A to 3D An example of a semiconductor device according to one embodiment of the present invention will be described.

[0269] Figure 3A is a top view of a semiconductor device. Figure 3B It is along Figure 3A The cross-sectional view of the portion along the dotted line A1-A2 in FIG. Figure 3C It is along Figure 3A A cross-sectional view of the portion taken along the dashed line A3-A4. Figure 3D It corresponds to Figure 3A A cross-sectional view of the portion along the dotted line A5-A6. Figure 3A In the top view, some components are omitted for clarity.

[0270] Note that in Figures 3A to 3D In the semiconductor device shown, components having the same functions as those of the semiconductor device shown in <Structural Example 1 of a Semiconductor Device> are denoted by the same reference numerals. In this section, the materials used to form the semiconductor device can be those described in detail in <Structural Example 1 of a Semiconductor Device>.

[0271] Figures 3A to 3D The semiconductor device shown is Figures 1A to 1D A modified example of the semiconductor device shown. Figures 3A to 3D The semiconductor device shown is Figures 1A to 1D The difference between the semiconductor devices shown is the shape of the insulator 283. In addition, Figures 3A to 3D The semiconductor device shown includes an insulator 274, which is also consistent with Figures 1A to 1D The semiconductor devices shown are different.

[0272] exist Figures 3A to 3D In the semiconductor device shown, insulators 214, 216, 222, 224, 272, 280, and 282 are patterned. Furthermore, insulator 283 covers insulators 214, 216, 222, 224, 272, 280, and 282. In other words, insulator 283 contacts the top and side surfaces of insulator 282 and the top surface of insulator 212. Thus, insulators 214, 216, 222, 224, 272, 280, and 282, including oxide 230 and the like, are isolated from the outside by insulators 283 and insulator 212. In other words, transistor 200 is disposed in a region enclosed by insulators 283 and 212.

[0273] For example, it is preferable that insulator 214 and insulator 282 be formed of a material capable of capturing and fixing hydrogen, and insulator 212 and insulator 283 be formed of a material capable of suppressing the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used as insulator 214 and insulator 282. Furthermore, silicon nitride can be typically used as insulator 212 and insulator 283.

[0274] By adopting the above-mentioned structure, it is possible to suppress the hydrogen contained in the region other than the sealed region from mixing into the sealed region.

[0275] In addition, Figures 3A to 3DIn the transistor 200 shown, the insulator 212 and the insulator 283 have a single-layer structure, but the present invention is not limited thereto. For example, the insulator 212 and the insulator 283 may both have a stacked structure of two or more layers.

[0276] Insulator 274 serves as an interlayer film. Insulator 274 preferably has a lower dielectric constant than insulator 214. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance between wirings. Insulator 274 can be formed using the same material as insulator 280, for example.

[0277] <Method for Manufacturing Semiconductor Device>

[0278] Next, use Figures 4A to 18D illustrate Figures 3A to 3D A method for manufacturing a semiconductor device according to one embodiment of the present invention is shown.

[0279] exist Figures 4A to 18D In each figure, A is a top view. In addition, B in each figure shows a cross-sectional view of a portion along the dot-dash line A1-A2 in A, which corresponds to a cross-sectional view in the channel length direction of transistor 200. C in each figure shows a cross-sectional view of a portion along the dot-dash line A3-A4 in A, which corresponds to a cross-sectional view in the channel width direction of transistor 200. In addition, each figure D is a cross-sectional view of a portion along the dot-dash line A5-A6 in each figure A. For the sake of clarity, some components are omitted in the top view of A in each figure.

[0280] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate. The insulator 212 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0281] Note that CVD methods can be divided into plasma-enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, CVD methods can be divided into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0282] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, because plasma is not used in the thermal CVD method, the plasma damage caused to the object to be processed can be reduced. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation (charge up) due to receiving charges from the plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charge. On the other hand, because the above-mentioned damage caused by exposure to plasma is not generated in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during film formation is not generated, so a film with fewer defects can be obtained.

[0283] Note that as the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD (Plasma Enhanced ALD) method using a reactant excited by plasma, or the like can be used.

[0284] In addition, the ALD method can utilize the self-regulation as a property of atoms to deposit the atoms of each layer, thereby achieving the effects of being able to form extremely thin films, being able to form films on structures with high aspect ratios, being able to form films with fewer defects such as pinholes, being able to form films with excellent coverage, and being able to form films at low temperatures. In addition, in the PEALD (Plasma Enhanced ALD) method, by utilizing plasma, film formation can be performed at lower temperatures, so it is sometimes preferred. The precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon than films formed using other film forming methods. In addition, the quantification of impurities can be measured using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

[0285] Unlike film-forming methods that deposit particles released from a target material, etc., CVD and ALD methods are methods of forming films due to reactions on the surface of the object being processed. Therefore, films formed by CVD and ALD methods are not easily affected by the shape of the object being processed and have good step coverage. In particular, films formed by the ALD method have good step coverage and thickness uniformity, so the ALD method is suitable for forming films that cover the surface of openings with high aspect ratios. However, the ALD method has a relatively slow film-forming speed, so it is sometimes preferable to use it in combination with other film-forming methods such as the CVD method, which has a faster film-forming speed.

[0286] CVD or ALD methods can control the composition of the resulting film by adjusting the flow ratio of the source gases. For example, when using CVD or ALD, a film of any composition can be formed by adjusting the flow ratio of the source gases. Furthermore, for example, when using CVD or ALD, a film whose composition continuously changes can be formed by changing the flow ratio of the source gases while the film is formed. When forming a film while changing the flow ratio of the source gases, the time required for transfer and pressure adjustment is eliminated, so the film formation time can be shortened compared to when multiple film formation chambers are used. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0287] In this embodiment, silicon nitride is formed as the insulator 212 by a sputtering method.

[0288] Thus, by using an insulator such as silicon nitride that does not easily transmit copper as the insulator 212, even if a metal such as copper that easily diffuses is used as the conductor of the layer below the insulator 212 (not shown), the metal can be suppressed from diffusing upward through the insulator 212. Furthermore, by using an insulator such as silicon nitride that does not easily transmit impurities such as water and hydrogen, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed.

[0289] Next, the insulator 214 is formed on the insulator 212. The insulator 214 can be formed by sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, aluminum oxide is formed by sputtering as the insulator 214.

[0290] The hydrogen concentration of insulator 214 is preferably lower than that of insulator 212. Silicon nitride having a low hydrogen concentration can be formed by sputtering as insulator 212. Furthermore, when aluminum oxide is used as insulator 214, the hydrogen concentration can be lower than that of insulator 212.

[0291] In a later step, the transistor 200 is formed on the insulator 214 . The hydrogen concentration of the film adjacent to the transistor 200 is preferably low, and the film with a high hydrogen concentration is preferably arranged spaced apart from the transistor 200 .

[0292] Next, an insulator 216 is formed over the insulator 214. The insulator 216 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is formed as the insulator 216 by sputtering.

[0293] Furthermore, insulators 212, 214, and 216 are preferably formed continuously under reduced pressure without being exposed to the atmosphere. Forming without exposure to the atmosphere prevents impurities or moisture from the atmosphere from adhering to insulators 212, 214, and 216, thereby maintaining cleanliness at the interface between insulators 212 and 214, and at the interface between insulators 214 and 216. This is preferable. When film formation is performed continuously, for example, a multi-chamber film formation apparatus can be used. Continuous film formation is preferable because it shortens the manufacturing process time for semiconductor devices.

[0294] Next, an opening is formed in insulator 216 that reaches insulator 214. The opening may include, for example, a groove or a slit. The region where the opening is formed is sometimes referred to as an opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. Insulator 214 is preferably selected from an insulator that functions as an etch stop film when etching insulator 216 to form the groove. For example, when a silicon oxide film or silicon oxynitride is used as insulator 216 to form the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as insulator 214.

[0295] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. In addition, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can also be adopted. In addition, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can also be adopted. In addition, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can also be adopted. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used.

[0296] After the opening is formed, a conductive film serving as the conductor 205a is formed. This conductive film preferably includes a conductor that inhibits oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of a conductor that inhibits oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0297] In this embodiment, a multilayer structure is employed as the conductive film serving as the conductor 205a. First, a tantalum nitride film is formed by sputtering, and titanium nitride is stacked on top of the tantalum nitride. By using this metal nitride as the lower layer of the conductor 205b, even when a readily diffusible metal such as copper is used as the conductive film serving as the conductor 205b, as described later, diffusion of the metal from the conductor 205a to the outside can be suppressed.

[0298] Next, a conductive film serving as the conductor 205b is formed. This conductive film can be formed using plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film serving as the conductor 205b.

[0299] Next, a CMP process is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, only the conductor 205a and the conductor 205b remain in the opening. Thus, the conductor 205 having a flat top surface can be formed (see FIG. 2 ). Figures 4A to 4D Note that a portion of the insulator 216 may be removed due to the CMP process.

[0300] Note that in the above process, the conductor 205 is formed so as to be embedded in the opening of the insulator 216. However, this embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and the insulator 216 may be subjected to CMP treatment to remove a portion of the insulator 216, thereby exposing the surface of the conductor 205.

[0301] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed. In addition, as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, it is possible to suppress the diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 into the inner side of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0302] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0303] Next, heat treatment is preferably performed. The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the proportion of oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere, and then in order to compensate for the detached oxygen, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0304] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes absorption of moisture and the like by the insulator 222 and the like.

[0305] In this embodiment, after forming insulator 222, a heat treatment is performed at 400°C for one hour with a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm. This heat treatment removes impurities such as water and hydrogen contained in insulator 222. Furthermore, when using a hafnium-containing oxide as insulator 222, this heat treatment can improve the crystallinity of insulator 222. Alternatively, heat treatment can be performed after forming insulator 224.

[0306] Next, insulator 224 is formed on insulator 222. Insulator 224 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is formed by ALD as insulator 224. Insulator 224 is preferably formed using a film formation method that uses a gas that reduces or removes hydrogen atoms. This reduces the hydrogen concentration in insulator 224. Insulator 224 will come into contact with oxide 230a in a later step, so reducing the hydrogen concentration in this manner is preferred.

[0307] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. The plasma treatment containing oxygen preferably uses, for example, a device including a power supply for generating high-density plasma using microwaves. Alternatively, it may include a power supply for applying RF (Radio Frequency) to one side of the substrate. High-density oxygen radicals can be generated by using high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224 by applying RF to one side of the substrate. Alternatively, after performing a plasma treatment containing an inert gas using such a device, a plasma treatment containing oxygen may be performed to fill the detached oxygen. In addition, by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 may be removed. At this time, heat treatment may not be performed.

[0308] Here, a film of aluminum oxide may be formed on the insulator 224, for example, by sputtering, and the aluminum oxide may be subjected to CMP treatment until it reaches the insulator 224. By performing this CMP treatment, the surface of the insulator 224 can be flattened and smoothed. By placing the aluminum oxide on the insulator 224 and performing the CMP treatment, it is easy to detect the end point of the CMP treatment. In addition, the thickness of the insulator 224 may sometimes be reduced due to a portion of the insulator 224 being polished by the CMP treatment, but the thickness can be adjusted when the insulator 224 is formed. By flattening and smoothing the surface of the insulator 224, it is sometimes possible to prevent a reduction in the coverage of the oxide formed below and a reduction in the yield of the semiconductor device. In addition, by forming a film of aluminum oxide on the insulator 224 by sputtering, oxygen can be added to the insulator 224, which is preferable.

[0309] Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see Figures 4A to 4D ).

[0310] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0311] For example, when the oxide films 230A and 230B are formed by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, when the oxide films are formed by sputtering, for example, a target such as the aforementioned In-M-Zn oxide can be used.

[0312] In particular, when forming the oxide film 230A, part of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0313] In the case of forming the oxide film 230B by sputtering, an oxygen-excess oxide semiconductor can be formed by forming a film under the condition that the proportion of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. Using an oxygen-excess oxide semiconductor for a channel formation region transistor can achieve relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 230B by sputtering, when the film is formed under the condition that the proportion of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%, an oxygen-deficient oxide semiconductor is formed. Using an oxygen-deficient oxide semiconductor for a channel formation region transistor can have a higher field effect mobility. In addition, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0314] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 1:3:4. Separately, oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 4:2:4.1. These oxide films can be formed by appropriately selecting film formation conditions and atomic ratios based on the desired properties of oxide 230a and oxide 230b.

[0315] Next, an oxide film 243A is formed on the oxide film 230B (see Figures 4A to 4D The oxide film 243A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target having an atomic ratio of In:Ga:Zn = 1:3:4.

[0316] It is preferable to continuously form oxide film 230A, oxide film 230B, and oxide film 243A under reduced pressure without exposure to the atmosphere. Forming the films without exposure to the atmosphere prevents impurities and moisture in the atmosphere from adhering to oxide film 230A, oxide film 230B, and oxide film 243A, thereby keeping the interface between oxide film 230A and oxide film 230B, and the interface between oxide film 230B and oxide film 243A, and the interface between oxide film 230A and oxide film 230B, and the interface between oxide film 230B and oxide film 243A, clean. For example, a multi-chamber film formation apparatus can be used. Continuous film formation is preferable because it shortens the semiconductor device manufacturing process time.

[0317] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range where the oxide film 230A, the oxide film 230B, and the oxide film 243A do not undergo polycrystallization, and can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the proportion of oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere, and then in order to compensate for the oxygen that has been released, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0318] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes absorption of moisture by the oxide films 230A, 230B, and 243A.

[0319] In this embodiment, heat treatment is performed at 550°C for one hour in a nitrogen atmosphere, followed by continuous treatment at 550°C for one hour in an oxygen atmosphere. This heat treatment removes impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment improves the crystallinity of the oxide film 230B, achieving a denser structure. This reduces the diffusion of oxygen and impurities in the oxide film 230B.

[0320] Next, a conductive film 242A is formed on the oxide film 243A (see Figures 4A to 4D). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride can be formed as the conductive film 242A by a sputtering method. In addition, heat treatment can be performed before forming the conductive film 242A. The heat treatment can also be performed under reduced pressure, and the conductive film 242A is continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen attached to the surface of the oxide film 243A can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be reduced. The temperature of the heat treatment is preferably not less than 100°C and not more than 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0321] Next, an insulating film 271A is formed on the conductive film 242A (see Figures 4A to 4D The insulating film 271A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Preferably, the insulating film 271A is an insulating film that has the function of suppressing oxygen permeation. For example, the insulating film 271A can be formed of aluminum oxide, hafnium oxide, silicon nitride, or the like by sputtering or ALD.

[0322] Next, a conductive film 248A is formed over the insulating film 271A (see FIG. 4 ). The conductive film 248A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, the conductive film 248A may be the same as the conductive film 242A.

[0323] In this embodiment, tantalum nitride is formed as the conductive film 242A, aluminum oxide is formed as the insulating film 271A, and tantalum nitride is formed as the conductive film 248A by a sputtering method.

[0324] The conductive film 242A, the insulating film 271A, and the conductive film 248A are preferably formed continuously under reduced pressure without exposure to the atmosphere. Forming the films without exposure to the atmosphere prevents impurities and moisture in the atmosphere from adhering to the conductive film 242A, the insulating film 271A, and the conductive film 248A, thereby keeping the interface between the conductive film 242A and the insulating film 271A, and the interface between the insulating film 271A and the conductive film 248A, and the interface between the insulating film 271A and the conductive film 248A, and the interface, and the interface, clean. For example, a multi-chamber film formation apparatus can be used. Continuous film formation is preferred because it shortens the semiconductor device manufacturing process time.

[0325] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A are processed into island shapes by photolithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 (see FIG. 5A to 5D ). This processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be formed under different conditions. Furthermore, during this process, the thickness of the insulator 224 in the region that does not overlap with the oxide 230a may become thinner.

[0326] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, when removing the resist mask, a dry etching process such as ashing or a wet etching process can be performed, or a wet etching process can be performed after a dry etching process, or a dry etching process can be performed after a wet etching process.

[0327] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material may be formed on the conductive film 242A, a resist mask may be formed thereon, and then the hard mask material may be etched to form a hard mask of the desired shape. The etching of the conductive film 242A and the like may be performed after removing the resist mask or without removing the resist mask. In the latter case, the resist mask may disappear during etching. Alternatively, the hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, the hard mask does not necessarily need to be removed. In this embodiment, the insulating layer 271B and the conductive layer 248 are used as hard masks.

[0328] Here, the insulating layer 271B and the conductive layer 248 are used as masks for forming the conductive layer 242B. Figures 5B to 5D As shown, the conductive layer 242B does not have a curved surface between the side surface and the top surface. Figure 3B and Figure 3D The ends of conductors 242a and 242b, where the side surfaces intersect the top surface, are angular. When the ends of conductors 242 intersect the top surface, angular, the cross-sectional area of ​​conductors 242 increases compared to when the ends have curved surfaces. This reduces the resistance of conductors 242, thereby increasing the on-state current of transistor 200.

[0329] Here, the oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and conductive layer 248 are formed so that at least a portion overlaps with the conductor 205. Furthermore, the side surfaces of the oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and conductive layer 248 are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and conductive layer 248 are substantially perpendicular to the top surface of the insulator 222, a reduced area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure can be employed in which the angle formed by the side surfaces of the oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and conductive layer 248 and the top surface of the insulator 222 is relatively low. In this case, the angle formed by the side surfaces of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and conductive layer 248 and the top surface of insulator 222 is preferably not less than 60 degrees and not more than 70 degrees. By adopting such a shape, coverage with insulator 272 and the like is improved in the subsequent steps, and defects such as voids can be reduced.

[0330] Next, the conductive layer 248 is removed. When removing the conductive layer 248, a dry etching method (see 6A to 6D ).

[0331] Next, an insulator 272 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIG. 2 ). 7A to 7D ). The insulator 272 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, aluminum oxide is formed by sputtering as the insulator 272. In particular, the insulator 272 is preferably formed by bias sputtering. In the bias sputtering method, the amount of oxygen injected into the insulator 224 serving as the base of the insulator 272 can be controlled by the magnitude of the RF power applied to the substrate. For example, if the RF power is 0.31 W / cm2 Above, preferably 0.62W / cm 2 More than 1.86W / cm 2 The above bias voltage can be applied to the substrate. In other words, the RF power used during the formation of insulator 272 can be used to adjust the amount of oxygen to an amount suitable for the characteristics of the transistor before implantation. Alternatively, an amount of oxygen suitable for improving the reliability of the transistor can be implanted. Furthermore, the RF frequency is preferably above 10 MHz. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0332] Insulator 272 thus has the function of injecting oxygen into the underlying film, but insulator 272 itself has the function of suppressing oxygen permeation. This prevents oxygen from directly diffusing from insulator 280 into oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B when insulator 280 is formed on insulator 272 in a subsequent step and oxygen diffuses from insulator 280.

[0333] Next, an insulating film, serving as insulator 280, is formed on insulator 224 and insulator 272. This insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by sputtering, and a silicon oxide film can be formed thereon using a PEALD method or a thermal ALD method. Furthermore, this insulating film is preferably formed using a film formation method using a gas that reduces or removes hydrogen atoms. This reduces the hydrogen concentration in insulator 280. Furthermore, a heat treatment can be performed before forming the insulating film. The heat treatment can also be performed under reduced pressure, and the insulating film can be continuously formed without being exposed to the atmosphere. This treatment can remove moisture and hydrogen adhering to the surfaces of insulators 224 and 272, and reduce the moisture and hydrogen concentrations in oxide 230a, oxide 230b, oxide layer 243B, and insulator 224. The heat treatment can employ the conditions described above for the heat treatment.

[0334] Next, the insulating film is subjected to CMP treatment to form an insulator 280 having a flat top surface (see Figures 8A to 8D ). In addition, similarly to the insulator 224 , for example, aluminum oxide may be formed on the insulator 280 by sputtering, and the aluminum oxide may be subjected to CMP until it reaches the insulator 280 .

[0335] Here, microwave treatment may also be performed. Microwave treatment is preferably performed in an oxygen-containing atmosphere and under reduced pressure. By performing microwave treatment, the electric field generated by the microwave is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., so that the V in the oxide 230b and the oxide 230a can be reduced. OH is divided into oxygen vacancies (V O ) and hydrogen (H). Sometimes, part of the hydrogen separated at this time is bonded to oxygen contained in the insulator 280 and removed as water molecules. In addition, sometimes, part of the hydrogen is gettered into the conductive layer 242B through the insulator 272 and the insulating layer 271B.

[0336] Alternatively, heat treatment may be performed after microwave treatment while maintaining the reduced pressure. This treatment can efficiently remove hydrogen from the insulator 280, the oxide 230b, and the oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0337] Furthermore, microwave treatment modifies the film quality of insulator 280, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, post-process heat treatment after forming insulator 280 can suppress the diffusion of hydrogen, water, impurities, etc. through insulator 280 into oxide 230.

[0338] Next, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. This opening is preferably formed so as to overlap with the conductor 205. By forming this opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see 9A to 9D ).

[0339] Note that when forming the opening, the top of oxide 230b may be removed. This removal of a portion of oxide 230b forms a groove in oxide 230b. Depending on the depth of the groove, the groove may be formed during the opening formation process or in a separate process.

[0340] Alternatively, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b may be processed by dry etching or wet etching. Processing using dry etching is suitable for microfabrication. This processing may also be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 272 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. Note that processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under conditions different from those for processing a portion of the oxide 230b.

[0341] Here, when a portion of the oxide 230b is removed by dry etching to form a groove, it is preferable to increase the bias power. For example, the power density of the bias power can be set to 0.02W / cm 2 Above, preferably set to 0.03W / cm 2 More preferably, it is set to 0.06W / cm 2 In addition, the processing time of the dry etching method can be appropriately set according to the depth of the groove portion.

[0342] Here, impurities adhering to the surfaces of oxides 230a and 230b, or diffused into them, are preferably removed. Furthermore, damaged regions formed on the surface of oxide 230b by the dry etching method are preferably removed. Examples of such impurities include: components contained in insulator 280, a portion of insulator 272, a portion of insulating layer 271B, and conductive layer 242B; components contained in components used in the apparatus used to form the openings; and components contained in the gas or liquid used for etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0343] In particular, impurities such as aluminum and silicon hinder CAAC-OS formation in the oxide 230b or the oxide 230c formed in a subsequent step. Therefore, it is preferable to reduce or remove impurity elements such as aluminum and silicon that hinder CAAC-OS formation. For example, the concentration of aluminum atoms at and near the interface between the oxide 230b and the oxide 230c can be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, further preferably 1.0 atomic % or less, and particularly preferably less than 0.3 atomic %.

[0344] Sometimes, the area of ​​metal oxide that is blocked from CAAC-OS by impurities such as aluminum or silicon and becomes a-like OS (amorphous-like oxide semiconductor) is called non-CAAC area. In the non-CAAC area, the density of the crystal structure is reduced, so a large amount of V O Therefore, it is preferable to reduce or remove the non-CAAC regions in the oxides 230 b and 230 c.

[0345] In contrast, oxide 230b and oxide 230c preferably have a CAAC structure. In particular, it is preferred that the lower end of the drain of oxide 230b and oxide 230c also have a CAAC structure. Here, in transistor 200, conductor 242a or conductor 242b and its vicinity are used as a drain. In other words, either or both of oxide 230b and oxide 230c near the lower end of conductor 242a (conductor 242b) preferably have a CAAC structure. In this way, by removing the damaged area of ​​oxide 230b in the drain end portion that has a significant impact on the drain withstand voltage and making it have a CAAC structure, the variation of the electrical characteristics of transistor 200 can be further suppressed. In addition, the reliability of transistor 200 can be further improved.

[0346] To remove these impurities, a cleaning process may be performed. Examples of cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning using heat treatment. These methods may also be combined as appropriate. Note that this cleaning process may deepen the grooves.

[0347] As wet cleaning, an aqueous solution of ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or pure water, pure water, or carbonated water can be used for cleaning. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water, or carbonated water. In addition, the above cleaning methods can be appropriately combined.

[0348] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia water. Furthermore, the concentration, temperature, etc. of the aqueous solution can be appropriately adjusted depending on the impurities to be removed, the structure of the semiconductor device being cleaned, etc. The ammonia concentration of the dilute ammonia water is set to be greater than 0.01% and less than 5%, preferably greater than 0.1% and less than 0.5%. Furthermore, the hydrogen fluoride concentration of the dilute hydrofluoric acid is set to be greater than 0.01 ppm and less than 100 ppm, preferably greater than 0.1 ppm and less than 10 ppm.

[0349] In addition, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide 230 b and the like can be reduced.

[0350] The above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, a treatment using dilute hydrofluoric acid or dilute ammonia water may be performed as the first washing treatment, and a treatment using pure water or carbonated water may be performed as the second washing treatment.

[0351] In this embodiment, the cleaning process is performed using dilute hydrofluoric acid for wet cleaning, followed by wet cleaning with pure water or carbonated water. This cleaning process removes impurities adhering to the surfaces of oxide 230a, oxide 230b, etc. or diffused into the interior thereof. Furthermore, the crystallinity of oxide 230c formed on oxide 230b can be improved.

[0352] By performing the dry etching method or the cleaning treatment, the thickness of the insulator 224 in the region overlapping the opening and not overlapping the oxide 230 b and the insulator 272 may be thinner than the thickness of the insulator 224 in the region overlapping the oxide 230 b.

[0353] Heat treatment may be performed after the etching or washing. The heat treatment is preferably performed at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen is supplied to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V O Furthermore, the heat treatment can improve the crystallinity of oxide 230b and also improve the crystallinity of oxide 230c formed in the groove of oxide 230b. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere and then continuously in a nitrogen atmosphere without exposure to the atmosphere.

[0354] Next, an oxide film 230C is formed (see 10A to 10D). Heat treatment may also be performed before forming the oxide film 230C, and preferably, the heat treatment is performed under reduced pressure so that the oxide film 230C is continuously formed without being exposed to the atmosphere. In addition, the heat treatment is preferably performed in an oxygen-containing atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably not less than 100°C and not more than 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0355] Here, oxide film 230C is preferably provided so as to be in contact with at least the inner wall of the groove formed in oxide 230b, a portion of the side surface of oxide 243, a portion of the side surface of conductor 242, a portion of the side surface of insulator 271, a portion of the side surface of insulator 272, and a portion of the side surface of insulator 280. Since conductor 242 is surrounded by oxide 243, insulator 272, insulator 271, and oxide film 230C, a decrease in conductivity due to oxidation of conductor 242 can be suppressed in subsequent steps.

[0356] The oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C can be formed using the same film formation method as the oxide film 230A or the oxide film 230B, depending on the desired properties of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:3, an oxide target with an In:Ga:Zn ratio of 5:1:3, an oxide target with an In:Ga:Zn ratio of 10:1:3, or an indium oxide target.

[0357] In particular, when forming the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Alternatively, when forming the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or greater, preferably 80% or greater, and more preferably 100%. Furthermore, by forming the oxide film 230C in the aforementioned atmosphere containing a large amount of oxygen, the oxide film 230C can be easily converted into a CAAC-OS.

[0358] The oxide film 230C is preferably formed while the substrate is heated. Setting the substrate temperature to 200°C or higher can reduce oxygen vacancies in the oxide film 230C and the oxide 230b. Forming the oxide film 230C while the substrate is heated can improve the crystallinity of the oxide film 230C and the oxide 230b.

[0359] Next, an oxide film 230D is formed (see 10A to 10D The oxide film 230D is preferably formed continuously from the oxide film 230C without being exposed to the atmosphere.

[0360] The oxide film 230D can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230D can be formed using the same film formation method as the oxide film 230A or the oxide film 230B, depending on the desired properties of the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target having an In:Ga:Zn ratio of 1:3:4 (atomic ratio).

[0361] In particular, when forming oxide film 230D, a portion of the oxygen contained in the sputtering gas may be supplied to oxide film 230C. Alternatively, when forming oxide film 230D, a portion of the oxygen contained in the sputtering gas may be supplied to insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0362] Next, an insulating film 250A is formed (see 10A to 10D A heat treatment may be performed before forming the insulating film 250A. Preferably, this heat treatment is performed under reduced pressure to continuously form the insulating film 250A without exposure to the atmosphere. Furthermore, this heat treatment is preferably performed in an oxygen-containing atmosphere. This treatment removes moisture and hydrogen adhering to the surface of the oxide film 230C and reduces the moisture and hydrogen concentrations in the oxides 230a and 230b, as well as the oxide film 230C. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0363] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 250A is preferably formed using a film-forming method that uses a gas that reduces or eliminates hydrogen atoms. This can reduce the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 in contact with the oxide 230d in a subsequent step, so reducing the hydrogen concentration in this manner is preferable.

[0364] When the insulator 250 has a two-layer stacked structure, the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250 are preferably formed continuously without being exposed to the atmospheric environment. By forming the insulating film without being exposed to the atmospheric environment, impurities and moisture from the atmospheric environment can be prevented from adhering to the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250, thereby keeping the interface between the insulating film forming the lower layer of the insulator 250 and the insulating film forming the upper layer of the insulator 250 clean.

[0365] Here, microwave treatment may be performed in an oxygen-containing atmosphere and under reduced pressure after the insulating film 250A is formed. By performing microwave treatment, an electric field generated by microwaves is applied to the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc., thereby increasing the V in the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. O H is separated into V O With hydrogen. At this time, part of the separated hydrogen is bonded to oxygen and is sometimes removed as H2O from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. In addition, part of the hydrogen is sometimes doped by the conductor 242 (the conductor 242a and the conductor 242b). In this way, by performing microwave treatment, the hydrogen concentration in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. In addition, by treating V in the oxide 230a, the oxide 230b, the oxide film 230D, and the oxide film 230C O H is separated into V O After reacting with hydrogen, V O Supply oxygen, which can repair or fill V O .

[0366] Alternatively, after the microwave treatment, the reduced pressure state may be maintained and heat treatment may be performed. By performing such treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed. In addition, a portion of the hydrogen is sometimes doped by the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, after the microwave treatment, the reduced pressure state may be maintained and heat treatment may be repeated several times. By repeatedly performing heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be further efficiently removed. Note that the heat treatment temperature is preferably not less than 300°C and not more than 500°C.

[0367] Furthermore, by modifying the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. This can prevent hydrogen, water, impurities, etc. from diffusing through the insulator 250 into the oxides 230b and 230a, etc., due to post-processing such as heat treatment after film formation of the conductive film that will become the conductor 260.

[0368] Next, the conductive film 260A and the conductive film 260B are sequentially formed (see 11A to 11D The conductive film 260A and the conductive film 260B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, the conductive film 260A is formed by ALD, and the conductive film 260B is formed continuously by CVD under reduced pressure without being exposed to the atmosphere.

[0369] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 12A to 12D ). Thus, oxide 230c is arranged to cover the opening that reaches oxide 230b and the inner walls (side walls and bottom surface) of the groove portion of oxide 230b. Furthermore, oxide 230d is arranged to cover the above-mentioned opening and the inner walls of the above-mentioned groove portion via oxide 230c. Furthermore, insulator 250 is arranged to cover the above-mentioned opening and the inner walls of the above-mentioned groove portion via oxide 230d. Furthermore, conductor 260 is arranged to fill the above-mentioned opening and the above-mentioned groove portion via oxide 230c, oxide 230d, and insulator 250.

[0370] Next, a heat treatment can be performed under the same conditions as the above-described heat treatment. In this embodiment, the treatment is performed at 400°C for one hour in a nitrogen atmosphere. This heat treatment can reduce the water and hydrogen concentrations in insulators 250 and 280. Alternatively, insulator 282 can be formed continuously after the above-described heat treatment without exposure to the atmosphere.

[0371] Next, an insulator 282 is formed on the oxide 230d, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIG. 2 ). 13A to 13D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form an aluminum oxide film by a sputtering method. By forming the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while the film is being formed. Thus, the insulator 280 can contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. In addition, by forming the insulator 282 in a manner that contacts the top surface of the conductor 260, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 during the subsequent heat treatment, which is preferable.

[0372] Next, a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 272, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, and a portion of the insulator 214 are processed to form an opening reaching the insulator 212 (see 14A to 14D ). The opening is sometimes formed so as to surround transistor 200. Alternatively, the opening is sometimes formed so as to surround a plurality of transistors 200. Therefore, in the opening, a portion of the side surface of insulator 282, a portion of the side surface of insulator 280, a portion of the side surface of insulator 272, a portion of the side surface of insulator 224, a portion of the side surface of insulator 222, a portion of the side surface of insulator 216, and a portion of the side surface of insulator 214 are exposed.

[0373] A portion of insulator 282, a portion of insulator 280, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, a portion of insulator 216, and a portion of insulator 214 can be processed using dry etching or wet etching. Processing using dry etching is suitable for microfabrication. This processing can also be performed under various conditions.

[0374] Next, the insulator 283 is formed so as to cover the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 (see 15A to 15D ). Insulator 283 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon nitride is formed by sputtering. As shown in FIG15 , insulator 283 is in contact with insulator 212 at the bottom of the opening. That is, the top and side surfaces of transistor 200 are surrounded by insulator 283, while the bottom surface is surrounded by insulator 212. In this way, by surrounding transistor 200 with insulator 283 and insulator 212 having high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

[0375] Next, an insulating film serving as insulator 274 is formed on insulator 283. The insulating film serving as insulator 274 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, silicon oxide is preferably formed using a CVD method. Furthermore, the insulating film serving as insulator 274 is preferably formed using a film formation method using a gas in which hydrogen atoms are reduced or removed, as described above. This can reduce the hydrogen concentration in the insulating film serving as insulator 274.

[0376] Next, the insulating film to be the insulator 274 is subjected to CMP treatment to form the insulator 274 having a flat top surface (see 16A to 16D ).

[0377] Next, openings reaching the conductor 242 are formed in the insulators 271, 272, 280, 282, and 283 (see FIG. 17A to 17D ). When forming the opening, photolithography can be used. Figure 17A The shape of this opening when viewed from above is circular, but is not limited to this. For example, when viewed from above, this opening can also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0378] Next, an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 17A to 17D The insulating film serving as the insulator 241 can be formed by sputtering, CVD, MBE, PLD, or ALD. As the insulating film serving as the insulator 241, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, aluminum oxide is preferably formed by ALD. Alternatively, silicon nitride is preferably formed by PEALD. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0379] Furthermore, dry etching, for example, can be used for anisotropic etching of the insulating film to become insulator 241. Providing insulator 241 on the sidewalls of the opening suppresses the permeation of oxygen from the outside, thereby preventing oxidation of conductors 240a and 240b to be formed subsequently. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0380] Next, conductive films serving as conductors 240a and 240b are formed. The conductive films serving as conductors 240a and 240b preferably have a laminated structure including a conductive material that inhibits the permeation of impurities such as water and hydrogen. For example, a laminated structure of tantalum nitride, titanium nitride, or the like with tungsten, molybdenum, copper, or the like can be used. The conductive film serving as conductor 240 can be formed using a sputtering method, CVD, MBE, PLD, ALD, or the like.

[0381] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductors 240a and 240b, thereby exposing the top surfaces of the insulators 283 and 274. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat top surfaces (see FIG. 17A to 17D Note that part of the top surface of the insulator 283 and part of the top surface of the insulator 274 may be removed by the CMP process.

[0382] Next, a conductive film is formed to serve as the conductor 246. The conductive film to serve as the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0383] Next, the conductive film to be the conductor 246 is processed by photolithography to form a conductor 246a in contact with the top surface of the conductor 240a and a conductor 246b in contact with the top surface of the conductor 240b (see FIG. 2 ). 18A to 18D At this time, although not shown in the figure, a portion of the insulator 283 in the region where the conductors 246a and 246b do not overlap with the insulator 283 may be removed.

[0384] Next, an insulator 286 is formed on the conductor 246 and the insulator 283 (see Figures 3A to 3D The insulator 286 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Furthermore, the insulator 286 can be a multilayer structure. For example, silicon nitride can be formed by sputtering and then silicon nitride can be formed on top of the silicon nitride by CVD.

[0385] Through the above process, it is possible to manufacture Figures 3A to 3D The semiconductor device of transistor 200 is shown. Figures 4A to 18D As shown, the transistor 200 can be manufactured by using the semiconductor device manufacturing method described in this embodiment. Note that when manufacturing a semiconductor device including Figures 1A to 1D When the semiconductor device of the transistor 200 is shown, it is also possible not to perform 14A to 16D A semiconductor device is manufactured by the steps shown.

[0386] <Structural Example 2 of Semiconductor Device>

[0387] use 19A to 19D Another structure of a semiconductor device including the transistor 200 is described. In the present invention, 19A to 19D As shown in the semiconductor device, the insulator 272 may not be provided.

[0388] 19A to 19D2 are a top view and a cross-sectional view of a semiconductor device including the transistor 200 . Figure 19A : is a top view of the semiconductor device. Figures 19B to 19D is a cross-sectional view of the semiconductor device. Figure 19B It is along Figure 19A The cross-sectional view along the dot-dash line A1-A2 in FIG. 1 is equivalent to a cross-sectional view along the channel length direction of the transistor 200. Figure 19C It is shown along Figure 19A 1 is a cross-sectional view of a portion taken along a dashed line A3 - A4 in FIG. 1 , which corresponds to a cross-sectional view of the transistor 200 in the channel width direction. Figure 19D It corresponds to Figure 19A A cross-sectional view of the portion along the dotted line A5-A6. Figure 19A In the top view, some components are omitted for clarity.

[0389] [Transistor 200]

[0390] like 19A to 19D As shown, transistor 200 includes: an insulator 216 on an insulator 214; a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in insulator 214 or insulator 216; an insulator 222 on insulator 216 and on conductor 205; an insulator 224 on insulator 222; an oxide 230a on insulator 224; an oxide 230b on oxide 230a; an oxide 243 (oxide 243a and oxide 243b) on oxide 230b. Oxide 243b) and oxide 230c; conductor 242a on oxide 243a; insulator 271a on conductor 242a; conductor 242b on oxide 243b; insulator 271b on conductor 242b; oxide 230d on oxide 230c; insulator 250 on oxide 230d; and conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with a portion of oxide 230c. In addition, oxide 230c is in contact with the side surface of oxide 243a, the side surface of oxide 243b, the side surface of conductor 242a, and the side surface of conductor 242b. Here, as shown in FIG. Figure 19B and Figure 19C As shown, the top surface of conductor 260 is substantially aligned with the top surfaces of insulator 250, oxide 230d, and oxide 230c. Insulator 282 is in contact with the top surfaces of conductor 260, insulator 250, oxide 230d, oxide 230c, and insulator 280.

[0391] An opening is provided in insulator 280 that reaches oxide 230b. Oxide 230d, oxide 230c, insulator 250, and conductor 260 are arranged within this opening. Furthermore, in the channel length direction of transistor 200, conductor 260, insulator 250, oxide 230d, and oxide 230c are provided between conductor 242a and oxide 243a, and conductor 242b and oxide 243b. Insulator 250 has a region in contact with the side surfaces of conductor 260 and a region in contact with the bottom surface of conductor 260. Furthermore, within the region overlapping with oxide 230b, oxide 230c has a region in contact with oxide 230b, a region overlapping with the side surfaces of conductor 260 via oxide 230d and insulator 250, and a region overlapping with the bottom surface of conductor 260 via oxide 230d and insulator 250.

[0392] In this structural example, oxygen is diffused from the insulator 280 containing excess oxygen into the oxide 230c, and oxygen is supplied from the oxide 230c to the channel formation region of the oxide 230b. This allows oxygen to be selectively supplied to the oxide 230c, which occupies most of the channel formation region, and to the region of the oxide 230b that is in contact with the oxide 230c.

[0393] In addition, excess oxygen contained in insulator 280 diffuses from the interface between insulator 280 and insulator 224 into insulator 224. Furthermore, excess oxygen contained in insulator 224 diffuses from the interface between insulator 224 and oxide 230c into oxide 230c. Furthermore, excess oxygen contained in oxide 230c diffuses from the interface between oxide 230c and oxide 230b into oxide 230b. As a result, excess oxygen contained in insulator 280 is supplied to a region serving as a channel formation region for transistor 200.

[0394] In other words, oxygen can be diffused from insulator 280 containing excess oxygen through insulator 224 to oxide 230c, and oxygen can be supplied from oxide 230c to the channel formation region of oxide 230b. Thus, oxygen can be selectively supplied to oxide 230c, which occupies most of the channel formation region, and to a region of oxide 230b that is in contact with oxide 230c.

[0395] Here, the process of forming oxide 230 b and the like into islands is interposed between the steps of forming insulator 224 and forming insulator 280 on insulator 224. Therefore, byproducts generated during the process of forming oxide 230 b and the like into islands may be deposited on insulator 224. When insulator 280 is formed on this layered byproduct, the amount of oxygen diffusing from insulator 280 to insulator 224 may be reduced. Therefore, it is preferable to perform an etching process to remove this layered byproduct before forming insulator 280.

[0396] Furthermore, some of the excess oxygen diffused into oxide 230c also diffuses into oxide 230d. Oxygen diffuses less easily into oxide 230d than into oxide 230c, so diffusion of oxygen into insulator 250 is relatively suppressed. This prevents oxidation of conductor 260 through insulator 250.

[0397] Furthermore, oxide 230b overlaps insulator 224 via oxide 230a, which has low oxygen permeability. Therefore, excess oxygen contained in insulator 224 is less likely to diffuse into oxide 230a than oxide 230c. Consequently, diffusion of excess oxygen contained in insulator 224 from the bottom surface of oxide 230b is relatively suppressed.

[0398] Specifically, insulator 280 used as an interlayer film preferably has a low dielectric constant. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance generated between wirings. Insulator 280 is preferably formed of the same material as insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with pores are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0399] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulator 280. Furthermore, it is preferable that insulator 280 have a low hydrogen concentration and include an oxygen-excess region or contain excess oxygen. For example, insulator 280 can be formed using the same material as insulator 216. Insulator 280 can also have a structure in which the aforementioned materials are stacked. For example, it can have a stacked structure of a silicon oxide film formed by sputtering and a silicon oxynitride film stacked thereon by chemical vapor deposition (CVD). Furthermore, silicon nitride can be further stacked thereon.

[0400] The insulator 282 is preferably used as a block insulating film that suppresses impurities such as water and hydrogen from diffusing from above into the insulator 280. In addition, the insulator 282 is preferably used as a block insulating film that suppresses oxygen permeation.

[0401] Furthermore, by forming the insulator 282 in an atmosphere containing oxygen, excess oxygen regions can be provided in the insulator 280 and the insulator 224. Therefore, as the insulator 282, for example, an insulator such as aluminum oxide, hafnium oxide, or silicon oxynitride can be used.

[0402] In particular, the insulator 282 is preferably formed of aluminum oxide or hafnium oxide by a bias sputtering method in an oxygen-containing atmosphere.

[0403] Thus, by forming aluminum oxide or hafnium oxide in an oxygen-containing atmosphere by bias sputtering, oxygen can be implanted into insulator 280 and insulator 224 disposed below insulator 282. Furthermore, the amount of oxygen implanted into insulator 280 and insulator 224 can be controlled by adjusting the RF power applied to the substrate. Therefore, the amount of oxygen implanted into insulator 224 can be adjusted to an amount suitable for improving transistor reliability.

[0404] For example, if 0.31 W / cm 2 Above, preferably 0.62W / cm 2 More than 1.86W / cm 2 The above bias voltage can be applied to the substrate. In other words, the amount of oxygen can be modified to an amount suitable for the characteristics of the transistor by using the RF power used when forming insulator 280. Furthermore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably above 10 MHz. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0405] In this manner, insulator 282 has the function of injecting oxygen into the film serving as the base, but insulator 282 itself has the function of inhibiting oxygen permeation. Therefore, by forming insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to insulator 280 and insulator 224 while the film is being formed. This allows insulator 280 to contain excess oxygen. In this case, it is preferable to form insulator 282 while the substrate is being heated. In addition, by forming insulator 282 so as to contact the top surface of conductor 260, it is preferable to inhibit oxygen contained in insulator 280 from being absorbed by conductor 260 during the subsequent heat treatment.

[0406] In this manner, oxygen can be selectively supplied to the channel formation region of the oxide semiconductor, achieving i-type or substantially i-type conversion, while oxygen diffusion into regions serving as source or drain regions can be suppressed, maintaining n-type conversion. This can suppress variations in the electrical characteristics of the transistor 200 and reduce variations in the electrical characteristics of the transistor 200 within the substrate plane.

[0407] By adopting the above structure, a semiconductor device with less variation in transistor characteristics can be provided. In addition, a semiconductor device with high reliability can be provided. In addition, a semiconductor device with good electrical characteristics can be provided.

[0408] <Variation Example 2 of Semiconductor Device>

[0409] The following uses 20A to 20D An example of a semiconductor device according to one embodiment of the present invention will be described.

[0410] Figure 20AIt is a top view of a semiconductor device. Figure 20B It corresponds to Figure 20A A cross-sectional view of the portion along the dashed line A1-A2. Figure 20C It corresponds to Figure 20A A cross-sectional view of the portion taken along the dashed line A3-A4. Figure 20D It corresponds to Figure 20A A cross-sectional view of the portion along the dotted line A5-A6. Figure 20A In the top view, some components are omitted for clarity.

[0411] Note that in 20A to 20D In the semiconductor device shown, components having the same functions as those of the semiconductor device shown in <Semiconductor Device Configuration Example 1> are denoted by the same reference numerals. In this section, the components of the semiconductor device can use the materials described in detail in <Semiconductor Device Configuration Example>.

[0412] 20A to 20D The semiconductor device shown is 19A to 19D A modified example of the semiconductor device shown. 20A to 20D The semiconductor device shown is 19A to 19D The difference between the semiconductor devices shown is the shape of the insulator 283. In addition, 20A to 20D The semiconductor device shown includes an insulator 274, which is also consistent with 19A to 19D The semiconductor devices shown are different.

[0413] exist 20A to 20D In the semiconductor device shown, insulators 214, 216, 222, 224, 280, and 282 are patterned. Furthermore, insulator 283 covers insulators 214, 216, 222, 224, 280, and 282. In other words, insulator 283 contacts the top and side surfaces of insulator 282 and the top surface of insulator 212. Thus, insulators 214, 216, 222, 224, 280, and 282, including oxide 230 and the like, are isolated from the outside by insulators 283 and 212. In other words, transistor 200 is disposed in a region enclosed by insulators 283 and 212.

[0414] For example, it is preferable that insulator 214 and insulator 282 be formed of a material capable of capturing and fixing hydrogen, and insulator 212 and insulator 283 be formed of a material capable of suppressing the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used as insulator 214 and insulator 282. Furthermore, silicon nitride can be typically used as insulator 212 and insulator 283.

[0415] In addition, 20A to 20D In the transistor 200 shown, the insulator 212 and the insulator 283 have a single-layer structure, but the present invention is not limited thereto. For example, the insulator 212 and the insulator 283 may both have a stacked structure of two or more layers.

[0416] By adopting the above-mentioned structure, it is possible to suppress the hydrogen contained in the region other than the sealed region from mixing into the sealed region.

[0417] <Application Examples of Semiconductor Devices>

[0418] Below, refer to Figure 21A and Figure 21B An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the above-mentioned <Semiconductor Device Structure Example 1>, <Semiconductor Device Structure Example 2>, <Semiconductor Device Modification Example 1>, and <Semiconductor Device Modification Example 2>, will be described. Figure 21A and Figure 21B In the semiconductor device shown in FIG. 1 , the semiconductor device having the same structure as the semiconductor device shown in FIG. 1 (see FIG. 1 ) Figures 1A to 1D ) are assigned the same reference numerals. In this section, the materials used to form the transistor 200 can be those described in detail in <Structural Example 1 of Semiconductor Device>, <Structural Example 2 of Semiconductor Device>, <Variation 1 of Semiconductor Device>, and <Variation 2 of Semiconductor Device>.

[0419] Figure 21A and Figure 21B A structure is shown in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded and sealed by the insulator 283 and the insulator 212. Figure 21A and Figure 21B Although transistors 200_1 to 200_n are shown as being arranged along the channel length direction, this is not limiting. Transistors 200_1 to 200_n may be arranged along the channel width direction or in a matrix. Alternatively, they may be arranged randomly depending on the design.

[0420] like Figure 21AAs shown, a portion of the insulator 283 that contacts the insulator 212 (hereinafter sometimes referred to as a sealing portion 265) is formed outside the plurality of transistors (transistors 200_1 to 200_n). Sealing portion 265 is formed to surround the plurality of transistors (transistors 200_1 to 200_n). By adopting this structure, the plurality of transistors (transistors 200_1 to 200_n) can be surrounded by insulator 283 and insulator 212. Thus, a group of transistors surrounded by sealing portion 265 is provided on the substrate.

[0421] Alternatively, dicing lines (sometimes referred to as dividing lines, breaking lines, or cutting lines) may be provided so as to overlap the sealing portion 265. The substrate is divided along the dicing lines, so that the transistor group surrounded by the sealing portion 265 is cut into a single chip.

[0422] in addition, Figure 21A An example is shown in which a plurality of transistors (transistors 200_1 to 200_n) are surrounded by one sealing portion 265, but the present invention is not limited thereto. Figure 21B As shown in FIG, a plurality of transistors (transistor 200_1 to transistor 200_n) may be surrounded by a plurality of sealing portions. Figure 21B In the embodiment, a plurality of transistors (transistor 200_1 to transistor 200_n) are surrounded by a sealing portion 265a, and the transistors are also surrounded by an outer sealing portion 265b.

[0423] When multiple transistors (transistors 200_1 to 200_n) are surrounded by multiple sealing portions, the insulator 283 and the insulator 212 have more contact portions, thereby further improving the adhesion between the insulator 283 and the insulator 212. This allows the multiple transistors (transistors 200_1 to 200_n) to be more securely sealed.

[0424] In this case, the cut line may be provided so as to overlap with the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0425] According to one embodiment of the present invention, a semiconductor device with less uneven transistor characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0426] As described above, the structures, methods, and the like described in this embodiment mode can be implemented in combination with the structures, methods, and the like described in other embodiments or examples as appropriate.

[0427] (Implementation Method 2)

[0428] In this embodiment, referring to Figure 22 and Figure 26 One embodiment of a semiconductor device will be described.

[0429] [Storage device 1]

[0430] Figure 22 An example of a semiconductor device (memory device) using one embodiment of the present invention is shown. The semiconductor device according to one embodiment of the present invention includes a transistor 200, a transistor 300, and a capacitor 100. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. The transistor 200 described in the above embodiment can be used as the transistor 200.

[0431] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Because transistor 200 has a low off-state current, its use in a memory device allows for long-term retention of stored data. In other words, since refresh operations are unnecessary or performed at an extremely low frequency, the memory device's power consumption can be significantly reduced.

[0432] exist Figure 22 In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0433] In addition, by Figure 22 The memory devices shown are arranged in a matrix to form a memory cell array.

[0434] <Transistor 300>

[0435] Transistor 300 is provided on substrate 311 and includes a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 comprising a portion of substrate 311, and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 may be a p-channel transistor or an n-channel transistor.

[0436] Here, in Figure 22 In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, a material that adjusts the work function can be used for the conductor 316. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also called a FIN-type transistor. In addition, an insulator for forming a mask for the convex portion can also be provided in a manner that contacts the upper surface of the convex portion. In addition, although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex portion.

[0437] Notice, Figure 22 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0438] <Capacitor 100>

[0439] Capacitor 100 is provided above transistor 200. Capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Insulator 130 is preferably an insulator that can be used as insulator 286 described in the above embodiment.

[0440] Alternatively, for example, the conductor 112 provided on the conductor 240 may be formed simultaneously with the conductor 110. The conductor 112 serves as a plug or wiring for electrically connecting the capacitor 100, the transistor 200, or the transistor 300.

[0441] exist Figure 22 In the embodiment, the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this and a stacked structure of two or more layers may be used. For example, a conductor having high contact with the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0442] In addition, the insulator 130 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like, and can be provided in a stacked layer or a single layer.

[0443] For example, insulator 130 preferably comprises a laminated structure of a material having a high dielectric constant (high-k) and a material having a high dielectric constant (high-k). This structure allows capacitor 100 to include a high dielectric constant (high-k) insulator to ensure sufficient capacitance and an insulator having a high dielectric constant (high-k) to improve dielectric constant (high-k) stress resistance, thereby suppressing electrostatic breakdown of capacitor 100.

[0444] Note that insulators that are high dielectric constant (high-k) materials (materials with a relatively high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like.

[0445] On the other hand, materials with high insulating stress resistance (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, silicon oxide with pores, resins, etc.

[0446] <Wiring Layer>

[0447] A wiring layer, including an interlayer film, wiring, and plugs, may also be provided between the various structures. Furthermore, the wiring layer may be provided in multiple layers depending on the design. In the case of a conductor that functions as a plug or a wiring, the same reference numeral may sometimes be used to represent multiple structures. Furthermore, in this specification and other text, a wiring and a plug electrically connected to the wiring may also be considered a single component. In other words, a portion of a conductor may sometimes function as wiring, and a portion of the conductor may sometimes function as a plug.

[0448] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on transistor 300. Furthermore, conductors 328 and 330, etc., which are electrically connected to capacitor 100 and transistor 200, are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 serve as plugs or wiring.

[0449] Alternatively, the insulator used as an interlayer film may be used as a planarization film to cover the concavo-convex shape thereunder. For example, to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0450] A wiring layer may be provided on the insulator 326 and the conductor 330. Figure 22 Insulator 350, insulator 352, and insulator 354 are stacked in this order. In addition, conductor 356 is formed in insulator 350, insulator 352, and insulator 354. Conductor 356 serves as a plug or wiring.

[0451] Similarly, insulators 210, 212, 214, and 216 are filled with conductors 218 and the conductors (conductors 205) that constitute transistor 200. Conductor 218 serves as a plug or wiring for electrically connecting capacitor 100 or transistor 300. Furthermore, insulator 150 is provided over conductor 120 and insulator 130.

[0452] Here, similar to the insulator 241 shown in the above embodiment, insulator 217 is provided so as to contact the side surface of conductor 218, which serves as a plug. Insulator 217 is provided so as to contact the inner walls of the openings in insulators 210, 212, 214, and 216. In other words, insulator 217 is provided between conductor 218 and insulators 210, 212, 214, and 216. Since conductor 205 can be formed in parallel with conductor 218, insulator 217 is sometimes formed so as to contact the side surface of conductor 205.

[0453] Insulator 217 can be made of, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Insulator 217 is provided in contact with insulators 210, 212, 214, 216, and 222. This prevents impurities such as water and hydrogen from entering oxide 230 from insulators 210 and 216 through conductor 218. Silicon nitride is particularly preferred because it has a high barrier property against hydrogen. Furthermore, it prevents oxygen contained in insulators 210 and 216 from being absorbed by conductor 218.

[0454] The insulator 217 can be formed using the same method as the insulator 241. For example, silicon nitride can be formed using PEALD, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0455] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

[0456] For example, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material based on the function of the insulator.

[0457] For example, insulator 150, insulator 280, insulator 210, insulator 352 and insulator 354 preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably contains silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with resin, a laminated structure with thermal stability and a low relative dielectric constant can be achieved. As resins, for example, polyesters, polyolefins, polyamides (nylon, aromatic polyamide, etc.), polyimides, polycarbonates, acrylic resins, etc. can be cited.

[0458] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that inhibits the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators that inhibit the permeation of impurities such as hydrogen and oxygen can be used as insulators 214, 212, and 350.

[0459] As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, and silicon nitride can be used.

[0460] As conductors that can be used for wiring and plugs, preferably used are materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0461] For example, conductors 328, 330, 356, 218, and 240 may be formed of metal materials, alloy materials, metal nitride materials, metal oxide materials, or the like, formed from the above materials, in a single layer or in a stacked layer. Preferably, a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and electrical conductivity, is used, with tungsten being particularly preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. Using a low-resistance conductive material can reduce wiring resistance.

[0462] <Wiring or Plug Provided with an Oxide Semiconductor Layer>

[0463] Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In this case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided therewith.

[0464] For example, in Figure 22 In the embodiment, the insulator 241 is preferably provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, and 283, the insulator 224 and the transistor 200 can have a structure sealed by the insulator having a barrier property.

[0465] That is, the insulator 241 can be provided to prevent excess oxygen in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, an impurity, from diffusing into the transistor 200 through the conductor 240.

[0466] Insulator 241 is preferably an insulating material that inhibits the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide is preferably used. Silicon nitride is particularly preferred because it has a high barrier property against hydrogen. Alternatively, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide may be used.

[0467] As in the above embodiment, the transistor 200 is preferably sealed by the insulators 212, 214, 282, and 283. This structure can reduce the mixing of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0468] Here, conductor 240 penetrates insulator 283 and insulator 282, conductor 218 penetrates insulator 214, insulator 212, and insulator 210, and, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters into insulators 212, 214, 282, and 283 through conductor 240 and conductor 218. Thus, transistor 200 can be more securely sealed by insulators 212, 214, 282, 283, insulator 241, and insulator 217, while reducing the amount of impurities such as hydrogen contained in insulator 274 and the like that enter from the outside.

[0469] Furthermore, as described in the above embodiment, insulators 216, 224, 280, 250, and 274 are preferably formed using a film formation method using a gas that reduces or eliminates hydrogen atoms. This can reduce the hydrogen concentration in insulators 216, 224, 280, 250, and 274.

[0470] In this way, the hydrogen concentration of the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration of the oxide 230 can be reduced.

[0471] <cutting line>

[0472] The following describes the dicing lines (sometimes also referred to as dividing lines, splitting lines, or cutting lines) used when dividing a large-area substrate into individual semiconductor components to obtain multiple chip-shaped semiconductor devices. In some cases, for example, the dicing method involves first forming grooves (dicing lines) in the substrate to separate the semiconductor components. The semiconductor components are then cut along the dicing lines to obtain multiple separated (divided) semiconductor devices.

[0473] Here, for example, Figure 22 As shown, it is preferable to design the insulator 283 so that the region in contact with the insulator 212 overlaps the cut line. That is, openings are provided in the insulators 282, 280, 272, 224, 222, 216, and 214 near the region serving as the cut line at the edge of the memory cell including the plurality of transistors 200.

[0474] That is, insulator 212 is in contact with insulator 283 in the openings provided in insulator 282, insulator 280, insulator 272, insulator 224, insulator 222, insulator 216, and insulator 214. Forming insulator 212 and insulator 283 using the same material and the same method can improve adhesion. For example, silicon nitride is preferably used.

[0475] With this structure, transistor 200 can be surrounded by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even when the substrate is divided into multiple chips for each circuit region in which the semiconductor device described in this embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surfaces of the divided substrates and diffusing into transistor 200.

[0476] Furthermore, by adopting this structure, excess oxygen in insulator 280 and insulator 224 can be prevented from diffusing to the outside. Consequently, excess oxygen in insulator 280 and insulator 224 is efficiently supplied to the channel-forming oxide in transistor 200. This oxygen reduces oxygen vacancies in the channel-forming oxide in transistor 200. Consequently, the channel-forming oxide in transistor 200 can be made into an oxide semiconductor with a low defect state density and stable characteristics. This means that variations in the electrical characteristics of transistor 200 can be suppressed while improving reliability.

[0477] Note that in Figure 22 The shape of the capacitor 100 in the memory device shown in FIG. 1 is a planar type, but the memory device shown in this embodiment is not limited to this. Figure 23 As shown, the capacitor 100 may also be in a cylindrical shape. Figure 23 The structure below the insulator 150 of the memory device shown is similar to Figure 22 The semiconductor devices shown are the same.

[0478] Figure 23 Capacitor 100 shown includes insulator 150 on insulator 130, insulator 142 on insulator 150, conductor 115 arranged in openings formed in insulator 150 and insulator 142, conductor 115 and insulator 145 on insulator 142, conductor 125 on insulator 145, and conductor 125 and insulator 152 on insulator 145. Here, at least a portion of conductor 115, insulator 145, and conductor 125 are arranged in openings formed in insulator 150 and insulator 142.

[0479] Conductor 115 serves as the lower electrode of capacitor 100, conductor 125 serves as the upper electrode of capacitor 100, and insulator 145 serves as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper electrode and the lower electrode are opposed to each other through the dielectric not only on the bottom surface but also on the side surfaces in the openings of insulator 150 and insulator 142, thereby increasing the electrostatic capacitance per unit area. The deeper the opening, the greater the electrostatic capacitance of capacitor 100. In this way, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or high integration of semiconductor devices can be promoted.

[0480] As the insulator 152, an insulator that can be used as the insulator 280 can be used. In addition, as the insulator 142, an insulator that is used as an etching stopper when forming an opening for the insulator 150 and can be used for the insulator 214 is preferably used.

[0481] Furthermore, the openings formed in insulators 150 and 142 can have a rectangular shape, a polygonal shape other than a rectangular shape, a polygonal shape with curved corners, or a circular shape such as an ellipse when viewed from above. It is preferred that the area of ​​overlap between the opening and transistor 200 when viewed from above be large. This structure can reduce the area occupied by the semiconductor device including capacitor 100 and transistor 200.

[0482] Conductor 115 is arranged so as to contact the openings formed in insulator 142 and insulator 150. The top surface of conductor 115 is preferably substantially aligned with the top surface of insulator 142. Furthermore, the bottom surface of conductor 115 contacts conductor 110 through the opening of insulator 130. Conductor 115 is preferably formed by ALD or CVD, for example, and any conductor that can be used for conductor 205 can be used.

[0483] Insulator 145 is arranged to cover conductor 115 and insulator 142. For example, insulator 145 is preferably formed by an ALD method or a CVD method. Examples of insulator 145 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. Insulator 145 may have a stacked-layer structure or a single-layer structure. For example, insulator 145 may include an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0484] The insulator 145 is preferably a laminated structure of a material having a high dielectric stress resistance such as silicon oxynitride or a high dielectric constant (high-k) material. Alternatively, a laminated structure of a material having a high dielectric stress resistance and a high dielectric constant (high-k) material may be used.

[0485] Note that examples of insulators made of high-k materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials allows capacitor 100 to maintain sufficient capacitance even when insulator 145 is thickened. By thickening insulator 145, leakage current generated between conductors 115 and 125 can be suppressed.

[0486] On the other hand, as materials with high insulation stress resistance, there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, resin, etc. For example, a silicon nitride (SiN) layer formed by ALD method can be used. x ), silicon oxide (SiOx ), silicon nitride (SiN x By using such an insulator with high dielectric strength, dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

[0487] Conductor 125 is arranged to fill the openings formed in insulator 142 and insulator 150. Conductor 125 is electrically connected to wiring 1005 via conductor 140 and conductor 153. Conductor 125 is preferably formed by ALD or CVD, for example, and any conductor that can be used for conductor 205 can be used.

[0488] Furthermore, the conductor 153 is provided on the insulator 154 and is covered by the insulator 156. The conductor that can be used for the conductor 112 can be used as the conductor 153, and the insulator that can be used for the insulator 152 can be used as the insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 140 and serves as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0489] [Storage device 2]

[0490] Figure 24 An example of a semiconductor device (memory device) using one embodiment of the present invention is described.

[0491] <Structural Example of Memory Device>

[0492] Figure 24 is a cross-sectional view of a semiconductor device including a memory device 290 . Figure 24 The memory device 290 is shown except Figures 1A to 1D In addition to transistor 200 , a capacitive device 292 is shown. Figure 24 This corresponds to a cross-sectional view of the transistor 200 along the channel length direction.

[0493] The capacitor device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 covering the insulator 272. That is, the capacitor device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. In addition, one of the pair of electrodes included in the capacitor device 292, namely the conductor 242b, can also serve as the source electrode of the transistor. In addition, the dielectric layer included in the capacitor device 292 can also serve as a protective layer provided in the transistor, namely the insulator 271 and the insulator 272. Therefore, the manufacturing process of the capacitor device 292 can also use part of the manufacturing process of the transistor, so a semiconductor device with high productivity can be obtained. Furthermore, since one of the pair of electrodes included in the capacitor element 292, namely the conductor 242b, also serves as the source electrode of the transistor, the area for arranging the transistor and the capacitor element can be reduced.

[0494] Note that, for example, the material that can be used for the conductor 242 may be used as the conductor 294 .

[0495] <Variation Examples of Memory Devices>

[0496] The following uses Figure 25A 、 Figure 25B 、 Figure 26 and Figure 27 An example of a semiconductor device including the transistor 200 and the capacitor 292 according to one embodiment of the present invention, which is different from the semiconductor device described in the above-mentioned <Structural Example of Memory Device>, will be described. Figure 25A 、 Figure 25B 、 Figure 26 and Figure 27 Among the semiconductor devices shown in the embodiment and the example of the structure of the memory device, the semiconductor device having the same structure as the semiconductor device shown in the embodiment and the example of the structure of the memory device (see Figure 24 ) structures having the same functions are denoted by the same reference numerals. In this section, the transistor 200 and the capacitor 292 may be made of the same materials as those described in detail in the above embodiment and in the <Structure Example of Memory Device>.

[0497] <<Memory Device Modification Example 1>>

[0498] Below, use Figure 25A An example of a semiconductor device 600 including the transistor 200 a , the transistor 200 b , the capacitor 292 a , and the capacitor 292 b according to one embodiment of the present invention will be described.

[0499] Figure 25AFIG2 is a cross-sectional view taken along the channel length of semiconductor device 600, which includes transistor 200a, transistor 200b, capacitor 292a, and capacitor 292b. Semiconductor device 600 includes: conductor 242b; insulator 271b on conductor 242b; insulator 272 in contact with the top surface, side surfaces, and side surfaces of insulator 271b; and conductor 294 covering insulator 272. Capacitor 292a includes: conductor 242a; insulator 271a on conductor 242a; insulator 272 in contact with the top surface, side surfaces, and side surfaces of insulator 271a; and conductor 294a covering insulator 272. Capacitive device 292b includes conductor 242b, insulator 271b on conductor 242b, insulator 272 in contact with the top surface, side surfaces of insulator 271b, and side surfaces of conductor 242b, and conductor 294b covering insulator 272.

[0500] like Figure 25A As shown, semiconductor device 600 has an axisymmetric structure with the dotted line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode and drain electrode of transistor 200a and the source electrode and drain electrode of transistor 200b. In addition, insulator 271c is provided on conductor 242c. Conductor 240, which serves as a plug, is used to connect conductor 246, which serves as wiring, to transistors 200a and 200b. In this way, by adopting the above-mentioned structure as the connection relationship between two transistors, two capacitor devices, wiring, and plugs, a semiconductor device that can achieve miniaturization or high integration can be provided.

[0501] The structures and effects of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b can be referred to. Figures 1A to 1D and Figure 24 An example of the structure of a semiconductor device is shown.

[0502] <<Variation Example 2 of Memory Device>>

[0503] In the above, the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b are shown as examples of the structure of the semiconductor device, but the semiconductor device described in this embodiment is not limited to this. Figure 25BAs shown, a structure in which semiconductor device 600 and a semiconductor device having a structure similar to semiconductor device 600 are connected via a capacitor portion may also be employed. In this specification, a semiconductor device including transistor 200a, transistor 200b, capacitor 292a, and capacitor 292b is referred to as a unit. The structures of transistor 200a, transistor 200b, capacitor 292a, and capacitor 292b can refer to the description of transistor 200a, transistor 200b, capacitor 292a, and capacitor 292b described above.

[0504] Figure 25B 1 is a cross-sectional view showing a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b, and a cell having the same structure as the semiconductor device 600, which are connected via a capacitor portion.

[0505] like Figure 25B As shown, the conductor 294b used as one electrode of the capacitor 292b included in the semiconductor device 600 also serves as one electrode of the capacitor included in the semiconductor device 601 having the same structure as the semiconductor device 600. In addition, although not shown, the conductor 294a used as one electrode of the capacitor 292a included in the semiconductor device 600 also serves as the left side of the semiconductor device 600, that is, Figure 25B In addition, on the right side of the semiconductor device 601, that is, Figure 25B The cells in the A2 direction also have the same structure. In other words, a cell array (also called a memory device layer) can be formed. By adopting the structure of the cell array, the distance between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and achieving high integration. In addition, by Figure 25B The structure of the cell array shown is arranged in a matrix, and a matrix cell array can be constructed.

[0506] As described above, by forming the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b in the structure described in this embodiment, the cell area can be reduced, thereby miniaturizing or highly integrating a semiconductor device constituting a cell array.

[0507] Furthermore, instead of arranging the cell array in a planar shape, the cell array may be stacked. Figure 26 FIG. 4 is a cross-sectional view showing a structure of a cell array 610 having n layers stacked. Figure 26 As shown, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), cells can be integrated without increasing the occupied area of ​​the cell arrays. In other words, a 3D cell array can be constructed.

[0508] <<Memory Device Modification Example 3>>

[0509] Figure 27 An example is shown in which the memory cell 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4 ).

[0510] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420 .

[0511] The memory device 420 is electrically connected to the memory device 420 included in the different memory device layer 415 and the transistor 200T included in the transistor layer 413 through the conductor 424 and the conductor 205 .

[0512] Memory cell 470 is sealed by insulators 212, 214, 282, and 283 (hereinafter referred to as a sealed structure for convenience). Insulator 274 is provided around insulator 283. Conductor 440 is provided between insulators 274, 283, and 212, and is electrically connected to element layer 411.

[0513] In addition, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0514] A material having a high barrier property against hydrogen is preferably used for the insulator 212 and the insulator 283. Furthermore, a material having a function of capturing or fixing hydrogen is preferably used for the insulator 214 and the insulator 282.

[0515] Examples of materials having a high barrier property against hydrogen include silicon nitride, silicon oxynitride, etc. Furthermore, examples of materials having the function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0516] The crystal structure of the materials used for insulators 212, 214, 282, and 283 is not particularly limited; they may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferably used as a material capable of capturing or fixing hydrogen. Amorphous aluminum oxide can sometimes capture or fix more hydrogen than highly crystalline aluminum oxide.

[0517] Here, the following model can be considered as a model for the diffusion of excess oxygen in the insulator 280 into hydrogen in the oxide semiconductor in contact with the insulator 280 .

[0518] The hydrogen in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. The hydrogen reacts with the hydrogen in the oxide semiconductor through the excess oxygen in the insulator 280 to form an OH bond, and diffuses in the insulator 280 as OH. When the hydrogen atoms with the OH bond reach the material having the function of capturing or fixing hydrogen (typically, the insulator 282), they react with the oxygen atoms bonded to the atoms in the insulator 282 (for example, metal atoms, etc.), and are captured or fixed by the insulator 282. On the other hand, it can be considered that the oxygen atoms with the excess oxygen in the OH bond remain in the insulator 280 as excess oxygen. In other words, in the diffusion of this hydrogen, the excess oxygen in the insulator 280 is likely to play a mediating role.

[0519] In order to satisfy the above-mentioned model, the manufacturing process of the semiconductor device is one of the important factors.

[0520] As an example, an insulator 280 containing excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. Afterwards, heat treatment is preferably performed. Specifically, the heat treatment is performed in an oxygen-containing atmosphere, a nitrogen-containing atmosphere, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is set to be at least 1 hour, preferably at least 4 hours, and more preferably at least 8 hours.

[0521] By performing the heat treatment, hydrogen in the oxide semiconductor can be suppressed from diffusing to the outside through the insulator 280 and the insulator 282. In other words, the absolute amount of hydrogen present in the oxide semiconductor and the vicinity of the oxide semiconductor can be reduced.

[0522] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high barrier property against hydrogen, and thus can suppress hydrogen from diffusing to the outside or from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0523] Note that although the heat treatment is performed after forming the insulator 282, the present invention is not limited thereto. For example, the heat treatment may be performed after forming the transistor layer 413 or after forming the memory device layers 415_1 to 415_3. Furthermore, when hydrogen is diffused outward by the heat treatment, the hydrogen diffuses upward or laterally from the transistor layer 413. Similarly, when the heat treatment is performed after forming the memory device layers 415_1 to 415_3, the hydrogen diffuses upward or laterally.

[0524] By using the above-mentioned manufacturing process and bonding the insulator 212 and the insulator 283 together, the above-mentioned sealing structure can be obtained.

[0525] Thus, by adopting the above structure and manufacturing process, a semiconductor device using an oxide semiconductor with a reduced hydrogen concentration can be provided. This can provide a highly reliable semiconductor device. Furthermore, according to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0526] The structures, methods, and the like described in this embodiment mode can be implemented in combination with the structures, methods, and the like described in other embodiment modes or examples as appropriate.

[0527] (Implementation 3)

[0528] In this embodiment, referring to Figure 28 A device that can be used to manufacture a semiconductor device according to one embodiment of the present invention will be described.

[0529] When manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a so-called multi-chamber apparatus comprising multiple processing chambers capable of sequentially forming different types of films. Each processing chamber can perform film formation processes such as sputtering, CVD, and ALD. For example, when a single processing chamber is used as a sputtering chamber, the sputtering chamber can be connected to a gas supply system, a gas purification system connected to the gas supply system, a vacuum pump, a target material, and the like.

[0530] In addition, each processing chamber may also perform substrate cleaning, plasma processing, reverse sputtering, etching, ashing, heating, etc. By appropriately performing different processes in each processing chamber, insulator, conductor, and semiconductor films can be formed without exposure to the atmosphere.

[0531] As a semiconductor film used in one embodiment of the present invention, an oxide semiconductor film is typically used. In particular, by using an oxide semiconductor film with a low impurity concentration and a low defect state density (few oxygen vacancies), a transistor with excellent electrical characteristics can be manufactured. Here, the low impurity concentration and low defect state density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0532] In a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film, there are few carrier generation sources, so the carrier concentration can be reduced. Therefore, a transistor having a channel formation region formed in the oxide semiconductor film rarely has an electrical characteristic of a negative threshold voltage (also called a normally-on characteristic). In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density and therefore sometimes has a low trap state density. In addition, the off-state current of a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is significantly small, even when the channel width is 1×10 6For a device with a channel length of 10 μm and a source-drain voltage (drain voltage) of 1 V to 10 V, the off-state current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1×10 -13 A or below.

[0533] Typical impurities in the oxide semiconductor film include water and hydrogen. In this specification, treatments to reduce or remove water and hydrogen from the oxide semiconductor film are sometimes referred to as dehydration or dehydrogenation. Treatments to add oxygen to the oxide semiconductor film are sometimes referred to as overoxidation, and a state in which the film contains oxygen exceeding the stoichiometric composition is sometimes referred to as an excess oxygen state.

[0534] Here, by continuously forming different types of films as an oxide semiconductor, an insulator or conductor located in a lower layer of the oxide semiconductor, and an insulator or conductor located in an upper layer of the oxide semiconductor without being exposed to the atmosphere, an essentially high-purity intrinsic oxide semiconductor film with a reduced concentration of impurities (especially hydrogen and water) can be formed.

[0535] First, use Figure 28 A detailed structural example of a device that can be used when manufacturing a semiconductor device according to one embodiment of the present invention is described. Figure 28 The device shown can continuously form a semiconductor film, an insulator or conductor located below the semiconductor film, and an insulator or conductor located above the semiconductor film, thereby suppressing impurities (especially hydrogen and water) that may enter the semiconductor film.

[0536] Figure 28 A top view of a clustered multi-chamber device 4000 is schematically shown.

[0537] The device 4000 includes: an atmospheric side substrate supply chamber 4010; an atmospheric side substrate transfer chamber 4012 for transferring substrates from the atmospheric side substrate supply chamber 4010; a loading lock chamber 4020a for transferring substrates and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unloading lock chamber 4020b for moving substrates out and switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transfer chamber 4029 and a transfer chamber 4039 for transferring substrates in a vacuum; a movable chamber 4030a and a movable chamber 4030b for connecting the transfer chamber 4029 and the transfer chamber 4039; and processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d and 4034e for performing film formation or heating.

[0538] Multiple processing chambers can perform different processes in parallel. This makes it easy to manufacture a stacked structure of different types of films. In addition, the maximum number of parallel processes that can be performed corresponds to the number of processing chambers. For example, Figure 28 The apparatus 4000 shown includes seven processing chambers, thereby enabling seven film forming processes to be performed continuously using one apparatus (also referred to as "in-situ" in this specification) without being exposed to the atmosphere.

[0539] On the other hand, in a stacked structure, the number of stacked layers that can be manufactured without exposure to the atmosphere is not necessarily the same as the number of processing chambers. For example, if the desired stacked structure has multiple layers of the same material, these layers can be formed in a single processing chamber, making it possible to manufacture a stacked structure having a greater number of stacked layers than the number of processing chambers provided.

[0540] The atmospheric side substrate supply chamber 4010 may also include a cassette interface 4014 for storing substrates and an alignment port 4016 for aligning substrates. Figure 28 (Including three) box interface 4014.

[0541] Furthermore, the atmospheric-side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the mobile chamber 4030a, the mobile chamber 4030b, and the processing chambers 4024a and 4024b. The mobile chambers 4030a and 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. Furthermore, the transfer chamber 4039 is connected to the mobile chamber 4030a, the mobile chamber 4030b, the processing chambers 4034a, 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0542] Furthermore, gate valves 4028 or 4038 are provided at the connection points of each chamber, allowing each chamber, except for the atmospheric-side substrate supply chamber 4010 and the atmospheric-side substrate transfer chamber 4012, to be independently maintained in a vacuum state. Furthermore, the atmospheric-side substrate transfer chamber 4012 includes a transfer robot 4018. The transfer chamber 4029 includes a transfer robot 4026, and the transfer chamber 4039 includes a transfer robot 4036. The transfer robots 4018, 4026, and 4036 each include multiple movable parts and an arm for holding a substrate, and can transfer substrates to each chamber.

[0543] In addition, the number of transfer chambers, processing chambers, load lock chambers, unload lock chambers and moving chambers is not limited to the above number, and the number can be appropriately determined according to the space in which they are installed or process conditions.

[0544] In particular, when a plurality of transfer chambers are included, it is preferable to include two or more moving chambers between one transfer chamber and the other transfer chambers. Figure 28 As shown, when the transfer chamber 4029 and the transfer chamber 4039 are included, it is preferable to arrange the moving chamber 4030a and the moving chamber 4030b in parallel between the transfer chamber 4029 and the transfer chamber 4039.

[0545] By arranging the movable chamber 4030a and the movable chamber 4030b in parallel, for example, the following processes can be performed simultaneously: the transfer robot 4026 transfers a substrate to the movable chamber 4030a; and the transfer robot 4036 transfers a substrate to the movable chamber 4030b. Furthermore, the following processes can be performed simultaneously: the transfer robot 4026 unloads a substrate from the movable chamber 4030b; and the transfer robot 4036 unloads a substrate from the movable chamber 4030a. In other words, by operating multiple transfer robots simultaneously, productivity is improved.

[0546] in addition, Figure 28 Although an example is shown in which one transfer chamber includes one transfer robot and is connected to a plurality of processing chambers, the present invention is not limited to this structure and one transfer chamber may include a plurality of transfer robots.

[0547] In addition, one or both of the transfer chamber 4029 and the transfer chamber 4039 are connected to a vacuum pump and a cryopump via a valve. Thus, the transfer chamber 4029 and the transfer chamber 4039 can be evacuated from atmospheric pressure to low vacuum or medium vacuum (several hundred Pa to about 0.1 Pa) using the vacuum pump, and then the valves can be switched to evacuate from medium vacuum to high vacuum or ultra-high vacuum (0.1 Pa to 1×10 -7 Pa) for exhaust.

[0548] Alternatively, for example, two or more cryopumps can be connected in parallel to a single transfer chamber. By having multiple cryopumps, even if one cryopump is undergoing regeneration, another cryopump can be used for evacuation. Note that regeneration, as described above, refers to the process of releasing molecules (or atoms) accumulated in the cryopump. When a cryopump accumulates too many molecules (or atoms), its evacuation capacity decreases, so it is preferable to regenerate it regularly.

[0549] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can perform different processes in parallel. In other words, each processing chamber can perform film formation, heat treatment, or plasma treatment using sputtering, CVD, MBE, PLD, ALD, or the like on a substrate placed therein. Furthermore, the film formation process can be performed after the heat treatment or plasma treatment in each processing chamber.

[0550] The apparatus 4000 includes multiple processing chambers, allowing substrates to be transferred between processes without being exposed to the atmosphere, thereby suppressing adsorption of impurities onto the substrates. Furthermore, since each processing chamber can perform different film deposition, heat treatment, or plasma treatment, the order of film deposition and heat treatment can be freely set.

[0551] Each processing chamber may also be connected to a vacuum pump via a valve. As the vacuum pump, for example, a dry pump, a mechanical booster pump, etc. may be used.

[0552] In addition, each processing chamber may be connected to a power source capable of generating plasma. As such, a DC power source, an AC power source, or a high-frequency (RF, microwave, etc.) power source may be provided. Alternatively, a pulse generator may be connected to the DC power source.

[0553] In addition, the processing chamber may also be connected to a gas purification device via a gas supply device. In addition, it is preferable to provide a gas supply device and a gas purification device according to the number of gas types.

[0554] For example, when film formation using sputtering is performed in a processing chamber, the processing chamber may also include a target, a backing plate connected to the target, a cathode facing the target with the backing plate interposed therebetween, an anti-fog plate, and a substrate stage. Furthermore, for example, the substrate stage may also include a structure for applying high-frequency power and thus applying substrate bias power, a substrate holding mechanism for holding the substrate, and a backside heater for heating the substrate from the backside.

[0555] Furthermore, the substrate stage is maintained approximately perpendicular to the floor surface during film formation and approximately horizontal to the floor surface during substrate transfer. By maintaining the substrate stage approximately perpendicular to the floor surface, the probability of dust and particles that may enter during film formation adhering to the substrate can be reduced compared to maintaining the substrate stage horizontally. However, maintaining the substrate stage approximately perpendicular (90°) to the floor surface can cause the substrate to fall. Therefore, the angle of the substrate stage relative to the floor surface is preferably set to be at least 80° and less than 90°.

[0556] Note that the structure of the substrate stage is not limited to the one described above. For example, a structure in which the substrate stage is approximately parallel to the floor surface can also be employed. In this configuration, the target is placed below the substrate stage, and the substrate is placed between the target and the stage. Furthermore, the substrate stage may include a substrate securing device or mechanism to prevent the substrate from falling.

[0557] Furthermore, installing an anti-fog plate in the processing chamber can prevent particles sputtered from the target from settling in unwanted areas. Furthermore, the anti-fog plate is preferably processed to prevent the deposited sputtered particles from peeling off. For example, sandblasting to increase surface roughness or creating irregularities on the anti-fog plate surface can be used.

[0558] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0559] The target material can be a conductor, an insulator, or a semiconductor. For example, when an oxide semiconductor such as a metal oxide is used as the target material, an oxide semiconductor film can be formed in the processing chamber. Furthermore, when a metal oxide is used as the target material, an oxynitride semiconductor film can be formed by using nitrogen gas as the film-forming gas.

[0560] In addition, each processing chamber can also be connected to a gas supply device through a gas heating mechanism. The gas heating mechanism is connected to a gas purification device through a gas supply device. As the gas introduced into the processing chamber, a gas having a dew point of below -80°C, preferably below -100°C, and more preferably below -120°C can be used. For example, oxygen gas, nitrogen gas and rare gas (argon gas, etc.) can be used. In addition, the gas introduced into the processing chamber can be heated to above 40°C and below 400°C, preferably to above 50°C and below 200°C, by using a gas heating mechanism. Note that the gas heating mechanism, gas supply device and gas purification device can be set according to the number of gas types.

[0561] In addition, each processing chamber can also be connected to a turbomolecular pump and a vacuum pump through a valve. In addition, each processing chamber can also be provided with a low temperature cold trap.

[0562] A cryogenic cold trap is a mechanism that can adsorb molecules (or atoms) with a relatively high melting point, such as water. Turbomolecular pumps can stably exhaust large molecules (or atoms) and have a low maintenance frequency, so they have an advantage in productivity, but their ability to exhaust hydrogen and water is relatively low. Therefore, in order to improve the ability to drain water, etc., a cryogenic cold trap can be used. The temperature of the refrigerator of the cryogenic cold trap is below 100K, preferably below 80K. In addition, when the cryogenic cold trap has multiple refrigerators, the temperature of each refrigerator can be made different to efficiently exhaust, so it is preferred. For example, the temperature of the refrigerator in the first stage can be set to below 100K, and the temperature of the refrigerator in the second stage can be set to below 20K.

[0563] The exhaust method for the processing chamber is not limited to the above method. The same exhaust method as that for the connected transfer chamber (using a cryopump and a vacuum pump) can also be used. Furthermore, the exhaust method for the transfer chamber can also be the same exhaust method as that for the processing chamber (using a turbomolecular pump and a vacuum pump).

[0564] In particular, a combination of a vacuum pump and a cryogenic trap can be used as a method for exhausting a process chamber for forming an oxide semiconductor film. The exhaust method provided in a process chamber for forming an oxide semiconductor film preferably has at least the function of adsorbing water molecules.

[0565] In addition, in a process chamber for forming an oxide semiconductor film, it is preferable that the partial pressure of hydrogen molecules is 1×10 -2 Pa or less and the partial pressure of water molecules is 1×10 -4 Pa or less. In addition, the pressure in the standby state of the processing chamber for forming the oxide semiconductor film is 8.0×10 -5 Pa or less, preferably 5.0×10 -5 Pa or less, more preferably 1.0×10 -5 Pa or less. The above-mentioned values ​​of the partial pressure of hydrogen molecules and the partial pressure of water molecules are values ​​for both when the processing chamber performing sputtering is in a standby state and in a film forming state (plasma is in a discharge state).

[0566] The total pressure and partial pressure of the processing chamber can be measured using a mass analyzer. For example, a quadrupole mass analyzer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0567] By setting the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the processing chamber to the above ranges, the concentration of impurities in the formed oxide semiconductor film can be reduced.

[0568] In particular, by using each processing chamber for film formation processing using sputtering, part of the structure of the transistor 200 described in the above embodiment can be manufactured using a stacked structure continuously formed in-situ.

[0569] In the method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are continuously formed using the apparatus 4000. Furthermore, the oxide film 230A, the oxide film 230B, and the oxide film 243A are continuously formed using the apparatus 4000. Furthermore, the conductive film 242A, the insulating film 271A, and the conductive film 248A are continuously formed using the apparatus 4000.

[0570] In other words, the insulator 212, the insulator 214, and the insulator 216 can be formed continuously without being exposed to the atmosphere. Furthermore, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed continuously without being exposed to the atmosphere. Furthermore, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be formed continuously without being exposed to the atmosphere.

[0571] By adopting the above structure, a stacked film can be formed in which impurities (typically, water, hydrogen, etc.) are completely removed. As a result, each interface of the stacked film is not exposed to the atmosphere, and the impurity concentration is reduced.

[0572] Furthermore, for example, when heat treatment is performed in a processing chamber, the processing chamber may include multiple heating stages capable of accommodating substrates. The heating stages may also have a multi-layer structure. By increasing the number of heating stages, multiple substrates can be heat treated simultaneously, thereby improving productivity.

[0573] As a heating mechanism that can be used in the processing chamber, for example, a heating mechanism that uses a resistance heating element or the like for heating can also be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation of a medium such as a heated gas to perform heating can also be used. For example, RTA (Rapid Thermal Anneal) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTA heats the object to be processed by radiating light (electromagnetic waves) emitted by lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas is used as the gas.

[0574] The load lock chamber 4020a may also include a substrate transfer stage, a backside heater for heating the substrate from the backside, and the like. The pressure in the load lock chamber 4020a is increased from a reduced pressure state to atmospheric pressure. When the pressure in the load lock chamber 4020a reaches atmospheric pressure, the transfer robot 4018 located in the atmospheric-side substrate transfer chamber 4012 receives the substrate from the substrate transfer stage. After the load lock chamber 4020a is evacuated and reduced in pressure, the transfer robot 4026 located in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0575] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via valves, and the unload lock chamber 4020b may have the same structure as the load lock chamber 4020a.

[0576] The atmospheric-side substrate transfer chamber 4012 includes a transfer robot 4018, allowing the transfer robot 4018 to transfer substrates between the cassette interface 4014 and the load lock chamber 4020a. Furthermore, a mechanism such as a HEPA filter (High Efficiency Particulate Air Filter) may be installed above the atmospheric-side substrate transfer chamber 4012 and the atmospheric-side substrate supply chamber 4010 to prevent the intrusion of dust and particles. Furthermore, the cassette interface 4014 can accommodate multiple substrates.

[0577] By using the apparatus 4000 described above to successively form an insulating film, a semiconductor film, and a conductive film without exposing them to the atmosphere, entry of impurities into the semiconductor film can be effectively suppressed.

[0578] Thus, by using the apparatus of one embodiment of the present invention, a stacked structure including semiconductor films can be continuously formed. This allows the production of a semiconductor film in which the absorption of impurities such as hydrogen and water into the semiconductor film is suppressed and the defect state density is low.

[0579] The structures, methods, and the like described in this embodiment mode can be used in combination as appropriate with the structures, methods, and the like described in other embodiment modes or examples.

[0580] (Implementation 4)

[0581] In this embodiment, referring to Figure 29A 、 Figure 29B as well as Figure 30A and Figure 30H This article describes a memory device using a transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor (hereinafter sometimes referred to as an OS memory device) using an oxide as a semiconductor according to one embodiment of the present invention. An OS memory device is a memory device that includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely low, the OS memory device has excellent retention characteristics, making it suitable for use as a nonvolatile memory.

[0582] <Configuration Example of Storage Device>

[0583] Figure 29A An example of the structure of an OS memory device is shown. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0584] Column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is connected to the memory cells included in memory cell array 1470, and its details are described below. The amplified data signal is output as data signal RDATA to the outside of memory device 1400 via output circuit 1440. Furthermore, row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and is capable of selecting the row to be accessed.

[0585] The memory device 1400 is externally supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Furthermore, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0586] Control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is a chip enable signal, control signal WE is a write enable signal, and control signal RE is a read enable signal. The signals processed by control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0587] Memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting memory cell array 1470 and row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a column, and other factors. Furthermore, the number of wirings connecting memory cell array 1470 and column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a row, and other factors.

[0588] In addition, although Figure 29A 14 shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. Figure 29B As shown, the memory cell array 1470 may be provided so as to overlap a portion of the peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.

[0589] exist Figures 30A to 30H An example of a structure of a memory cell that can be suitably used for the above-mentioned memory cell MC is described in FIG.

[0590] [DOSRAM]

[0591] Figures 30A to 30C An example of a circuit structure of a DRAM memory cell is shown. In this specification, etc., a DRAM using a 1-OS transistor-1-capacitor type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 30A The illustrated memory cell 1471 includes a transistor M1 and a capacitor CA. Furthermore, transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0592] A first terminal of transistor M1 is connected to a first terminal of capacitor CA, a second terminal of transistor M1 is connected to wiring BIL, a gate of transistor M1 is connected to wiring WOL, and a back gate of transistor M1 is connected to wiring BGL. A second terminal of capacitor CA is connected to wiring CAL.

[0593] Wiring BIL serves as a bit line, and wiring WOL serves as a word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. When writing or reading data, a low-level potential is preferably applied to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0594] Here, Figure 30A The storage unit 1471 shown corresponds to Figure 24 That is, the transistor M1 corresponds to the transistor 200 , and the capacitor CA corresponds to the capacitive device 292 .

[0595] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt Figure 30B The back gate of the transistor M1 is not connected to the wiring BGL but to the wiring WOL as in the memory cell 1472 shown in FIG. Figure 30C The memory cell 1473 shown is a memory cell composed of a transistor with a single gate structure, that is, a transistor M1 that does not include a back gate.

[0596] When the semiconductor device described in the above embodiment is used in the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. In other words, because the transistor M1 can retain written data for a long time, the refresh frequency of the memory cell can be reduced. In addition, the memory cell refresh operation can be omitted. In addition, because the leakage current is extremely low, multi-valued data or analog data can be retained in the memory cells 1471, 1472, and 1473.

[0597] Furthermore, in DOSRAM, when a sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cell.

[0598] [NOSRAM]

[0599] Figures 30D to 30G An example circuit configuration of a gain unit type memory cell with two transistors and one capacitor is shown. Figure 30D The illustrated memory cell 1474 includes a transistor M2, a transistor M3, and a capacitor CB. Furthermore, transistor M2 includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and other documents, a memory device including a gain-unit type memory cell using an OS transistor for transistor M2 is sometimes referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0600] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, a gate of transistor M2 is connected to wiring WOL, and a back gate of transistor M2 is connected to wiring BGL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to a first terminal of capacitor CB.

[0601] Wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring WOL serves as a word line. Wiring CAL serves as a wiring for applying a specified potential to the second terminal of capacitor CB. When writing, retaining, and reading data, a low-level potential is preferably applied to wiring CAL. Wiring BGL serves as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0602] Here, Figure 30D The storage unit 1474 shown corresponds to Figure 22 The memory device shown in FIG. 1 is a block diagram of a memory device. That is, transistor M2 corresponds to transistor 200, capacitor CB corresponds to capacitor 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0603] In addition, the memory cell MC is not limited to the memory cell 1474, and its circuit structure can be changed appropriately. For example, the memory cell MC can also adopt Figure 30E The back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL as in the memory cell 1475 shown in FIG. Figure 30F The memory cell MC may also have a single-gate structure transistor, that is, a memory cell composed of a transistor M2 without a back gate, such as the memory cell 1476 shown in FIG. Figure 30G The memory cell 1477 shown has a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL.

[0604] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely low. Thus, since the written data can be retained for a long time by the transistor M2, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely low, multi-valued data or analog data can be retained in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0605] In addition, the transistor M3 may also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The field effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, a Si transistor may also be used as the transistor M3 used as a readout transistor. In addition, by using a Si transistor for the transistor M3, the transistor M2 may be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0606] Alternatively, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured with only n-type transistors.

[0607] also, Figure 30H An example of a gain unit type memory cell having three transistors and one capacitor is shown. Figure 30H The illustrated memory cell 1478 includes transistors M4 to M6 and a capacitor CC. Capacitor CC can be provided as appropriate. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0608] The transistor M4 is an OS transistor including a back gate, and the back gate is electrically connected to the wiring BGL. Alternatively, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include a back gate.

[0609] Furthermore, transistors M5 and M6 can each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, transistors M4 to M6 can all be OS transistors. In this case, only n-type transistors can be used to form a circuit in memory cell array 1470.

[0610] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC. Using an OS transistor as the transistor M4 can minimize leakage current of the transistor M4.

[0611] Note that the structures of the peripheral circuit 1411 and the memory cell array 1470 described in this embodiment are not limited to those described above. The arrangement or function of these circuits and wiring connected to them, circuit elements, and the like may be changed, removed, or added as needed.

[0612] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on their applications. Figure 31 Various storage devices are shown in layers. The storage devices at the upper layers require faster access speeds, while the storage devices at the lower layers require larger storage capacities and higher storage densities. Figure 31, the memory implemented as registers in arithmetic processing devices such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown in order from the top.

[0613] Because registers are used to temporarily store calculation results, they are frequently accessed by processors such as CPUs. Therefore, they require higher operating speed than storage capacity. Registers also hold settings for the processors.

[0614] SRAM is used, for example, for cache memory. Cache memory has the function of copying a portion of the data stored in main memory. By copying frequently used data to cache memory, access speed to the data can be increased.

[0615] DRAM is used for main memory, for example. Main memory has the function of storing programs or data read from storage. The storage density of DRAM is approximately 0.1 to 0.3 Gbit / mm. 2 .

[0616] 3D NAND memory is used, for example, for storage. Storage has the function of storing data that needs to be stored for a long time or various programs used by a processing device. Therefore, storage requires a large storage capacity and high storage density rather than operating speed. The storage density of storage devices used for storage is generally 0.6 to 6.0 Gbit / mm. 2 .

[0617] A storage device according to one embodiment of the present invention can retain data for a long period of time and has a high operating speed. The storage device according to one embodiment of the present invention can be preferably used as a storage device located in a boundary area 901 between a cache memory layer and a main memory layer. Furthermore, the storage device according to one embodiment of the present invention can be preferably used as a storage device located in a boundary area 902 between a main memory layer and a storage layer.

[0618] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes or examples as appropriate.

[0619] (Implementation 5)

[0620] In this embodiment, referring to Figure 32A and Figure 32B An example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described. Multiple circuits (systems) are mounted on the chip 1200. The technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a system on chip (SoC).

[0621] like Figure 32A As shown, the chip 1200 includes a CPU 1211 , a GPU 1212 , one or more simulation operation units 1213 , one or more storage controllers 1214 , one or more interfaces 1215 , one or more network circuits 1216 , and the like.

[0622] Bumps (not shown) are provided on the chip 1200. Figure 32B As shown, it is connected to the first surface of the package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201, and the bumps 1202 are connected to the motherboard 1203.

[0623] Furthermore, a storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment may be applied to the DRAM 1221. Furthermore, the NOSRAM described in the above embodiment may be applied to the flash memory 1222.

[0624] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM may be applied to the memory. In addition, the GPU 1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention as the GPU 1212, image processing and product-sum operations can be performed with low power consumption.

[0625] In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and the GPU 1212, and the calculation results can be transferred from the GPU 1212 to the CPU 1211 after the calculation in the GPU 1212 is completed at high speed.

[0626] The analog operation unit 1213 includes one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. Furthermore, the analog operation unit 1213 may also include the aforementioned product-sum operation circuit.

[0627] The memory controller 1214 includes a circuit serving as a controller of the DRAM 1221 and a circuit serving as an interface with the flash memory 1222 .

[0628] The interface 1215 includes an interface circuit for connecting to external devices such as a display device, a speaker, a microphone, an image capture device, and a controller. Controllers include a mouse, a keyboard, and a game console controller. Examples of these interfaces include the Universal Serial Bus (USB) and the High-Definition Multimedia Interface (HDMI) (registered trademark).

[0629] The network circuit 1216 includes a network circuit such as a local area network (LAN) and may also include a network security circuit.

[0630] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing steps, and the chip 1200 can be manufactured at low cost.

[0631] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0632] Because the GPU module 1204 includes chip 1200 using SoC technology, its size can be reduced. Furthermore, due to its high image processing capabilities, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable (portable) game consoles. Furthermore, by utilizing the product-sum operation circuit using GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be implemented. This allows the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0633] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes, examples, etc. as appropriate.

[0634] (Implementation 6)

[0635] This embodiment mode describes an example of an electronic component and an electronic device in which the storage device described in the above embodiment modes and the like are mounted.

[0636] <Electronic Components>

[0637] First, refer to Figure 33A and Figure 33B An example of an electronic component in which the storage device 720 is incorporated will be described.

[0638] Figure 33A A perspective view of an electronic component 700 and a substrate (circuit board 704 ) on which the electronic component 700 is mounted is shown. Figure 33A The electronic component 700 shown includes a memory device 720 within a mold 711. Figure 33A In the figure, a portion of electronic component 700 is omitted to illustrate its interior. Electronic component 700 includes lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, which are electrically connected to storage device 720 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. By combining multiple electronic components and electrically connecting them on printed circuit board 702, circuit board 704 is completed.

[0639] The storage device 720 includes a driving circuit layer 721 and a storage circuit layer 722 .

[0640] Figure 33B A perspective view of an electronic component 730 is shown. Electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board). A semiconductor device 735 and multiple memory devices 720 are provided on interposer 731.

[0641] The example in which the storage device 720 is used as a high bandwidth memory (HBM) in the electronic component 730 is shown. In addition, the semiconductor device 735 can use an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0642] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0643] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal spacings. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon interposer is used, TSV (Through Silicon Via) can also be used as a through electrode.

[0644] A silicon interposer is preferably used as the interposer 731. Because silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Wiring on silicon interposers can be formed using semiconductor processes, making it easy to form fine wiring that is difficult to form using resin interposers.

[0645] To achieve a wide memory bandwidth in HBM, numerous wiring connections are required. Therefore, the interposer on which HBM is mounted must be able to form fine wiring at a high density. Therefore, a silicon interposer is preferred for HBM mounting.

[0646] Furthermore, in SiPs and MCMs using silicon interposers, reliability degradation due to differences in thermal expansion coefficients between the integrated circuit and the interposer is less likely to occur. Furthermore, due to the high surface flatness of the silicon interposer, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly suitable for 2.5D packaging (2.5D assembly), in which multiple integrated circuits are arranged horizontally on the interposer.

[0647] Alternatively, a heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the integrated circuits provided on the interposer 731 aligned in height. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the storage device 720 and the semiconductor device 735 aligned in height.

[0648] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Figure 33B This example shows electrodes 733 formed using solder balls. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 can be formed using conductive pins. Arranging conductive pins in a matrix on the bottom of the package substrate 732 enables PGA (Pin Grid Array) mounting.

[0649] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded Package), or QFN (Quad Flat Non-leaded Package) can be used.

[0650] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes or examples as appropriate.

[0651] (Implementation 7)

[0652] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiment is described. The semiconductor device described in the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an e-book reader terminal, a digital camera (including a video camera), a video playback device, a navigation system, etc.). Note that here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the above embodiment can be applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). Figures 34A to 34E Several structural examples of removable storage devices are schematically shown. For example, the semiconductor devices described in the above embodiments are processed into packaged memory chips and used in various storage devices or removable memories.

[0653] Figure 34A Schematic diagram of a USB memory device. USB memory device 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. Substrate 1104 is housed in housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on substrate 1104. The semiconductor devices described in the above embodiment modes can be incorporated into memory chip 1105 and the like.

[0654] Figure 34B This is a schematic diagram of the appearance of an SD card. Figure 34CThe figure is a schematic diagram of the internal structure of an SD card. SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. Substrate 1113 is housed in housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on substrate 1113. By also providing memory chip 1114 on the back side of substrate 1113, the capacity of SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on substrate 1113. Thus, data can be read from and written to memory chip 1114 through wireless communication between a host device and SD card 1110. The semiconductor device described in the above embodiment can be incorporated into memory chip 1114, etc.

[0655] Figure 34D This is a schematic diagram of the appearance of SSD. Figure 34E This is a schematic diagram of the internal structure of an SSD. SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. Substrate 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are mounted on substrate 1153. Memory chip 1155 serves as working memory for controller chip 1156 and, for example, a DOSRAM chip can be used. Providing memory chip 1154 on the back side of substrate 1153 also increases the capacity of SSD 1150. The semiconductor devices described in the above embodiments can be incorporated into memory chip 1154 and the like.

[0656] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes or examples as appropriate.

[0657] (Implementation 8)

[0658] A semiconductor device according to one embodiment of the present invention can be applied to a processor or chip such as a CPU or a GPU. Figures 35A to 35H Specific examples of...

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulator to a third insulator in sequence; forming a fourth insulator, a first oxide film, a second oxide film, a third oxide film, a first conductive film, a first insulating film, and a second conductive film in sequence on the third insulator; Processing the first oxide film, the second oxide film, the third oxide film, the first conductive film, the first insulating film, and the second conductive film into island shapes to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer; removing the second conductive layer; forming a fifth insulator on the fourth insulator, the first oxide, the second oxide, the first oxide layer, the first conductive layer, and the first insulating layer; forming a sixth insulator on the fifth insulator; forming an opening reaching the second oxide layer in the first oxide layer, the first conductive layer, the first insulating layer, the fifth insulator, and the sixth insulator; By forming the opening, a third oxide and a fourth oxide are formed from the first oxide layer, a first conductor and a second conductor are formed from the first conductive layer, and a seventh insulator and an eighth insulator are formed from the first insulating layer; as well as forming a fifth oxide in the opening, a ninth insulator on the fifth oxide, and a third conductor on the ninth insulator, The fifth insulator is formed by sputtering in an oxygen-containing atmosphere by applying RF power.

2. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulator to a third insulator in sequence; forming a fourth insulator, a first oxide film, a second oxide film, a third oxide film, a first conductive film, a first insulating film, and a second conductive film in sequence on the third insulator; Processing the first oxide film, the second oxide film, the third oxide film, the first conductive film, the first insulating film, and the second conductive film into island shapes to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer; removing the second conductive layer; forming a fifth insulator on the fourth insulator, the first oxide, the second oxide, the first oxide layer, the first conductive layer, and the first insulating layer; forming an opening reaching the second oxide layer in the first oxide layer, the first conductive layer, the first insulating layer, and the fifth insulator; When forming the opening, a third oxide and a fourth oxide are formed from the first oxide layer, a first conductor and a second conductor are formed from the first conductive layer, and a sixth insulator and a seventh insulator are formed from the first insulating layer; forming a fifth oxide in the opening, an eighth insulator on the fifth oxide, and a third conductor on the eighth insulator; as well as forming a ninth insulator on the fifth insulator, the fifth oxide, the eighth insulator, and the third conductor; The ninth insulator is formed by sputtering in an oxygen-containing atmosphere by applying RF power.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, The first to third insulators are continuously formed under reduced pressure using an apparatus including a plurality of processing chambers.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, The first to third oxide films are continuously formed under reduced pressure using an apparatus including a plurality of process chambers.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, The first conductive film, the first insulating film, and the second conductive film are continuously formed under reduced pressure using an apparatus including a plurality of process chambers.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, The first to third insulators, the first to third oxide films, the first conductive film, the first insulating film, the second conductive film, and the fifth oxide are formed by sputtering.

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