Apparatus and method for reducing lock time through band calibration

Abstract

Apparatuses and related methods related to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and / or injection-locked oscillator (ILO) adaptive values during start-up, and loading the pre-calibrated values during rate changes. In an illustrative example, an integrated circuit can include a controllable frequency circuit operable at a frequency within each of a plurality of frequency bands. A data store can store an operating setting associated with each frequency in the plurality of frequency bands. A state machine can be coupled to the controllable frequency circuit and the data store, the data store configured to select a predetermined frequency band in response to an instruction signal, extract the operating setting associated with the predetermined frequency band from the data store, and apply the extracted operating setting to the controllable frequency circuit. Through pre-calibration, PLL and / or ILO lock time during rate changes in a multi-rate serializer / deserializer (SERDES) link can be advantageously reduced.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to band calibration. BACKGROUND

[0002] Data represents information that has useful value. Data can take the form of storing information. Data storage can be in analog form. Data storage can also be in digital form. Digital format data can be communicated between two nodes. For example, when data is transmitted, it can be received and interpreted as a function of time. Some systems that receive data in digital format can determine when to sample a voltage signal based on a clock, for example, to decide whether a symbol in a data stream is a one or a zero. Sometimes, data can be received without knowing its specific phase information. Phase alignment can be performed prior to transmitting or receiving data to ensure data accuracy and data integrity. SUMMARY

[0003] Apparatuses and methods related to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and / or injection-locked oscillator (ILO) adaptive values during startup, and loading the pre-calibrated values during rate change. In one example, an integrated circuit can include a controllable frequency circuit operable at a frequency within each of a plurality of frequency bands. A data store can store an operating setting associated with each frequency in the plurality of frequency bands. A state machine can be coupled to the controllable frequency circuit and the data store, the data store configured to select a predetermined frequency band in response to an instruction signal, extract the operating setting associated with the predetermined frequency band from the data store, and apply the extracted operating setting to the controllable frequency circuit. By pre-calibrating, PLL and / or ILO lock time during rate change in a multi-rate serializer / deserializer (SERDES) link can be advantageously reduced.

[0004] Various embodiments can achieve one or more advantages. For example, in some embodiments, the lock time of a PLL and / or ILO can be accelerated. Some embodiments can be flexibly employed, for example, to allow for in-field reconfiguration of frequency band and / or rate change operation in programmable logic such as a field programmable gate array (FPGA). In some embodiments, for example, by implementation on a solid state hardware platform such as an application specific integrated circuit (ASIC) to reduce cost, size, or power. Some embodiments can involve execution of preprogrammed instructions and / or software by a processor to implement reduced lock time when changing rates in a controllable frequency circuit. In some embodiments, the apparatus and / or method can enable a PLL and / or ILO to work for a large range of protocols, for example, peripheral component interconnect express (PCIe). In various embodiments, the apparatus and / or method can avoid the need for a dedicated narrow band PLL with cost effectiveness. In some embodiments, fewer hardware resources can be employed, and a pre-calibration circuit and / or state machine can be shared by different transceivers to achieve a smaller area.

[0005] In one example aspect, an integrated circuit includes a controllable frequency circuit operable at a frequency within each of a plurality of frequency bands. A data store is configured to store operational settings associated with each of the plurality of frequency bands. The integrated circuit further includes a state machine coupled to the controllable frequency circuit and the data store, the state machine configured to select a predetermined frequency band in response to an instruction signal, extract the operational settings associated with the predetermined frequency band from the data store, and apply the extracted operational settings to the controllable frequency circuit.

[0006] In some embodiments, the controllable frequency circuit can include a phase-locked loop (PLL). The phase-locked loop can include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit can include an injection-locked oscillator (ILO). In some embodiments, the instruction signal can be associated with an operation that changes from a first frequency band of the plurality of frequency bands to a second frequency band of the plurality of frequency bands. In some embodiments, the integrated circuit can further include a pre-calibration circuit to pre-calibrate the controllable frequency circuit to generate the operational settings. The pre-calibration circuit (250a) can be configured to pre-calibrate parameters of a decision feedback equalizer (DFE) of a serializer / deserializer (SERDES) link. The pre-calibration circuit (250a) can be further configured to pre-calibrate parameters of a clock data recovery (CDR) of a serializer / deserializer (SERDES) link.

[0007] In some embodiments, the state machine can be configured to enable the pre-calibration circuit to perform an automatic band selection for the controllable frequency circuit to generate the operational settings. In some embodiments, the state machine can be further configured to disable the pre-calibration circuit (250b) in response to the generated operational settings.

[0008] In another example aspect, a method of configuring a controllable frequency circuit includes receiving a user instruction signal by a state machine to configure the controllable frequency circuit to generate a desired frequency. The method also includes selecting a predetermined frequency band in response to the instruction signal, extracting a corresponding operating setting associated with the predetermined frequency band, and applying the extracted operating setting to the controllable frequency circuit.

[0009] In some embodiments, the controllable frequency circuit can include a phase-locked loop (PLL). The phase-locked loop can include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit can include an injection-locked oscillator (ILO). The injection-locked oscillator can include a voltage-controlled oscillator (VCO). In some embodiments, the controllable frequency circuit can include a phase-locked loop (PLL) in series with an injection-locked oscillator (ILO).

[0010] In some embodiments, the corresponding operating setting can be pre-calibrated by pre-determining one or more desired frequencies f(n) to be generated by the controllable frequency circuit, enabling a pre-calibration circuit by the state machine to perform automatic frequency band selection, setting the controllable frequency circuit to the frequency f(n), reading and storing the corresponding frequency band and operating parameters in a data memory when the frequency f(n) is locked, and disabling the automatic frequency band selection until each of the one or more frequencies f(n) has a corresponding frequency band and operating parameters.

[0011] In some embodiments, the pre-calibration circuit can pre-calibrate parameters of a decision feedback equalizer (DFE) of a serializer / deserializer (SERDES) link. In some embodiments, the pre-calibration circuit can pre-calibrate parameters of a clock data recovery (CDR) of a serializer / deserializer (SERDES) link. In some embodiments, the instruction signal can be associated with an operation that changes a first frequency band of a plurality of frequency bands to a second frequency band of the plurality of frequency bands.

[0012] The details of the multiple embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 An exemplary programmable integrated circuit (IC) on which the disclosed circuits and processes can be implemented is described;

[0014] Figure 2 An exemplary controllable frequency circuit implemented in a high-speed digital computing system is described;

[0015] Figure 3A An exemplary clock signal generator embedded in an FPGA is described;

[0016] Figure 3BAnother example clock signal generator embedded in an FPGA is described;

[0017] Figure 4 A flowchart of an example method for pre-calibrating a controllable frequency circuit is described;

[0018] Figure 5 A flowchart of an example run-time method for calibrating a controllable frequency circuit is described.

[0019] In the various drawings, like reference numerals refer to like elements. DETAILED DESCRIPTION

[0020] To facilitate understanding, the document is organized as follows. First, reference is made to Figure 1 An example platform (e.g., FPGA) suitable for performing PLL and / or ILO calibration is briefly introduced. Second, reference is made to Figures 2-3B , which discusses turning to introduce how the adapted values of the PLL and / or ILO are pre-calibrated and stored to the load during rate changes. Third, Figure 4 How to pre-calibrate the PLL and / or ILO is described. Finally, reference is made to Figure 5 , which discusses an example implementation of run-time frequency band calibration is disclosed.

[0021] Figure 1 An example programmable integrated circuit (IC) on which the disclosed circuits and processes can be implemented is described. The programmable integrated circuit 100 includes FPGA logic. The programmable integrated circuit 100 is implemented with a variety of programmable resources and can be referred to as a system on a chip (SOC). Various examples of FPGA logic include several different types of programmable logic blocks in an array.

[0022] For example, Figure 1 A programmable IC 100 is shown that includes a large number of different programmable tile blocks, including multi-gigabit transceivers (MGTs) 101, configurable logic blocks (CLBs) 102, bram blocks (BRAMs) 103, input / output blocks (lOBs) 104, configuration and clocking logic (CONFIG / CLOCKS) 105, digital signal processing blocks (DSPs) 106, specialized input / output blocks (I / O) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a processor block (PROC) 110. The programmable IC 100 can include internal and external reconfiguration ports (not shown).

[0023] In various examples, serializer / deserializers can be implemented using 101. MGT 101 can include various data serializers and deserializers. Data serializers can include implementations of various multiplexers. Data deserializers can include implementations of various de-multiplexers.

[0024] In some examples of FPGA logic, each programmable cell block includes programmable interconnect elements (INT) 111 having standard connections 124 to and from corresponding interconnect elements in each adjacent cell block. Thus, the programmable interconnect elements together implement a programmable interconnect fabric for the illustrated FPGA logic. Programmable interconnect elements INT 111 include intra-connections 120 to and from programmable logic elements in the same cell block, as included in Figure 1 as illustrated in examples of Figure 1 as illustrated in examples of

[0025] For example, configurable logic block 102 can include configurable logic elements (CLE) 112 that can be programmed to implement user logic along with a single programmable interconnect element INT 111. BRAM 103 can include BRAM logic elements (BRL) 113 along with one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a cell block depends on the height of the cell block. In the illustrated implementation method, BRAM cell blocks have the same height as 5 CLBs, but other numbers (e.g., 4) can also be used. DSP cell block 106 can include DSP logic elements (DSPL) 114 along with one or more programmable interconnect elements. For example, IOB 104 can include two instances of I / O logic elements (IOL) 115 along with one instance of programmable interconnect element INT 111. Actual I / O pads connected to I / O logic elements 115 can use metal layers that are stacked above various illustrated logic blocks, and can not be limited to the area of I / O logic elements 115, for example.

[0026] In the illustrated embodiment, a columnar region (shown in shading in Figure 1 near the center of the die is used for configuration, clock, and other control logic. Horizontal regions 109 extending from the columns distribute clock and configuration signals across the width of programmable integrated circuit IC 100. Notably, references to “columnar” and “horizontal” regions are relative to viewing the figure in a portrait orientation.

[0027] Utilizing Figure 1 Some programmable ICs of the illustrated architecture can include other logic blocks that disrupt the regular, columnar structure that makes up most programmable ICs. Other logic blocks can be programmable cell blocks and / or dedicated logic. For example, Figure 1 The illustrated processing block PROC 110 spans several columns of CLBs 102 and BRAMs 103.

[0028] Figure 1 An example of a programmable IC architecture is illustrated. The number of logic blocks in a column, the relative widths of the columns, the number and order of the columns, the kinds of logic blocks included in the columns, the relative sizes of the logic blocks, and the implementation of the interconnect / logic are provided as examples only. For example, in an actual programmable IC, more than one adjacent column of CLBs 102 can be included wherever CLBs 102 appear, to facilitate efficient implementation of user logic.

[0029] At least one transceiver can be embedded in the FPGA to transmit and receive data during communication. Data can be transmitted or received at different frequencies. The transceiver can use a phase-locked loop (PLL) and / or an injection-locked oscillator (ILO) to generate clock signals at different frequencies and / or phases. A wide range of frequency outputs is needed to support because different customers can use FPGAs with various protocols having different frequencies.

[0030] Figure 2 An exemplary controllable frequency circuit implemented in a high-speed digital computing system is described. The high-speed digital computing system 205 includes a plurality of interconnected circuit subsystems, one of which is a central processing unit (CPU) 210 electrically connected with a FPGA 215. The FPGA 215 can include a plurality of high-speed data transmission lines.

[0031] In the described example, the FPGA 215 includes a peripheral component interconnect express (PCIe) unit 220. The PCIe unit 220 is configured to connect the FPGA 215 to the CPU 210. The FPGA 215 also includes a first transceiver 225 and a second transceiver 230 configured to perform data transmission.

[0032] In the described example, each of the first transceiver 220 and the second transceiver 225 includes a controllable frequency circuit to generate one or more desired clock signals needed during data transmission. In the described example, the controllable frequency circuit includes a phase-locked loop (PLL) 235 and / or an injection-locked oscillator (ILO) 240.

[0033] The PLL 235 of the described example has a voltage controlled oscillator (VCO) 245 that can be used to generate clock signals having different frequencies. To support a wide range of frequencies, the VCO 245 for the PLL 235 and / or the ILO 240 can be configured to operate in multiple frequency bands. To select the best frequency band, when a controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240) attempts to lock to a frequency, the pre-calibration circuit 250 can go through the individual frequency bands one by one, monitor the voltage of the VCO 255 to see if it is within the desired range, and make adjustments if necessary. For example, the pre-calibration circuit 250 is configured to calibrate the controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240) during a serializer / deserializer (SERDES) link rate change. In some embodiments, the pre-calibration circuit 250 can be disposed off-chip. In the described example, the pre-calibration circuit 250 is disposed in the FPGA 215.

[0034] In various examples, some protocols can have strict requirements on the rate change time. For example, for PCIe, a lock time specification of 1 ms needs to be met. To reduce the lock time, a state machine 255 is introduced to control the pre-calibration circuit 250. The state machine 255 controls the pre-calibration circuit 250 in the transceiver 230. More specifically, the state machine 255 enables or disables the pre-calibration circuit 250 to perform automatic frequency band selection for the PLL 235 and / or the ILO 240. The state machine 255 can also be configured to receive one or more user instruction signals through a user input interface. For example, a serializer / deserializer (SERDES) link can use four different frequencies fl (e.g., 2.5 Gb / s), f2 (e.g., 5.0 Gb / s), f3 (e.g., 8.0 Gb / s), and f4 (e.g., 16.0 Gb / s) for PCIe. A user can input these four frequencies into the state machine 255. The state machine 255 can cause the pre-calibration circuit 250 to calibrate these four frequencies during the enablement period. When the pre-calibration circuit 250 performs the calibration for the respective frequency (e.g., frequency fl) and the controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240) is locked for that frequency (e.g., frequency fl), the calibration settings related to acquiring the frequency fl can be stored in a non-volatile memory (NVM) 260. When all four different frequencies fl, f2, f3, and f4 are pre-calibrated and the respective settings are obtained, one or more lookup tables can be formed and stored in the NVM 260. For example, the calibration values can be loaded to the controllable frequency circuit (e.g., the PLL 235 and / or the ILO 240) during a SERDES rate change.

[0035] Although in the described example, the state machine 255 is placed on the same programmable logic (e.g., FPGA 215) as the transceivers 225 / 230, in various embodiments, the state machine 255 can be implemented in different programmable logic (e.g., in another FPGA) to control pre-calibration.

[0036] In some embodiments, the state machine 255 can be implemented as a hard block fixed circuit. For example, an application specific integrated circuit (ASIC) can provide a state machine for controlling pre-calibration. In some embodiments, some or all of the functions of the state machine 255 can be implemented in a processor configured to execute a set of instructions stored in a data store to control pre-calibration. The processor can be disposed on the same integrated circuit, which can be an FPGA (e.g., FPGA 215) with the transceivers 230. For example, the state machine 255 and data store (e.g., NVM 260) can be implemented in a programmable logic block of a system on a chip (SoC), or in a hard block of fixed circuitry using the SoC, and the transceivers 230 can be implemented in another hard block of fixed circuitry using the SoC.

[0037] Figure 3A An exemplary clock signal generator embedded in an FPGA is described. The exemplary clock signal generator 300a includes a controllable frequency circuit. In the described example, the controllable frequency circuit includes a PLL (e.g., PLL 235). The PLL 235 receives an input clock signal 305a and generates an output clock signal 310a. The PLL 235 can be set to generate different output clock signals 310a having different frequencies. In some embodiments, the controllable frequency circuit can be configured with an ILO (e.g., ILO 240) in place of the PLL 235 to generate clock signals having different phases.

[0038] The clock signal generator 300a also includes a pre-calibration circuit 250a connected to the PLL 235. When used in a multi-rate SERDES link, multiple frequencies can be needed. The multiple frequencies can be predetermined by a user. The pre-calibration circuit 250a can go through each frequency band one by one and monitor the voltage of the VCO (e.g., VCO 245) to see if the VCO 245 is within the ideal range. When the phase-locked loop 235 is locked, the corresponding frequency band and operating settings of the phase-locked loop 235 can be obtained to produce the locked frequency.

[0039] The pre-calibration circuit 250a is controlled by a state machine 255a. The state machine 255a controls the pre-calibration circuit 250 to start pre-calibration at startup and stop calibration when all pre-determined frequencies have corresponding frequency bands and operational settings. A look-up table is established during startup calibration and can be used during rate changes. In the example described, the look-up table is stored in non-volatile memory (e.g., NVM 260).

[0040] The state machine 255a, which can be configured to have a user interface, allows a user to select frequency bands and operational settings in a manual override mode from the look-up table during PLL rate changes and configure the PLL 235 with the selected frequency bands and operational settings. By selecting the stored adaptive values directly from the startup calibration, there is no longer a need to scan through different PLL frequency bands during PLL lock. As a result, lock time is significantly reduced. In some embodiments, the pre-calibration circuit 250a can be configured to calibrate other SERDES link adaptation parameters. For example, parameters of a decision feedback equalizer (DFE) and / or parameters of a clock data recovery (CDR) can be pre-calibrated and stored. Pre-calibration can also reduce adaptation and link lock time for a SERDES.

[0041] Figure 3B Another example clock signal generator embedded in an FPGA is described. The example clock signal generator 300b includes a controllable frequency circuit. The controllable frequency circuit includes a PLL (e.g., PLL 235) in series with an ILO (e.g., ILO 240). The controllable frequency circuit receives an input clock signal 350a and generates an output clock signal 310b. In some embodiments, the order of the PLL 235 and the ILO 240 can be changed.

[0042] The clock signal generator 300b also includes a pre-calibration circuit 250b connected to both the PLL 235 and the ILO 240. When used in a SERDES, multiple frequencies can be used. The multiple frequencies can be pre-determined by a user. The pre-calibration circuit 250b can go through each frequency band individually and monitor the voltage of the VCO to see if the VCO 245 is within the ideal range. When the PLL 235 and the ILO 240 are locked, the corresponding frequency band and operational settings can be obtained to generate a locked frequency.

[0043] The pre-calibration circuit 250b is controlled by a state machine 255b. The state machine 255b controls the pre-calibration circuit 250 to start pre-calibration at startup and stop pre-calibration when all pre-determined frequencies have corresponding frequency band selections and operational settings. A look-up table is established during startup calibration and can be used during rate changes. In the example described, the look-up table is stored in non-volatile memory (e.g., NVM 260).

[0044] The state machine 255, which can be configured with a user interface, allows a user to select the frequency band and operating settings in manual override mode from the look-up table during a PLL rate change and to reset the PLL 235 and ILO 240 with the selected frequency band and operating settings. By selecting the stored adaptive values directly from the start-up calibration, there is no longer a need to scan through different PLL and ILO frequency bands during PLL and ILO lock. As a result, the lock time is significantly reduced. In some embodiments, the pre-calibration circuit 250b can be configured to calibrate other SERDES adaptation parameters. For example, parameters of a decision feedback equalizer (DFE) and / or parameters of a clock data recovery (CDR) can be pre-calibrated and stored. Pre-calibration can also reduce the adaptation and link lock time of the SERDES.

[0045] Although the described figures present an exemplary hardware implementation using circuits, some or all of the functionality of the state machine 255 can be implemented by a general purpose processor (e.g., a microcontroller) executing a program of instructions that performs the described operations.

[0046] Figure 4 A flowchart of an exemplary method for pre-calibrating a controllable frequency circuit is described. The method 400 of pre-calibrating the controllable frequency circuit 234, 240 in the clock signal generator 300b is discussed below. The method steps 400 include, in step 405, triggering a calibration routine by enabling automatic frequency band selection of a pre-calibration circuit (e.g., the pre-calibration circuit 250b). The triggering can be controlled by a state machine (e.g., the state machine 255b). In step 410, the state machine (e.g., the state machine 255b) introduces a variable n and initializes the variable n to 1. In step 415, the state machine 255b sets the PLL 235 to a first predetermined frequency (e.g., fi). In step 420, the PLL 235 and ILO 240 in the controllable frequency circuit are reset. In step 425, the state machine dynamically monitors whether the controllable frequency circuit is locked at the first predetermined frequency. In step 430, if the controllable frequency circuit is locked, the state machine 255b reads the PLL and ILO frequency band selection and parameter settings for the first predetermined frequency and stores the frequency band selection and parameter settings in a memory (e.g., the NVM 260).

[0047] In step 430, when there are more predetermined frequencies (e.g., f2, f3, f4) that a user needs, the state machine 255b increments the variable n at step 435 and loops back to step 415. If all predetermined frequencies have corresponding frequency band selection and operating settings, the state machine 255b disables the calibration routine by disabling the automatic frequency band selection of the pre-calibration circuit 250b in step 440. The pre-calibration is then complete.

[0048] Figure 5A flowchart of an exemplary run-time method for calibrating a controllable frequency circuit is described. The run-time method 500 includes, in step 505, the state machine 255a, 255b dynamically determining whether a user wants to configure the controllable frequency circuit to generate a different frequency. If so, then proceed to step 510, e.g., the state machine receives a user desired frequency value through a user interface. In step 515, the state machine 255a, 255b extracts the corresponding frequency band and parameter settings from a data store, e.g., NVM 260.

[0049] In step 520, the state machine applies the extracted frequency band and parameter settings to the controllable frequency circuit and resets the controllable frequency circuit.

[0050] In some embodiments, when the controllable frequency circuit includes only one PLL, e.g., PLL 235, the look-up table can include only one look-up table for the PLL 235. Subsequently, the state machine, e.g., state machine 255a, can apply the extracted corresponding frequency band and parameter settings to the PLL 235.

[0051] Although various embodiments have been described with reference to the accompanying drawings, other embodiments are possible implementation. For example, the clock signal generator can include more than one PLL and / or more than one ILO. The pre-calibration circuit can calibrate the PLL and / or ILO to obtain one or more desired frequencies and / or phases. In some embodiments, each transceiver in the FPGA can be calibrated by a separate pre-calibration circuit. In some embodiments, two or more transceivers in the FPGA can share one pre-calibration circuit. In some embodiments, each pre-calibration circuit can be controlled by a corresponding state machine. In some embodiments, two or more pre-calibration circuits can be controlled by the same state machine.

[0052] In some aspects of embodiments, the state machine 255 access such as look-up tables can be implemented as a computer system. For example, various embodiments can include digital and / or analog circuitry, computer hardware, firmware, software, or combinations thereof. The apparatus units can be implemented in a computer program product tangibly embodied in an information carrier, e.g., in a machine-readable storage device, executed by a programmable processor; and methods executed by a programmable processor in response to instructions of an instruction program program to perform a function by operating on input data and generating output. Some embodiments can be advantageously implemented in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage, at least one input, and / or at least one output. For example, the data storage includes one or more registers or memory locations in a storage space. A computer program is a set of instructions that can be used directly or indirectly in a computer to perform a certain activity or bring about a certain result. Computer programs can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0053] While various embodiments can be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), other embodiments can be implemented in fixed instantiations (e.g., ASICs) or single integrated circuits (e.g., SoCs). While specialized hard block circuitry in ASIC implementations can not be reconfigurable once instantiated in an integrated circuit, in some implementations ASIC implementations can provide a platform for minimization such as power consumption and / or die area.

[0054] Suitable processors for executing instruction programs include, but are not limited to, general-purpose and special-purpose microprocessors, which may include a single processor or one of a plurality of processors. Typically, the processor receives instructions and data from read-only memory or random access memory, or both. The fundamental elements of a computer are a processor for executing instructions and one or more memories for storing instructions and data. Suitable storage devices for tangibly embodying computer program instructions and data include all forms of non-volatile memory, such as semiconductor storage devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks and removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented or incorporated into an ASIC (Application-Specific Integrated Circuit), or combined in a single integrated circuit (e.g., a SoC). In some embodiments, the processor and memory may be supplemented or incorporated into a programmable logic device (e.g., an FPGA).

[0055] In some implementations, each system can be programmed with the same or similar information and / or initialized with substantially the same information stored in volatile and / or non-volatile memory. For example, a data interface can be configured to perform automatic configuration, automatic download, and / or automatic update functions when coupled to an appropriate host device (e.g., a desktop computer or server).

[0056] In some implementations, one or more user interface features can be customized to perform specific functions. Exemplary embodiments can be implemented in computer systems that include a graphical user interface and / or an internet browser. To provide interaction with the user, some embodiments can be implemented on a computer with a display device, such as an LCD (liquid crystal display) monitor for displaying information to the user, a keyboard, and indicating devices (e.g., a mouse, or a trackball through which the user can provide input to the computer).

[0057] In various embodiments, the system can communicate using suitable communication methods, devices, and techniques. For example, the system can communicate with compatible devices (e.g., devices capable of transmitting data to and / or from the system) using a point-to-point communication approach, in which messages are transmitted directly from a source to a receiver over a dedicated physical link (e.g., a fiber optic link, an infrared link, an ultrasonic link, point-to-point wiring, a daisy chain). The components of the system can exchange information through analog or digital data communications of any form or medium, including packet-based messages over a communications network. Examples of communications networks include, for example, LANs (local area networks), WANs (wide area networks), MANs (metropolitan area networks), wireless and / or optical networks, and the computers and networks that form the Internet. Other embodiments can transmit messages by broadcasting to all or substantially all devices coupled together through a communications network, for example, by using an omnidirectional radio frequency (RF) signal. Other embodiments can transmit messages with a high degree of directionality, for example, radio frequency signals transmitted using directional (i.e., narrow-beam) antennas or infrared signals optionally used with focusing optics. Other embodiments using appropriate interfaces and protocols are also possible, including but not limited to, USB 2.0, FireWire, ATA / IDE, RS-232, RS-422, RS-485, 802.11a / b / g / n, Wi-Fi, WiFi-Direct, Li-Fi, Bluetooth, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), Token Ring networks, or frequency, time, or code division multiplexing techniques. Some embodiments can optionally include functionality such as error checking and correction (ECC) for data integrity, or security measures such as encryption (e.g., WEP) and password protection.

[0058] In various embodiments, a computer system can include a non-transitory memory. The memory can be connected to one or more processors, which can be configured for storing data and computer-readable instructions, including program instructions executable by the processor. The one or more processors can access the data and computer-readable instructions. The processor-executable program instructions, when executed by the one or more processors, can cause the one or more processors to perform various operations.

[0059] Various examples of modules can be implemented using circuitry including various electronic hardware. The hardware can include, without limitation, transistors, resistors, capacitors, switches, integrated circuits, and / or other modules. In various examples, the modules can include analog and / or digital logic manufactured on silicon substrates containing various integrated circuits (e.g., FPGAs, ASICs, SoCs), discrete components, traces, and / or memory circuits. In some embodiments, the modules can involve software executed by preprogrammed instructions and / or by a processor. For example, various modules can involve both hardware and software.

[0060] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. For example, advantageous results can be achieved if steps of the described techniques were performed in a different order and / or if components of the described systems were combined in a different manner, and / or if the components were supplemented with other components. Therefore, other embodiments are within the scope of the following claims.

Claims

1. An integrated circuit (300a), characterized in that, The integrated circuit (300a) includes: The controllable frequency circuit (235, 240) can operate in multiple frequency bands; The data memory (260) is configured to store the corresponding operating settings and corresponding frequency bands associated with each of the multiple frequencies, as well as the parameters of the decision feedback equalizer of the serializer / deserializer link or the parameters of the clock data recovery of the serializer / deserializer link. Pre-calibration circuits (250a, 250b) are operable to pre-calibrate the controllable frequency circuits (235, 240) and the parameters of the decision feedback equalizer and the clock data recovery by checking the operation of the controllable frequency circuits in the plurality of frequency bands; and A state machine (255a, 225b), coupled to the controllable frequency circuit (235, 240), the data memory (260), and the pre-calibration circuit, is configured to: Enable the pre-calibration circuits (250a, 250b) to perform automatic frequency band selection for the controllable frequency circuits (235, 240) to generate various operating settings and frequency bands associated with the plurality of frequencies; In response to a command signal, a predetermined frequency band is selected from the plurality of frequency bands; Extract the first operating setting from the data memory (260) among a plurality of operating settings associated with a predetermined frequency band and the first parameter of the decision feedback equalizer or the clock data recovery parameter; The extracted first operation settings are applied to the controllable frequency circuit; and The extracted first parameter is applied to the serializer / deserializer link.

2. The integrated circuit (300a) according to claim 1, characterized in that, The controllable frequency circuit (235, 240) includes at least one of the following: Phase-locked loop (235); or Injection-locked oscillator (240).

3. The integrated circuit (300a) according to claim 1, characterized in that, The controllable frequency circuit includes a phase-locked loop (235) and a voltage-controlled oscillator (245).

4. The integrated circuit (300a) according to claim 1, characterized in that, The command signal instructs the operation of changing the first frequency band of the plurality of frequency bands to the second frequency band of the plurality of frequency bands.

5. The integrated circuit (300a) according to claim 1, characterized in that, The state machines (255a, 255b) are also configured to disable the pre-calibration circuits (250a, 250b) in response to generating the operation settings.

6. A method for configuring a controllable frequency circuit, characterized in that, The method includes: The controllable frequency circuit (235, 240) is configured to generate a desired frequency by receiving user instruction signals through a state machine, wherein the controllable frequency circuit can operate in multiple frequency bands; By checking the operation of the controllable frequency circuit in the multiple frequency bands, the controllable frequency circuit is precalibrated, enabling the precalibration circuit to perform automatic frequency band selection for the controllable frequency circuit (235, 240) to generate corresponding operating settings and corresponding frequency bands associated with each of the multiple frequencies; Parameters of the decision feedback equalizer for the pre-calibrated serializer / deserializer link or parameters for clock data recovery of the serializer / deserializer link; In response to the command signal, a predetermined frequency band among the plurality of frequency bands is selected via a state machine; Extract a first operating setting from a plurality of operating settings associated with the predetermined frequency band and a first parameter of the decision feedback equalizer or the clock data recovery parameter from a data memory (260), wherein the data memory is configured to store the operating settings and frequency band associated with each of the plurality of frequencies and the parameters of the decision feedback equalizer or the clock data recovery parameter; The extracted operation settings are applied to the controllable frequency circuit and The extracted first parameter is applied to the serializer / deserializer link.

7. The method according to claim 6, characterized in that, The controllable frequency circuit (235, 240) includes at least one of the following: Phase-locked loop (235); Inject lock-in oscillator (240); or A phase-locked loop connected in series with an injection-locked oscillator.

8. The method according to claim 6, characterized in that, The controllable frequency circuit (235, 240) includes a phase-locked loop (235) and a voltage-controlled oscillator (245).

9. The method according to claim 6, characterized in that, The controllable frequency circuit includes an injection-locked oscillator (240), which includes a voltage-controlled oscillator (245).

10. The method according to claim 6, characterized in that, The method also includes pre-calibrating the corresponding operating settings in the following manner: One or more desired frequencies f(n) to be generated by a controllable frequency circuit are predetermined; Automatic frequency band selection is performed by enabling the pre-calibration circuits (250a, 250b) via the state machine; Set the controllable frequency circuit (235, 240) to a frequency f(n); When the frequency f(n) is locked, the corresponding frequency band and operating parameters are read and stored in the data memory (260); and, The automatic frequency band selection is disabled until each of the one or more frequencies f(n) has a corresponding frequency band and operating parameters.

11. The method according to claim 6, characterized in that, The command signal is associated with an operation to change from the first frequency band in the frequency band to the second frequency band in the plurality of frequency bands.

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