Fan-out package structure and method of forming the same

Abstract

Embodiments of the present application provide a fan-out package structure, comprising: a circuit layer; a first chip and a second chip on the circuit layer; a reinforcement structure on the circuit layer, the reinforcement structure surrounding sidewalls of the first chip and the second chip, the reinforcement structure having a patterned circuit, the patterned circuit electrically connected to the circuit layer. The present application aims to provide a fan-out package structure and a forming method thereof to improve the performance of the fan-out package structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to fan-out packaging structures and methods for forming the same. Background Technology

[0002] Currently, in the fan-out substrate-on-chip (FOCoS) structure of post-chip technology, there is a problem that the filler material is prone to cracking. This is determined because the filler material expands during high-temperature processes, causing delamination and cracks at the interface between the filler material and the chip [e.g., application-specific integrated circuit (ASIC) chips and high bandwidth memory (HBM)], which then damages the circuit layer downwards.

[0003] Furthermore, currently, if there is a need to integrate passive components (such as capacitors) into a package, the passive components are assembled onto the substrate. This design causes the capacitor's charge to be transferred to the chip through the substrate's trace path and the circuit layer. Since the entire circuit is relatively long, charge loss is likely to occur, reducing the product's electrical performance. If the passive components are built onto the circuit layer, the overall size of the package on the circuit layer will increase. Summary of the Invention

[0004] In view of the problems existing in the related technologies, the purpose of this invention is to provide a fan-out packaging structure and a method for forming the same, so as to improve the performance of the fan-out packaging structure.

[0005] An embodiment of this application provides a fan-out package structure, including: a circuit layer; a first chip and a second chip located on the circuit layer; and a reinforcement structure located on the circuit layer, the reinforcement structure surrounding the sidewalls of the first chip and the second chip, the reinforcement structure having a patterned circuit electrically connected to the circuit layer.

[0006] In some embodiments, the patterned circuitry is closer to the first chip than to the second chip.

[0007] In some embodiments, the patterned circuit is a capacitor circuit or an inductor circuit.

[0008] In some embodiments, the patterned circuit is located on the bottom surface of the reinforcement structure and faces the circuit layer.

[0009] In some embodiments, the circuitry further includes an interconnect, through which the patterned circuitry is electrically connected to the line layer.

[0010] In some embodiments, the reinforcement further includes a filler material located between the inner sidewall of the reinforcing structure and the sidewalls of the first chip and the second chip.

[0011] In some embodiments, the reinforcing structure is fixed to the circuit layer.

[0012] In some embodiments, the reinforcing structure and the circuit layer form a cavity, the first chip and the second chip are located in the cavity, and the reinforcing structure covers the upper surfaces of the first chip and the second chip.

[0013] In some embodiments, the reinforcement structure has a plurality of thermally conductive holes located above the first chip and the second chip.

[0014] In some embodiments, the thermally conductive hole includes a thermally conductive material.

[0015] In some embodiments, the thermally conductive material is a metallic material.

[0016] In some embodiments, the inner wall of the heat-conducting hole further includes a seed layer, which surrounds the heat-conducting material.

[0017] In some embodiments, the area covered by the thermal via located above the first chip is greater than the area covered by the thermal via located above the second chip.

[0018] Embodiments of this application provide a method for forming a fan-out package structure, comprising: providing a substrate; performing a patterning process on the substrate to form a reinforcing structure; disposing the reinforcing structure on a circuit layer, the reinforcing structure surrounding the sidewalls of a first chip and a second chip on the circuit layer, the reinforcing structure being electrically connected to the circuit layer.

[0019] In some embodiments, the patterning process includes forming a capacitor circuit or an inductor circuit.

[0020] In some embodiments, an accommodating space is formed in the substrate, and the first chip and the second chip are located in the accommodating space.

[0021] In some embodiments, the accommodating space and the circuit layer form a cavity, and the reinforcing structure also covers the top surfaces of the first chip and the second chip.

[0022] In some embodiments, the patterning process includes forming thermally conductive holes located in the substrate.

[0023] In some embodiments, the method further includes forming a filler material located in the reinforcing structure and the first chip and the second chip structure.

[0024] In some embodiments, a filler material is also located between the reinforcing structure and the circuit layer, the filler material encapsulating a portion of the outer wall of the reinforcing structure. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0026] Figures 1 to 9 The formation process of the fan-out packaging structure of this application is shown.

[0027] Figures 10 to 13 Different embodiments of the fan-out packaging structure of this application are shown. Detailed Implementation

[0028] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0029] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0030] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0031] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0032] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0033] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0034] See Figure 1 A substrate 10 is provided, which enhances the robustness of the entire structure. In some embodiments, the substrate 10 is a silicon wafer.

[0035] See Figure 2 The substrate 10 is etched to form multiple trenches 20 on both sides of the substrate 10.

[0036] See Figure 3 The first line structure 30 is formed in multiple trenches 20.

[0037] See Figure 4 A second circuit structure 40 is formed on the first circuit structure 30. The first circuit structure 30 and the second circuit structure 40 are combined to form a patterned circuit 42. In some embodiments, the patterned circuit 42 is a capacitor circuit or an inductor circuit.

[0038] See Figure 5 An accommodating space 50 is formed in the substrate 10. Thus, the reinforcing structure 52 of this application is formed.

[0039] See Figure 6 A first chip 62 and a second chip 64 are formed on the circuit layer 60. In some embodiments, the circuit layer 60 is a fan-out circuit layer. In some embodiments, the circuit layer 60 is a redistribution circuit layer (RDL).

[0040] See Figure 7 A reinforcing structure 52 is formed on the circuit layer 60. The accommodating space 50 becomes part of a cavity enclosed by the reinforcing structure 52 and the circuit layer 60. An adhesive layer 70 is located in the cavity 72 between the top surfaces of the first chip 62 and the second chip 64 and the reinforcing structure. In some embodiments, the reinforcing structure 52 comprises a patternable material. In some embodiments, the reinforcing structure 52 comprises silicon.

[0041] See Figure 8 The filling material 80 is filled into the cavity 72, and the filling material 80 also covers part of the sidewall of the reinforcing structure 52.

[0042] See Figure 9 The reinforcing structure 52 and the circuit layer 60 are encapsulated using molding compound 90.

[0043] See Figure 10 In some embodiments, a plurality of thermally conductive holes 100 are formed on the top surface of the reinforcing structure 52. In some embodiments, the thermally conductive holes 100 include a seed layer that contacts the substrate 10 and a thermally conductive material located in the seed layer.

[0044] See Figure 11 In some embodiments, a planarization process is performed so that the molding compound 90, the reinforcing structure 52, and the top surfaces of the first chip 62 and the second chip 64 are flush.

[0045] See Figure 12 In some embodiments, the first chip 62 and the second chip 64 are different chips, and the number of heat-conducting holes 100 on the first chip 62 is greater than the number of heat-conducting holes 100 on the second chip 64.

[0046] See Figure 13 In some embodiments, etching removes the filler material 80 located between the first chip 62 and the second chip 64, and separates the reinforcing structure 52 located above the first chip 62 and the second chip 64.

[0047] This application provides a reinforcing structure 52, which is placed above the chip. After thermal processing, this reinforcing structure 52 suppresses structural stretching tension, prevents material interface cracking, and effectively suppresses chip expansion. The reinforcing structure 52 also includes a patterned circuit 42 connected to the circuit layer 60. Unlike conventional methods that integrate capacitors onto the substrate, where charge must travel through the substrate's circuit paths to reach the chip, resulting in charge loss and reduced product performance, this application integrates the patterned circuit 42 directly connected to the circuit layer 60 (fan-out circuit layer), reducing the charge transfer distance and enabling the fan-out packaging structure to achieve better performance.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fan-out packaging structure, characterized in that, include: Line layer; The first chip and the second chip are located on the circuit layer; A reinforcement structure is located on the circuit layer, the reinforcement structure surrounds the sidewalls of the first chip and the second chip, the reinforcement structure has a patterned circuit, the patterned circuit is a capacitor circuit or an inductor circuit, the patterned circuit is electrically connected to the circuit layer, so that charge is transferred through the first chip, the circuit layer, and the patterned circuit in the reinforcement structure to provide electrical connection for the first chip.

2. The fan-out packaging structure according to claim 1, characterized in that, Compared to the second chip, the patterned circuit is closer to the first chip.

3. The fan-out packaging structure according to claim 1, characterized in that, The patterned circuit is located on the bottom surface of the reinforcement structure and faces the circuit layer.

4. The fan-out packaging structure according to claim 1, characterized in that, Also includes: Interconnectors, through which the patterned circuitry is electrically connected to the line layer.

5. The fan-out packaging structure according to claim 1, characterized in that, Also includes: The filling material is located between the inner wall of the reinforcing structure and the sidewalls of the first chip and the second chip.

6. The fan-out packaging structure according to claim 1, characterized in that, The reinforcing structure is fixed to the circuit layer.

7. The fan-out packaging structure according to claim 1, characterized in that, The reinforcing structure and the circuit layer form a cavity, the first chip and the second chip are located in the cavity, and the reinforcing structure covers the upper surface of the first chip and the second chip.

8. The fan-out packaging structure according to claim 1, characterized in that, The reinforcing structure has multiple heat-conducting holes located above the first chip and the second chip.

9. The fan-out packaging structure according to claim 8, characterized in that, The heat-conducting hole contains a heat-conducting material.

10. The fan-out packaging structure according to claim 9, characterized in that, The thermally conductive material is a metallic material.

11. The fan-out packaging structure according to claim 9, characterized in that, The inner wall of the heat-conducting hole also includes a seed layer, which surrounds the heat-conducting material.

12. The fan-out packaging structure according to claim 8, characterized in that, The area covered by the thermal via located above the first chip is greater than the area covered by the thermal via located above the second chip.

13. A method for forming a fan-out package structure, characterized in that, include: Provide a base; A patterning process is performed on the substrate to form a reinforcing structure, the reinforcing structure having patterned circuitry; The reinforcing structure is disposed on the circuit layer, and the reinforcing structure surrounds the sidewalls of the first chip and the second chip on the circuit layer. The patterned circuit is a capacitor circuit or an inductor circuit. The reinforcing structure is electrically connected to the circuit layer, so that charge is transferred through the first chip, the circuit layer, and the patterned circuit within the reinforcing structure to provide electrical connection for the first chip.

14. The method for forming a fan-out package structure according to claim 13, characterized in that, An accommodating space is formed in the substrate, and the first chip and the second chip are located in the accommodating space.

15. The method for forming a fan-out package structure according to claim 14, characterized in that, The accommodating space and the circuit layer form a cavity, and the reinforcing structure also covers the top surfaces of the first chip and the second chip.

16. The method for forming a fan-out package structure according to claim 13, characterized in that, Also includes: A filling material is formed in the reinforcing structure and the first and second chip structures.

Images