Method for preparing MOSFET device

Abstract

A method for preparing a MOSFET device, which relates to the field of semiconductor technology, comprises: sequentially forming a first mask layer and a second mask layer on a wide bandgap drift layer; removing a portion of the second mask layer to define a first injection window; injecting through the first injection window to form a well region, to obtain a first device structure; forming a third mask layer on the first device structure, etching a portion of the third mask layer to define a second injection window; injecting through the second injection window to form a heavily doped region, to obtain a third device structure; forming a fifth mask layer on the third device structure, etching a portion of the fifth mask layer to expose the third mask layer, removing the second mask layer to define a third injection window; injecting through the third injection window to form a JFET injection region, to obtain a fourth device structure. The method can improve the preparation stability of MOSFET devices.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a MOSFET device. Background Art

[0002] Wide bandgap materials offer advantages such as high saturation mobility, high breakdown field strength, and high thermal conductivity. Power devices made from wide bandgap materials are widely used in emerging fields such as aerospace, industrial power supplies, and electric vehicles due to their high breakdown voltage, high switching frequency, low switching losses, and high operating temperature. MOSFETs (metal oxide semiconductor field-effect transistors), in particular, offer advantages such as low on-resistance, fast switching speed, and high temperature reliability. They have become the most important power electronic components in large-scale and ultra-large-scale integrated circuits such as microprocessors and semiconductor memories.

[0003] During MOSFET device fabrication, JFET region implantation is typically performed using either a photomask or full-wafer JFET implantation. The photomask approach is subject to photolithography and overlay errors, making it prone to implantation into the channel region and resulting in poor stability. The full-wafer implantation approach requires adjusting the implant parameters for other regions simultaneously whenever the JFET region implant parameters are adjusted, making the changes more complex. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a method for preparing a MOSFET device, which can improve the stability of the MOSFET device preparation process, reduce the use of masks, and reduce costs.

[0005] The embodiments of the present disclosure are implemented as follows:

[0006] In one aspect of the present disclosure, a method for preparing a MOSFET device is provided, the method comprising: providing a wide bandgap epitaxial wafer, the wide bandgap epitaxial wafer comprising a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate; forming a first mask layer on the wide bandgap drift layer, and forming a second mask layer on the first mask layer; removing a portion of the second mask layer to define a first injection window, the first injection window exposing the first mask layer; forming a well region through ion implantation through the first injection window to obtain a first device structure; forming a third mask layer on the entire surface of the first device structure, etching a portion of the third mask layer, retaining the third mask layer on the sidewalls of the first injection window and the third mask layer in the middle region of the first injection window to define a second injection window The first mask layer is exposed at the bottom of the second injection window; ion implantation is performed through the second injection window to form a heavily doped region to obtain a third device structure; a fifth mask layer is formed on the entire surface of the third device structure, and a portion of the fifth mask layer is removed to expose the third mask layer; the second mask layer is removed, and the third mask layer on the side wall of the first injection window, the fifth mask layer in the second injection window, and the third mask layer in the middle area of ​​the second injection window are retained to define the third injection window, and the first mask layer is exposed at the bottom of the third injection window; ion implantation is performed through the third injection window to form a JFET injection region to obtain a fourth device structure, wherein the doping type of the JFET injection region is the same as the doping type of the heavily doped region and different from the doping type of the well region.

[0007] Another aspect of the present disclosure provides a method for preparing a MOSFET device, the method comprising: providing a wide bandgap epitaxial wafer, the wide bandgap epitaxial wafer comprising a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate; forming a first mask layer on the wide bandgap drift layer, and forming a second mask layer on the first mask layer; removing a portion of the second mask layer to define a first injection window, the first injection window exposing the first mask layer; forming a well region through ion implantation through the first injection window to obtain a first device structure; forming a third mask layer on the entire surface of the first device structure, removing a portion of the third mask layer, retaining the third mask layer and the first injection window sidewalls. The third mask layer in the middle area of ​​the window exposes part of the second mask layer and the first mask layer, defining a second injection window, and the second injection window exposes the first mask layer; ion implantation is performed through the second injection window to form a heavily doped area; the second mask layer is removed, and the third mask layer on the side wall of the first injection window and the third mask layer in the middle area of ​​the first injection window are retained to define a third injection window, and the first mask layer is exposed at the bottom of the third injection window; ion implantation is performed through the third injection window to form a JFET injection area, thereby obtaining a second device structure, wherein the doping type of the JFET injection area is the same as the doping type of the heavily doped area, and different from the doping type of the well area.

[0008] The beneficial effects of the present disclosure include:

[0009] The method for preparing a MOSFET device provided by the present disclosure can improve the stability of the MOSFET device preparation process, reduce the use of masks, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 One of the flow charts of the method for preparing a MOSFET device provided in some embodiments of the present disclosure;

[0012] Figure 2 This is one of the state diagrams of a MOSFET device provided in some embodiments of the present disclosure;

[0013] Figure 3 The second state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0014] Figure 4 The third state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0015] Figure 5 This is a fourth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0016] Figure 6 The fifth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0017] Figure 7 The sixth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0018] Figure 8 The seventh state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0019] Figure 9 The eighth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0020] Figure 10 A ninth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0021] Figure 11 The second flow chart of the method for preparing a MOSFET device provided in some embodiments of the present disclosure;

[0022] Figure 12 The tenth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0023] Figure 13 The eleventh state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0024] Figure 14 The twelfth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0025] Figure 15 The thirteenth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0026] Figure 16 The fourteenth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0027] Figure 17 The fifteenth state diagram of a MOSFET device provided in some embodiments of the present disclosure;

[0028] Figure 18 This is the sixteenth state diagram of a MOSFET device provided in some embodiments of the present disclosure.

[0029] Icons: 10-wide bandgap epitaxial wafer; 11-well region; 12-heavily doped region; 13-JFET injection region; 14-first injection region; 20-first mask layer; 30-second mask layer; 31-first injection window; 40-third mask layer; 41-second injection window; 401-first part; 402-second part; 50-fifth mask layer; 51-third injection window; 60-fourth mask layer; 61-fourth injection window; 100-first device structure; 200-second device structure; 300-third device structure; 400-fourth device structure. DETAILED DESCRIPTION

[0030] The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0031] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to regionally distinguish one element from another element. For example, without departing from the scope of this disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extended onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extended onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0033] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region, as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0034] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It should also be understood that when used herein, the term "comprising" indicates the presence of the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meanings as those in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless otherwise explicitly defined herein.

[0036] Please refer to Figure 1 The present disclosure provides a method for preparing a MOSFET device, the method comprising the following steps:

[0037] S110 , providing a wide bandgap epitaxial wafer 10 , wherein the wide bandgap epitaxial wafer 10 includes a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate.

[0038] S120 , forming a first mask layer 20 on the wide bandgap drift layer, and forming a second mask layer 30 on the first mask layer 20 .

[0039] S130 , removing a portion of the second mask layer 30 to define a first injection window 31 , where the first injection window 31 exposes the first mask layer 20 .

[0040] S140 , forming a well region 11 by ion implantation through the first implantation window 31 , thereby obtaining a first device structure 100 .

[0041] S150, forming a third mask layer 40 on the entire surface of the first device structure 100, etching a portion of the third mask layer 40, retaining the third mask layer 40 on the side wall of the first injection window 31 and the third mask layer 40 in the middle area of ​​the first injection window 31, defining a second injection window 41, and the second injection window 41 exposing the first mask layer 20.

[0042] S160 , ion implantation is performed through the second implantation window 41 to form a heavily doped region 12 .

[0043] S170 , removing the second mask layer 30 , retaining the third mask layer 40 on the sidewalls of the first injection window 31 and the third mask layer 40 in the middle area of ​​the first injection window 31 to define a third injection window 51 , with the first mask layer 20 exposed at the bottom of the third injection window 51 .

[0044] S180 , forming a JFET injection region 13 by ion implantation through the third injection window 51 to obtain a second device structure 200 , wherein the doping type of the JFET injection region 13 is the same as the doping type of the heavily doped region 12 and different from the doping type of the well region 11 .

[0045] S190 , forming a fourth mask layer 60 on the entire surface of the second device structure 200 , removing part of the fourth mask layer 60 , retaining the fourth mask layer 60 on the sidewall of the third injection window 51 and the fourth mask layer 60 located on the sidewall of the second injection window 41 , and defining a fourth injection window 61 .

[0046] S191 , ion implantation is performed through the fourth implantation window 61 to form a first implantation region 14 . The first implantation region 14 and the JFET implantation region 13 have different doping types.

[0047] The present disclosure utilizes a self-alignment process to more accurately position the heavily doped region 12, the JFET injection region 13, and the first injection region 14, thereby preventing ions from being injected into the channel or terminal region during ion implantation to form the JFET injection region 13. The present disclosure also utilizes a self-alignment process to precisely control the formation of the first injection region 14 within the JFET injection region 13 when ion implantation is performed within the JFET injection region 13 to form the first injection region 14. The present disclosure utilizes a self-alignment process to reduce the use of photomasks. Furthermore, the present disclosure's fabrication process is simpler and more controllable than prior art. Furthermore, the present disclosure retains the implantation mask layer (i.e., the first mask layer 20) when forming the well region 11, the heavily doped region 12, the JFET injection region 13, and the first injection region 14 through ion implantation. This effectively avoids surface damage to the wide bandgap epitaxial wafer 10 that may be caused by ion implantation.

[0048] Among them, such as Figure 2 As shown, in step S110, the wide bandgap epitaxial wafer 10 may be made of silicon carbide. In some embodiments, the wide bandgap epitaxial wafer 10 may include a wide bandgap substrate and a wide bandgap drift layer formed on the wide bandgap substrate. Both the wide bandgap substrate and the wide bandgap drift layer may be made of silicon carbide. The present disclosure does not limit the doping type and dopant ion concentration of the wide bandgap substrate and the wide bandgap drift layer. Those skilled in the art may select any wide bandgap substrate and wide bandgap drift layer doping type and dopant ion concentration that satisfies known MOSFET device structures.

[0049] In step S120, Figure 2As shown, the material of the first mask layer 20 can be silicon nitride. It should be understood that using silicon nitride as the material of the first mask layer 20 is merely an example provided in the present disclosure, and those skilled in the art may also select other feasible materials based on common sense. In some embodiments, the thickness of the first mask layer 20 is between 30 nm and 60 nm. In some embodiments, the first mask layer 20 provided in the present disclosure can be deposited on the wide bandgap epitaxial wafer 10 via low-pressure chemical vapor deposition (i.e., LPCVD). In some embodiments, the material of the second mask layer 30 can be silicon oxide. In some embodiments, the thickness of the second mask layer 30 can be between 1 μm and 2 μm. In some embodiments, the second mask layer 30 can be deposited on the first mask layer 20 via plasma-enhanced chemical vapor deposition (i.e., PECVD) or LPCVD. In some embodiments, the thickness of the second mask layer 30 is greater than the thickness of the first mask layer 20.

[0050] In step S130, Figure 3 As shown, removing a portion of the second mask layer 30 can define a first injection window 31. In some embodiments, removing a portion of the second mask layer 30 can be achieved through an etching process. In some embodiments, when removing the second mask layer 30, since the side of the second mask layer 30 close to the wide bandgap epitaxial wafer 10 also has the first mask layer 20, after removing a portion of the second mask layer 30, the first mask layer 20 will be exposed. In some embodiments, the exposed first mask layer 20 can be used as an injection mask layer for ion implantation to form the well region 11. In this way, the present disclosure solves the problem of interface damage that may be caused when performing ion implantation to form the well region 11.

[0051] In step S140, Figure 3 As shown, after removing part of the second mask layer 30 to define the first injection window 31, the present disclosure performs ion implantation through the first injection window 31 to form the well region 11, thus obtaining the following Figure 3 The first device structure 100 is shown. In some embodiments, the well region 11 is doped with P-type ions.

[0052] In step S150, Figure 4As shown, the third mask layer 40 is formed entirely on the first device structure 100. "Entirely forming the third mask layer 40" means that the third mask layer 40 completely covers the side of the first device structure 100 away from the wide bandgap epitaxial wafer 10. In some embodiments, the third mask layer 40 can be deposited entirely on the third device structure 300 by LPCVD. In some embodiments, the material of the third mask layer 40 can be polycrystalline silicon. It will be readily understood that the material, thickness, and growth method of the third mask layer 40 are merely examples provided herein. In other embodiments, those skilled in the art may also select other feasible material types, thickness ranges, and growth methods based on actual needs.

[0053] In some embodiments, as Figure 5 As shown, after the third mask layer 40 is formed on the entire surface, the present disclosure partially removes the third mask layer 40, leaving the third mask layer 40 on the sidewall of the first injection window 31 (ie, corresponding to Figure 5 The first portion 401) and the third mask layer 40 in the middle area of ​​the first injection window 31 (ie corresponding to Figure 5 The second portion 402 is exposed to expose the second mask layer 30 and a portion of the first mask layer 20 (the portion of the first mask layer 20 corresponds to Figure 5 The first mask layer 20 between the first portion 401 and the second portion 402 is referred to as the middle portion. The second injection window 41 is defined, and the bottom of the second injection window 41 exposes the first mask layer 20. In some embodiments, the thickness of the third mask layer 40 on the second mask layer 30 is between 5000 Å and 1 μm.

[0054] In step S160, Figure 5 As shown, ion implantation is performed through the second implantation window 41 defined in step S150 to obtain a heavily doped region 12. In some embodiments, the heavily doped region 12 is N-type ion doped.

[0055] In step S170, if Figure 6 As shown, the second mask layer 30 is removed, and the third mask layer 40 (ie, corresponding to the side wall of the first injection window 31) is retained. Figure 6 The first portion 401) and the third mask layer 40 in the middle area of ​​the first injection window 31 (ie corresponding to Figure 6 The second portion 402 in the middle of the film is formed to define a third implantation window 51, with the bottom of the third implantation window 51 exposing the first mask layer 20. In some embodiments, the third implantation window 51 is an ion implantation window for forming the JFET implantation region 13. In some embodiments, the size of the third implantation window 51 can be selected by those skilled in the art, and can be adjusted by changing etching parameters.

[0056] In step S180, Figure 7 As shown, ion implantation is performed through the third implantation window 51 to form a JFET implantation region 13. The JFET implantation region 13 obtained by the preparation method provided by the present disclosure has a more accurate formation position. Figure 7 The second device structure 200 is shown. In some embodiments, the JFET implant region 13 is N-type ion doped.

[0057] In some embodiments, after executing step S180, the present disclosure may further include steps S190 and S291. In step S190, if Figure 8 As shown, after obtaining the second device structure 200, a fourth mask layer 60 is formed entirely on the second device structure 200 in step S190. In some embodiments, the fourth mask layer 60 is formed entirely on the surface, i.e., the fourth mask layer 60 completely covers the surface of the second device structure 200 facing away from the wide bandgap epitaxial wafer 10. In some embodiments, the fourth mask layer 60 is made of polycrystalline silicon and has a thickness between 0.1 μm and 1 μm. In some embodiments, the fourth mask layer 60 can be deposited entirely on the second device structure 200 using an LPCVD process.

[0058] In some embodiments, as Figure 9 As shown, the fourth injection window 61 can be obtained by removing a portion of the fourth mask layer 60, retaining the fourth mask layer 60 on the sidewalls of the third injection window 51 and the fourth mask layer 60 located on the sidewalls of the second injection window 41. In some embodiments, the size of the fourth injection window 61 can be selected by those skilled in the art, and the size of the fourth injection window 61 can be adjusted by changing the etching parameters.

[0059] In step S191, if Figure 10 As shown, ion implantation is performed through the fourth implantation window 61 to form a first implantation region 14 in the JFET implantation region 13. The obtained first implantation region 14 is precisely located in the JFET implantation region 13. In some embodiments, the first implantation region 14 is P-type ion doped.

[0060] Please refer to Figure 11 The present disclosure also provides another method for preparing a MOSFET device, the method comprising the following steps:

[0061] S210 , providing a wide bandgap epitaxial wafer 10 , wherein the wide bandgap epitaxial wafer 10 includes a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate.

[0062] S220 , forming a first mask layer 20 on the wide bandgap drift layer, and forming a second mask layer 30 on the first mask layer 20 .

[0063] S230 , removing a portion of the second mask layer 30 to define a first injection window 31 , where the first injection window 31 exposes the first mask layer 20 .

[0064] S240 , forming a well region 11 by ion implantation through the first implantation window 31 , thereby obtaining a first device structure 100 .

[0065] S250. Form a third mask layer 40 on the entire surface of the first device structure 100, etch a portion of the third mask layer 40, retain the third mask layer 40 on the side wall of the first injection window 31 and the third mask layer 40 in the middle area of ​​the first injection window 31, define the second injection window 41, and expose the first mask layer 20 at the bottom of the second injection window 41.

[0066] S260 , forming a heavily doped region 12 by ion implantation through the second implantation window 41 , thereby obtaining a third device structure 300 .

[0067] S270. Form a fifth mask layer 50 on the entire surface of the third device structure 300, remove part of the fifth mask layer 50 to expose the third mask layer 40; remove the second mask layer 30, retain the third mask layer 40 on the side wall of the first injection window 31, the fifth mask layer 50 in the second injection window 41, and the third mask layer 40 in the middle area of ​​the second injection window 41, define the third injection window 51, and expose the first mask layer 20 at the bottom of the third injection window 51.

[0068] S280 , forming a JFET injection region 13 by ion implantation through the third injection window 51 to obtain a fourth device structure 400 , wherein the doping type of the JFET injection region 13 is the same as the doping type of the heavily doped region 12 and different from the doping type of the well region 11 .

[0069] S291. Form a fourth mask layer 60 on the entire surface of the fourth device structure 400, remove part of the fourth mask layer 60, retain the fourth mask layer 60 on the side wall of the third injection window 51 and the fourth mask layer 60 on the side wall of the fifth mask layer 50 located in the second injection window 41, define the fourth injection window 61, and the fourth injection window 61 exposes the first mask layer 20.

[0070] S292 , ion implantation is performed through the fourth implantation window 61 to form a first implantation region 14 . The first implantation region 14 and the JFET implantation region 13 have different doping types.

[0071] The present disclosure uses a self-alignment process to make the implantation positions of the heavily doped region 12, the JFET implantation region 13, and the first implantation region 14 more precise, thereby preventing ions from being implanted into the channel or terminal region when performing ion implantation to form the JFET implantation region 13. The present disclosure can also use a self-alignment process to precisely control the formation of the first implantation region 14 in the center region of the JFET implantation region 13 when performing ion implantation in the JFET implantation region 13. The present disclosure can reduce the use of masks through the self-alignment process. At the same time, the preparation process of the present disclosure is simpler and more controllable than the prior art. The present disclosure retains the implantation mask layer (i.e., the first mask layer 20) when forming the well region 11, the heavily doped region 12, the JFET implantation region 13, and the first implantation region 14 through ion implantation. This effectively avoids the problem of surface damage to the wide bandgap epitaxial wafer 10 that may be caused by ion implantation. The present disclosure can also avoid the collapse of the third mask layer 40 when defining the third injection window 51 when the third mask layer 40 is relatively thin, thereby improving the manufacturing reliability of the MOSFET device.

[0072] like Figure 2 As shown, in step S210, the wide bandgap epitaxial wafer 10 may be made of silicon carbide. In some embodiments, the wide bandgap epitaxial wafer 10 may include a wide bandgap substrate and a wide bandgap drift layer formed on the wide bandgap substrate. In some embodiments, both the wide bandgap substrate and the wide bandgap drift layer may be made of silicon carbide. In some embodiments, the doping type and dopant ion concentration of the wide bandgap substrate and the wide bandgap drift layer are not limited by this disclosure. Persons skilled in the art may select any doping type and dopant ion concentration of the wide bandgap substrate and the wide bandgap drift layer that satisfies known MOSFET device structures.

[0073] like Figure 2 As shown, the material of the first mask layer 20 can be silicon nitride. In some embodiments, those skilled in the art can also choose other feasible materials based on common sense. In some embodiments, the thickness of the first mask layer 20 is between 30nm and 60nm. In some embodiments, the first mask layer 20 provided by the present disclosure can be deposited on the wide bandgap epitaxial wafer 10 by low pressure chemical vapor deposition (i.e., LPCVD). In some embodiments, the material of the second mask layer 30 can be silicon oxide. In some embodiments, the thickness of the second mask layer 30 can be between 1μm and 2μm. In some embodiments, the second mask layer 30 can be deposited on the first mask layer 20 by plasma enhanced chemical vapor deposition (i.e., PECVD) or LPCVD. In some embodiments, the thickness of the second mask layer 30 is greater than the thickness of the first mask layer 20.

[0074] In step S230, Figure 3As shown, a portion of the second mask layer 30 is removed to define a first injection window 31. In some embodiments, the removal of the portion of the second mask layer 30 can be achieved by an etching process. In some embodiments, when the portion of the second mask layer 30 is removed, since the side of the second mask layer 30 close to the wide bandgap epitaxial wafer 10 has the first mask layer 20, after the portion of the second mask layer 30 is removed, the first mask layer 20 will be exposed. In some embodiments, the exposed first mask layer 20 can be used for ion implantation to form an implantation mask layer for the well region 11. In this way, the present disclosure solves the problem of interface damage that may be caused when performing ion implantation to form the well region 11.

[0075] In step S240, Figure 3 As shown, after removing part of the second mask layer 30 to define the first injection window 31, the present disclosure performs ion implantation through the first injection window 31 to form the well region 11, thus obtaining the following Figure 3 The first device structure 100 is shown. In some embodiments, the well region 11 is doped with P-type ions.

[0076] In step S250, Figure 4 As shown, the third mask layer 40 is formed entirely on the third device structure 300. The entire surface of the third mask layer 40 is formed, which means that the side of the first device structure 100 away from the wide bandgap epitaxial wafer 10 is completely covered by the third mask layer 40. In some embodiments, the third mask layer 40 can be deposited entirely on the third device structure 300 by LPCVD. In some embodiments, the material of the third mask layer 40 can be polycrystalline silicon. It is easy to understand that the material, thickness, and growth method of the third mask layer 40 are merely examples provided in this disclosure. In other embodiments, those skilled in the art can also select other feasible material types, thickness ranges, and growth methods according to actual needs.

[0077] In some embodiments, as Figure 5 As shown, after the third mask layer 40 is formed on the entire surface, the present disclosure partially etches the third mask layer 40 to retain the third mask layer 40 on the sidewall of the first injection window 31 (i.e., corresponding to Figure 5 The first portion 401) and the third mask layer 40 in the middle area of ​​the first injection window 31 (ie corresponding to Figure 5 The second portion 402 is exposed in the middle, exposing a portion of the second mask layer 30 and the first mask layer 20 (the portion of the first mask layer 20 corresponds to Figure 5 The middle portion (above) of the first mask layer 20 between the first portion 401 and the second portion 402 defines a second injection window 41, with the bottom of the second injection window 41 exposing the first mask layer 20. In some embodiments, the thickness of the third mask layer 40 on the sidewalls of the second mask layer 30 is between 1000 Å and 1 μm.

[0078] In step S260, Figure 12 As shown, ion implantation is performed through the second implantation window 41 defined in step S250 to obtain a heavily doped region 12, thereby obtaining a third device structure 300. In some embodiments, the heavily doped region 12 is N-type ion doped.

[0079] In step S270, if Figure 13 As shown, after obtaining the third device structure 300, a fifth mask layer 50 is formed entirely on the third device structure 300. Forming the fifth mask layer 50 entirely means that the side of the third device structure 300 facing away from the wide bandgap epitaxial wafer 10 is completely covered with the fifth mask layer 50. In some embodiments, the material of the fifth mask layer 50 is polycrystalline silicon. In some embodiments, the thickness of the fifth mask layer 50 is between 0.1 μm and 1 μm. In some embodiments, the fifth mask layer 50 can be deposited on the third device structure 300 using an LPCVD process.

[0080] like Figure 14 and Figure 15 As shown, after partially removing the fifth mask layer 50 to expose the third mask layer 40, the second mask layer 30 is removed, leaving the third mask layer 40 on the sidewalls of the first injection window 31 (i.e., first portion 401), the third mask layer 40 within the second injection window 41, and the third mask layer 40 in the middle region between the fifth mask layer 50 and the second injection window 41 (i.e., second portion 402), thereby defining the third injection window 51. The bottom of the third injection window 51 exposes the first mask layer 20. In some embodiments, the size of the third injection window 51 can be selected by those skilled in the art, and can be adjusted by changing etching parameters.

[0081] In step S280, Figure 16 As shown, ion implantation is performed through the third implantation window 51 to form a JFET implantation region 13. In some embodiments, the JFET implantation region 13 obtained by the preparation method provided by the present disclosure is formed at a more precise position. In some embodiments, the JFET implantation region 13 is N-type ion doped.

[0082] In some embodiments, after executing step S280, the present disclosure may further include steps S292 and S293. In step S291, as shown in FIG. Figure 17As shown, after obtaining the fourth device structure 400, a fourth mask layer 60 is formed entirely on the fourth device structure 400 in step S291. Forming the fourth mask layer 60 entirely means that the surface of the fourth device structure 400 facing away from the wide bandgap epitaxial wafer 10 is completely covered with the fourth mask layer 60. In some embodiments, the material of the fourth mask layer 60 is polycrystalline silicon. In some embodiments, the thickness of the fourth mask layer 60 is between 0.1 μm and 1 μm. In some embodiments, the fourth mask layer 60 can be deposited entirely on the fourth device structure 400 using an LPCVD process.

[0083] In some embodiments, as Figure 18 As shown, removal of a portion of the fourth mask layer 60 can be achieved using a dry etching process. In some embodiments, the fourth injection window 61 can be formed by removing a portion of the fourth mask layer 60, retaining the fourth mask layer 60 on the sidewalls of the third injection window 51 and the fourth mask layer 60 on the sidewalls of the fifth mask layer 50 located within the second injection window 41. In some embodiments, the fourth injection window exposes the first mask layer 20. In some embodiments, the size of the fourth injection window 61 can be selected by those skilled in the art, and can be adjusted by changing etching parameters.

[0084] In step S292, if Figure 18 As shown, ion implantation is performed through the fourth implantation window 61 to form a first implantation region 14 in the JFET implantation region 13. The obtained first implantation region 14 is precisely located in the JFET implantation region 13. In some embodiments, the first implantation region 14 is P-type ion doped.

[0085] The foregoing description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be within the scope of protection of the present disclosure.

[0086] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

Claims

1. A method for preparing a MOSFET device, characterized in that: include: Providing a wide bandgap epitaxial wafer, the wide bandgap epitaxial wafer comprising a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate; forming a first mask layer on the wide bandgap drift layer, and forming a second mask layer on the first mask layer; removing a portion of the second mask layer to define a first injection window, wherein the first injection window exposes the first mask layer; Forming a well region by ion implantation through the first implantation window to obtain a first device structure; forming a third mask layer on the entire surface of the first device structure, etching a portion of the third mask layer, retaining the third mask layer on the sidewall of the first injection window and the third mask layer in the middle area of ​​the first injection window, defining a second injection window, with the first mask layer exposed at the bottom of the second injection window; Forming a heavily doped region by ion implantation through the second implantation window to obtain a third device structure; forming a fifth mask layer on the entire surface of the third device structure, and removing a portion of the fifth mask layer to expose the third mask layer; removing the second mask layer, retaining the third mask layer on the sidewall of the first injection window, the fifth mask layer in the second injection window, and the third mask layer in the middle area of ​​the second injection window, defining a third injection window, wherein the first mask layer is exposed at the bottom of the third injection window; Forming a JFET injection region through ion implantation in the third injection window to obtain a fourth device structure, wherein the doping type of the JFET injection region is the same as the doping type of the heavily doped region and different from the doping type of the well region; Ion implantation is performed in the JFET implantation region by a self-aligned process to form a first implantation region, wherein the first implantation region has a different doping type from the JFET implantation region.

2. The method for preparing a MOSFET device according to claim 1, characterized in that: The method of performing ion implantation in the JFET implantation region by a self-aligned process to form a first implantation region, wherein the first implantation region has a different doping type from the JFET implantation region, comprises: forming a fourth mask layer on the entire surface of the fourth device structure, removing a portion of the fourth mask layer, retaining the fourth mask layer on the sidewall of the third injection window and the fourth mask layer on the sidewall of the fifth mask layer located in the second injection window, defining a fourth injection window, wherein the fourth injection window exposes the first mask layer; Ions are implanted through the fourth implantation window to form a first implantation region, where the first implantation region and the JFET implantation region have different doping types.

3. The method for preparing a MOSFET device according to claim 2, characterized in that: The material of the wide bandgap epitaxial wafer is silicon carbide; And / or, the material of the first mask layer is silicon nitride; And / or, the material of the second mask layer is silicon oxide; And / or, the material of the third mask layer is polysilicon; And / or, the material of the fourth mask layer is polysilicon; And / or, the material of the fifth mask layer is polysilicon.

4. The method for preparing a MOSFET device according to claim 2, characterized in that: The thickness of the first mask layer is between 30nm and 60nm; And / or, the thickness of the second mask layer is between 1 μm and 2 μm; And / or, the thickness of the fourth mask layer is between 0.1 μm and 1 μm; And / or, the thickness of the fifth mask layer is between 0.1 μm and 1 μm.

5. The method for preparing a MOSFET device according to claim 2, characterized in that: The well region is doped with P-type ions, the heavily doped region is doped with N-type ions, the JFET injection region is doped with N-type ions, and the first injection region is doped with P-type ions.

6. The method for preparing a MOSFET device according to claim 1, characterized in that: The thickness of the third mask layer located on the side wall of the second mask layer is between 1000Å and 1μm.

7. The method for preparing a MOSFET device according to claim 1, characterized in that: The thickness of the second mask layer is greater than the thickness of the first mask layer.

8. A method for preparing a MOSFET device, characterized in that: include: Providing a wide bandgap epitaxial wafer, the wide bandgap epitaxial wafer comprising a wide bandgap substrate and a wide bandgap drift layer disposed on the wide bandgap substrate; forming a first mask layer on the wide bandgap drift layer, and forming a second mask layer on the first mask layer; removing a portion of the second mask layer to define a first injection window, wherein the first injection window exposes the first mask layer; Forming a well region by ion implantation through the first implantation window to obtain a first device structure; forming a third mask layer on the entire surface of the first device structure, removing a portion of the third mask layer, retaining the third mask layer on the sidewall of the first injection window and the third mask layer in the middle area of ​​the first injection window, exposing a portion of the second mask layer and the first mask layer, defining a second injection window, wherein the second injection window exposes the first mask layer; Ion implantation forms a heavily doped region through the second implantation window; removing the second mask layer, retaining the third mask layer on the sidewall of the first injection window and the third mask layer in the middle area of ​​the first injection window, defining a third injection window, wherein the first mask layer is exposed at the bottom of the third injection window; Forming a JFET injection region by ion implantation through the third injection window to obtain a second device structure, wherein the doping type of the JFET injection region is the same as the doping type of the heavily doped region and different from the doping type of the well region; Ion implantation is performed in the JFET implantation region by a self-aligned process to form a first implantation region, wherein the first implantation region has a different doping type from the JFET implantation region.

9. The method for preparing a MOSFET device according to claim 8, characterized in that: The method of performing ion implantation in the JFET implantation region by a self-aligned process to form a first implantation region, wherein the first implantation region has a different doping type from the JFET implantation region, comprises: forming a fourth mask layer on the entire surface of the second device structure, removing a portion of the fourth mask layer, retaining the fourth mask layer on the sidewall of the third injection window and the fourth mask layer located on the sidewall of the second injection window, and defining a fourth injection window; Ions are implanted through the fourth implantation window to form a first implantation region, where the first implantation region and the JFET implantation region have different doping types.

10. The method for preparing a MOSFET device according to claim 9, characterized in that: The material of the wide bandgap epitaxial wafer is silicon carbide; And / or, the material of the first mask layer is silicon nitride; And / or, the material of the second mask layer is silicon oxide; And / or, the material of the third mask layer is polysilicon; And / or, the material of the fourth mask layer is polysilicon.

11. The method for preparing a MOSFET device according to claim 9, characterized in that: The thickness of the first mask layer is between 30nm and 60nm; And / or, the thickness of the second mask layer is between 1 μm and 2 μm; And / or, the thickness of the fourth mask layer is between 0.1 μm and 1 μm.

12. The method for preparing a MOSFET device according to claim 9, characterized in that: The well region is doped with P-type ions, the heavily doped region is doped with N-type ions, the JFET injection region is doped with N-type ions, and the first injection region is doped with P-type ions.

13. The method for preparing a MOSFET device according to claim 8, characterized in that: The thickness of the third mask layer located on the side wall of the second mask layer is between 5000Å and 1μm.

14. The method for preparing a MOSFET device according to claim 8, characterized in that: The thickness of the second mask layer is greater than the thickness of the first mask layer.

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