Semiconductor structure and method for forming the same

Abstract

The method includes forming a first dielectric layer, forming a first redistribution line, the first redistribution line including a first through hole extending into the first dielectric layer and a first trace located above the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a through hole opening. The first redistribution line is exposed through the through hole opening. The method also includes depositing a conductive material into the through hole opening to form a second through hole in the second dielectric layer, and a conductive pad above and contacting the second through hole, and forming a conductive bump above the conductive pad. The conductive pad is larger than the conductive bump, and the second through hole is offset from the centerline of the conductive bump. Embodiments of the present application also relate to semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] As semiconductor technology advances, semiconductor chips / dies are becoming increasingly smaller. Simultaneously, more functionality needs to be integrated into semiconductor dies. Consequently, semiconductor dies require increasingly larger numbers of I / O pads to be packed into smaller areas, and the density of I / O pads has increased rapidly over time. As a result, semiconductor die packaging has become increasingly difficult, negatively impacting the yield of the packaged components.

[0003] A typical bonding structure may include an under bump metallurgy (UBM) as a metal pad and a metal pillar on the UBM. A solder region may be used to bond the metal pillar to another electrical connector of another package component. Summary of the Invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first dielectric layer; forming a first redistribution line, the first redistribution line comprising a first through-hole extending into the first dielectric layer and a first trace located above the first dielectric layer; forming a second dielectric layer covering the first redistribution line; patterning the second dielectric layer to form a through-hole opening, wherein the first redistribution line is exposed through the through-hole opening; depositing a conductive material into the through-hole opening to form a second through-hole in the second dielectric layer and a conductive pad located above and contacting the second through-hole; and forming a conductive bump above the conductive pad, wherein the conductive pad is larger than the conductive bump and the second through-hole is offset from a centerline of the conductive bump.

[0005] Other embodiments of the present application provide a semiconductor structure comprising: a first dielectric layer; a first through-hole extending into the first dielectric layer; a conductive trace located above the first dielectric layer, wherein the conductive trace is located above the first through-hole and coupled to the first through-hole; a second dielectric layer covering the conductive trace; a second through-hole located in the second dielectric layer; a conductive pad located above and contacting the second through-hole; and a conductive bump located above and contacting the conductive pad, wherein the conductive pad extends laterally beyond an edge of the conductive bump, and wherein the second through-hole and the conductive bump are eccentric.

[0006] Still other embodiments of the present application provide a semiconductor structure comprising: a plurality of dielectric layers; a plurality of redistribution lines in the plurality of dielectric layers, wherein each of the plurality of redistribution lines comprises a through-hole and a trace above and contacting the through-hole, and the through-holes in the plurality of redistribution lines are stacked to form a through-hole stack, and the through-holes are vertically aligned; a top through-hole above and contacting a top trace in a top redistribution line of the plurality of redistribution lines; a conductive pad above and contacting the top through-hole; and a conductive bump above and coupled to the conductive pad, wherein the conductive pad and the conductive bump share a common centerline, and the top through-hole deviates from the common centerline, and at least a portion of the top through-hole overlaps with the conductive bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 12 A cross-sectional view is shown of an intermediate stage in forming an interconnect assembly including an off-center engagement structure, according to some embodiments.

[0009] Figure 13 A package including an off-center engagement structure is shown according to some embodiments.

[0010] Figure 14 A cross-sectional view of an off-center engagement structure is shown, according to some embodiments.

[0011] Figure 15 A top view of an over-center engagement structure is shown, according to some embodiments.

[0012] Figure 16 A cross-sectional view of an off-center engagement structure is shown, according to some embodiments.

[0013] Figure 17 A top view of an over-center engagement structure is shown, according to some embodiments.

[0014] Figure 18 and Figure 19 Shown is a structure simulated according to some embodiments.

[0015] Figure 20 A process flow for forming an interconnect assembly including an off-center joint structure is shown, according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples of different components for implementing the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or structures discussed.

[0017] Further, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to easily describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] Provided are a package including an eccentric bonding structure and a method for forming the same. According to some embodiments of the present invention, a conductive bump (which may be a metal column) is formed, and a conductive pad is formed under the conductive bump, wherein the conductive pad is larger than the conductive bump. A first through-hole is located below the conductive pad and bonded to the conductive pad. The first through-hole deviates vertically from the center of the conductive bump above. A plurality of second through-holes located below the first through-hole and electrically connected to the first through-hole also deviate from the first through-hole. This deviation can prevent the through-holes and pads with high coefficient of thermal expansion (CTE) values ​​from being vertically aligned, and thus can reduce stress. The embodiments discussed herein will provide examples to enable the subject matter of the present invention to be carried out or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to indicate the same elements. Although the method embodiments discussed can be performed in a particular order, other method embodiments can be performed in any logical order.

[0019] Figures 1 to 12 1 shows a cross-sectional view of an intermediate stage in forming an interconnect assembly including an eccentric joint structure according to some embodiments of the present invention. The corresponding process is also schematically shown in FIG. Figure 20It will be appreciated that although the interconnect assembly including the off-center bonding structure is formed starting from a carrier, it may also be formed starting from other components such as a fan-out interconnect structure of a device die, a portion of a device die, or an interposer.

[0020] Figure 1 A carrier 20 and a release film 22 formed on the carrier 20 are shown. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, or the like. According to some embodiments, the carrier 20 may have a circular top view shape. The release film 22 may be formed of a polymer-based material (such as a light-to-heat conversion (LTHC) material) that can be decomposed under radiation such as a laser beam, thereby allowing the carrier 20 to be peeled off from the structure formed thereon in a subsequent process. According to some embodiments of the present invention, the release film 22 is formed of an epoxy-based thermal release material applied to the carrier 20.

[0021] like Figures 1 to 4 As shown in FIG, a plurality of dielectric layers and a plurality of RDLs are formed on the release film 22. The corresponding process is shown in FIG. Figure 20 The process 202 in the process flow 200 is shown. Figure 1 , first, a dielectric layer 24 is formed on the release film 22. According to some embodiments of the present invention, the dielectric layer 24 is formed of a polymer, which may also be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which can be easily patterned using a photolithography process.

[0022] According to some embodiments, redistribution lines (RDLs) 26 are formed over dielectric layer 24. The formation of RDLs 26 may include forming a seed layer (not shown) over dielectric layer 24, forming a patterned mask (not shown) such as a photoresist over the seed layer, and then performing a metal plating process on the exposed seed layer. The patterned mask and the portion of the seed layer covered by the patterned mask are then removed, leaving a layer such as Figure 1 According to some embodiments of the present invention, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or a similar process. The plating can be performed using, for example, electroless plating.

[0023] Further references Figure 1, a dielectric layer 28 is formed on RDL 26. The bottom surface of dielectric layer 28 contacts the top surface of RDL 26 and dielectric layer 24. According to some embodiments of the present invention, dielectric layer 28 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc. Alternatively, dielectric layer 28 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. Dielectric layer 28 is then patterned to form openings 30 therein. As a result, portions of RDL 26 are exposed through openings 30 in dielectric layer 28.

[0024] Next, refer to Figure 2 , forming RDL 32 to connect to RDL 26. RDL 32 includes metal traces (metal lines) located above dielectric layer 28. RDL 32 also includes vias extending into openings 30 in dielectric layer 28. RDL 32 can also be formed by a plating process, wherein each RDL 32 includes a seed layer (not shown) and a plated metal material located above the seed layer. According to some embodiments, the formation of RDL 32 may include: depositing a blanket metal seed layer extending into the via opening; and forming and patterning a plating mask (such as a photoresist), wherein the opening is formed directly above the via opening. A plating process is then performed to plate a metal material that completely fills the via opening 30 and has some portions that are higher than the top surface of dielectric layer 28. The plating mask is then removed, followed by an etching process to remove the exposed portions of the metal seed layer previously covered by the plating mask. The remaining portions of the metal seed layer and the plated metal material are RDL 32.

[0025] The metal seed layer and the plating material can be formed of the same material or different materials. The metal material in the RDL 32 can include a metal or a metal alloy, and the metal or metal alloy includes copper, aluminum, tungsten or an alloy thereof. The RDL 32 includes an RDL line (also referred to as a trace or trace portion) 32L and a through-hole portion (also referred to as a via) 32V, wherein the trace portion 32L is located above the dielectric layer 28 and the through-hole portion 32V is located in the dielectric layer 28. Because the trace portion 32L and the through-hole portion (also referred to as a via) 32V are formed in the same plating process, there is no distinguishable interface between the through-hole 32V and the corresponding trace portion 32L above. Moreover, each through-hole 32V can have a tapered profile, wherein the upper portion is wider than the corresponding lower portion.

[0026] refer to Figure 3 , dielectric layer 34 is formed over RDL 32 and dielectric layer 28. Dielectric layer 34 may be formed using a polymer, which may be selected from the same group of candidate materials as those of dielectric layer 28. For example, dielectric layer 34 may be formed of PBO, polyimide, BCB, etc. Alternatively, dielectric layer 34 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc.

[0027] Figure 3 Also shown is the formation of RDL 36 electrically connected to RDL 32. RDL 36 may be formed using methods and materials similar to those used to form RDL 32. RDL 36 includes trace portions (RDL lines) 36L and via portions (vias) 36V, wherein trace portions 36L are located above dielectric layer 34 and via portions 36V extend into dielectric layer 34. Furthermore, each via 36V may have a tapered profile, wherein an upper portion is wider than a corresponding lower portion.

[0028] Figure 4 The formation of dielectric layers 38 and 42 and RDLs 40 and 44 is shown. According to some embodiments of the present invention, dielectric layers 38 and 42 are formed of materials selected from the same group of candidate materials used to form dielectric layers 34 and 38, and may include organic or inorganic materials as described above. It should be understood that while in the exemplary embodiment shown, four dielectric layers 28, 34, 38, and 42 and corresponding RDLs 32, 36, 40, and 44 formed therein are discussed as examples, fewer or more dielectric and RDL layers may be employed depending on routing requirements.

[0029] Figures 5 to 10 The through-hole 56, the conductive pad 58 and the conductive bump 60 are shown in accordance with some embodiments. Figure 10 ) formation. Figure 5 , forming a dielectric layer 46. The corresponding process is shown as Figure 20 The process 204 in the process flow 200 is shown. According to some embodiments, the dielectric layer 46 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc. The dielectric layer 46 is patterned to form a via opening 48, thereby partially exposing the pad of the underlying RDL line 44L. The corresponding process is shown as Figure 20 Process 206 of process flow 200 is shown. According to some embodiments, the via opening 48 is laterally offset from the corresponding underlying via 44V. Figure 5 As shown, some vias 44V (such as via 44V-1) may be aligned with the center of an upper RDL line 44L (such as 44L1). Some other vias 44V may be offset from the center of the corresponding upper RDL line 44L. For example, via 44V-2 is offset to the right from the middle of RDL line 44L-2.

[0030] refer to Figure 6 , depositing a metal seed layer 51. The corresponding process is shown as Figure 20The process 208 in the process flow 200 is shown. According to some embodiments, the metal seed layer 51 includes a titanium layer and a copper layer located above the titanium layer. According to an alternative embodiment, the metal seed layer 51 includes a single copper layer that physically contacts the dielectric layer 46. Then, a plating mask 50 is formed and patterned, wherein an opening 52 is formed in the plating mask 50. The corresponding process is shown as Figure 20 Process 210 of process flow 200 is shown. Via opening 48 is located below and bonded to opening 52. The top view shape of opening 52 may include a circle or a polygonal shape such as a hexagon, octagon, or the like.

[0031] refer to Figure 7 , metal material 54 is deposited by plating process. The corresponding process is shown as Figure 20 The process 212 in the process flow 200 is shown. The plating process may include electrochemical plating, chemical plating, etc. According to some embodiments, the metal material 54 includes copper or a copper alloy. The process conditions may be adjusted so that the top surface of the plated material 54 can be flat. According to an optional embodiment, the top surface portion of the metal material 54 may have a groove, as shown by the dotted line 53, which is formed by the filling of the through-hole opening 48 ( Figure 7 ).

[0032] In the subsequent process, the plating mask 50, which may be a photoresist, may be removed, for example, by an ashing process. The corresponding process is shown as follows: Figure 20 This is process 214 of process flow 200. As a result, a portion of the underlying metal seed layer 51 is exposed.

[0033] refer to Figure 8 Without removing the metal seed layer 51, a plating mask 57 is formed on the metal seed layer 51 and the plating material 54, and an opening 52' is formed to expose the plating material 54. The corresponding process is shown as follows Figure 20 The process 216 in the process flow 200 is shown. Next, the conductive bump 60 is formed by a plating process which may be, for example, an electrochemical plating process or an electroless plating process. The corresponding process is shown as Figure 20 The process 218 in the process flow 200 is shown. The entire conductive bump 60 can be formed of a homogeneous material such as copper or a copper alloy. There can be a distinguishable interface between the conductive bump 60 and the underlying plated material 54, or the conductive bump 60 and the underlying plated material 54 can merge with each other (for example, when both are formed of copper) without a distinguishable interface between the two. The conductive bumps 60 are also called metal pillars or metal rods due to their shape. For example, Figure 19 An exemplary conductive bump 60 is shown having a circular top view shape, while other shapes such as hexagonal, octagonal, etc. may also be employed depending on the top view shape of the opening 52 ′. Figure 9Also shown is the deposition of a solder region 62, also deposited by plating, according to some embodiments. Solder region 62 may be formed of or include AgSn, AgSnCu, SnPb, etc. According to alternative embodiments, solder region 62 is not formed.

[0034] In the subsequent process, the plating mask 57 is removed, for example, by ashing. The corresponding process is shown as Figure 20 Next, an etching process, which may be a wet etching process or a dry etching process, is performed to remove the exposed portion of the metal seed layer 51. The corresponding process is shown as Figure 20 The process flow 200 is shown as process 222. The portion of the metal seed layer 51 directly below the metallization material 54 remains. Throughout the specification, the metal material 54 and the remaining portion of the metal seed layer 51 below are collectively referred to as the via 56 (also referred to as the top via) and the conductive pad 58. Figure 10 The resulting structure is shown in FIG. Via 56 is the portion located within dielectric layer 46, while conductive pad 58 is the portion located above dielectric layer 46. Each via 56 and conductive pad 58 may include a remaining portion of metal seed layer 51 and a portion of plating material 54. Conductive bump 60 is directly above conductive pad 58 and is laterally recessed from the edge of conductive pad 58. In other words, conductive pad 58 is larger than conductive bump 60.

[0035] Throughout the specification, the structure located above the release film 22 is referred to as the interconnect assembly 64. In a subsequent process, the interconnect assembly 64 can be placed on a frame (not shown), wherein the solder area 62 is adhered to the tape in the frame. The interconnect assembly 64 is then peeled off from the carrier 20, for example, by projecting UV light or a laser beam onto the release film 22, thereby causing the release film 22 to decompose under the heat of the UV light or laser beam. The corresponding process is shown as Figure 20 The process 224 of the process flow 200 is shown. Thus, the interconnect assembly 64 is peeled from the carrier 20. The resulting interconnect assembly 64 is Figure 11 In the resulting structure, the dielectric layer 24 may be exposed. If solder regions 62 are formed, they may be reflowed to have a rounded surface.

[0036] Further references Figure 11, forming electrical connector 66 to electrically connect to RDL 26. According to some embodiments, electrical connector 66 is a UBM. The formation process of UBM 66 may also include: patterning dielectric layer 24 to form an opening; depositing a metal seed layer that may include a titanium layer and a copper layer located on the titanium layer; forming and patterning a plating mask; plating a conductive material; removing the plating mask, and etching the metal seed layer. According to other embodiments, electrical connector 66 is a solder region, and the formation process may include patterning dielectric layer 24 (e.g., by laser drilling) to form an opening, placing a solder ball into the opening, and performing a reflow process to reflow the solder region.

[0037] In a subsequent process, interconnect component 64 is separated in a sawing process to form a plurality of identical interconnect components 64 ′ (also referred to as package components 64 ′). The sawing process may be performed by sawing interconnect component 64 along scribe lines 68 .

[0038] Interconnect assembly 64 ′ may be used to form a package. Figure 12 1 shows a portion of an exemplary structure including bonding interconnect assembly 64' to package assembly 70. According to some embodiments, electrical connectors 72 located on a surface of package assembly 70 may be bonded to interconnect assembly 64' via solder regions 74. Solder regions 74 may include, for example, Figure 11 The solder region 62 is shown. The electrical connector 72 may be a UBM, a metal pillar, a bonding pad, etc. According to alternative embodiments, the electrical connector 72 is a metal pillar and is bonded to the conductive bump 60 by direct metal-to-metal bonding. According to these embodiments, the solder region 62 is not formed ( Figure 11 ), and the conductive bump 60 is physically bonded to the electrical connector 72. According to some embodiments, an underfill 76 is dispensed into the gap between the package component 70 and the interconnect component 64'. The underfill 76 contacts the sidewalls and top surface of the extended portion of the conductive pad 58, and the extended portion extends laterally beyond the edge of the conductive bump 60 above. An encapsulant 78, which can be formed of or include a molding compound, is dispensed. A planarization process can be performed to make the top surface of the package component 70 flush with the top surface of the encapsulant 78.

[0039] Figure 13 An application of an interconnect assembly 64' is shown. Figure 12 The structure shown can also be Figure 13 Each interconnect assembly 64' is bonded to one or more package assemblies 70 (including 70A and 70B as examples). Some structural details such as the eccentric bonding structure are not shown in detail and are referenced. Figure 11 and Figure 12 as well as Figures 14 to 16These details can be found at . According to some embodiments, the package assembly 70 includes a logic die that can be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller (MCU) die, an input and output (IO) die, a baseband (BB) die, an application processing (AP) die, etc. The package assembly 70 may also include a memory die such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc. The memory die may be a discrete memory die, or may be a die stack in the form of a plurality of stacked memory dies. The package assembly 70 may also include a system on chip (SOC) die.

[0040] According to some embodiments, package assembly 70 includes package assembly 70A, which may be a logic die or a SOC die. According to some embodiments, package assembly 70A includes a semiconductor substrate 71 and an integrated circuit device (not shown, for example, including a transistor). Package assembly 70 may also include package assembly 70B, which may be a memory die or a memory stack. Underfill 76 and molding compound 78 are also shown.

[0041] Interconnect component 64' is also bonded to package component 80. According to some embodiments, package component 80 is or includes an interposer, a package substrate, a printed circuit board, etc. Bonding can be achieved through solder regions 82. Underfill 84 is dispensed between interconnect component 64' and package component 80.

[0042] Figure 14 and Figure 15 sectional view and top view of a portion of an eccentric structure according to some embodiments are shown, respectively. Figure 12 According to some embodiments, the conductive bump 60 and the conductive pad 58 both have symmetrical structures. For example, Figure 15 The conductive bump 60 and the conductive pad 58 are shown to have a circular top view shape. The conductive bump 60 and the conductive pad 58 may have a common centerline 60C, and the conductive bump 60 and the conductive pad 58 are symmetrical with respect to the centerline 60C. According to other embodiments, the conductive bump 60 and the conductive pad 58 may have other symmetrical top view shapes, including but not limited to hexagons, octagons, etc. that are also symmetrical with respect to the centerline 60C. The through hole 56 is offset from the centerline 60C. For example, the through hole 56 is at Figure 14 On the other hand, through-hole 44V is offset from through-hole 56. Through-holes 40V, 36V, and 32V may be vertically aligned with through-hole 44V or may be offset from through-hole 44V. Throughout this specification, due to the vertical misalignment of the center lines of through-hole 56 and conductive bump 60, the corresponding bonding structure is referred to as an off-center bonding structure.

[0043] In conventional structures, through-hole 56 is aligned with centerline 60C. However, this creates a problem. For example, conductive bump 60, conductive pad 58, and through-holes 44V, 40V, and 36V are formed of metal having a much larger CTE value than the coefficient of thermal expansion (CTE) of surrounding materials such as dielectric layers 46, 42, and 38, bottom filler 76, and sealant 78. When through-holes 56, 44V (and possible through-holes 40V and 36V) are also aligned with centerline 60C, there is high stress in the resulting structure, which may cause delamination and trace fracture. In order to reduce stress, if through-hole 44V is moved laterally (while through-hole 56 is aligned with centerline 60C) to deviate from conductive pad 58, the resulting structure will occupy a larger chip area. In the present invention, through-hole 56 deviates from centerline 60C, so that through-hole 44V can deviate from through-hole 56 without causing loss of area, while reducing stress. For example, when the temperature rises and via 56 applies a downward force to the underlying portion of RDL line 44L, this force will not be transferred to via 44V (or at least a reduced force will be transferred) due to the flexibility of RDL line 44L, and thus this force (if any) will not be added to the force generated by the expansion of via 44V and the underlying RDL lines and vias.

[0044] Figure 18 and Figure 19 Two structures are shown on which the simulations were performed. Figure 18 The structure shown in FIG. 5 represents a conventional structure with conductive bumps 60 ′, vias 56 ′, RDL pads 44L′, and vias 44V′ vertically aligned. Figure 19 The structure shown in FIG. 1 represents a structure having a conductive bump 60, a conductive pad 58, a via 56, an RDL line 44L, and a via 44V formed according to some embodiments of the present invention. The via 56 is offset from the center line of the conductive bump 60 and the conductive pad 58. The via 44V is offset from the via 56. Simulation results show that when the RDL line 40L' ( Figure 18 ) has a normalized magnitude of 1.0, applied to the RDL line 40L ( Figure 19 ) has a normalized magnitude of 0.9, which means that the embodiment of the present invention has a 10% reduced stress compared to the conventional structure.

[0045] Reference again Figure 14 According to some embodiments, the through hole 56 is offset from the center line 60C of the conductive bump 60 by a spacing S1. The offset spacing S1 may be equal to or greater than about 8.5 μm, and may be in a range between about 8.5 μm and about 20 μm. In addition, it is desirable that the through hole 56 at least partially overlaps the conductive bump 60. For example, Figure 14The right side portion of the through hole 56 is shown overlapping the conductive bump 60, while the left side portion of the through hole 56 extends beyond the left edge of the conductive bump 60. The (at least partial) overlap of the conductive bump 60 advantageously allows the through hole 56 to support both the conductive pad 58 and the conductive bump 60 and to adequately transfer the stress received by the through hole 56 from the conductive pad 58 to the RDL line 44L. This allows the RDL line 44L to absorb a sufficient amount of stress. According to alternative embodiments, such as Figure 15 As shown, the through hole 56 can be slightly offset to the right to a position as shown at 56', so that the entire through hole 56 overlaps the conductive bump 60. For example, according to some embodiments, the left edge of the through hole 56 can be aligned with the left edge of the conductive bump 60. Figure 15 It can be realized that increasing the size of the conductive pad 58 to be larger than the size of the conductive bump 60 allows the via 56 to be offset a desired distance.

[0046] like Figure 14 As shown, according to some embodiments of the present invention, via 44V is offset from both centerline 60C and via 56. Via 44V and via 56 may also be offset in opposite directions relative to centerline 60C. According to some embodiments, vias 56 and 44V are on opposite sides of centerline 60C, and no portion of via 56 or via 44V passes through centerline 60C. Deviating vias 56 and 44V in opposite directions from centerline 60C can increase the distance between vias 56 and 44V and increase the length of the portion of RDL line 44L that interconnects vias 56 and 44V. This can also improve the ability of RDL line 44L to absorb stress. According to some embodiments, vias 40V, 36V, and / or 32V are vertically aligned with via 44V. According to alternative embodiments, each or all of vias 40V, 36V, and / or 32V may be laterally offset to the left or right from via 44V.

[0047] According to an alternative embodiment, the centerline 44VC of the via 44V is still offset from the centerline 60C by a small offset, while the via 44V still passes through the centerline 60C. The offset of the via 44V in the opposite direction of the via 56 still creates a lateral spacing between the vias 56 and 44V and improves the stress absorption of the RDL line 44L. On the other hand, the via 44V can overlap with the conductive pad 58 and the conductive bump 60, so that the via 44V will not occupy additional chip area (unless needed for signal rerouting reasons) because it occupies the same chip area occupied by the conductive pad 58 and the conductive bump 60.

[0048] Reference again Figure 15, with some dimensions marked. According to some embodiments, from a top view, the lateral spacing S2 between the centerline 60C and the edge of the through-hole 56 can be in a range between about 4 μm and about 12 μm. The diameter Dia58 of the conductive pad 58 can be in a range between about 30 μm and 50 μm. The diameter Dia60 of the conductive bump 60 can be in a range between about 20 μm and 40 μm. The diameters Dia56 and Dia44V can be in a range within 30 μm. In some embodiments, the diameters Dia56 and Dia44V can be in a range between about 7 μm and about 20 μm.

[0049] Figure 16 and Figure 17 The cross-sectional view and top view of a portion of the eccentric structure according to an optional embodiment are shown respectively. Figure 12 These embodiments are similar to those of Figure 14 and Figure 15 , except that via 44V is aligned with the centerline 60C of conductive bump 60. Each or all of vias 40V, 36V, and 32V may be vertically aligned with via 44V or laterally offset to the left or right from via 44V. These embodiments may be employed when the spacing between vias 56 and 44V is large enough to provide adequate stress absorption by pad-and-trace portion 44L, e.g., when the reduction approaches saturation, and when further increases in spacing do not produce a significant reduction in stress. Figure 14 Compared to the structure shown, with via 44V (and vias 40V and 36V) offset to the left, additional RDL for routing (such as RDL lines 44A, 40A, and 36A) can be provided on the right side of the chip area.

[0050] Depending on the size of through-hole 56 and through-hole 44V, a small portion of through-hole 44V may overlap with through-hole 56, or alternatively, the entire through-hole 44V may be offset from through-hole 56. Respective through-holes 56 and 44V are shown as dashed lines ( Figure 17 ), marked as through holes 56" and 44V' respectively.

[0051] In the exemplary embodiments provided above, the eccentric bonding structure is formed in a build-up substrate. According to optional embodiments, the eccentric bonding structure may be formed in an interposer that may include a semiconductor substrate and a through-hole located in the semiconductor substrate. For example, when an RDL for the interposer is formed after backside polishing is used to expose the through-hole, the eccentric bonding structure may be formed as part of the RDL structure of the interposer. According to other optional embodiments, the eccentric bonding structure may be formed in a chip-on-wafer-on-substrate (CoWoS) package, wherein the eccentric bonding structure may be formed in one or both of the wafer and the package substrate. According to other optional embodiments, the eccentric bonding structure may be formed in a fan-out package, wherein the eccentric bonding structure may be formed in a fan-out RDL that is formed after molding of the device die.

[0052] In the embodiments shown above, some processes and components for forming three-dimensional (3D) packages are discussed according to some embodiments of the present invention. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. For example, the test structure may include test pads formed in a redistribution layer or on a substrate to allow the use of probes and / or probe cards, etc. to test the 3D package or 3DIC. Verification tests can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0053] Embodiments of the present invention have several advantageous features. By forming an eccentric joint structure, stress in the joint structure and surrounding components is reduced. This stress reduction does not increase manufacturing costs or cause a loss of chip area.

[0054] According to some embodiments of the present invention, a method includes forming a first dielectric layer; forming a first redistribution line, the first redistribution line including a first via extending into the first dielectric layer and a first trace located above the first dielectric layer; forming a second dielectric layer covering the first redistribution line; patterning the second dielectric layer to form a via opening, wherein the first redistribution line is exposed through the via opening; depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad located above and contacting the second via; and forming a conductive bump above the conductive pad, wherein the conductive pad is larger than the conductive bump and the second via is offset from a centerline of the conductive bump. According to an embodiment, the second via and the conductive pad are formed by a common plating process. According to an embodiment, the second via, the conductive pad, and the conductive bump are formed using the same metal seed layer. According to an embodiment, the method further includes bonding a package component above the conductive bump; and dispensing an underfill, wherein the underfill contacts a first sidewall of the conductive bump and the underfill also contacts a top surface and a second sidewall of the conductive pad. According to an embodiment, the second through hole includes a first portion overlapping the conductive bump and a second portion extending beyond a corresponding edge of the conductive bump. According to an embodiment, the first through hole is further offset from a centerline of the conductive bump, and the first through hole and the second through hole are on opposite sides of the centerline of the conductive bump. According to an embodiment, the first through hole includes at least a portion overlapping the conductive bump. According to an embodiment, the first through hole is aligned with the centerline of the conductive bump.

[0055] According to some embodiments of the present invention, a structure includes a first dielectric layer; a first via extending into the first dielectric layer; a conductive trace located above the first dielectric layer, wherein the conductive trace is located above and bonded to the first via; a second dielectric layer covering the conductive trace; a second via located in the second dielectric layer; a conductive pad located above and contacting the second via; and a conductive bump located above and contacting the conductive pad, wherein the conductive pad extends laterally beyond an edge of the conductive bump, and wherein the second via and the conductive bump are off-center. In one embodiment, the conductive bump and the conductive pad have a circular top view shape. In one embodiment, the second via has a first portion that overlaps the conductive bump. In one embodiment, the second via further includes a second portion that extends beyond the edge of the conductive bump. In one embodiment, the first via is aligned with a centerline of the conductive bump. In one embodiment, the first via is offset from the centerline of the conductive bump. In one embodiment, the first via and the second via are on opposite sides of the centerline of the conductive bump, and the second via also partially overlaps the conductive bump.

[0056] According to some embodiments of the present invention, a structure includes a plurality of dielectric layers; a plurality of redistribution lines located in the plurality of dielectric layers, wherein each of the plurality of redistribution lines includes a via and a trace located above and contacting the via, and the vias in the plurality of redistribution lines are stacked to form a via stack, and the vias are vertically aligned; a top via located above and contacting a top trace of a top redistribution line in the plurality of redistribution lines; a conductive pad located above and contacting the top via; and a conductive bump located above and bonded to the conductive pad, wherein the conductive pad and the conductive bump share a common centerline, and the top via is offset from the common centerline, and at least a portion of the top via overlaps the conductive bump. According to an embodiment, the common centerline does not pass through the top via. According to an embodiment, the top via completely overlaps the conductive bump. According to an embodiment, the top via partially overlaps the conductive bump. According to an embodiment, the structure further includes an underfill in contact with a first sidewall of the conductive bump and a second sidewall and a top surface of the conductive pad.

[0057] The features of several embodiments have been summarized above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first dielectric layer; forming a first redistribution line comprising a first via extending into the first dielectric layer and a first trace over the first dielectric layer; forming a second dielectric layer covering the first redistribution line; patterning the second dielectric layer to form a via opening, wherein the first redistribution line is exposed through the via opening; depositing a conductive material into the via opening to form a second via in the second dielectric layer and a conductive pad overlying and contacting the second via; and forming a conductive bump over the conductive pad, wherein the conductive pad is larger than the conductive bump, and the second through hole is offset from a center line of the conductive bump, Wherein, the first through hole deviates from the center line of the conductive bump, and the first through hole and the second through hole are on opposite sides of the center line of the conductive bump, and the first through hole and the second through hole are both partially arranged within the lateral range of the conductive bump and completely arranged within the lateral range of the conductive pad.

2. The method according to claim 1, wherein The second through hole and the conductive pad are formed by a common plating process.

3. The method according to claim 1, wherein The second through hole, the conductive pad, and the conductive bump are formed using a same metal seed layer.

4. The method according to claim 1, further comprising: bonding a package component over the conductive bump; as well as An underfill is dispensed, wherein the underfill contacts a first sidewall of the conductive bump and the underfill also contacts a top surface and a second sidewall of the conductive pad.

5. The method according to claim 1, wherein The conductive bumps are formed by a plating process.

6. The method according to claim 1, wherein The conductive bump and the conductive pad have a common center line, and the conductive bump and the conductive pad are symmetrical with respect to the center line.

7. The method according to claim 1, wherein The conductive bump has a circular top view shape.

8. The method according to claim 1, wherein The conductive bump is formed of a homogeneous material.

9. A semiconductor structure comprising: a first dielectric layer; a first through hole extending into the first dielectric layer; a conductive trace over the first dielectric layer, wherein the conductive trace is over and bonded to the first via; a second dielectric layer covering the conductive traces; a second via in the second dielectric layer and contacting the conductive trace; a conductive pad located above and contacting the second through hole; and a conductive bump located above and contacting the conductive pad, wherein the conductive pad extends laterally beyond an edge of the conductive bump, and wherein the second through hole and the conductive bump are off-center, Wherein, the first through hole deviates from the center line of the conductive bump, and the first through hole and the second through hole are on opposite sides of the center line of the conductive bump, and the first through hole and the second through hole are both partially arranged within the lateral range of the conductive bump and completely arranged within the lateral range of the conductive pad.

10. The semiconductor structure according to claim 9, wherein The conductive bumps and the conductive pads have a circular top view shape.

11. The semiconductor structure according to claim 9, wherein The conductive bump is formed of a homogeneous material.

12. The semiconductor structure according to claim 11, wherein The homogeneous material includes copper.

13. The semiconductor structure according to claim 9, wherein The conductive bump and the conductive pad have a common center line.

14. The semiconductor structure according to claim 9, wherein: The conductive bumps and the conductive pads are symmetrical with respect to the center line.

15. The semiconductor structure according to claim 9, wherein The offset pitch of the second through hole from the center line of the conductive bump is equal to or greater than 8.5 μm.

16. A semiconductor structure comprising: multiple dielectric layers; a plurality of redistribution lines disposed in the plurality of dielectric layers, wherein each of the plurality of redistribution lines comprises a via and a trace disposed over and contacting the via, and wherein the vias in the plurality of redistribution lines are stacked to form a via stack, and wherein the vias are vertically aligned; a top via located above and contacting a top trace in a top redistribution line of the plurality of redistribution lines; a conductive pad located above and contacting the top through-hole; and a conductive bump overlying and bonded to the conductive pad, wherein the conductive pad and the conductive bump share a common centerline, and the top via is offset from the common centerline, and a portion of the top via overlaps the conductive bump, Wherein, the through hole deviates from the center line of the conductive bump, and the through hole and the top through hole are on opposite sides of the center line of the conductive bump, and the through hole and the top through hole are both partially arranged within the lateral range of the conductive bump and completely arranged within the lateral range of the conductive pad.

17. The semiconductor structure according to claim 16, wherein The conductive bump is formed of a homogeneous material.

18. The semiconductor structure according to claim 16, wherein The conductive bumps and the conductive pads are symmetrical with respect to the center line.

19. The semiconductor structure according to claim 16, wherein The top through hole deviates from the center line of the conductive bump by an offset pitch equal to or greater than 8.5 μm.

20. The semiconductor structure of claim 16, further comprising The bottom filler contacts the first sidewall of the conductive bump and the second sidewall and top surface of the conductive pad.

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