Chip Packaging Test Structure and Its Preparation Method

Abstract

The present invention provides a chip package test structure and a preparation method thereof. The chip package test structure includes a base wafer, a protective layer located on the surface of the base wafer, and conductive bumps located on the protective layer. Before forming the conductive bumps on the surface of the base wafer, the present invention first forms a protective layer on the surface of the wafer, thereby enhancing the adhesion between the conductive bumps and the wafer, avoiding the detachment of the conductive bumps in subsequent processes such as cleaning, and effectively improving the stability of the test structure, which helps to reduce the test cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a chip bonding package test structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the device integration degree has been increasing day by day. The density of the interconnect structure used in the packaging process has been continuously increasing while the packaging thickness has been continuously compressed. Some advanced packaging technologies, such as WLP (wafer-level packaging), TSV (through-silicon via), 2.5D silicon interposer packaging, 3D packaging, fan out (fan-out packaging), etc., have emerged one after another.

[0003] To ensure the performance of the packaged chip, electrical testing is usually required after chip bonding. During chip bonding package testing, a large number of conductive bumps are usually prepared on the surface of the silicon substrate wafer for testing. After that, the chip is soldered to the conductive bumps using a soldering flux and then cleaned to remove the residual soldering flux. The substrate wafer is usually a bare wafer without any structure prepared on its surface, that is, the surface is a smooth single-crystalline silicon or polycrystalline silicon layer. Since the adhesion between the conductive bumps and the surface of the silicon substrate wafer is very poor, the conductive bumps often fall off during the subsequent cleaning or stripping process of the soldering flux, resulting in damage to the test structure. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a chip bonding package test structure, a preparation method, and a chip bonding package test method based on the chip bonding package test structure, which are used to solve the problems that in the prior art, when forming conductive bumps directly on a bare wafer and flipping the chip onto the conductive bumps during chip bonding package testing, the conductive bumps are likely to fall off during the subsequent cleaning or stripping process, resulting in damage to the test structure.

[0005] To achieve the above object and other related objects, the present invention provides a preparation method of a chip bonding package test structure, including the steps of:

[0006] Providing a substrate wafer, and forming a protective layer on the surface of the substrate wafer;

[0007] Forming conductive bumps on the protective layer.

[0008] Optionally, the formation method of the protective layer includes one or a combination of two of the oxidation method and the chemical vapor deposition method.

[0009] Optionally, the protective layer includes one of silicon nitride layer, silicon oxide layer, and silicon oxynitride layer or a stack composed of multiple types.

[0010] Optionally, the thickness of the protective layer is 500 nm - 5000 nm.

[0011] The present invention also provides a chip-scale package (CSP) test structure, which includes a substrate wafer, a protective layer on the surface of the substrate wafer, and conductive bumps on the protective layer.

[0012] Optionally, the protective layer includes one of silicon nitride layer, silicon oxide layer, and silicon oxynitride layer or a stack composed of multiple of them.

[0013] Optionally, the thickness of the protective layer is 500 nm - 5000 nm.

[0014] The present invention also provides a CSP test method, including the steps of:

[0015] Providing a substrate wafer and forming a protective layer on the surface of the substrate wafer;

[0016] Forming conductive bumps on the surface of the protective layer;

[0017] Inverting a chip to be tested onto the surface of the conductive bumps through a soldering flux to obtain a test structure;

[0018] Cleaning the test structure;

[0019] Testing the test structure.

[0020] Optionally, the method for forming the protective layer includes one or a combination of two of oxidation method and chemical vapor deposition (CVD) method.

[0021] Optionally, the protective layer includes one of silicon nitride layer, silicon oxide layer, and silicon oxynitride layer or a stack composed of multiple of them.

[0022] As described above, the CSP test structure and its preparation method of the present invention have the following beneficial effects: Before forming the conductive bumps on the surface of the substrate wafer, the present invention first forms a protective layer on the surface of the wafer, thereby enhancing the adhesion between the conductive bumps and the wafer, avoiding the conductive bumps from falling off in subsequent processes such as cleaning, effectively improving the stability of the test structure, and helping to reduce the test cost. Description of the Drawings

[0023] Figures 1-5 A schematic diagram showing the CSP test process in the prior art.

[0024] Figures 6-11 Schematic diagrams showing each step of the CSP test method provided by the present invention.

[0025] Description of Element Numbers

[0026] 11, 21 Substrate wafer

[0027] 12 Protective layer

[0028] 13, 23 Conductive bumps

[0029] 14, 24 Chips

[0030] 141 Conductive pins

[0031] 15, 25 Flux Detailed implementation manners

[0032] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples, and they should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0033] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0034] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0035] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex. To make the diagrams as concise as possible, not all structures are labeled in each drawing.

[0036] To ensure the performance of the packaged chip, usually after the chip is soldered to the packaging substrate, a chip-on-board packaging test is carried out to test the electrical performance of the chip. The process of a common chip-on-board packaging test is as Figures 1-5 shown, including providing a substrate wafer 21 (refer to Figure 1 ), preparing a plurality of conductive bumps 23 on the test wafer 21 (refer to Figure 2 ), dropwise applying a soldering flux 25 on the surface of the pins of the chip 24 to be tested (refer to Figure 3 ), and then soldering the chip 24 to the conductive bumps 23 with the pins facing the conductive bumps 23 (i.e., flip chip, flip-chip bonding) to obtain Figure 4 the structure shown. After soldering, cleaning (flux clean) is carried out to avoid chip contamination caused by residual soldering flux and affect the performance of the chip. For example, to avoid problems such as a decrease in the electrical insulation performance and short circuit of the chip caused by the soldering flux. After cleaning, the electrical performance test of the chip is carried out. Since the test wafers used in the prior art are usually bare silicon wafers without any device structures (including any film layers) prepared on their surfaces, the adhesion of the formed conductive bumps on the surface of the bare silicon wafer is very poor and is prone to falling off during the cleaning process (refer to the A area marked by the dotted circle in Figure 5 ), resulting in the destruction of the die-bonding test structure and the inability to normally test the chip performance. In response to this, the inventor has proposed an improvement solution after long-term research.

[0037] Specifically, the present invention provides a method for preparing a chip-on-board packaging test structure, including the steps of:

[0038] Providing a substrate wafer 11, forming a protective layer 12 on the surface of the substrate wafer 11. The protective layer 12 can reduce the stress between the subsequently prepared conductive bumps 13 and the substrate wafer 11, improve the adhesion of the conductive bumps 13 on the surface of the substrate wafer 11, and avoid the conductive bumps 13 from falling off during the subsequent cleaning process, thereby improving the stability of the chip-on-board packaging test structure; the substrate wafer 11 is preferably a bare wafer without any device structures prepared on its surface, especially a dummy wafer commonly used for testing in a semiconductor factory. Its material can be silicon, germanium, or silicon-germanium, and preferably a silicon wafer. Its structure can be referred to Figure 6As shown in the figure; the formed protective layer 12 is preferably an insulating layer to reduce the influence on subsequent electrical tests. For example, the protective layer 12 includes, but is not limited to, one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer or a stacked layer composed of multiple layers. The forming method includes, but is not limited to, one or a combination of two of the oxidation method and the chemical vapor deposition method. More specifically, in one example, the substrate wafer 11 is a bare silicon wafer, and a silicon oxide layer can be formed on the surface of the bare silicon wafer by the thermal oxidation method and / or the chemical vapor deposition method as the protective layer 12. In another example, a silicon oxide layer can be first formed on the surface of the bare silicon wafer by the thermal oxidation method, and then a silicon nitride or silicon oxynitride layer can be formed on the surface of the silicon oxide layer by the chemical vapor deposition method to obtain a composite film layer, which will help avoid damage to the substrate wafer 11 during the test and realize the recycling of the substrate wafer 11. The thickness of the protective layer 12 is preferably 500 nm - 5000 nm (including the end point values. In the description of the numerical range in this specification, unless otherwise specified, the end point values are included), such as 500 nm, 1000 nm, 1500 nm, 2000 nm, etc. The structure after forming the protective layer 12 is as shown in Figure 7 As shown in the figure; after forming the protective layer 12, high-temperature annealing can be performed to reduce the lattice mismatch between the protective layer 12 and the substrate wafer 11;

[0039] A conductive bump 13 is formed on the protective layer 12. Specifically, the method for forming the conductive bump 13 is preferably the sputtering method. The formed conductive bump 13 can be a copper pillar, an aluminum pillar, a silver pillar, or a combination of multiple metal pillars. And the conductive bump 13 is preferably a cylindrical bump, and there are usually multiple conductive bumps 13. Multiple conductive bumps 13 are usually arranged in an array to correspond to multiple chips 14. The structure obtained after this step is as shown in Figure 8 As shown in the figure. Of course, in other examples, the forming method of the conductive bump 13 can also transfer and fix the prepared conductive pillar to the protective layer 12, but the sputtering method is preferably used to prepare the conductive bump 13, and the required structure can be flexibly formed according to the test needs, further improving the adhesion between the conductive bump 13 and the substrate.

[0040] For the convenience of welding the chip 14, as an example, a solder pad (not shown) can be formed on the conductive bump 13. The solder pad includes, but is not limited to, a silver pad, an aluminum pad, a tin pad, or a combination of multiple solder pads. Or after forming the conductive bump 13, the conductive bump 13 can be etched back to form a groove (not shown) on the surface of the conductive bump 13, and the solder pad can be formed on the inner surface of the groove, which will help improve the stability of the subsequent test structure. The height of the conductive bump 13 should not be too high or too small. Preferably, it is 3000 nm - 8000 nm.

[0041] Before forming the conductive bumps 13 on the surface of the base wafer 11, a protective layer 12 is first formed on the surface of the wafer, thereby enhancing the adhesion between the conductive bumps 13 and the wafer, avoiding the detachment of the conductive bumps 13 during subsequent processes such as cleaning, effectively improving the stability of the test structure, and enabling the recycling of the test structure, which helps to reduce the test cost.

[0042] The present invention also provides a chip-on-package test structure, which can be prepared based on any of the foregoing methods, so the foregoing content can be incorporated herein by reference in its entirety. Specifically, as Figure 8 shown, the chip-on-package test structure includes a base wafer 11, a protective layer 12 on the surface of the base wafer 11, and conductive bumps 13 on the protective layer 12. The base wafer 11 is preferably a bare wafer without any structures prepared on its surface, including but not limited to silicon wafers, germanium wafers, germanium-silicon wafers, SOI substrates, etc. The protective layer 12 includes, but is not limited to, one or a combination of silicon oxide layers and silicon nitride layers, and preferably has a thickness of 500 nm - 5000 nm. The conductive bumps 13 are usually multiple, and the multiple conductive bumps 13 can be arranged in an array so that the chip-on-package test structure can simultaneously perform chip-on-package tests on multiple chips 14. The conductive bumps 13 include, but are not limited to, any one or a combination of copper pillars, silver pillars, aluminum pillars, or other metal pillars. A solder pad may be formed on the surface of the conductive bumps 13, and the solder pad includes, but is not limited to, one or a combination of silver pads, aluminum pads, and tin pads. A groove may also be formed on the surface of the conductive bumps 13 to facilitate subsequent bonding with the chip 14 to be tested, for example, to prevent the solder flux 15 from flowing out to the surfaces of the conductive bumps 13 and / or the chip 14 during the subsequent die bond process.

[0043] The present invention also provides a chip-on-package test method, including the steps of:

[0044] Providing a base wafer 11, and forming a protective layer 12 on the surface of the base wafer 11. The protective layer 12 can reduce the stress between the subsequently prepared conductive bumps 13 and the base wafer 11, improve the adhesion of the conductive bumps 13 on the surface of the base wafer 11, and avoid the detachment of the conductive bumps 13 during subsequent cleaning processes to improve the stability of the chip-on-package test structure; the base wafer 11 is preferably a bare wafer without any device structures prepared on its surface, especially a dummy wafer dedicated for testing commonly used in semiconductor factories, and its material can be silicon, germanium, or germanium-silicon, preferably a silicon wafer, and its structure can refer to Figure 6As shown; the formed protective layer 12 is preferably an insulating layer to reduce the influence on subsequent electrical tests. For example, the protective layer 12 includes, but is not limited to, one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer or a stack composed of multiple types. Its forming method includes, but is not limited to, one or a combination of two of the oxidation method and the chemical vapor deposition method. More specifically, in one example, the substrate wafer 11 is a bare silicon wafer. The silicon oxide layer can be formed on the surface of the bare silicon wafer by the thermal oxidation method and / or the chemical vapor deposition method as the protective layer 12. Or in other examples, the silicon oxide layer can be first formed on the surface of the bare silicon wafer by the thermal oxidation method, and then the silicon nitride or silicon oxynitride layer can be formed on the surface of the silicon oxide layer by the chemical vapor deposition method to obtain a composite film layer. This will help avoid damage to the substrate wafer 11 during the test and realize the recycling of the substrate wafer 11. The thickness of the protective layer 12 is preferably 500 nm - 5000 nm (including the end point values. In the description of the numerical range in this specification, unless otherwise specified, the end point values are included). For example, it can be 500 nm, 1000 nm, 1500 nm, 2000 nm, etc. The structure after forming the protective layer 12 is as Figure 7 shown; after forming the protective layer 12, high-temperature annealing can be performed to eliminate the stress between the protective layer 12 and the substrate wafer 11;

[0045] Form conductive bumps 13 on the surface of the protective layer 12; specifically, the method for forming the conductive bumps 13 is preferably the sputtering method. The formed conductive bumps 13 can be copper pillars, aluminum pillars, silver pillars or a combination of multiple metal pillars. And the conductive bumps 13 are preferably cylindrical bumps. And there are usually multiple conductive bumps 13, and multiple conductive bumps 13 are usually arranged in an array to correspond to multiple chips 14. The structure obtained after this step is as Figure 8 shown;

[0046] Flip one or more chips 14 to be tested onto the surface of the conductive bumps 13 through a flux 15 to obtain a test structure; specifically, the flux 15 can be an organic or inorganic material with a melting point lower than that of the conductive bumps 13. For example, the rosin resin-based flux 15 composed of rosin, resin, a halogen-containing activator, additives, and organic solvents. The flux 15 can be coated on the surface of the conductive pins 141 of the chip 14 through a drop coating process (die flux dipping), or the flux 15 can be drop-coated on the surface of the conductive bumps 13, or the flux 15 can be drop-coated on the surfaces of both the conductive bumps 13 and the conductive pins 141 of the chip 14 at the same time. Then the chip 14 is welded to the surface of the conductive bumps 13 (i.e., flip chip) with the conductive pins 141 and welded to the substrate wafer 11. This process can be referred to Figure 9 shown, and the structure obtained after flip-chip welding is as Figure 10 shown;

[0047] During the flip-chip soldering process, the solder flux 15 easily flows onto the surface of the conductive bumps 13 and / or the chip 14, causing contamination of the chip 14 and / or adhesion between different conductive pins 141, resulting in problems such as degradation of the electrical insulation performance of the chip 14 and short circuit. Therefore, after the flip-chip soldering process, the test structure is usually cleaned, for example, with a stripping solution to remove the residual solder flux 15. The obtained structure is as shown in FIG. Figure 11 As shown, the cleaned package structure can be dried and then tested, and the chip can be peeled off after the test is completed. Since the protective layer 12 is formed on the surface of the base wafer 11 in advance in the present invention, the conductive bumps 13 can be more firmly attached to the surface of the base wafer 11, so in the step of cleaning the solder flux 15, the conductive bumps 13 will not fall off from the surface of the base wafer 11, and the subsequent test can be completed smoothly.

[0048] In summary, the present invention provides a patch packaging test structure and a preparation method thereof. The patch packaging test structure includes a base wafer, a protective layer located on the surface of the base wafer, and a conductive bump located on the protective layer. Before forming the conductive bump on the surface of the base wafer, the present invention first forms a protective layer on the surface of the wafer, thereby enhancing the adhesion between the conductive bump and the wafer, preventing the conductive bump from falling off during subsequent cleaning and other processes, thereby effectively improving the stability of the test structure and helping to reduce the test cost. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A preparation method of a chip-scale package test structure, characterized in that, Including the steps of: Providing a base wafer, and forming a protective layer on the surface of the base wafer by combining one or both of an oxidation method and a chemical vapor deposition method; the protective layer includes one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer or a stack composed of multiple layers; the thickness of the protective layer is 500 nm - 5000 nm; Performing high-temperature annealing after forming the protective layer; Forming a conductive bump on the protective layer; The protective layer reduces the stress between the conductive bump and the base wafer and improves the adhesion of the conductive bump on the surface of the base wafer.

2. A chip package test structure, characterized in that The chip-on-package test structure is A structure fabricated according to the manufacturing method described in claim 1, the chip-on-package test structure includes a base wafer, a protective layer located on the surface of the base wafer, and a conductive bump located on the protective layer; the protective layer includes one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer or a stack composed of multiple layers; the thickness of the protective layer is 500 nm - 5000 nm; the protective layer reduces the stress between the conductive bump and the base wafer and improves the adhesion of the conductive bump on the surface of the base wafer.

3. A method for testing a chip-scale package, characterized in that, Including the steps of: Providing a base wafer, and forming a protective layer on the surface of the base wafer by combining one or both of an oxidation method and a chemical vapor deposition method; the protective layer includes one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer or a stack composed of multiple layers; the thickness of the protective layer is 500 nm - 5000 nm; Performing high-temperature annealing after forming the protective layer; Forming a conductive bump on the surface of the protective layer; the protective layer reduces the stress between the conductive bump and the base wafer and improves the adhesion of the conductive bump on the surface of the base wafer; Inverting the chip to be tested onto the surface of the conductive bump with a soldering flux to obtain a test structure; Cleaning the test structure; Testing the test structure.

Images