Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, belonging to the field of display technology. The array substrate includes: a substrate substrate and a driving circuit. The array substrate has a display area and an opening area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the target conductive shielding block is used to shield the active layer of the target thin film transistor adjacent to the opening area, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the opening area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the opening area.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] At present, various smart terminals such as mobile phones, tablet computers, and smart wearable devices are equipped with display panels, and display panels have been widely used. Active matrix organic light-emitting diode (AMOLED) display panels generally include a driving circuit, which is used to drive the light-emitting element to emit light. In order to make the display area of ​​the display panel account for a larger proportion and the non-display area account for a smaller proportion. An opening area is set on the display panel to set components such as the camera and the earpiece in the opening area, which can greatly save the occupied area of ​​the non-display area corresponding to the frame position, which is more conducive to the design of a narrow frame.

[0003] In the related art, there is an array substrate, in which the frame of the opening area of ​​the array substrate is narrow, and the virtual pixel driving circuit arranged around the opening area is removed, so that the display area occupies a larger proportion.

[0004] In the above array substrate, due to external light, the stability of the thin film transistors adjacent to the edge of the opening area is poor. Summary of the invention

[0005] The embodiment of the present application provides an array substrate and a display panel. The technical solution is as follows:

[0006] According to a first aspect of the present application, an array substrate is provided, the array substrate comprising: a base substrate and a driving circuit located on the base substrate;

[0007] The array substrate has a display area and an opening area, the display area at least partially surrounds the opening area, and the driving circuit includes a plurality of thin film transistors located in the display area, a plurality of constant voltage signal lines and at least one target conductive shielding block;

[0008] The plurality of thin film transistors include at least one target thin film transistor, the at least one target thin film transistor corresponds to the at least one target conductive shielding block one by one, and the target thin film transistor includes at least one thin film transistor adjacent to the opening area among the plurality of thin film transistors;

[0009] The multiple constant voltage signal lines include at least one target constant voltage signal line segment, at least one of the multiple target conductive shielding blocks is electrically connected to at least one of the target constant voltage signal line segments, the at least one target conductive shielding block is located on a side of the corresponding target thin film transistor away from the substrate, and the orthographic projection of the at least one target conductive shielding block on the substrate overlaps with the orthographic projection of the active layer of the corresponding target thin film transistor on the substrate.

[0010] Optionally, the at least one target constant voltage signal line segment is located at a target side of the target thin film transistor, and the target thin film transistor is a thin film transistor on the target side adjacent to the opening area.

[0011] Optionally, there are multiple target thin film transistors, and the multiple target thin film transistors are arranged in multiple columns on the substrate, and at least one column of the multiple columns of target thin film transistors includes at least two target thin film transistors;

[0012] There are multiple target constant voltage signal line segments, and the multiple target constant voltage signal line segments correspond one-to-one to the multiple columns of target thin film transistors. The target conductive blocking blocks corresponding to at least two target thin film transistors in at least one column of target thin film transistors are electrically connected to the target constant voltage signal line segments corresponding to the at least one column of target thin film transistors.

[0013] Optionally, the at least one column of target constant-voltage signal line segments is electrically connected to at least other constant-voltage signal lines in the driving circuit except the at least one target constant-voltage signal line segment.

[0014] Optionally, a plurality of the target constant voltage signal line segments are electrically connected.

[0015] Optionally, the plurality of target constant voltage signal line segments are all located outside the first area of ​​the opening area;

[0016] The opening area is divided into the first area and the second area by a first straight line, and the first straight line passes through the center of the opening area and is parallel to the arrangement direction of the at least one column of target thin film transistors.

[0017] Optionally, the opening area is circular, and the first straight line passes through the center of the opening area.

[0018] Optionally, the array substrate further includes a source-drain metal layer, and the at least one target constant voltage signal line segment is located in the source-drain metal layer.

[0019] Optionally, the array substrate also includes a dielectric layer, and the target conductive blocking block and the target constant voltage signal line segment are respectively located on both sides of the dielectric layer in a direction perpendicular to the base substrate, at least one of the target conductive blocking blocks is electrically connected to at least one of the target constant voltage signal line segments through a via, and the via passes through the dielectric layer.

[0020] Optionally, the target thin film transistor is a dual-gate thin film transistor, which includes two gates, and the orthographic projection of the target conductive blocking block on the substrate overlaps with the orthographic projection of the channel region between the two gates on the substrate.

[0021] Optionally, the target constant voltage signal line segment includes a constant voltage power line.

[0022] According to another aspect of the present application, a display panel is provided, comprising any one of the above array substrates.

[0023] Optionally, the display panel further includes a plurality of light emitting units located on the array substrate, the array substrate includes a driving circuit, the driving circuit includes a plurality of pixel circuits, and at least one of the pixel circuits is electrically connected to at least one of the light emitting units.

[0024] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0025] Provided is an array substrate including a substrate and a driving circuit located on the substrate. The array substrate has a display area and an opening area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the target conductive shielding block shields the active layer of the target thin film transistor adjacent to the opening area, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the opening area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the opening area. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a structural schematic diagram of an array substrate;

[0028] Figure 2 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0029] Figure 3 yes Figure 1 A schematic diagram of a partial structure of an array substrate shown;

[0030] Figure 4 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0031] Figure 5 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0032] Figure 6 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0033] Figure 7 is a schematic diagram of the cross-sectional structure of another array substrate provided in an embodiment of the present application;

[0034] Figure 8 It is a schematic diagram of the structure of each film layer of a driving circuit provided in an embodiment of the present application;

[0035] Fig. 9 is a schematic diagram of the structure of another driving circuit provided in an embodiment of the present application;

[0036] Fig.10 is a circuit diagram of a driving circuit provided in an embodiment of the present application;

[0037] Fig.11 It is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application.

[0038] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] like Figure 1 As shown, Figure 1The present invention is a schematic diagram of the structure of an array substrate. The array substrate 101 includes a base substrate 1011 and a driving circuit 1012 located on the base substrate 1011. The array substrate 101 has a display area 1013 and an opening area 1014, and the display area 1013 at least partially surrounds the opening area 1014. The array substrate can also be used for quantum dot display, etc.

[0041] The driving circuit 1012 has a plurality of pixel circuits, each of which includes a plurality of thin film transistors and a constant voltage power signal line. The active layer of at least one thin film transistor among the plurality of thin film transistors is not completely blocked by the gate. If the active layer is exposed, it is more susceptible to light and unstable.

[0042] In this regard, the driving circuit includes at least one conductive shielding block corresponding to the exposed active layer of at least one thin film transistor to shield the active layer of the at least one thin film transistor. The conductive shielding block is electrically connected to the power signal line of the pixel circuit adjacent to it, so that the voltage of the conductive shielding block is constant, thereby preventing the voltage change of the conductive shielding block from affecting the potential of the exposed active layer.

[0043] The array substrate 101 may also have a non-display area 1015 around the opening area 1014, and the driving circuit 1012 may also include a virtual pixel driving circuit. The virtual pixel driving circuit provided in the non-display area 1015 has the same structure as the pixel circuit, but does not display an image, and can be used to provide a constant voltage power supply for the conductive blocking block in the pixel circuit adjacent to the non-display area in the display area. However, the non-display area 1015 makes the frame of the opening area 1014 wider. At the same time, the screen ratio of the display area 1011 is also reduced. In order to make the frame of the opening area 1014 narrower and increase the screen ratio of the display area 1011, the virtual pixel driving circuit can be removed.

[0044] However, after the virtual pixel driving circuit is removed, one side of a portion of the pixel circuit loses the adjacent virtual pixel driving circuit, that is, a portion of the conductive shielding blocks arranged along the edge of the opening area 1014 loses the power signal line that can be electrically connected to it. Then, the conductive shielding blocks are removed together with the virtual pixel driving circuit. However, this makes the exposed active layer of a portion of the thin film transistors in the driving circuit 1012 adjacent to the opening area 1014 easily affected by light and has poor stability.

[0045] The embodiments of the present application provide an array substrate and a display panel, which can solve the problems existing in the above-mentioned related technologies.

[0046] Figure 2 Schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Figure 2As shown, the array substrate 10 may include: a base substrate 11 and a driving circuit 12 located on the base substrate 11 .

[0047] The array substrate 10 may have a display (English: Active Area; abbreviated: AA) area 13 and an opening area (English: AA Hole) 131. The display area 13 at least partially surrounds the opening area 131. The opening area 131 may be used to place components such as a camera and an earpiece.

[0048] like Figure 3 As shown, Figure 3 yes Figure 2 The schematic diagram of the structure of a part 10A of the array substrate is shown in FIG. The driving circuit may include a plurality of thin film transistors 121 located in the display area, a plurality of constant voltage signal lines 122, and at least one target conductive shielding block 123. The target conductive shielding block 123 may be used to block light.

[0049] The plurality of thin film transistors 121 include at least one target thin film transistor 1211, and the at least one target thin film transistor 1211 corresponds one-to-one to at least one target conductive shielding block 123. The one-to-one correspondence may mean that one target thin film transistor 1211 corresponds to one target conductive shielding block 123, and the number of target thin film transistors 1211 may be consistent with the number of target conductive shielding blocks 123.

[0050] The target thin film transistor 1211 includes at least one thin film transistor adjacent to the opening area 131 among the plurality of thin film transistors 121. Adjacent to the opening area 131 may mean that no other thin film transistor is disposed between the target thin film transistor 1211 and the opening area 131.

[0051] The plurality of constant voltage signal lines 122 include at least one target constant voltage signal line segment 1221 , and at least one target conductive shielding block 123 among the plurality of target conductive shielding blocks 123 is electrically connected to the at least one target constant voltage signal line segment 1221 .

[0052] At least one target conductive shielding block 123 is located on a side of the corresponding target thin film transistor 1211 away from the base substrate 11, and the orthographic projection of at least one target conductive shielding block 123 on the base substrate overlaps with the orthographic projection of the active layer of the corresponding target thin film transistor 1211 on the base substrate 11. The active layer of the target thin film transistor 1211 is more easily affected by light, making it less stable.

[0053] In this way, the target conductive shielding block 123 can prevent external light from irradiating onto the active layer of the corresponding target thin film transistor 1211 , thereby improving the stability of the active layer of the target thin film transistor 1211 .

[0054] In addition, at least one target conductive blocking block 123 is electrically connected to at least one target constant voltage signal line 1221, and a constant voltage electrical signal is also loaded on the target conductive blocking block 123. The target conductive blocking block 123 can effectively shield the external electric field from interfering with the active layer of the corresponding target thin film transistor 1211, thereby avoiding the electrical characteristics of the active layer of the corresponding target thin film transistor 1211 from being unstable.

[0055] In summary, the embodiment of the present application provides an array substrate including a substrate substrate and a driving circuit located on the substrate substrate. The array substrate has a display area and an opening area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the target conductive shielding block is used to shield the active layer of the target thin film transistor adjacent to the opening area, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the opening area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the opening area.

[0056] For further information, please refer to Figure 4 , Figure 4 1 is a schematic diagram of the structure of another array substrate provided in an embodiment of the present application. At least one target constant voltage signal line segment 1221 is located at the target side B1 of the target thin film transistor 1211, and the target thin film transistor 1211 is a thin film transistor whose target side B1 is adjacent to the opening area 131. Then the target constant voltage signal line segment 1221 can be located only on one side of the target thin film transistor 1211, and at least one target constant voltage signal line segment 1221 is located between the target thin film transistor 1211 and the opening area 131.

[0057] Alternatively, if Figure 4 As shown, the number of target thin film transistors 1211 is multiple. Multiple target thin film transistors 1211 can be arranged in multiple columns on the base substrate 11. That is, multiple target thin film transistors 1211 can be arranged in columns along the f1 direction on the base substrate 11. Multiple columns of target thin film transistors 1211 can be arranged along the f2 direction. f1 and f2 intersect. In this way, the opening area 131 can be circular, and multiple target thin film transistors 1211 can be arranged along the edge of the opening area 131 without changing the original arrangement of the thin film transistors in the array substrate.

[0058] Among the multiple columns of target thin film transistors 1211, at least one column of target thin film transistors 1211 may include at least two target thin film transistors 1211. The multiple columns of target thin film transistors 1211 may be arranged in a zigzag shape along the edge of the opening area so that the multiple columns of target thin film transistors 1211 fit the shape of the opening area 131 as much as possible.

[0059] There are multiple target constant voltage signal line segments 1221 , and the multiple target constant voltage signal line segments 1221 correspond one-to-one to the multiple columns of target thin film transistors 1211 . The multiple target constant voltage signal line segments 1221 may be arranged outside the edge of the opening area 131 .

[0060] The target conductive shielding blocks 123 corresponding to at least two target thin film transistors 1211 of at least one column of target thin film transistors 1211 are electrically connected to the target constant voltage signal line segments 1221 corresponding to at least one column of target thin film transistors 1211 .

[0061] In this way, a plurality of target constant voltage signal line segments corresponding to each other can be set only on the target side of the plurality of columns of target thin film transistors. The footprint of the constant voltage signal line on the substrate can be further reduced. Thus, the frame of the opening area can be further reduced. Moreover, the target conductive shielding block can stabilize the performance of the active layer of the target thin film transistor, thereby improving the stability of the target thin film transistor adjacent to the opening area on the array substrate, and further improving the display effect of the display panel adjacent to the opening area.

[0062] Alternatively, if Figure 4 As shown, at least one target constant voltage signal line segment 1221 is electrically connected to at least one other constant voltage signal line 1222 in the driving circuit except the at least one target constant voltage signal line segment 1221 , so that a constant voltage signal can be loaded on the at least one target constant voltage signal line segment 1221 .

[0063] In the embodiment of the present application, the target constant voltage signal line segment 1221 is a line for electrically connecting to the target conductive shielding block to stabilize the voltage of the target conductive shielding block. The other constant voltage signal lines 1222 in the array substrate may refer to constant voltage signal lines in the driving circuit that are not directly connected to the target conductive shielding block. The other constant voltage signal lines may be arranged in multiple columns on the array substrate.

[0064] Exemplarily, the target constant voltage signal line segment in the embodiment of the present application may include two types, such as Figure 4 As shown, a target constant voltage signal line segment may be a first target constant voltage signal line segment 1211A, which extends along the f1 direction (the f1 direction may be parallel to the arrangement direction of at least one column of target thin film transistors 1211) and may be a straight line segment. The first target constant voltage signal line segment 1211A may be electrically connected to other constant voltage signal lines in the same column.

[0065] Another type, at least one target constant voltage signal line segment is a second target constant voltage signal line segment 1211B, and the second target constant voltage signal line segment 1211B includes a first line segment s1 extending along the f1 direction, and a second line segment s2 extending along the f2 direction (for example, the f2 direction can be perpendicular to the f1 direction). The first line segment s1 is connected to the second line segment s2. The first line segment s1 can be electrically connected to other constant voltage signal lines 1222 in the same column, and the second line segment s2 can be electrically connected to other constant voltage signal lines 1222 in other columns.

[0066] Among them, other constant voltage signal lines 1222 may extend along the f1 direction. Figure 4 The other signal lines 1223 extending along the f2 direction may include gate lines or reference signal lines.

[0067] In an alternative example, Figure 5 As shown, Figure 5 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present application. A plurality of target constant voltage signal line segments 1221 are electrically connected to each other. A plurality of target constant voltage signal line segments 1221 can be regarded as one target constant voltage signal line segment 1221, so that the process of the target constant voltage signal line segment 1221 in the manufacturing process of the array substrate can be simplified. All target thin film transistors in the array substrate can be connected through one target constant voltage signal line segment 1221.

[0068] The first end C1 of the target constant voltage signal line segment 1221 can be electrically connected to at least one other constant voltage signal line 1222 in the driving circuit 12 , and the second end C2 of the target constant voltage signal line segment 1221 can be electrically connected to at least one other constant voltage signal line 1222 in the driving circuit 12 .

[0069] In an optional implementation, Figure 6 As shown, Figure 6 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present application. The opening area 131 is divided into a first area 1311 and a second area 1312 by a first straight line L1. Multiple target constant voltage signal line segments 1221 are all located outside the first area 1311 of the opening area 131. That is, the orthographic projections of multiple target constant voltage signal line segments 1221 and the first area 1311 of the opening area 131 on the substrate 11 do not overlap. And multiple target constant voltage signal line segments 1221 are located outside the first area 1311 away from the second area 1312. In this way, the target constant voltage signal line can be set only outside the first area of ​​the opening area. The footprint of the constant voltage signal line on the substrate can be reduced. Thereby, the border of the opening area can be further reduced.

[0070] The first straight line L1 passes through the center C1 of the opening area 131 and is parallel to the arrangement direction of at least one column of target thin film transistors 1211. The arrangement direction of at least one column of target thin film transistors 1211 may be parallel to the first direction f1.

[0071] It should be noted that the parallelism may not be strictly parallel, and may also include the case where the angle between the arrangement direction of at least one column of target thin film transistors 1211 and the first direction f1 is less than or equal to 10 degrees. Further, the opening area 131 may be circular, and the first straight line L1 passes through the center C1 of the opening area 131. It should be noted that the opening area 131 may also be rectangular, square, hexagonal, etc., and the embodiment of the present application is not limited thereto.

[0072] In an alternative example, Figure 7 As shown, Figure 7 1 is a schematic diagram of a cross-sectional structure of another array substrate provided in an embodiment of the present application. The array substrate also includes a source & drain (English: source & drain; abbreviated: SD) metal layer, and at least one target constant voltage signal line segment 1221 can be located in the source & drain metal layer. At least one target constant voltage signal line segment 1221 and the source & drain metal pattern in the source & drain metal layer can be formed by a single patterning process, thereby saving the manufacturing process of the array substrate.

[0073] Alternatively, if Figure 7 As shown, the array substrate also includes a dielectric layer (English: Inter Layer Dielectric; abbreviated: ILD) 15, the target conductive blocking block 123 and the target constant voltage signal line segment 1221 are respectively located on both sides of the dielectric layer 15 in a direction perpendicular to the base substrate, at least one target conductive blocking block 123 and at least one target constant voltage signal line segment 1221 can be electrically connected through a via 151, and the via 151 can penetrate the dielectric layer 15.

[0074] In an exemplary implementation, Figure 8 As shown, Figure 8 Schematic diagram of the film layer structure of a driving circuit provided in an embodiment of the present application. The driving circuit may include an active layer pattern 21. A first conductive pattern 22, the first conductive pattern 22 may include a first electrode 221 of a capacitor structure, a gate line 111 and a gate. A second conductive pattern 23, the second conductive pattern 23 may include a second electrode 231 of a capacitor structure and a target conductive shielding block 123. A dielectric layer 15, the dielectric layer 15 has a via 151. A third conductive pattern 24, the third conductive pattern 24 may include a target constant voltage signal line segment 1221, a node connection line 119, a source and a drain. A fourth conductive pattern 25, the fourth conductive pattern 25 may include a data signal line 112.

[0075] In an optional implementation, Fig. 9 As shown, Fig. 9 1 is a schematic diagram of another driving circuit provided in an embodiment of the present application. The driving circuit may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7 and a capacitor structure Cst1.

[0076] Among them, the first thin film transistor T1 can be a first initial thin film transistor, the second thin film transistor T2 can be a compensation thin film transistor, the third thin film transistor T3 can be a driving thin film transistor, the fourth thin film transistor T4 can be a data writing transistor, the fifth thin film transistor T5 can be an operation control thin film transistor, the sixth thin film transistor T6 can be an emission control thin film transistor, and the seventh thin film transistor T7 can be a second initial thin film transistor. It should be noted that T1~T7 can include low temperature polysilicon thin film transistors (English: Low Temperature Poly-Silicon; abbreviated: LTPS) and / or oxide thin film transistors (English: oxide thin-film transistor; abbreviated: O-TFT). T1~T7 can also be other types of thin film transistors, which are not limited in the embodiments of the present application.

[0077] The target thin film transistor may be a dual-gate thin film transistor, which may correspond to Fig. 9 The compensation thin film transistor T2 in the embodiment. The dual-gate transistor refers to a transistor including two switch tubes connected in series. Fig. 9 As shown, the dual-gate thin-film transistor T2 includes two gates (T21 and T22), and the orthographic projection of the target conductive blocking block 123 on the substrate overlaps with the orthographic projection of the channel region T23 between the two gates (T21 and T22) on the substrate. The channel region T23 between the two gates (T21 and T22) may be L-shaped. The channel region T23 may refer to the channel region T23 in the active layer of the dual-gate thin-film transistor T2 that is not covered by the two gates (T21 and T22), that is, the orthographic projection of the channel region T23 on the substrate does not overlap with the orthographic projection of the two gates (T21 and T22) on the substrate.

[0078] like Fig.10 As shown, Fig.10 The gate of the third thin film transistor T3 is connected to the first node N1, the source of the third thin film transistor T3 is connected to the second node N2, and the drain of the third thin film transistor T3 is connected to the third node N3.

[0079] A gate of the fourth thin film transistor T4 is connected to the gate line (Gate) 111 , a source of the fourth thin film transistor T4 is connected to the data signal line (Data) 112 , and a drain of the fourth thin film transistor T4 is connected to the second node N2 .

[0080] A gate of the second thin film transistor T2 is connected to the gate line 111 , a source of the second thin film transistor T2 is connected to the third node N3 , and a drain of the second thin film transistor T2 is connected to the first node N1 .

[0081] A gate of the first thin film transistor T1 is connected to a reset signal line (Reset) 113 , a drain of the first thin film transistor T1 is connected to a first reference signal line (Vinit) 114 - 1 , and a source of the first thin film transistor T1 is connected to a first node N1 .

[0082] The gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 are connected to the light emitting signal line (EM) 115, the source of the fifth thin film transistor T5 is connected to the constant high potential (VDD) 116, the drain of the fifth thin film transistor T5 is connected to the second node N2, the source of the sixth thin film transistor T6 is connected to the third node N3, the drain of the sixth thin film transistor T6 is connected to the anode of the light emitting device (OLED) 117, and the cathode of the light emitting device 117 is connected to the low potential (VSS) 118.

[0083] A gate of the seventh thin film transistor T7 is connected to the gate line 111 , a drain of the seventh thin film transistor T7 is connected to the second reference signal line 114 - 2 , and a source of the seventh thin film transistor T7 is connected to the anode of the light emitting device 117 .

[0084] One end of the capacitor structure Cst1 may be connected to the first node N1 , and the other end of the capacitor structure Cst1 may be connected to the constant voltage high potential 116 .

[0085] The voltage values ​​of the first reference signal line 114 - 1 and the second reference signal line 114 - 2 may be different. For example, the voltage values ​​of the first reference signal line 114 - 1 and the second reference signal line 114 - 2 differ by 1V to 5V.

[0086] Alternatively, the first reference signal line 114 - 1 and the second reference signal line 114 - 2 may be connected to the same signal input terminal.

[0087] It should be noted that, as in this specification, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in this specification, the "source" and the "drain" can be interchanged. The embodiments of the present application do not limit this.

[0088] The compensation thin film transistor T2 may be electrically connected to the gate driving terminal, the first node N1 and the third node N3 respectively. The compensation thin film transistor T2 may be used to adjust the potentials of the first node N1 and the third node N3 in response to the gate driving signal. The gate driving terminal is used to provide the gate driving signal.

[0089] The first node N1 may be connected to the gate of the third thin film transistor T3, the drain of the second thin film transistor T2, the drain of the first thin film transistor T1, and one end of the storage capacitor C1. Therefore, the potential at the first node N1 is more easily affected by other structures in the driving circuit, resulting in poor stability of the potential of the first node N1.

[0090] Alternatively, if Fig. 9 As shown, the target constant voltage signal line segment may include a constant voltage power line 116. The constant voltage power line is used to provide a driving power signal. The driving power line is connected to the source of the fifth thin film transistor. The compensation thin film transistor T2 is connected to the driving gate electrode of the driving thin film transistor T1 through the node connection line 119. Since the voltage at the N1 node is relatively unstable, the voltage on the node connection line 119 is also relatively unstable and is more susceptible to the influence of external voltage. Because the voltage on the data signal line will change with the control state of the driving circuit, it will affect the node connection line 119. The constant voltage power line 116 can be located between the node connection line 119 and the data signal line 112 to shield the influence of the data signal line 112 on the node connection line 119.

[0091] When the target conductive shielding block is connected to the constant voltage power line from the side close to the N1 node, it needs to bypass the N1 node and the node connection line 119 before connecting to the constant voltage power line. This makes the size of the driving circuit larger, which is not conducive to miniaturization of the array substrate.

[0092] Therefore, the target conductive shielding block may be connected to the constant voltage power line from a side away from the N1 node, so that the size of the driving circuit is small.

[0093] In summary, the embodiment of the present application provides an array substrate including a substrate substrate and a driving circuit located on the substrate substrate. The array substrate has a display area and an opening area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the target conductive shielding block is used to shield the active layer of the target thin film transistor adjacent to the opening area, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the opening area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the opening area.

[0094] Fig.11 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application, and the method can be used to manufacture the array substrate provided in the above embodiment. Fig.11 As shown, the method includes:

[0095] Step 201: Obtain a substrate.

[0096] The material of the substrate may include glass or polyimide.

[0097] Step 202: forming an active layer pattern, a gate insulating layer and a first conductive pattern in sequence on the base substrate.

[0098] Step 202 may include the following steps:

[0099] 1) The active layer thin film can be formed on the substrate by any of a variety of methods such as deposition, coating and sputtering, and the active layer pattern can be obtained by performing a patterning process on the active layer thin film.

[0100] 2) An insulating film may be formed on the substrate with the active layer pattern by any of a plurality of methods such as deposition, coating and sputtering to form a gate insulating layer. Optionally, the material of the insulating film may include inorganic materials such as silicon nitride, silicon oxide or silicon oxynitride.

[0101] 3) A first conductive film can be formed on a substrate formed with an insulating film by any of a plurality of methods such as deposition, coating and sputtering. A first conductive pattern can be obtained by performing a patterning process on the first conductive film. The first conductive pattern can include: a first plate of a capacitor structure, a gate line and a gate. Optionally, the material of the first conductive pattern can include metal materials such as metal aluminum, metal silver, metal molybdenum or alloys.

[0102] Step 203: sequentially forming a first insulating layer and a second conductive pattern on the base substrate on which the first conductive pattern is formed.

[0103] First, a first insulating layer is formed on the substrate having the first conductive pattern by any of a plurality of methods such as deposition, coating and sputtering. Optionally, the material of the first insulating layer may include silicon nitride, silicon oxide or silicon oxynitride.

[0104] Then, a second conductive film can be formed on the substrate formed with the first insulating layer by any of a plurality of methods such as deposition, coating and sputtering. A second conductive pattern can be obtained by performing a patterning process on the second conductive film. The second conductive pattern may include: a second plate of a capacitor structure, a target conductive shielding block and a reference signal line. The orthographic projection of the target conductive shielding block on the substrate overlaps with the orthographic projection of the active layer of the corresponding target thin film transistor on the substrate.

[0105] Optionally, the material of the first conductive pattern may include metal materials such as metal aluminum, metal silver, metal molybdenum or alloys.

[0106] Step 204 , forming a dielectric layer and a third conductive pattern in sequence on a side of the second conductive pattern facing away from the substrate.

[0107] Wherein, a via hole connected to the second conductive pattern and the third conductive pattern is formed on the dielectric layer. The second conductive pattern may include: a power signal line, a node connection line, a source electrode and a drain electrode.

[0108] First, a dielectric layer is formed on the substrate with the first conductive pattern by any of a plurality of methods such as deposition, coating and sputtering, and a patterning process is performed on the dielectric layer to form a via hole for overlapping the target conductive shielding block and the power signal line.

[0109] Then, a third conductive film can be formed on the substrate with the dielectric layer formed thereon by any one of a plurality of methods such as deposition, coating and sputtering, and a third conductive pattern can be obtained by performing a patterning process on the third conductive film.

[0110] Optionally, the material of the third conductive pattern may include metal materials such as metal aluminum, metal silver, metal molybdenum or alloys.

[0111] It should be noted that a single patterning process in the embodiment of the present application may include: photoresist coating, exposure, development, etching and photoresist stripping.

[0112] In summary, an embodiment of the present application provides a method for manufacturing an array substrate. In the method, the array substrate includes a substrate substrate and an array substrate of a driving circuit located on the substrate substrate. The array substrate has a display area and an aperture area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines, and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the active layer of the target thin film transistor adjacent to the aperture area is shielded by the target conductive shielding block, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the aperture area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the aperture area.

[0113] According to another aspect of the present application, a display panel is provided, and the display panel includes an array substrate in any of the above embodiments. The array substrate may include a substrate substrate and a driving circuit located on the substrate substrate. The array substrate has a display area and an aperture area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines, and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By making at least one target conductive shielding block located on the side of the corresponding target thin film transistor away from the substrate substrate, the orthographic projection of at least one target conductive shielding block on the substrate substrate overlaps with the orthographic projection of the active layer of the corresponding target thin film transistor on the substrate substrate. The stability of the target thin film transistor can be improved, and the target thin film transistor includes at least one thin film transistor adjacent to the aperture area among the plurality of thin film transistors. Thus, the stability of the target thin film transistor adjacent to the aperture area on the array substrate can be improved.

[0114] Optionally, the display panel further includes a plurality of light emitting units located on the array substrate. The array substrate includes a driving circuit, the driving circuit may include a plurality of pixel circuits, and at least one pixel circuit is electrically connected to at least one light emitting unit. The display panel may also include a display area and an opening area, and the positions of the display area and the opening area on the display panel may correspond to the positions of the display area and the opening area on the array substrate.

[0115] The array substrate can ensure that the brightness of at least one light-emitting unit adjacent to the opening area is normal, thereby improving the display effect of the display panel adjacent to the opening area.

[0116] In summary, the embodiment of the present application provides a display panel including an array substrate. The array substrate may include a substrate substrate and a driving circuit located on the substrate substrate. The array substrate has a display area and an aperture area, and the driving circuit includes a plurality of thin film transistors, a plurality of constant voltage signal lines and at least one target conductive shielding block. At least one target thin film transistor corresponds to at least one target conductive shielding block one by one. At least one target conductive shielding block among the plurality of target conductive shielding blocks is electrically connected to at least one target constant voltage signal line. By setting a target constant voltage signal line and a target conductive shielding block electrically connected to the target constant voltage signal line, the target conductive shielding block shields the active layer of the target thin film transistor adjacent to the aperture area, so that the performance of the target thin film transistor can be made more stable, which solves the problem of poor stability of the thin film transistor adjacent to the edge of the aperture area in the related art, and achieves the effect of improving the stability of the thin film transistor adjacent to the edge of the aperture area.

[0117] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0118] In the present application, the terms "first", "second", "third", "fourth", "fifth", "sixth" and "seventh" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly limited.

[0119] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a base substrate and a driving circuit located on the base substrate; The array substrate has a display area and an opening area, the display area at least partially surrounds the opening area, and the driving circuit includes a plurality of thin film transistors located in the display area, a plurality of constant voltage signal lines and at least one target conductive shielding block; The plurality of thin film transistors include at least one target thin film transistor, the at least one target thin film transistor corresponds to the at least one target conductive shielding block one by one, and the target thin film transistor includes at least one thin film transistor adjacent to the opening area among the plurality of thin film transistors; The multiple constant voltage signal lines include at least one target constant voltage signal line segment, at least one target conductive shielding block among the multiple target conductive shielding blocks is electrically connected to at least one target constant voltage signal line segment, the at least one target conductive shielding block is located on a side of the corresponding target thin film transistor away from the substrate, and an orthographic projection of the at least one target conductive shielding block on the substrate overlaps with an orthographic projection of an active layer of the corresponding target thin film transistor on the substrate; At least one of the target constant voltage signal line segments is located between the target thin film transistor and the opening area.

2. The array substrate according to claim 1, characterized in that: The at least one target constant voltage signal line segment is located at a target side of the target thin film transistor, and the target thin film transistor is a thin film transistor on the target side adjacent to the opening area.

3. The array substrate according to claim 2, characterized in that: There are multiple target thin film transistors, and the multiple target thin film transistors are arranged in multiple columns on the substrate. Among the multiple columns of target thin film transistors, at least one column of target thin film transistors includes at least two target thin film transistors. There are multiple target constant voltage signal line segments, and the multiple target constant voltage signal line segments correspond one-to-one to the multiple columns of target thin film transistors. The target conductive blocking blocks corresponding to at least two target thin film transistors in at least one column of target thin film transistors are electrically connected to the target constant voltage signal line segments corresponding to the at least one column of target thin film transistors.

4. The array substrate according to claim 3, characterized in that: The at least one column of target constant voltage signal line segments is electrically connected to at least other constant voltage signal lines in the driving circuit except the at least one target constant voltage signal line segment.

5. The array substrate according to claim 4, characterized in that: The plurality of target constant voltage signal line segments are all electrically connected.

6. The array substrate according to claim 3, characterized in that: The plurality of target constant voltage signal line segments are all located outside the first area of ​​the opening area; The opening area is divided into the first area and the second area by a first straight line, and the first straight line passes through the center of the opening area and is parallel to the arrangement direction of the at least one column of target thin film transistors.

7. The array substrate according to claim 6, characterized in that: The opening area is circular, and the first straight line passes through the center of the opening area.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The array substrate further includes a source-drain metal layer, and the at least one target constant voltage signal line segment is located in the source-drain metal layer.

9. The array substrate according to any one of claims 1 to 7, characterized in that: The array substrate also includes a dielectric layer, the target conductive shielding block and the target constant voltage signal line segment are respectively located on both sides of the dielectric layer in a direction perpendicular to the base substrate, at least one of the target conductive shielding blocks is electrically connected to at least one of the target constant voltage signal line segments through a via, and the via runs through the dielectric layer.

10. The array substrate according to any one of claims 1 to 7, characterized in that: The target thin film transistor is a dual-gate thin film transistor including two gates, and the orthographic projection of the target conductive shielding block on the substrate overlaps with the orthographic projection of the channel region between the two gates on the substrate.

11. The array substrate according to any one of claims 1 to 7, characterized in that: The target constant voltage signal line segment includes a constant voltage power line.

12. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1-11.

13. The display panel according to claim 12, characterized in that: The display panel further comprises a plurality of light emitting units located on the array substrate. The array substrate comprises a driving circuit. The driving circuit comprises a plurality of pixel circuits. At least one of the pixel circuits is electrically connected to at least one of the light emitting units.

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