An operational amplifier circuit

Abstract

The present invention discloses an operational amplifier circuit, including two differential signal input terminals, two differential signal output terminals, a bias circuit, a full differential operational amplifier main circuit and a common mode feedback circuit, wherein the full differential operational amplifier main circuit includes a first differential amplifier circuit as a first stage and a forward amplification compensation and push-pull drive circuit as a second stage, wherein the forward amplification compensation and push-pull drive circuit includes two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull drive. The operational amplifier circuit of the present invention can achieve a larger bandwidth and lower power consumption.

Description

[Technical field]

[0001] The present invention relates to an integrated circuit, and in particular to an operational amplifier circuit. [Background Technology]

[0002] An operational amplifier is an electronic integrated circuit containing a multi-stage amplifier circuit. The invention with application number CN201310123747.1 discloses an operational amplifier circuit with adjustable bandwidth, which includes a bias circuit, a fully differential operational amplifier main circuit and a common-mode feedback circuit, wherein: the bias circuit is used to provide a stable bias current that is independent of temperature and process for the fully differential operational amplifier main circuit and the common-mode feedback circuit; the fully differential operational amplifier main circuit is a two-stage amplification full-swing output structure, which is used to provide gain and required bandwidth under the action of the bias current, and output a common-mode level to the common-mode feedback circuit; the common-mode feedback circuit is used to stabilize the common-mode level output by the fully differential operational amplifier main circuit to a constant voltage. The bandwidth-adjustable operational amplifier circuit of the invention needs to obtain a larger bandwidth. It needs to be exchanged by increasing power consumption. [Summary of the invention]

[0003] The technical problem to be solved by the present invention is to provide an operational amplifier circuit with large bandwidth and low power consumption.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is an operational amplifier circuit, including two differential signal input terminals, two differential signal output terminals, a bias circuit, a fully differential operational amplifier main circuit and a common-mode feedback circuit. The fully differential operational amplifier main circuit includes a first differential amplifier circuit as a first stage and a forward amplification compensation and push-pull drive circuit as a second stage. The forward amplification compensation and push-pull drive circuit includes two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull drive.

[0005] In the operational amplifier circuit described above, the first differential amplifier circuit includes a first NMOS tube, a second NMOS tube, a third PMOS tube, and a fourth PMOS tube, and the forward amplification compensation and push-pull driving circuit includes a fifth PMOS tube, a sixth PMOS tube, and the two groups of switchable switch tube arrays; the drain of the first NMOS tube is connected to the positive electrode of the power supply through the third PMOS tube, and the drain of the second NMOS tube is connected to the positive electrode of the power supply through the fourth PMOS tube; the source of the first NMOS tube is connected to the source of the second NMOS tube and then connected to the bias circuit, the gate of the first NMOS tube is connected to the first differential signal input terminal, and the gate of the second NMOS tube is connected to the second differential signal input terminal; each group of switchable switch tube arrays includes a plurality of switchable parallel-connected NMOS tubes, the gate of the fifth PMOS tube is connected to the drain of the first NMOS tube, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube; the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to the positive electrode of the power supply, and the drain of the fifth PMOS tube is connected to the first differential signal output terminal. And it is grounded through the NMOS tube of the first group of switchable switch tube arrays; the drain of the sixth PMOS tube is connected to the second differential signal output end, and is grounded through the NMOS tube of the second group of switchable switch tube arrays; the gate of the NMOS tube connected in parallel to the first group of switchable switch tube arrays is connected to the gate of the second NMOS tube through the first AC coupling capacitor, and the gate of the NMOS tube connected in parallel to the second group of switchable switch tube arrays is connected to the gate of the first NMOS tube through the second AC coupling capacitor.

[0006] In the operational amplifier circuit described above, the common-mode feedback circuit includes a second differential amplifier circuit and a common-mode sampling circuit; the second differential amplifier circuit includes a fifth NMOS tube, a sixth NMOS tube, two groups of switchable parallel PMOS tubes and a common-mode sampling circuit, the drain of the fifth NMOS tube is connected to the positive electrode of the power supply through the first group of switchable parallel PMOS tubes, and the drain of the sixth NMOS tube is connected to the positive electrode of the power supply through the second group of switchable parallel PMOS tubes; the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube and then connected to the bias circuit, the gate of the fifth NMOS tube is connected to the output end of the common-mode sampling circuit, and the gate of the sixth NMOS tube is connected to the reference voltage signal input end; the common-mode sampling circuit includes two sampling resistors connected in series, and the connection point of the two sampling resistors is the output end of the common-mode sampling circuit; the two ends of the common-mode sampling circuit are respectively connected to the first differential signal output end and the second differential signal output end.

[0007] In the operational amplifier circuit described above, the common-mode feedback circuit includes a common-mode feedback compensation circuit, and the common-mode feedback compensation circuit includes a first RC lag compensation circuit and a second RC lag compensation circuit; the source of the first group of switchable parallel PMOS tubes and the source of the second group of switchable parallel PMOS tubes are connected to the positive electrode of the power supply, the drain and gate of the first group of switchable parallel PMOS tubes are connected to the drain of the fifth NMOS tube, and the drain and gate of the second group of switchable parallel PMOS tubes are connected to the drain of the sixth NMOS tube; the gate of the first group of switchable parallel PMOS tubes is connected to the positive electrode of the power supply through the second RC lag compensation circuit, and is connected to the gate of the third PMOS tube and the gate of the fourth PMOS tube; the gate of the fifth NMOS tube is grounded through the first RC lag compensation circuit.

[0008] The operational amplifier circuit, the forward amplification compensation and push-pull driving circuit described above includes two Miller compensation capacitors, the first Miller compensation capacitor is connected between the gate and the drain of the fifth PMOS tube, and the second Miller compensation capacitor is connected between the gate and the drain of the sixth PMOS tube.

[0009] In the operational amplifier circuit described above, the bias circuit includes a reference current source, a first NMOS tube of the bias circuit, a second NMOS tube of the bias circuit and a bias circuit switchable switch tube array, wherein the bias circuit switchable switch tube array includes a plurality of switchable NMOS tubes connected in parallel; the input end of the reference current source is connected to the positive electrode of the power supply, and the output end is connected to the drain of the first NMOS tube of the bias circuit, the drain of the first NMOS tube of the bias circuit is connected to the gate, and the source of the first NMOS tube of the bias circuit is grounded; the gate of the second NMOS tube of the bias circuit is connected to the gate of the first NMOS tube of the bias circuit, the source of the second NMOS tube of the bias circuit is grounded, and the drain is connected to the source of the first NMOS tube of the first differential amplifier circuit and the source of the second NMOS tube; the gate of the NMOS tube of the bias circuit switchable switch tube array is connected to the gate of the first NMOS tube of the bias circuit, the source of the NMOS tube of the bias circuit switchable switch tube array is grounded, and the drain is connected to the source of the fifth NMOS tube of the second differential amplifier circuit and the source of the sixth NMOS tube.

[0010] In the operational amplifier circuit described above, the gates of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are connected to the gate of the first NMOS tube of the bias circuit through the first bias resistor, and the gates of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are connected to the gate of the first NMOS tube of the bias circuit through the second bias resistor; the drains of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are connected to the drain of the fifth PMOS tube, and the sources of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are grounded; the drains of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are connected to the drain of the sixth PMOS tube, and the sources of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are grounded.

[0011] The operational amplifier circuit described above adjusts the number of NMOS tubes connected in parallel in the two groups of switchable switch tube arrays of the forward amplification compensation circuit and the push-pull drive circuit according to the requirements of bandwidth and current consumption.

[0012] The operational amplifier circuit described above adjusts the number of PMOS tubes connected in parallel in the two groups of switchable parallel PMOS tubes and / or the number of NMOS tubes connected in parallel in the bias circuit switchable switch tube array according to the requirements of bandwidth and power consumption of the common-mode feedback loop.

[0013] The operational amplifier circuit of the present invention can achieve a larger bandwidth and lower power consumption. [Drawings]

[0014] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] Figure 1 It is a principle block diagram of an operational amplifier circuit according to an embodiment of the present invention.

[0016] Figure 2 is a circuit diagram of an operational amplifier circuit according to an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of an NMOS switching array according to an embodiment of the present invention.

[0018] Figure 4 Schematic diagram of a PMOS switching array according to an embodiment of the present invention. [Specific implementation method]

[0019] The structure and principle of the operational amplifier circuit of the embodiment of the present invention are as follows Figures 1 to 4 As shown, it includes the positive power input terminal VDD, the differential signal input terminal V IP 、V IN , two differential signal output terminals V 0P 、V 0N , bias circuit, fully differential operational amplifier main circuit and common-mode feedback circuit.

[0020] The bias circuit is used to provide a stable bias current that is independent of temperature and process for the main circuit and common-mode feedback circuit of the fully differential operational amplifier. The main circuit of the fully differential operational amplifier adopts a two-stage amplification full-swing output structure to provide gain and the required bandwidth under the action of the bias current, and output the common-mode level to the common-mode feedback circuit. The common-mode feedback circuit is used to stabilize the common-mode level output by the main circuit of the fully differential operational amplifier to a constant voltage.

[0021] like Figure 1 As shown, the fully differential operational amplifier main circuit includes a first differential amplifier circuit as a first stage and a forward amplifier compensation and push-pull driving circuit as a second stage.

[0022] like Figure 2 As shown, the first differential amplifier circuit includes a first NMOS transistor M N1 , the second NMOS tube M N2 , the third PMOS tube M P3 , the fourth PMOS tube M P4 The forward amplification compensation and push-pull driving circuit includes a fifth PMOS tube M P5 , the sixth PMOS tube M P6 , two sets of switchable switch tube arrays and two Miller compensation capacitors. The first NMOS tube M N1 The drain of the third PMOS tube M P3 The drain of the second NMOS tube MN2 is connected to the positive power supply VDD through the fourth PMOS tube MP4. N1 The source of the second NMOS tube M N2 The source of the first NMOS tube M is connected to the bias circuit. N1 The gate of the first differential signal input terminal V IP , the second NMOS tube M N2 The gate of the second differential signal input terminal V IN Each group of switchable switch tube array M N3 and M N4 , each comprising a plurality of switchable, parallel-connected NMOS tubes.

[0023] The fifth PMOS tube M P5 The gate of the first NMOS tube M N1 The drain of the sixth PMOS tube M P6 The gate of the second NMOS tube M N2 The drain of the fifth PMOS tube M P5 The source of the sixth PMOS tube M P6 The source of is connected to the positive power supply VDD, the first Miller compensation capacitor C M1 Connect to the fifth PMOS tube M P5 Between the gate and drain, the second Miller compensation capacitor C M2 Connected to the sixth PMOS tube M P6 The fifth PMOS tube M P5 The drain of the first differential signal output terminal V OP . And through the first group of switchable switch tube array M N3 The NMOS tube of the sixth PMOS tube M is grounded. P6 The drain of the second differential signal output terminal V ON , and through the second set of switchable switch tube array M N4That is, the first group of switchable switch tube array M N3 The drain of the parallel-connected NMOS tube is connected to the fifth PMOS tube M P5 The drain of the first group of switchable switch tube arrays M N3 The source of the parallel-connected NMOS tube is grounded. N4 The drain of the parallel-connected NMOS tube is connected to the sixth PMOS tube M P6 The drain of the second group of switchable switch tube array M N4 The source of the parallel-connected NMOS tube is grounded. N3 The gate of the parallel-connected NMOS tube is connected through the first AC coupling capacitor C F1 Connect to the second NMOS tube M N2 The gate of the second group of switchable switch tube array M N4 The gate of the parallel-connected NMOS tube is connected through the second AC coupling capacitor C F2 Connect to the first NMOS tube M N1 of the gate.

[0024] The common mode feedback circuit includes a second differential amplifier circuit and a common mode sampling circuit. The second differential amplifier circuit includes a fifth NMOS transistor M N5 , the sixth NMOS tube M N6 , two sets of switchable parallel PMOS tubes M P1 、M P2 and common mode sampling circuit, the fifth NMOS tube M N5 The drain of the first group of switchable parallel PMOS tubes M P1 The drain of the sixth NMOS transistor MN6 is connected to the positive electrode of the power supply VDD, and the drain of the sixth NMOS transistor MN6 is connected to the positive electrode of the power supply VDD. P2 The source of the fifth NMOS transistor MN5 is connected to the positive electrode of the power supply VDD. N6 The source of the fifth NMOS tube M is connected to the bias circuit. N5 The gate of the sixth NMOS tube M is connected to the output end of the common mode sampling circuit. N6 The gate is connected to the reference voltage signal V REF The input terminal.

[0025] The common mode sampling circuit includes two sampling resistors R S1 and R S2 , two sampling resistors R S1 and R S2 The connection point is the output end of the common mode sampling circuit and the fifth NMOS tube M N5 The two ends of the common mode sampling circuit are respectively connected to the first differential signal output terminal V OP and the second differential signal output terminal V ON .

[0026] The common-mode feedback circuit also includes a common-mode feedback compensation circuit, which includes a resistor R C1 With capacitor C C1 The first RC hysteresis compensation circuit is composed of a series resistor R C2 With capacitor C C2 The second RC hysteresis compensation circuit is composed of a first group of switchable parallel PMOS tubes M P1 The source of the second set of switchable parallel PMOS tubes M P2 The source of each of the switchable parallel PMOS tubes M is connected to the positive electrode of the power supply VDD. P1 The drain and gate of the fifth NMOS tube M are connected N5 The drain of the second set of switchable parallel PMOS tubes M P2 The drain and gate of the sixth NMOS tube M are connected. N6 The drain of the first group of switchable parallel PMOS tubes M P1 The gate of the second RC hysteresis compensation circuit is connected to the positive power supply VDD, and is connected to the third PMOS tube M P3 The gate and the fourth PMOS tube M P4 The gate of the fifth NMOS tube M N5 The gate of is grounded through a first RC lag compensation circuit.

[0027] The bias circuit includes a reference current source I B , bias circuit first NMOS tube M CM0 , bias circuit second NMOS tube M CM2 and bias circuit switchable switch tube array M CM1 , reference current source I B , bias circuit first NMOS tube M CM0 , bias circuit second NMOS tube M CM2 and bias circuit switchable switch tube array M CM1 The current mirror structure composed of the two circuits provides bias current for the fully differential operational amplifier main circuit and the common-mode feedback circuit.

[0028] Bias circuit switchable switch tube array M CM1 It includes multiple switchable NMOS tubes connected in parallel. Reference current source I B The input end is connected to the positive power supply VDD, and the output end is connected to the first NMOS tube M of the bias circuit. CM0 The drain of the bias circuit is the first NMOS tube M CM0 The drain of the bias circuit is connected to the gate, and the first NMOS tube M CM0 The source of the bias circuit is grounded. CM2The gate of the bias circuit is connected to the first NMOS tube M CM0 The gate of the bias circuit is the second NMOS tube M CM2 The source is grounded, and the drain is connected to the first NMOS tube M of the first differential amplifier circuit. N1 The source of the second NMOS tube M N2 The bias circuit can switch the switch tube array M CM1 The gate of the middle NMOS tube is connected to the bias circuit of the first NMOS tube M CM0 The gate and bias circuit can switch the switch tube array M CM1 The source of the NMOS tube is grounded, and the drain is connected to the fifth NMOS tube M of the second differential amplifier circuit. N5 The source of the sixth NMOS tube M N6 The source.

[0029] The first group of switchable switch tube array M N3 The gate of the parallel-connected NMOS tube is also connected through the first bias resistor R F1 Connect the first NMOS tube M of the bias circuit CM0 The gate of the second group of switchable switch tube array M N4 The gate of the parallel-connected NMOS tube is also connected through the second bias resistor R F2 Connect the first NMOS tube M of the bias circuit CM0 of the gate.

[0030] The first differential amplifier circuit of the fully differential operational amplifier main circuit of the operational amplifier circuit of the embodiment of the present invention includes an NMOS transistor M N1 ,M N2 ,M CM2 And PMOS tube M P3 ,M P4 . The differential input signal V IP ,V IN Connect to M N1 ,M N2 The gate of M N1 ,M N2 The amplification of M N1 ,M N2 The drain level V ON1 and V OP1 The first-stage amplified signal of the differential input is obtained. P3 ,M P4 It is an active load, providing high impedance, which makes the first stage of the operational amplifier have high gain.

[0031] The forward amplification compensation and push-pull driving circuit as the second stage includes an NMOS tube M N3 ,M N4 ,PMOS tube M P5 ,M P6, and compensation capacitor C M1 ,C M2 . NMOS tube M N3 ,M N4 It has two functions: (1) forward amplification compensation and (2) push-pull drive stage. N3 ,M N4 Through C F1 and C F2 Connected to positive feedback, that is, M N3 The gate of C F1 AC coupled to V IN , the drain is connected to V OP , providing a forward amplification compensation path. N4 The gate of C F2 AC coupled to V IP , the drain is connected to V ON , providing another forward amplification compensation path to achieve broadband compensation. N3 ,M N4 The static current of these two NMOS tubes is determined by the bias circuit, but their dynamic current will change with the size of the input signal. The larger the input signal, the larger the dynamic current, which has the characteristics of a push-pull drive stage. P5 ,M P6 The gate input is connected to V ON1 ,V OP1 , the drain is connected to V OP and V ON , do the second stage amplification, in addition, PMOS tube M P5 ,M P6 The dynamic current also changes with the input signal, and has the characteristics of a push-pull drive stage. N3 and M N4 It has two functions at the same time. In order to increase the design flexibility of frequency compensation, C M1 and C M2 , to fine-tune the phase margin so that various process angles can meet the phase margin requirements.

[0032] The common mode feedback circuit includes NMOS tube M N5 ,M N6 ,M CM1 And PMOS tube M P1 ,M P2 -The differential amplifier structure composed of resistor R S1 ,R S2 Detect the output common mode level and stabilize the output common mode level to a stable voltage V through negative feedback REF In the common-mode feedback loop, V cmfb and V fBoth nodes are compensated by RC series (R C1 ,C C1 and R C2 ,C C2 ), to achieve the purpose of zero-point compensation and help the phase margin of the common-mode feedback loop.

[0033] The operational amplifier circuit of the embodiment of the present invention can adjust M according to different bandwidths. N3 and M N4 The number of MOS tubes connected in parallel, the architecture of the NMOS switching array of the embodiment of the present invention is as follows Figure 3 As shown, the architecture of the PMOS switching array is as follows Figure 4 As shown, the current consumption can be increased or decreased according to different bandwidth requirements. The power consumption of the common-mode feedback loop is adjusted according to different bandwidths, so the bias circuit can switch the switch array M CM1 You can also use Figure 3 In order to reduce the systematic offset, two sets of switchable parallel PMOS tubes M in the common mode feedback circuit are used. P1 、M P2 Can be used Figure 4 The number of parallel MOS tubes can be adjusted before leaving the factory and during use.

[0034] The dynamic current of the push-pull output stage used in the above embodiments of the present invention varies with the input signal size. The larger the input signal, the larger the dynamic current, and vice versa. Therefore, a smaller static current can be used to bias the push-pull output stage. Moreover, when analyzing the push-pull output stage with a small signal, the equivalent transconductance is g under the same static current. mn +g mp , and the equivalent transconductance g of the output stage of the traditional operational amplifier mn (or g mp ) can be magnified 1.5-2 times.

[0035] The frequency compensation method of the above embodiments of the present invention is considered with a broadband target, and considers selecting feed-forward amplification compensation or cross-feedback Miller compensation as in the background art.

[0036] The above embodiments of the present invention combine the two functions of forward amplification compensation and push-pull drive stage in the switchable switch tube array. Since no additional current is required for forward amplification compensation, power can be saved. In addition, the advantage of forward amplification compensation is that the proper design of the transconductance of the forward amplification stage can remove the traditional Miller compensation capacitor, so that the bandwidth can be easily pushed out. In combination with the use of a push-pull drive stage, a lower static current can be used to drive a larger load, thereby achieving the purpose of power saving. After the main circuit bandwidth is pushed out, the phase margin of the common-mode feedback loop needs to be processed. The above embodiments of the present invention use two RC series (R C1 ,C C1 and R C2 ,C C2 ) compensation can achieve the effect of zero-point compensation and save the power consumption of the common-mode feedback loop.

Claims

1. An operational amplifier circuit, comprising two differential signal input terminals, two differential signal output terminals, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, characterized in that: The main circuit of the fully differential operational amplifier includes a first differential amplifier circuit as a first stage and a forward amplification compensation and push-pull driving circuit as a second stage, wherein the forward amplification compensation and push-pull driving circuit includes two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull driving; The first differential amplifier circuit includes a first NMOS tube, a second NMOS tube, a third PMOS tube, and a fourth PMOS tube. The forward amplification compensation and push-pull driving circuit includes a fifth PMOS tube, a sixth PMOS tube, and the two groups of switchable switch tube arrays. The drain of the first NMOS tube is connected to the positive electrode of the power supply through the third PMOS tube, and the drain of the second NMOS tube is connected to the positive electrode of the power supply through the fourth PMOS tube. The source of the first NMOS tube is connected to the source of the second NMOS tube and then connected to the bias circuit. The gate of the first NMOS tube is connected to the first differential signal input terminal, and the gate of the second NMOS tube is connected to the second differential signal input terminal. Each group of switchable switch tube arrays includes a plurality of switchable parallel-connected NMOS tubes. The gate of the fifth PMOS tube is connected to the drain of the first NMOS tube, and the gate of the sixth PMOS tube is connected to the drain of the first NMOS tube. The gate of the OS tube is connected to the drain of the second NMOS tube; the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to the positive electrode of the power supply, the drain of the fifth PMOS tube is connected to the first differential signal output end, and is grounded through the NMOS tube of the first group of switchable switch tube arrays; the drain of the sixth PMOS tube is connected to the second differential signal output end, and is grounded through the NMOS tube of the second group of switchable switch tube arrays; the gates of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are connected to the gate of the second NMOS tube through the first AC coupling capacitor, and the gates of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are connected to the gate of the first NMOS tube through the second AC coupling capacitor.

2. The operational amplifier circuit according to claim 1, characterized in that: The common-mode feedback circuit includes a second differential amplifier circuit and a common-mode sampling circuit; the second differential amplifier circuit includes a fifth NMOS tube, a sixth NMOS tube, and two groups of switchable parallel PMOS tubes, the drain of the fifth NMOS tube is connected to the positive electrode of the power supply through the first group of switchable parallel PMOS tubes, and the drain of the sixth NMOS tube is connected to the positive electrode of the power supply through the second group of switchable parallel PMOS tubes; the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube and then connected to the bias circuit, the gate of the fifth NMOS tube is connected to the output end of the common-mode sampling circuit, and the gate of the sixth NMOS tube is connected to the reference voltage signal input end; the common-mode sampling circuit includes two sampling resistors connected in series, and the connection point of the two sampling resistors is the output end of the common-mode sampling circuit; the two ends of the common-mode sampling circuit are respectively connected to the first differential signal output end and the second differential signal output end.

3. The operational amplifier circuit according to claim 2, characterized in that: The common-mode feedback circuit includes a common-mode feedback compensation circuit, which includes a first RC hysteresis compensation circuit and a second RC hysteresis compensation circuit; the source of the first group of switchable parallel PMOS tubes and the source of the second group of switchable parallel PMOS tubes are connected to the positive electrode of the power supply, the drain and the gate of the first group of switchable parallel PMOS tubes are connected to the drain of the fifth NMOS tube, and the drain and the gate of the second group of switchable parallel PMOS tubes are connected to the drain of the sixth NMOS tube; the gate of the first group of switchable parallel PMOS tubes is connected to the positive electrode of the power supply through the second RC hysteresis compensation circuit, and is connected to the gate of the third PMOS tube and the gate of the fourth PMOS tube; the gate of the fifth NMOS tube is grounded through the first RC hysteresis compensation circuit.

4. The operational amplifier circuit according to claim 1, wherein: The forward amplification compensation and push-pull driving circuit includes two Miller compensation capacitors, the first Miller compensation capacitor is connected between the gate and the drain of the fifth PMOS tube, and the second Miller compensation capacitor is connected between the gate and the drain of the sixth PMOS tube.

5. The operational amplifier circuit according to claim 2, wherein: The bias circuit includes a reference current source, a first NMOS tube of the bias circuit, a second NMOS tube of the bias circuit and a switchable switch tube array of the bias circuit, wherein the switchable switch tube array of the bias circuit includes a plurality of switchable NMOS tubes connected in parallel; the input end of the reference current source is connected to the positive pole of the power supply, the output end is connected to the drain of the first NMOS tube of the bias circuit, the drain of the first NMOS tube of the bias circuit is connected to the gate, and the source of the first NMOS tube of the bias circuit is grounded; the gate of the second NMOS tube of the bias circuit is connected to the gate of the first NMOS tube of the bias circuit, the source of the second NMOS tube of the bias circuit is grounded, and the drain is connected to the source of the first NMOS tube of the first differential amplifier circuit and the source of the second NMOS tube; The gate of the bias circuit switchable switch array NMOS tube is connected to the gate of the first NMOS tube of the bias circuit, the source of the bias circuit switchable switch array NMOS tube is grounded, and the drain is connected to the source of the fifth NMOS tube and the source of the sixth NMOS tube of the second differential amplifier circuit.

6. The operational amplifier circuit according to claim 5, characterized in that: The gates of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are connected to the gate of the first NMOS tube in the bias circuit through the first bias resistor, and the gates of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are connected to the gate of the first NMOS tube in the bias circuit through the second bias resistor; the drains of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are connected to the drain of the fifth PMOS tube, and the sources of the NMOS tubes connected in parallel to the first group of switchable switch tube arrays are grounded; the drains of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are connected to the drain of the sixth PMOS tube, and the sources of the NMOS tubes connected in parallel to the second group of switchable switch tube arrays are grounded.

7. The operational amplifier circuit according to claim 1, wherein: According to the requirements of bandwidth and current consumption, the number of NMOS tubes connected in parallel in the two groups of switchable switch tube arrays of the forward amplification compensation circuit and the push-pull driving circuit is adjusted.

8. The operational amplifier circuit according to claim 5, characterized in that: According to the bandwidth and power consumption requirements of the common-mode feedback loop, the number of PMOS tubes connected in parallel in the two groups of switchable parallel PMOS tubes and / or the number of NMOS tubes connected in parallel in the bias circuit switchable switch tube array are adjusted.

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