Circuit device and method for bidirectional data transmission

Abstract

The present invention provides a transformer device for signal transmission, the transformer arrangement comprising at least one transformer having a primary coil and a secondary coil and a controller. The controller is configured to control a first current flowing through the primary coil to increase until a predetermined standard is reached during a magnetization phase, wherein the duration of the magnetization phase is longer than a time constant of the primary coil of at least one transformer. The controller is configured to apply a voltage to at least one transformer during a voltage application phase so that a second current flows through the primary coil, wherein the second current changes polarity relative to the first current during the voltage application phase, wherein the duration of the voltage application phase is shorter than twice the time constant of the primary coil of at least one transformer.

Description

[0001] This application is a divisional application of an invention patent application with an application date of June 16, 2014, application number 201710898225.7, and invention name “Circuit device and method for bidirectional data transmission”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application is related to and claims the benefit of U.S. Provisional Patent Application No. 61 / 835,745 filed on June 17, 2013, entitled “Circuit Device and Method for Bidirectional Data Transmission,” which is hereby incorporated by reference into this application. Technical Field

[0004] Various embodiments generally relate to the transmission of a clock signal and a data signal across an electrically isolated interface. The electrically isolated interface may be a transformer, such as a coreless transformer. The clock signal may be transmitted across the interface in one direction, and the data signal may be transmitted across the interface in the same or opposite direction. The transmission of the clock signal and the data signal may be synchronous. Background Art

[0005] Various embodiments may be used in products that transmit energy through an additional coreless transformer. Since the efficiency of energy transmission is very low, this requires lower energy consumption on the side that receives the clock signal and sends the data signal. An example of such a product may be an electrically isolated analog-to-digital converter (ADC) with an integrated electrically isolated power supply. The transmitted clock signal may be used as the clock signal in the analog-to-digital converter. The analog-to-digital converter may be a sigma-delta transformer. The data signal to be transmitted in the other direction may be data provided by one or two sigma-delta transformers. The transmission in both directions needs to be sufficiently robust relative to the common-mode signal at the electrically isolated interface. In particular, the clock signal needs to be transmitted in a sufficiently robust manner so that the common-mode signal does not add additional jitter to it. Summary of the invention

[0006] Many implementations of transmitting a clock signal edge to a receiver may use edges of opposite polarity at the primary coil (or a pair of primary coils) of the transformer. Reversed polarity may be applied to obtain an inverted clock signal edge. Prior to transmitting the clock signal edge, the primary coil may have been magnetized in the opposite direction. The time required for magnetization may be longer than the L / R time constant of the primary coil. After transmitting the clock signal edge, the primary coil may have been demagnetized. Drivers with symmetrical impedances may be used to magnetize and demagnetize the coil to avoid common mode signals being converted to differential signals between the two transformers.

[0007] It is not necessary to demagnetize to zero; demagnetization can be stopped at a very small value. When the driver is then turned off, the magnetization can jump to zero, which will induce oscillations at the resonant frequency in the pair of transformers. This resonant frequency can be lowered by adding an additional capacitor in the resonant circuit. The damping of the resonant circuit or oscillation can be partially or completely compensated by a circuit with a negative differential resistance. The oscillations in the pair of transformers can then last longer or not damp out.

[0008] The damping of the resonant circuit can be increased from the secondary side by means of a switch for short-circuiting the secondary coil. The resulting damping should be large enough so that the induced oscillations decay quickly enough even when a circuit with a negative differential resistance is present. On the primary side, it can be detected whether and how quickly the oscillations decay, for example with the aid of an amplitude detector, or by counting the number of oscillations exceeding a given amplitude.

[0009] Opening and closing the switch can be performed with very low energy consumption and allows one bit of data to be transmitted with each clock signal edge. Thus, two bits of data can be transmitted in one clock cycle. Since the pair of transformers has a symmetrical structure and a high resonant frequency, the transmission is robust enough to resist interference from common mode signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, the same reference numerals generally refer to the same components throughout the different views. The drawings are not necessarily drawn to scale, emphasis instead being placed on illustrating the principles of the invention. In the drawings, the leftmost digit of a reference number identifies the drawing in which the reference number first appears. The same reference numerals are used throughout the drawings to denote the same features and components. In the following detailed description, many embodiments of the invention are described with reference to the following drawings, wherein:

[0011] Figure 1 An embodiment of a transformer device is shown;

[0012] Figure 2 A detailed embodiment of a transformer device is shown;

[0013] Figure 3 An example of a signal sequence for a transformer device is shown;

[0014] Figure 4 An embodiment of a circuit is shown;

[0015] Figure 5 An example of a signal sequence for a transformer device is shown;

[0016] Figure 6 An example of a signal sequence for a transformer device is shown;

[0017] Figure 7 An embodiment of a circuit arrangement is shown;

[0018] Figure 8 An example of a signal sequence for a transformer device is shown;

[0019] Fig. 9 An embodiment of a circuit arrangement is shown;

[0020] Fig.10 An example of a signal sequence for a transformer arrangement is shown;

[0021] Fig.11 An embodiment of a circuit for encoding data and clock signals is shown; and

[0022] Fig.12 An embodiment of a circuit for encoding clock and additional data signals is shown. DETAILED DESCRIPTION

[0023] The following detailed description, with reference to the accompanying drawings, shows, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0024] “Exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0025] Figure 1 An embodiment of a transformer device 100 for bidirectional signal transmission is shown. The transformer device 100 may have a low side LS and a high side HS. The low side LS and the high side HS may be electrically isolated from each other by at least one transformer 102. The clock signal T on the low side LS may be used to generate a clock signal t on the high side HS. The data signals d1, d2 on the high side HS may be used to generate data signals D1, D2 on the low side LS. The high side HS may have one or two analog-to-digital converters 108, which may provide data signals d1, d2. The analog-to-digital converter 108 may be timed by a clock signal t based on the clock signal T. The data signal may be synchronized with the clock signal.

[0026] At least one transformer 102 may have multiple transformers. In the following embodiment, there are two transformers 102, but different numbers of transformers may also be used. Each transformer 102 may have a primary coil P1, P2 and a secondary coil S1, S2. The primary coils P1, P2 are arranged on the low side LS or the primary side, and the secondary coils S1, S2 are arranged on the high side HS or the secondary side. The primary coils P1, P2 of the multiple transformers may be connected in series. The node PG between the primary coils P1, P2 is connected to a reference voltage. The secondary coils S1, S2 of the multiple transformers may be connected in series. The node SG between the secondary coils S1, S2 is connected to another reference voltage. The high symmetry of the transformer 102 may well suppress common mode interference. However, some embodiments may use only one transformer 102. The transformer 102 may be a coreless transformer.

[0027] The low side LS may have a low side circuit 104. The low side circuit 104 may have an input terminal of a clock signal T and two data output terminals D1, D2. The low side circuit is further connected to the primary coils P1, P2 and the node PG. The high side HS may have a high side circuit 106. The high side circuit 106 may have an output terminal of a clock signal t and two data input terminals d1, d2. The high side circuit is further connected to the secondary coils S1, S2 and the node SG.

[0028] Figure 2 An embodiment is shown that details the low-side circuit 104 and the high-side circuit 106. The low-side circuit 104 may have a controller 202. The high-side circuit 106 may have a receiving circuit 204.

[0029] The controller 202 may be coupled to the primary coils P1, P2. The controller is used as a driver for the primary coils P1, P2, for example, to transmit a clock signal across the transformer 102. The transmission may include a magnetization phase MP, a voltage application phase VP, and a demagnetization phase DP. In the magnetization phase MP, resistors are gradually connected in parallel between the primary coils P1, P2 and the power supply voltage. In the voltage application phase VP, also called the pulse phase, the voltage on the primary coils P1, P2 and the current flowing through the primary coils may change polarity. In the demagnetization phase DP, the resistors between the primary coils P1, P2 and the power supply voltage are gradually disconnected.

[0030] During the magnetization phase MP, the controller 202 is configured to control the first current to flow through the primary coils P1 and P2 until the current increases to reach a predetermined standard. The magnetization phase MP may be longer than the time constant TP=L / R of the primary coils P1 and P2 of the transformer 102. L is the inductance value of the primary coils P1 and P2, and R is the resistance value of the primary coils P1 and P2. For example, the magnetization phase MP may be longer than twice the time constant TP of the primary coils P1 and P2 of the transformer 102. The controller 202 may be configured so that the duration of the magnetization phase MP is in the range of about 5 ns to about 30 ns. For example, it may be in the range of about 7 ns to about 20 ns. For example, it may be in the range of about 9 ns to about 15 ns. For example, it may be about 10 ns.

[0031] The time constant TP=L / R of the primary coils P1 and P2 of the transformer 102, TP may be in the range of about 1 ns to about 10 ns. For example, it may be in the range of about 2 ns to about 6 ns. For example, it may be in the range of about 3 ns to about 4 ns. The controller 202 is further configured to apply a voltage to the transformer 102 during the voltage application phase VP so that a second current flows through the primary coils P1 and P2. The second current may magnetize the transformer 102. The second current has a polarity that changes during the voltage application phase VP compared to the polarity of the first current. The duration of the voltage application phase VP may be shorter than twice the time constant TP of the primary coils P1 and P2 of the transformer 102. For example, it may be shorter than the time constant TP of the primary coils P1 and P2 of the transformer 102. The controller 202 may be configured so that the duration of the voltage application phase VP is in the range of about 0.5 ns to about 6 ns. For example, it may be in the range of about 1 ns to about 4 ns. For example, it may be in the range of about 2 ns to about 3 ns.

[0032] During the demagnetization phase DP, the controller 202 is further configured to control the third current flowing through the primary coils P1 and P2 to decrease. The third current can demagnetize the transformer 102. The demagnetization phase DP can be longer than the time constant TP of the primary coils P1 and P2 of the transformer 102. For example, the duration of the magnetization phase MP can be longer than twice the time constant TP of the primary coils P1 and P2 of the transformer 102. The controller 202 can be configured so that the duration of the demagnetization phase DP is in the range of about 5 ns to about 30 ns. For example, it can be in the range of about 7 ns to about 20 ns. For example, it can be in the range of about 9 ns to about 15 ns. For example, it can be about 10 ns.

[0033] Figure 3An example of a signal sequence 302 of a current IP1 flowing through the primary coil P1, a signal sequence 304 of a voltage VP1 across the primary coil P1, and a signal sequence 306 of a voltage VS1 across the secondary coil S1 is shown. The signal sequences 302, 304, and 306 may correspond to a magnetization phase MP from a time period t0 to t1, a voltage application phase VP from a time period t1 to t2, and a demagnetization phase DP from a time period t2 to t3.

[0034] At time t0, the current IP1 flowing through the primary coil P1 may begin to increase slowly in the negative direction. It may increase until it reaches a negative maximum value at time t1. The time period between t0 and t1 may be greater than the time constant TP=L / R of the primary coil P1. The increase in current IP1 may be selected so that only a small and substantially constant negative voltage VS1 is present in the secondary coil S1.

[0035] At time t1, the primary coil P1 may be connected to a predetermined voltage Vpd, such as a supply voltage. This connection may last until time t2, see signal sequence 304. The time period between t1 and t2 may be less than the time constant TP=L / R of the primary coil P1. The time period may be selected so that the current IP1 has opposite polarities, such as the same magnitude, at time t1 and t2. For example, at time t1, IP1 may be negative and have a magnitude of -A, and at time t2, IP1 may be positive and have a magnitude of +A. As a result, a large positive pulse is induced in the secondary coil S1, see signal sequence 306. This pulse may decrease in an exponential manner.

[0036] At time t2, the current IP1 flowing through the primary coil P1 may begin to slowly decrease towards 0. The current reaches the value 0 at time t3. The duration between time t2 and t3 may be greater than the time constant TP=L / R of the primary coil P1. The decrease in current IP1 may be selected so that only a small and substantially constant negative voltage VS1 is present in the secondary coil S1.

[0037] Reversing the magnetization of the transformer before inducing the pulse in the secondary coil S1 is beneficial to reducing the maximum current required to be provided by the power supply. Furthermore, the ratio of the voltage in the reverse direction generated in the secondary coil to the amount of charge required to be provided by the power supply is also higher.

[0038] In the case where the transformer 102 is symmetrical, i.e., it has two complementary primary coils P1, P2 and two complementary secondary coils S1, S2, each signal sequence IP1, VP1, VS1 may have a complementary signal sequence IP2, VP2, VS2. When there is no common mode interference and the current flowing into the primary coil P1 is the same as the current flowing out of the primary coil P2, no current will flow through the common node PG. The controller 202 is used to implement Figure 3The signal sequence shown in .

[0039] Figure 4 An embodiment of a circuit 400 that can be coupled to a controller 202 is shown. The controller 202 can be configured to gradually increase a first current flowing through the primary coils P1, P2 of the transformer 102. The circuit 400 can be used to provide slowly increasing and decreasing currents IP1, IP2 for driving the primary coils P1, P2. The circuit can have a plurality of branch circuits 402 connected in parallel. Each branch circuit 402 can include a switch S and a resistor R connected in series. A first terminal 404 of each branch circuit 402 can be coupled to a reference voltage Vs, GND, and a second terminal 406 of each branch circuit 402 can be coupled to the transformer 102, such as one of the primary coils P1, P2 of the transformer. A node PG between the primary coils P1 and P2 can be connected to a reference voltage Vref. The reference voltage Vref can be approximately half of the power supply voltage Vs.

[0040] A first plurality of circuits 408 of the branch circuits 402 may have a first terminal 404 connected to a first voltage, such as a power supply voltage Vs, and a second terminal 406 connected to the primary coil P1. The switches S in the first plurality of circuits 408 of the branch circuits 402 may be controlled by signals g5 to g8 to provide a step-by-step changing current IP1 in one direction in the primary coil P1. The magnitude of the current IP1 may be gradually reduced.

[0041] The second plurality of circuits 412 of the branch circuit 402 may have a first terminal 404 connected to a second voltage, such as a ground voltage GND, and a second terminal 406 connected to the primary coil P2. The switches S in the second plurality of circuits 412 of the branch circuit 402 may also be controlled by signals g5 to g8 to provide a step-changing current IP2 in one direction in the primary coil P2. The magnitude of the current IP2 may be gradually reduced.

[0042] The third plurality of circuits 410 of the branch circuit 402 may have a first terminal 404 connected to a first voltage, such as a power supply voltage Vs, and a second terminal 406 connected to the primary coil P2. The switches S in the third plurality of circuits 410 of the branch circuit 402 may be controlled by signals g1 to g4 to provide a step-by-step current IP2 in the primary coil P2, the direction of which is opposite to the direction of the current IP2 provided by the second plurality of circuits 412. The magnitude of the current IP2 may be gradually increased.

[0043] The fourth plurality of circuits 414 of the branch circuits 402 may have a first terminal 404 connected to a second voltage, such as a ground voltage GND, and a second terminal 406 connected to the primary coil P1. The switches S in the fourth plurality of circuits 414 of the branch circuits 402 may also be controlled by the signals g1 to g4 to provide a step-by-step current IP1 in the primary coil P1, the direction of which is opposite to the direction of the current IP1 provided by the first plurality 408. The magnitude of the current IP1 may be gradually increased.

[0044] For clarity, the plurality of circuits 408, 410, 412, 414 of the branch circuits 402 for magnetization and demagnetization are shown with four branch circuits 402. However, any number of branch circuits 402 may be used, such as 6 to 8. Some branch circuits 402, such as the branch circuit 402 controlled by the signal g5, may have a resistor R with zero resistance.

[0045] In principle, it is also possible to increase or decrease the current using a series connected resistor R. However, this may be detrimental to the total chip area required for the switch and its parasitic capacitance.

[0046] By gradually connecting and disconnecting the resistors in parallel between the primary coils P1, P2 and the power supply Vs, it is possible to achieve a highly symmetrical drive of the primary coils P1, P2. The use of resistors may have the advantage that a symmetrical output resistance of the driver can always be provided. Symmetrical output resistance may be difficult to achieve with graduated PMOS and NMOS, because the output resistance is only symmetrical within the allowed range of the symmetry of the complementary transistors. The switches may be arranged symmetrically.

[0047] Figure 4 A circuit 400 is shown for transmitting a positive pulse with a rising edge. The same circuit 400 may be used to transmit a negative pulse. In this case, the connections to P1 and P2 may need to be swapped. The resistor R may be shared so that only the switch S needs to be re-provided.

[0048] The resistance of at least some of the resistors R may be greater than the resistance of the primary coil. The resistance of at least some of the resistors R may be in the range of about 10 ohms to about 1000 ohms. The resistance of all resistors R may be the same. The resistance value of the primary coils P1, P2 is in the range of about 1 ohm to about 50 ohms.

[0049] Figure 5 An example of a signal sequence 502 with signals g1 to g8 for controlling the switch S, a signal sequence 504 for the current IP1 flowing through the primary coil P1, a signal sequence 506 for the voltage VP1 across the primary coil P1, and a signal sequence 508 for the voltage VS1 across the secondary coil S1 is shown. For clarity, Figure 5Only the signal sequence 504 of the current IP1 of the primary coil P1, the signal sequence 506 of the voltage VP1 of the primary coil P1, and the signal sequence 508 of the voltage VS1 are shown. The signal sequence of the current IP2 flowing through the primary coil P2, the signal sequence of the voltage VP2 across the primary coil P2, and the signal sequence of the voltage VS2 across the secondary coil S2 may be complementary or inverse to the signal sequence shown.

[0050] All switches S may be open when no signal needs to be transmitted. They may be open before the magnetization phase MP starting at time point t0. The switches S controlled by signals g1 to g4 may be closed one by one in the magnetization phase MP. Since the resistor R is connected in parallel with the switches, the current IP1 flowing through the primary coil P1 may be gradually increased.

[0051] At time point t1, all switches S controlled by signals g1 to g4 may be opened, and switches S controlled by signal g5 may be closed at the same time. During the time period from time point t1 to t2, which may be a voltage application phase VP or a pulse phase, switches S controlled by signals g6 to g8 may be closed, for example, closed at the same time. Then, the current IP1 flowing through the primary coil P1 may increase sharply in the opposite direction.

[0052] During the time period from time point t2 to t3, which may be a demagnetization phase DP, the switches S controlled by signals g5 to g8 may be opened one by one, for example in a sequence starting from the switch S controlled by signal g5. As the resistors R are disconnected one by one, the current IP1 flowing through the primary coil P1 may be gradually weakened. After the demagnetization phase is terminated, all switches S may be opened.

[0053] The evaluation of the voltages VS1, VS2 at the secondary coils S1, S2 and the reconstruction of the clock signal T can be realized by using comparators and storage elements, for example RS flip-flops. Figure 5 As shown, the transmission of a rising edge signal in the primary coil P1 may cause a large positive pulse PP accompanied by a plurality of smaller negative pulses NP in the secondary coil S1. Conversely, the transmission of a falling edge signal in the primary coil may cause a large negative pulse accompanied by a plurality of smaller positive pulses in the secondary coil. Therefore, when the pulses have opposite polarities, the comparator should only capture the large pulses and be insensitive to the smaller pulses. The sensitivity of the comparator or, in other words, the threshold of the comparator should therefore be between the amplitude of the large pulse and the amplitude of the smaller pulse. The sensitivity may be fixed or have a temperature dependency which may compensate for the temperature dependency of the transmission path.

[0054] Oscillations in the gaps of the transmission clock signal can be used to transmit data in the reverse direction and can also appear in the signal of the secondary coil and at the input of the comparator. The amplitude of these oscillations can be difficult to reproduce. They can depend on the quality factor Q of the resonant circuit formed by one or a pair of transformers. A comparator with an automatically regulating or adaptive sensitivity is thus obtained.

[0055] Figure 6 Examples are shown of a signal sequence 602 of the secondary voltage VS1, a signal sequence 604 of the output K1 of the first comparator, a signal sequence 606 of the output K2 of the second comparator, a signal sequence 608 of the first output K3p of the third comparator, and a signal sequence 610 of the second output K3n of the third comparator.

[0056] Signal sequence 602 shows a typical voltage waveform of voltage VS1 in secondary coil S1, including transmission at the rising edge of clock signal PE, oscillation OS in the opposite direction or reverse transmission, and transmission at the falling edge of clock signal NE. Receiving circuit 204 can use two window comparators with adjustable sensitivity or threshold. The threshold can be symmetrical about zero. The output of the comparator can be inactive and its signal can be "0", for example, when no input signal is applied to it. When the input signal exceeds the threshold of the comparator, the output of the comparator can be active and may output a signal "1", for example.

[0057] The threshold of one of the window comparators can be adjusted, that is, it can be increased or decreased until the duty cycle between active and inactive reaches a predetermined value, such as 2%. Figure 6 The comparator is shown in signal sequence 602 as E1p at positive voltage and E1n at negative voltage. The output of the comparator is shown as K1 in signal sequence 604. The time during which the signal VS1 is greater than E1p can be T1. The time during which the signal VS1 is less than E1n can also be T1. The thresholds E1p, E1n can be close to or close to the amplitude of the large pulse. If some of the large pulses do not have the same amplitude, for example in the presence of an interference signal, the large pulse may not appear in K1. However, this is not decisive, because only the average duty cycle during multiple pulses is meaningful.

[0058] Another of the window comparators has a threshold that can be adjusted, that is, it can be increased or decreased until the duty cycle between active and inactive reaches another predetermined value, such as 10%. Figure 6The comparator is shown in signal sequence 602 as E2p for positive voltage and E2n for negative voltage. The output of the comparator is shown as K2 in signal sequence 606. The time during which the signal VS1 is greater than E2p can be T2. The time during which the signal VS1 is less than E2n can also be T2. In the case where the large pulse time is shorter than 10% of the interval time between them, the threshold of the stable state can be some but usually not all pulses at the output terminal K2 of the comparator for transmission in the reverse direction.

[0059] Further, the two comparators used may not be window comparators, that is, they will only detect signals in one direction. However, they may rely on control signals for adjusting the sensitivity or threshold of the comparators as well as window comparators. One of the comparators may only detect signals that exceed its threshold E3p in the positive direction, and the other comparator may only detect signals that exceed its threshold E3n in the negative direction. The sensitivity or threshold E3 of the two comparators may be adjusted to the average value of the steady-state thresholds E1 and E2. This will result in the highest transmission reliability, in which all large pulses and no smaller pulses or oscillations will be evaluated by the two transformers to recover the clock signal.

[0060] As an alternative, two identical comparators with swapped inputs may also be used. Further, each of the window comparators may be implemented by two comparators with swapped inputs and an "or" output. This may have the advantage that all comparators may be constructed in the same way and have very similar performance. A circuit arrangement using these alternatives is shown in Figure 7 .

[0061] Figure 7 An embodiment of a circuit device 700 is shown. The circuit device 700 may be a receiving circuit 204 for receiving pulses at the secondary coils S1, S2. The circuit device 700 may have at least three comparators 702, 704, 706 and a control circuit. The first comparator 702, the second comparator 704 and the third comparator 706 may be coupled to the secondary coils S1, S2. The first comparator 702, the second comparator 704 and the third comparator 706 may all be configured to receive the same signal, such as the voltage VS between the secondary coils S1, S2. The three comparators 702, 704, 706 may be constructed and designed in the same manner. The sensitivity or comparator threshold of each comparator 702, 704, 706 may be adjusted independently of the other two of the comparators 702, 704, 706. The control circuit may have a first feedback control system 710, a second feedback control system 712 and coupling elements 714, 716.

[0062] The first comparator 702 may have a first feedback control system 710. The first feedback control system 710 may adjust the sensitivity of the first comparator 702 or the first comparator threshold E1p, E1n according to the duty cycle of the signal K1 at the output of the first comparator 702, so as to achieve a first reference duty cycle. The feedback signal F1 output by the first feedback control system 710 may be connected to the threshold adjustment input 718 of the first comparator 702. The first feedback control system 710 may have, for example, a capacitor, which is charged when the output of the first comparator 702 is active and discharged when the output of the first comparator 702 is inactive. The discharge current may be, for example, 2% of the charging current. The voltage across the capacitor may represent or be the first comparator threshold. The capacitor may act as an integrated circuit and smooth the feedback signal F1. The afterwave of the feedback signal F1 is usually ineffective.

[0063] Similarly, the second comparator 704 may have a second feedback control system 712. The second feedback control system 712 may adjust the sensitivity of the second comparator 704 or the second comparator threshold E2p, E2n according to the duty cycle of the signal K2 at the output of the second comparator 704, thereby achieving a second reference duty cycle. The feedback signal F2 output by the second feedback control system 712 may be connected to the threshold adjustment input 720 of the second comparator 704. The second feedback control system 712 may have, for example, a capacitor, which is charged when the output of the second comparator 704 is active and discharged when the output of the second comparator 704 is inactive. The discharge current may be, for example, 10% of the charging current. The voltage across the capacitor may represent or be the second comparator threshold. The capacitor may act as an integrated circuit and smooth the feedback signal F2. The afterwave of the feedback signal F2 is usually ineffective.

[0064] The sensitivity of the third comparator 706 or the third comparator threshold E3p, E3n can be adjusted to be within a range between the sensitivity E1p, E1n of the first comparator 702 and the sensitivity E2p, E2n of the second comparator. The signal F3 can be connected to the threshold adjustment input 722 of the third comparator 706. The signal F3 can be coupled to the feedback signal F1 through the coupling element 714, and can be coupled to the feedback signal F2 through the coupling element 716. Therefore, the value of the signal F3 is within a range between the value of the feedback signal F1 and the value of the feedback signal F2. The coupling elements 714, 716 can be, for example, resistors, which can have the same resistance, for example.

[0065] The control circuit may be configured to adjust the first comparator thresholds E1p, E1n so that the first comparator circuit 702 is in a first comparator output state, such as logic “1”, within a first time period T1 of a predefined time interval.

[0066] The control circuit can be further configured to adjust the second comparator thresholds E2p, E2n so that within a second time period T2 of a predefined time interval, the second comparator circuit 704 is in the state of the first comparator output, such as logic "1", wherein the second time period T2 is longer than the first time period T1.

[0067] The control circuit is configured to set the third comparator threshold E3p, E3n to be within a range between the first comparator threshold E1p, E1n and the second comparator threshold E2p, E2n.

[0068] At least one of the first time period T1 and the second time period T2 may be a sum of a plurality of sub-time periods.

[0069] At least one of the first comparator circuit 702 and the second comparator circuit 704 may be configured as a window comparator circuit. The third comparator circuit 706 may be configured to provide an evaluation output signal K3p, K3n.

[0070] The storage element 708 may be coupled to the output terminals K3n, K3p of the third comparator circuit 706 to store the evaluation output signal. The storage element 708 may be a trigger, such as an RS trigger. The set input terminal S may be connected to the output terminal K3p, and the reset input terminal R may be connected to the output terminal K3n. The output of the storage element 708 may be a clock signal t.

[0071] The control circuits 710 , 712 may be configured to adjust at least one of the first thresholds E1p, E1n according to the output signal K1 provided by the first comparator circuit 702 , and to adjust the second thresholds E2p, E2n according to the output signal K2 provided by the second comparator circuit 704 .

[0072] The control circuits 710 , 712 may be configured to adjust at least one of the first thresholds E1p, E1n based on a time-based evaluation of the output signal K1 provided by the first comparator circuit 702 ; and to adjust the second thresholds E2p, E2n based on a time-based evaluation of the output signal K2 provided by the second comparator circuit 704 .

[0073] The control circuits 710 and 712 can be configured to adjust at least one of the first thresholds E1p and E1n according to the output signal K1 provided by the first comparator circuit 702, wherein the first signal state of the output signal K1 and the second signal state of the output signal K1 are weighted in different ways; and to adjust the second thresholds E2p and E2n according to the output signal K2 provided by the second comparator circuit 704, wherein the first signal state of the output signal K2 and the second signal state of the output signal K2 are weighted in different ways.

[0074] The control circuits 710 and 712 may be configured to adjust at least one of the first thresholds E1p and E1n according to the average value of the output signal K1 provided by the first comparator circuit 702 ; and to adjust the second thresholds E2p and E2n according to the average value of the output signal K2 provided by the second comparator circuit 704 .

[0075] Figure 8 An example of a signal sequence 802 of a current IP1 flowing through a primary coil P1, a signal sequence 804 of a voltage VP1 across the primary coil P1, and a signal sequence 806 of a switch control signal SD over a time t is shown. Signal sequences 802, 804, and 806 are generated during data transmission across a transformer (e.g., a coreless transformer), during which they are transmitted in one direction by pulses. Each pulse may induce an oscillation in the transformer. Data may be transmitted in the other direction by suppressing or not suppressing the induced oscillation.

[0076] Current IP1 relative to Figure 3 and Figure 5 The current IP1 shown is modified because the current IP1 also slowly decreases from the time point t2, but does not reach zero. Instead, it suddenly stops at the time point t3 and jumps to 0, which can induce or start oscillation in the transformer or transformer pair. The oscillation frequency can be the resonant frequency of the transformer or transformer pair. This frequency can be reduced when an oscillating current capacitor is used.

[0077] When using a transformer pair, a common tank circuit capacitor may be useful. The oscillations on the primary coils P1, P2 may initially have opposite phases to each other. The common tank circuit capacitor may prevent changes in the phase relationship due to slightly different resonant frequencies of the transformer coils. The resonant circuit may then consist of a primary coil and a capacitor connected in series.

[0078] The damping of the oscillations may depend to a large extent on the quality factor Q of the resonant circuit, which in turn is influenced by the quality factor of the transformer. The quality factor of the transformer integrated on the semiconductor chip may be relatively low, for example in the range of 5 to 10. An excitation circuit, for example with a dynamic negative internal resistance, which compensates for the losses in the transformer, may be used to extend the time of the oscillation after the pulse. For example, an excitation circuit of an LC oscillator may be used. The degree of excitation may be reduced with the oscillation amplitude to avoid overexcitation. In the case of overexcitation it will be difficult to separate large pulses from the oscillation, as previously described in connection with Figure 6 discussed.

[0079] The switch 206 may be arranged on the secondary side or high side HS, for example Figure 2As shown. Switch 206 can be used to short-circuit secondary coils S1 and / or S2. The quality factor of the primary side or low side LS is much lower when switch 206 is closed compared to when switch 206 is open. If the excitation is not too large, the amplitude of the oscillation will decrease very quickly when switch 206 is closed.

[0080] The circuit for controlling the switch 206 on the high side HS can be configured to close the switch 206 for a certain time period TD after receiving a pulse in the clock signal direction if the data to be transmitted in the data signal direction has a certain value (e.g., "1"), and not close the switch 206 if the data bit to be transmitted has another value (e.g., "0"). The time period TD can be shorter than the time period TT between two clock signal edges so as not to interfere with the reception of the next clock signal edge.

[0081] The LC oscillator may not start oscillating immediately after the switch 206 is opened, because the oscillation has been greatly damped at this time, and the excitation is not generated in time due to the sudden end of demagnetization. If the oscillation has been damped sufficiently before this, the LC oscillator can only provide an oscillation amplitude that increases exponentially, but the oscillation amplitude will start from a very small value.

[0082] In principle, the switch 206 can be kept closed until the next clock signal edge is received. The premise is that the switch has a current limiting characteristic, that is, it has an on-resistance that increases rapidly as the current flowing through it increases. This characteristic can be achieved by driving the field effect transistor with a gate voltage slightly higher than the threshold voltage. The voltage pulse on the secondary side can be suppressed by the current limiting switch being closed when the next clock signal edge is received. However, if the current limit is of appropriate size, it will still have a value sufficient to be detected. In this regard, combined with Figure 6 and Figure 7 The detection circuits and methods described are useful.

[0083] The detection of the data bits in the data direction of the low side LS can be realized, for example, by means of an amplitude detection, for example by means of an amplitude detection circuit 210. In case the switch 206 on the high side HS is closed only for a certain period of time, the amplitude of the oscillation can be detected at a delayed point in time, which is delayed with respect to the transmission of the last clock signal edge by as long as the time during which the switch 206 on the high side HS was closed, but most directly before the transmission of the next clock signal edge. If the switch 206 on the high side HS remains closed until the next clock signal edge is received, it is sufficient to carry out the amplitude detection directly before the transmission of the next clock signal, or more precisely before the next magnetization phase.

[0084] As an alternative to the above, the number of oscillations or periods detected by a comparator can be counted, the comparator having a specified threshold value. If a "1" is transmitted, only a few oscillations or periods will be detected, while if a "0" is transmitted, a significantly larger number of oscillations or periods will be detected. A digital evaluation circuit can statistically evaluate the individual count values ​​and can adjust the threshold value to be below the number of oscillations interpreted as a "1" and also to be above the number of oscillations interpreted as a "0".

[0085] Since one data bit can be transmitted between two clock signal edge transmissions, it is possible to transmit two bits of data in a data stream in each clock signal cycle. For example, the clock signal can be used to transmit a data stream of two Sigma-Delta regulators that are clocked. Alternatively and as an example, a data stream of a Sigma-Delta regulator and a data stream of additional redundant information can be transmitted. If more than two bits of data are to be transmitted in one clock signal cycle, it is possible to repeat the transmission of each clock signal edge after a quarter of a clock cycle and to send another bit of data thereafter in the data stream direction.

[0086] A transformer device for signal transmission may have at least one transformer, a controller and a switching circuit. The transformer may have a primary coil and a secondary coil. The transformer device may have a resonant frequency. The controller may be configured to terminate the driving of the primary coil so that the transformer device oscillates at the resonant frequency. The switching circuit may be coupled to the secondary coil and configured to, in a first switching state, cause the transformer device to oscillate, and, in a second switching state, reduce the oscillation of the transformer device. Driving the primary coil may be at least one of a magnetization phase, a demagnetization phase and a voltage application phase. The primary coil may be driven after a certain period of time has passed after the driving of the primary coil is terminated. The transformer device may further have an amplitude detection circuit that may be coupled to the primary coil. For the specific time period, if the switching circuit is in the second switching state, it should be selected to be long enough to reduce the oscillation, and there is a long enough time for the reduction of the oscillation amplitude to be detected by the amplitude detection circuit. The time that the switching circuit is in the second switching state may be shorter than the specific time period before starting to drive the coil. The directions of magnetization in the phases of continuously driving the primary coil may have opposite polarities. For a certain number of consecutive driving primary coil stages, the magnetization directions of the consecutive driving primary coil stages have the same polarity. In a specific time period before starting to drive the coil, one bit of data is transmitted by detecting whether the oscillation decreases.

[0087] Combination Figure 4The circuit arrangement 400 described for magnetizing and demagnetizing a transformer or a transformer pair needs to provide some closely spaced and consecutive time points in order to sequentially add or remove resistance. The time intervals between the time points are significantly shorter than the time constant L / R of the primary coil. The time constant L / R of a transformer integrated on a semiconductor chip can be in the range of 5 ns. Therefore, the time points need to be provided with a time interval of 1 ns to 2 ns between them.

[0088] The symmetry of the peak current in the primary coil at the time points t1 and t2 may depend largely on the time intervals between the holding time points t0 to t1 and between the time points t1 to t2. Further, the amplitude of the post-pulse oscillation generated after the abrupt end of the demagnetization phase DP depends on the time interval between the holding time points t2 to t3. The generation of continuous data signals in short time intervals can be achieved by using inverter chains. However, inverter chains are not sufficiently accurate because the delay through the inverters can be significantly affected by process parameters, power supply voltage and temperature. Another method for generating continuous signals in time intervals of a few nanoseconds is to use a digital PWM (pulse width modulation) modulator. Here, a clock signal cycle can be divided into equal time intervals by using a feedback control circuit and adjustable delay elements. The circuit may require the number of delay elements to be adjusted according to the clock signal frequency, which requires considerable effort during chip design and when using the transmission channel in a higher-level system. Simple self-excited circuit devices are provided to generate continuous signals with fairly accurate and reproducible time intervals.

[0089] The circuit arrangement is based on the understanding that the total delay time between the input signal and the output signal is irrelevant, and it is the time interval between the output signals that is meaningful. Delay circuits with different delay times can be used. The input signals can be applied to the inputs of the delay circuits simultaneously, resulting in the signals at the outputs of the delay circuits being staggered from each other. The delay elements are constructed so that at least one processing parameter has the greatest effect on the delay element with the shortest delay and has a staggered smaller effect on the delay element with a larger delay. The processing parameters designed to affect the circuit are, for example, the width or lateral dimensions of the resistors and capacitors. The size of the capacitor can be increased with the required delay. If the capacitor is not constructed using unit capacitors, the capacitor with a larger delay time will be less dependent on changes in the width of the structure.

[0090] Delay elements with the shortest delay can have resistors with very small widths. Resistors in delay elements with longer delays can have larger widths. The width of the resistors can be proportional to the delay time. For a given resistor value, resistors with larger widths need to be longer. Ultimately, the achievable ratio between the longest delay time and the shortest delay time is a question of chip space.

[0091] Delay circuits can use out-of-phase or inverted signals in the delay elements. Thus, the dependence of the inverter on the threshold voltage is reduced. Delay circuits can be built in a symmetrical way. They can process both the signal and the compensation signal. Thus, the coding of the control signal of the switch is simplified, since there is a compensation signal for each signal and the number of gates in each signal path is constant.

[0092] Fig. 9 An embodiment of a circuit arrangement 900 is shown. The circuit arrangement 900 may have three delay circuits 902, 904, and 914. Each of the delay circuits 902, 904, and 914 may have two delay stages 920, 924, and 928. The two delay stages 920, 924, and 928 may operate in an anti-phase manner. The delay stage 920 may use a resistor 906 with a resistance of R and a capacitor 910 with a capacitance of C. The width of the resistor 906 may be, for example, 400nm. The capacitor 910 may be, for example, 2x2μm. The sub-delay circuit 924 may use a resistor 908 with a resistance of R and a capacitor 912 with a capacitance of 1.5C. The width of the resistor 908 may be, for example, 600nm. The capacitor 912 may be, for example, 2x3μm. The sub-delay circuit 928 may use a resistor 916 with a resistance of R and a capacitor 918 with a capacitance of 2C. The width of the resistor 916 may be, for example, 800nm. Capacitor 918 may be, for example, 2 x 4 μm.

[0093] The signal DL2 at the output of the delay circuit 904 may be delayed by a current limiting resistor RC relative to the signal DL1 at the output of the delay circuit 902. The signal DL3 at the output of the delay circuit 914 may be delayed by another current limiting resistor RC. R may be a resistance value selected by design to increase according to the various variables of the thin film resistor, but without considering the influence of the various variables on the width or lateral dimensions of the structure. The capacitors 910, 912 and 918 may be made as MOS capacitors with a high tight tolerance. The nonlinear errors commonly associated with MOS capacitors may be compensated by the series delay stages 920, 924 and 928 running in anti-phase so that the symmetry of the rising and falling edge delay times is not affected.

[0094] For all delay circuits, the transmission delay and delay time caused by their lines are the same and do not affect the time difference between the output signals DL1 , DL2 , and DL3 .

[0095] The circuit arrangement 900 may be a pulse generating circuit arrangement configured to provide pulses. It may generate two signals or pulses from a common input signal. The time delay of the first of the two signals relative to the common input signal is shorter than the time delay of the second signal relative to the common input signal. The time delay of the first signal relative to the time delay of the second signal has a higher sensitivity to the generation parameters.

[0096] The circuit device 900 may have a first signal delay circuit 902 and a second signal delay circuit 904. The first signal delay circuit 902 and the second signal delay circuit 904 are configured to receive the same signal S to be delayed. The second signal delay circuit 904 may have a longer signal delay time relative to the first signal delay circuit 902. The circuit device 900 may be used as a pulse generating circuit device configured to provide a pulse. The pulse generating circuit may be configured to provide a pulse so that the pulse is started by a signal provided by the first signal delay circuit and terminated by a signal provided by the second signal delay circuit.

[0097] The first signal delay circuit 902 may have a first element controlled by a process variable. The first element may affect the signal delay time of the first signal delay circuit 902.

[0098] The second signal delay circuit 904 may include a second element that is controlled by the same process variables as the first element, and the second element may affect the signal delay time of the second signal delay circuit 904 .

[0099] The degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit 904 is smaller than the degree of influence of the process variable of the first element on the signal delay time of the first signal delay circuit 902 .

[0100] The degree of influence of the process variable of the first element on the signal delay time of the first signal delay circuit is inversely proportional to the influence of the first element on the signal delay time of the first signal delay circuit. The degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit may be inversely proportional to the influence of the second element on the signal delay time of the second signal delay circuit.

[0101] Therefore, the influence of the process variable on the delay time of the first element and the second element may be the same in absolute value, for example in nanoseconds. Therefore, the first signal delay and the second signal delay may not depend on the process variable, that is, the influence of the process variable is weakened.

[0102] The first element may have a first resistor 906. The second element may have a second resistor 908. The first resistor 906 and the second resistor 908 may have different resistance widths. The first resistor 906 and the second resistor 908 may have the same nominal resistance value R.

[0103] The first signal delay circuit 902 may further include a first capacitor 910 having a first capacitance of C. The second signal delay circuit 904 may further include a second capacitor 912 having a second capacitance. The second capacitance may be different from the first capacitance. The second capacitance may be higher than the first capacitance. For example, the first capacitance may be C and the second capacitance may be 1.5C.

[0104] The circuit device 900 may further include a third signal delay circuit 914, wherein the delay circuit 914 includes a third element, and the third element is controlled by the same process variable as the first element. The third element may affect the signal delay time of the third signal delay circuit 914. The degree of influence of the process variable of the third element on the signal delay time of the third signal delay circuit 914 is smaller than the degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit 904.

[0105] The first signal delay circuit 902 may include a series connection of a plurality of sub-delay circuits 920. Each sub-delay circuit 920 may have a first element 906 and a signal inverter 922. The second signal delay circuit 904 may include a series connection of a plurality of sub-delay circuits 924. Each sub-delay circuit 924 may have a second element 908 and a signal inverter 926.

[0106] As mentioned above and Figure 8 In the example shown, pulses with opposite polarity can be transmitted alternately across the coreless transformer in the direction of the clock signal. The alternation of pulses can contain a high amount of redundancy. Some redundancy can be discarded to allow additional data to be transmitted in the direction of the clock signal.

[0107] The additional data may be, for example, configuration information, for example for changing or calibrating a sigma-delta regulator gain. As another example, a successive approximation analog-to-digital converter may be used instead of a sigma-delta regulator, the conversion of which is started by the transmission of additional information in addition to the clock signal. Further, the additional data may transmit fine-tuning or configuration information of circuit elements of the high side HS, which may be stored, for example, on the low side LS in the case where the high side HS does not have a non-volatile memory. The fine-tuning or configuration information may be, for example, for calibrating a bandgap reference or a zero error of an analog-to-digital converter provided on the high side HS.

[0108] Additional data may be transmitted in the direction of the clock signal by inverting individual pulses. For example, in a sequence of interleaved positive and negative pulses, a negative pulse is replaced by a positive pulse or a positive pulse is replaced by a negative pulse. In order that the integrity of the received pulses can still be detected, only a small fraction of all transmitted pulses may be inverted. For example, every 8th or 16th pulse may be inverted.

[0109] The RS trigger is used as the receiving circuit of the memory, such as Figure 7 As shown, consecutive pulses with the same polarity are ignored. The receiving circuit may need to compare the received pulse polarity with the state of the storage element and change the storage element to prevent deviations in the alternating pulse sequence. It can output additional pulses for logical decoding of additional data. When the polarity of several consecutive received pulses is opposite to the expected polarity due to the state of the storage element, synchronization of the storage element with the received signal is necessary.

[0110] Fig.10 An example of a signal sequence 1002 of a clock signal, a signal sequence 1004 for transmitting a clock signal, and a signal sequence 1006 of additional data is shown. For simplicity, only rectangular pulses without magnetization and demagnetization are shown. The rising edge of the signal sequence 1002 may cause a positive pulse, which is shown as a protrusion "r" in the signal sequence 1004. The falling edge of the signal sequence 1002 may cause a negative pulse, which is shown as a protrusion "f" in the signal sequence 1004. The rising edge and the falling edge of the clock signal may be transmitted by pulses with different polarities. When no additional data needs to be transmitted, the signal sequence 1002 may be a pulse sequence with alternating polarities.

[0111] For example, positive pulses instead of negative pulses may be transmitted at the falling edges of the third and seventh clock pulses. The polarity of pulses 3f, 7f has changed from negative to positive. The receiving circuit may detect that the polarity of the received clock signal (negative) does not match the expected polarity (positive). It will generate a "1" at the output, which may last for, for example, one clock signal period T, as shown in signal sequence 1006. Signal sequence 1006 can be used to transmit data in the clock signal direction.

[0112] If one pulse is inverted every N pulses, the receiving circuit can be configured to output a "1" every N pulses. For example, if at most one pulse is inverted during the eighth pulse, the receiving circuit outputs a "1" during the entire eight pulse period or four clock cycles. In this way, many "1"s and many "0"s will be transmitted in the additional channel. Data can be transmitted through the same interface in the same direction as the clock signal, and its transmission is achieved by inverting a number of pulses, and the pulse inversion depends on the data to be transmitted.

[0113] Fig.11A circuit 1100 for transmitting data and a clock signal is shown, for example, across a transformer 102. The term "additional data" may be used to refer to data that is transmitted in the same direction as the clock signal T, for example, across the transformer 102. It may be data that is transmitted from the primary coil (or low side) to the secondary coil (or high side). In contrast, data that is transmitted in the opposite direction of the transmission direction of the clock signal T, that is, data that is transmitted from the secondary coil (or high side) to the primary coil (or low side), for example, d1, d2. Data can therefore be transmitted across the transformer 102 in both directions, although the clock signal T is transmitted in only one direction.

[0114] Circuit 1100 can be used with Figure 2 Shown and combined Figure 2 The circuit 1100 is similar to the described circuit 202 and includes an input terminal for the clock signal T. Further, the circuit may have an input terminal for transmitting an additional data signal AD, and the signal AD is transmitted in the same direction as the clock signal T. The circuit 1100 may have an output terminal coupled to the primary coil of the transformer 102. The primary coil may be, for example, a single primary coil P1, P2 coupled in series with each other. The first terminal 1118 of the primary coil P1 provides a first connection point of the primary coil, and the second terminal 1124 of the primary coil P2 provides a second connection point of the primary coil. The second terminal 1120 of the primary coil P1 can be coupled to the first terminal 1122 of the primary coil P2 to form a node PG between the primary coils P1 and P2. The node PG can be connected to a reference voltage.

[0115] The circuit 1100 may have a delay circuit 900, an encoder 1101, a rising edge logic circuit 1102, a falling edge logic circuit 1104, a first multiplexer circuit 1106, a second multiplexer circuit 1108, a first driver circuit 400, and a second driver circuit 400'.

[0116] The clock signal T may be applied to the delay circuit 900. The delay circuit 900 may provide a plurality of different delays to the time signal T. The relative delay between the signals may be increased by a constant delay from one signal to another. The delay circuit 900 may, for example, be combined with Fig. 9 The circuit arrangement 900 described above can be implemented in the same manner. The delay can be triggered by a rising edge or a falling edge of the clock signal T. Thus, a signal delayed by a rising edge or a falling edge of the clock signal T can be generated.

[0117] A plurality of signals with different delays may be connected as inputs to the rising edge logic circuit 1102 and the falling edge logic circuit 1104. The rising edge logic circuit 1102 may generate signals g1r to g8r at each rising edge. The signals g1r to g8r may be, for example, similar to Figure 5 Shown and combined Figure 5 However, the rising edge logic circuit 1102 does not generate a signal at the falling edge. The falling edge logic circuit 1104 may generate signals g1f to g8fr at each falling edge. The signals g1f to g8f may be similar to Figure 5 Shown and combined Figure 5 However, the falling edge logic circuit 1102 does not generate a signal on the rising edge.

[0118] The rising edge logic circuit 1102 and the falling edge logic circuit 1104 can be implemented as complementary circuits to each other, that is, they have components and potentials of opposite polarity. In another embodiment, the rising edge logic circuit 1102 and the falling edge logic circuit 1104 can be used in the same manner, however, one of them will invert the multiple signals with different delays at its input.

[0119] The first multiplexer circuit 1106 may transmit the signals g1r to g8r or the signals g1f to g8f to the first driver circuit 400, as the signals g1 to g8, according to the signal SE provided by the encoder 1101. Similarly, the second multiplexer circuit 1108 may transmit the signals g1f to g8f or the signals g1r to g8r to the second driver circuit 400', as the signals g1' to g8', according to the signal SE provided by the encoder 1101.

[0120] The first driver circuit 400 and the second driver circuit 400′ may be as follows Figure 4 Shown and combined Figure 4 The same applies as described above. They can share a set of resistors, as described above. The first output terminal 1110 of the first driver circuit 400 and the second output terminal 1116 of the second driver circuit 400' can be coupled to the first connection point 1118 of the primary coil. The second output terminal 1112 of the first driver circuit 400 and the first output terminal 1114 of the second driver circuit 400' can be coupled to the second connection point 1124 of the primary coil.

[0121] The additional data AD may need to be synchronized with the clock signal T so that it does not interfere with the signal generated by the clock signal T, for example Figure 5 The signal ADsync (eg a delayed clock signal with a delay at least as long as the longest signal delay provided by the delay circuit 900 ) can be used for synchronization. This synchronization occurs in the encoder 1101 .

[0122] In the case where no additional data AD is to be transmitted, the signal SE may have a first value for controlling the first multiplexer circuit 1106 and the second multiplexer circuit 1108. The signals g1r to g8r may be transmitted to the first driver 400 through the first multiplexer circuit 1106 as the signals g1 to g8. The signals g1f to g8f may be transmitted to the first driver 400' through the second multiplexer circuit 1108 as the signals g1' to g8'.

[0123] At each rising edge of the clock signal T, the first driver circuit 400 can provide a signal to the primary coils P1 and P2. Figure 5 Shown and combined Figure 5 504 and 506. At each falling edge of the clock signal T, the second driver circuit 400' can provide a signal to the primary coils P1 and P2. The signal is as follows: Figure 5 Shown and combined Figure 5 504 and 506. In other words, when no additional data AD is transmitted, adjacent pulses transmitted across transformer 102 may have staggered polarities.

[0124] In the case where additional data AD is to be transmitted, the signal SE provided by the decoder may have a second value for controlling the first multiplexer circuit 1106 and the second multiplexer circuit 1108, so that when data is transmitted, the signals g1f to g8f are used as inputs to the first multiplexer circuit 1106, and the signals g1r to g8r are used as inputs to the second multiplexer circuit 1108. In other words, the falling edge of the clock signal T may result in the output of the first driver 400, while the rising edge of the clock signal T will result in the output of the second driver 400'.

[0125] The encoder 1101 can encode the additional data AD in various ways. In the first example, after the rising edge of the additional data AD occurs, only one rising edge of the clock signal T can be reversed in polarity at the primary coil by passing the transmission signals g1r to g8r through the second multiplexer circuit 1108. After the falling edge of the additional data AD occurs, only one falling edge of the clock signal T can be reversed in polarity in the primary coil by passing the transmission signals g1f to g8f through the first multiplexer circuit 1106. The encoder 1101 can output a corresponding signal SE according to the additional data AD for controlling the first multiplexer circuit 1106 and the second multiplexer circuit 1108.

[0126] In the second example, if the first value, such as "0", is used as the additional data AD of the encoder 1101, the polarity of the pulses corresponding to the rising and falling edges of the clock signal T is not reversed. If the second value, such as "1", is used as the additional data AD of the encoder 1101, the polarity of every Nth pulse is reversed. "N" can be an integer. The integer can be greater than 2, that is, N>2. At this time, adjacent pulses have enough time to stagger polarity so that the transmission of the clock signal T can be detected. For example, "N" is 8.

[0127] Fig.12 An embodiment 1200 of a circuit for decoding a clock signal and an additional signal is shown, which signal may be transmitted across a transformer 102, for example. The circuit 1200 may have an input terminal coupled to a secondary coil of the transformer 102. The secondary coil may be, for example, a single secondary coil S1, S2 coupled in series with each other. A first end 1202 of the secondary coil S1 provides a first connection point of the secondary coil, and a second end 1208 of the secondary coil S2 provides a second connection point of the secondary coil. The second end 1204 of the secondary coil S1 may be coupled to a first end 1206 of the secondary coil S2 to form a node SG between the secondary coils S1, S2. The node SG may be connected to a reference voltage, such as a ground voltage. The circuit 1200 may be equivalent to the following. Figure 2 The receiving circuit shown has an output terminal for a clock signal t and an additional output terminal for an additional data signal ad.

[0128] The circuit 1200 may have a first comparator 1210, a second comparator 1213, a first counter 1218, a second counter 1230, a first OR gate 1242, a second OR gate 1244, a storage element such as a flip-flop 1246, and a decoder 1248. The storage element may output a clock signal t. The decoder 1248 may output an additional data signal ad.

[0129] The first connection point 1202 of the secondary coil is connected to the positive input 1211 of the first comparator 1210 and the negative input 1215 of the second comparator 1213. The second connection point 1208 of the secondary coil is connected to the negative input 1212 of the first comparator 1210 and the positive input 1214 of the second comparator 1213. The first comparator 1210 and the second comparator 1213 are equivalent to Figure 7 Shown and combined Figure 7 Comparator 706 is described.

[0130] The output terminal K3p of the first comparator 1210 can be connected to the clock input terminal 1220 of the first counter 1218 and the reset input terminal 1232 of the second counter 1230. The output terminal K3n of the second comparator 1213 can be connected to the reset input terminal 1222 of the first counter 1218 and the clock input terminal 1234 of the second counter 1230.

[0131] The first counter 1218 and the second counter 1230 may have first outputs 1224, 1236, second outputs 1226, 1238, and third outputs 1228, 1240, respectively. The counters 1218, 1230 may be configured as follows: a first pulse at a clock input 1220, 1234 generates a pulse at the first output 1224, 1236. A second pulse at the clock input 1220, 1234 generates a pulse at the second output 1226, 1238. A third pulse and subsequent pulses at the clock input 1220, 1234 generate corresponding pulses at the third output 1228, 1240.

[0132] The first OR gate 1242 has three input terminals, which are respectively connected to the first output terminal 1224, the third output terminal 1228 of the first counter 1218, and the second output terminal 1238 of the second counter 1230. The second OR gate 1244 has three input terminals, which are respectively connected to the first output terminal 1236, the third output terminal 1240 of the second counter 1230, and the second output terminal 1226 of the first counter 1218.

[0133] The output of the first OR gate 1242 may be connected to the set input S of the flip-flop 1246. The output of the second OR gate 1244 may be connected to the reset input R of the flip-flop 1246. The flip-flop 1246 may have an output terminal for generating a clock signal t. The clock signal t is equivalent to Fig.11 The clock signal T transmitted on the primary coil of the transformer 102 is shown. The trigger 1246 can be used, for example, as Figure 7 Shown and combined Figure 7 A storage element 708 is depicted.

[0134] The decoder 1248 may have two input terminals, one of which may be connected to the second output terminal 1226 of the first counter 1218 , and the other of which may be connected to the second output terminal 1238 of the second counter 1230 .

[0135] In the case where no additional data AD is transmitted, the transformer 102 can transmit adjacent pulses with opposite polarity, see also Fig.11Description. A positive pulse can be detected as an output of the first comparator 1210. The output K3p can cause the first counter 1218 to output a pulse at its first output terminal 1224 and reset the second counter 1230. A negative pulse can be detected as an output K3n of the second comparator 1213. The output K3n can cause the second counter 1230 to output a pulse at its first output terminal 1236 and reset the first counter 1218. In other words, in the absence of attachment data AD being transmitted, pulses are alternately output at the first output terminals 1224, 1236 of the counters 1218, 1230. The flip-flop 1246 can be switched at each pulse transmission. In other words, the counters 1218, 1230 and the OR gates 1242, 1244 can be considered transparent, and the circuit 1200 can be used as Figure 7 Shown and combined Figure 7 Runs as described.

[0136] In the case where additional data AD is transmitted, two pulses of the same polarity may be connected and transmitted across the transformer 102. At this time, one of the counters 1218, 1230 will continue to count as if it is not reset by the positive pulse. If the additional data is transmitted correctly, a pulse polarity is reversed at this time, and a third pulse with the same polarity will follow the previous two pulses. After the third pulse, a pulse with opposite polarity will follow, which can reset the corresponding counter. Therefore, the first and second counters 1218, 1230 usually count no more than 3. The flip-flop 1246 can continue to switch when each pulse is transmitted, because the second pulse is associated with one of the input terminals R, S of the flip-flop 1246 through one of the OR gates 1244, 1242, and the first and second pulses are associated with the other of the input terminals S, R of the flip-flop 1246 through the other of the OR gates 1242, 1244.

[0137] The flip-flop 1246 can be switched at each pulse transmission, independent of the transmission of the additional data AD, so that the clock signal t is still generated when only a few single pulses are inverted. Further, the flip-flop 1246 will no longer be continuously in the wrong state even if the count is missed (for example, the polarity of more than one pulse is inverted).

[0138] Decoding of the transmitted additional data may depend on the encoding method of the additional data AD. Fig.11In the first example described, after the rising edge of the additional data AD appears, only one rising edge of the clock signal T is reversed in polarity, and after the falling edge of the additional data AD appears, only one falling edge of the clock signal T can be reversed in polarity, and the second output terminals 1226 and 1238 of the counters 1218 and 1230 can be directly connected to the two input terminals R and S of the second flip-flop. The additional data ad can be obtained from the output terminal of the second flip-flop. In this case, the decoder 1248 can include the second flip-flop (or storage element).

[0139] In a second example, where the polarity of every Nth pulse is used to transmit a "1", the second counter output terminals 1226, 1238 may be an "OR" output and applied to the clock input terminal of the additional counter. The decoder 1248 may include the additional counter. The additional counter may then count the pulses of the first output terminals 1224, 1236 of the counters 1218, 1230. Since the pulses of the second and third counter output terminals 1226, 1228 and 1238, 1240 are not counted, the additional counter is reset once the count reaches N-2. If the second counter output terminals 1226, 1238 provide more pulses, the additional counter does not need to be reset.

[0140] As another example, an additional counter may count the decoded pulses at the clock output t and be reset after the count reaches N / 2.

[0141] Although the present invention has been described and illustrated in detail with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made to the present invention without departing from the spirit and scope of the present invention as defined by the attached clauses. The scope of the present invention is therefore defined by the attached clauses, and all changes in meaning and scope equivalent to the clauses are included within the scope of the present invention.

[0142] Alternatively and / or additionally, the scope of the present disclosure specifically includes, but is not limited to, at least the embodiments described in the following enumerated clauses. Similar contents are also explicitly included in the present invention.

[0143] 1. A transformer device for signal transmission, the transformer device comprising:

[0144] at least one transformer including a primary coil and a secondary coil; and

[0145] A controller configured to:

[0146] During a magnetization phase, the first current flowing through the primary coil is controlled to increase until a predetermined standard is reached, wherein the magnetization phase is longer than one of the following:

[0147] A time constant of said primary coil of said at least one transformer; and

[0148] twice the time constant of the primary coil of the at least one transformer;

[0149] In a voltage application phase, a voltage is applied to the at least one transformer to cause a second current to flow through the primary coil, wherein the second current has a polarity that changes during the voltage application phase relative to the first current, wherein the voltage application phase is shorter than one of the following:

[0150] twice the time constant of the primary coil of the at least one transformer; and

[0151] The time constant of the primary coil of the at least one transformer.

[0152] 2. A transformer device as described in clause 1,

[0153] The controller is further configured to, during a demagnetization phase, control the third current flowing through the primary coil to decrease, wherein the demagnetization phase is longer than one of the following:

[0154] said time constant of said primary coil of said at least one transformer; and

[0155] twice the time constant of the primary coil of the at least one transformer

[0156] 3. A transformer device as described in clauses 1 to 2,

[0157] The controller is configured to gradually increase the first current flowing through the primary coil of the at least one transformer.

[0158] 4. A transformer device as described in clauses 1 to 3,

[0159] Wherein the at least one transformer is a coreless transformer.

[0160] 5. The transformer device according to clauses 1 to 4, further comprising:

[0161] A circuit coupled to the controller, the circuit comprising a plurality of branch circuits connected in parallel;

[0162] Each branch circuit includes a switch and a resistor connected in series;

[0163] A first end of each branch circuit is coupled to a reference voltage, and a second end of each branch circuit is coupled to the at least one transformer.

[0164] 6. A transformer device as claimed in clause 5,

[0165] The controller is configured to open all switches before the magnetization phase begins.

[0166] 7. A transformer device as described in clauses 5 to 6,

[0167] The controller is configured to close the first set of switches one by one during the magnetization phase to gradually increase the current.

[0168] 8. A transformer device as described in clause 7,

[0169] The controller is configured to open the first set of switches and close the second set of switches during the voltage application phase.

[0170] 9. A transformer device as claimed in clause 8,

[0171] The controller is configured to turn off the second set of switches one by one during the demagnetization phase to gradually reduce the current.

[0172] 10. A transformer device as claimed in clauses 5 to 9,

[0173] The controller is configured to turn off all switches after the demagnetization phase is terminated.

[0174] 11. A transformer device as claimed in clauses 5 to 10,

[0175] The resistance of at least some of the resistors is greater than the resistance of the primary coil.

[0176] 12. A transformer device as claimed in clause 11,

[0177] The resistance of at least a portion of the resistors is in a range of about 10 ohms to about 1000 ohms.

[0178] 13. A transformer device as described in clauses 11 to 12,

[0179] Wherein the resistance of the primary coil is in a range of about 1 ohm to about 50 ohms.

[0180] 14. A transformer device as claimed in clauses 1 to 13,

[0181] wherein the at least one transformer comprises a plurality of transformers, each transformer of the plurality of transformers comprises a primary coil and a secondary coil;

[0182] wherein the primary coils of the plurality of transformers are connected in series; and

[0183] The node between the primary coils is connected to a reference voltage.

[0184] 15. A transformer device as claimed in clause 14,

[0185] The reference voltage is approximately half of the power supply voltage.

[0186] 16. A transformer device as claimed in clauses 1 to 15,

[0187] The controller is further configured to make the magnetization phase one of the following:

[0188] in the range of about 5 ns to about 30 ns;

[0189] in the range of about 7 ns to about 20 ns;

[0190] In the range of about 9 ns to about 15 ns; and

[0191] About 10ns.

[0192] 17. A transformer device as claimed in clauses 1 to 16,

[0193] The controller is further configured to make the voltage application phase one of the following:

[0194] in the range of about 0.5 ns to about 6 ns;

[0195] in the range of about 1 ns to about 4 ns; and

[0196] In the range of about 2ns to about 3ns.

[0197] 18. A transformer device as claimed in clauses 2 to 17,

[0198] The controller is further configured to make the duration of the demagnetization phase one of:

[0199] in the range of about 5 ns to about 30 ns;

[0200] In the range of about 7 ns to about 20 ns;

[0201] In the range of about 9 ns to about 15 ns; and

[0202] About 10ns.

[0203] 19. A transformer device as claimed in clauses 1 to 18,

[0204] The time constant of the primary coil of the at least one transformer is one of the following:

[0205] In the range of about 1 ns to about 10 ns;

[0206] In the range of about 2 ns to about 6 ns; and

[0207] In the range of about 3ns to about 4ns.

[0208] 20. A transformer device according to any one of clauses 5 to 19, further comprising:

[0209] another circuit coupled to the controller, the another circuit comprising a plurality of branch circuits connected in parallel;

[0210] Each branch circuit includes a switch and a resistor connected in series;

[0211] A first end of each branch circuit is coupled to a reference voltage, a second end of each branch circuit is coupled to the at least one transformer, and the another circuit is connected to the transformer with a polarity opposite to that of the another circuit.

[0212] 21. A transformer device as claimed in clause 20,

[0213] The branch circuit of the circuit and the branch circuit of the other circuit share their corresponding resistors.

[0214] 22. A transformer device according to clause 20 or 21,

[0215] The switches of the branch circuit of the circuit and the branch circuit of the other circuit are arranged symmetrically to each other.

[0216] 23. A transformer device as claimed in clauses 20 to 22,

[0217] The switches of the circuit and the branch circuits of the other circuit are controlled by the same control signal.

[0218] 24. A transformer device as claimed in clauses 20 to 23,

[0219] The resistance of all resistors is equal.

[0220] 25. A circuit device comprising:

[0221] a first comparator circuit having a first comparator threshold;

[0222] a second comparator circuit having a second comparator threshold;

[0223] a third comparator circuit having a third comparator threshold;

[0224] A control circuit configured to:

[0225] adjusting the first comparator threshold so that the first comparator circuit is in a first comparator output state for a first time period in a predefined time interval, adjusting the second comparator threshold so that the second comparator circuit is in the first comparator output state for a second time period in the predefined time interval, wherein the second time period is longer than the first time period, and

[0226] The third comparator threshold is set between the first comparator threshold and the second comparator threshold.

[0227] 26. A circuit arrangement as claimed in clause 25,

[0228] At least one of the first time period and the second time period is a sum of a plurality of sub-time periods.

[0229] 27. The circuit arrangement of clause 25 or 26, further comprising:

[0230] at least one transformer including a primary coil and a secondary coil;

[0231] The first comparator circuit, the second comparator circuit and the third comparator circuit are coupled to the secondary coil.

[0232] 28. A circuit arrangement as claimed in any one of clauses 25 to 27,

[0233] The first comparator circuit, the second comparator circuit and the third comparator circuit are all configured to receive the same signal.

[0234] 29. A circuit arrangement as claimed in any one of clauses 25 to 28,

[0235] At least one of the first comparator circuit and the second comparator circuit is configured as a window comparator circuit.

[0236] 30. A circuit arrangement as claimed in any one of clauses 25 to 29,

[0237] Wherein the third comparator circuit is configured to provide an evaluation output signal.

[0238] 31. The circuit arrangement of clause 30, further comprising:

[0239] A storage element, coupled to the output of the third comparator circuit, is used to store the evaluation output signal.

[0240] 32. A circuit arrangement as claimed in any one of clauses 25 to 31,

[0241] The control circuit is configured as at least one of the following:

[0242] adjusting the first threshold based on an output signal provided by the first comparator circuit; and

[0243] The second threshold is adjusted based on an output signal provided by the second comparator circuit.

[0244] 33. A circuit arrangement according to clause 32,

[0245] The control circuit is configured as at least one of the following:

[0246] adjusting the first threshold based on a time-based evaluation of an output signal provided by the first comparator circuit; and

[0247] The second threshold is adjusted based on a time-based evaluation of an output signal provided by the second comparator circuit.

[0248] 34. A circuit arrangement as claimed in any one of clauses 25 to 33,

[0249] The control circuit is configured as at least one of the following:

[0250] adjusting the first threshold value based on an output signal provided by the first comparator circuit, wherein a first signal state of the output signal and a second signal state of the output signal are weighted in different ways; and

[0251] The second threshold value is adjusted based on an output signal provided by the second comparator circuit, wherein a first signal state of the output signal and a second signal state of the output signal are weighted in different ways.

[0252] 35. A circuit arrangement according to clause 33 or 34,

[0253] The control circuit is configured as at least one of the following:

[0254] adjusting the first threshold based on an average value of an output signal provided by the first comparator circuit; and

[0255] The second threshold is adjusted based on an average value of an output signal provided by the second comparator circuit.

[0256] 36. A transformer device for signal transmission, the transformer device comprising:

[0257] at least one transformer including a primary coil and a secondary coil;

[0258] The transformer device has a resonant frequency;

[0259] a controller configured to terminate driving the primary coil so that the transformer device oscillates at the resonant frequency;

[0260] A switching circuit is coupled to the secondary winding and is configured to oscillate the transformer device in a first switching state and to reduce the oscillation of the transformer device in a second switching state.

[0261] 37. A transformer device as claimed in clause 36,

[0262] Wherein driving the primary coil comprises at least one of the following:

[0263] Magnetization stage;

[0264] demagnetization phase; and

[0265] Voltage application stage.

[0266] 38. A transformer device according to clause 36 or 37, further comprising:

[0267] After a certain period of time has passed after the driving of the primary coil is terminated, the primary coil is driven.

[0268] 39. A transformer device according to any one of clauses 36 to 39, further comprising:

[0269] An amplitude detection circuit is coupled to the primary coil.

[0270] 40. A transformer device as claimed in clause 39,

[0271] The specific time period is selected to be long enough to reduce the oscillation if the switching circuit is in the second switching state, and long enough that a reduction in the oscillation amplitude can be detected in the amplitude detection circuit.

[0272] 41. A transformer arrangement according to clauses 38 to 40, wherein:

[0273] The time period during which the switch circuit is in the second switch state is shorter than the specific time period before starting to drive the coil.

[0274] 42. A transformer device as claimed in any one of clauses 36 to 41,

[0275] Wherein the at least one transformer is a coreless transformer.

[0276] 43. A transformer device as claimed in any one of clauses 37 to 42,

[0277] The magnetization directions of the primary coil stages in which the primary coil is driven consecutively have opposite polarities.

[0278] 44. A transformer arrangement according to clauses 37 to 42, wherein:

[0279] For a certain number of consecutive driving stages of the primary coil, the magnetization directions of the consecutive driving stages of the primary coil have the same polarity.

[0280] 45. A transformer device as claimed in any one of clauses 38 to 44,

[0281] One bit of data is transmitted by detecting whether the oscillation decreases during the specific period before starting to drive the coil.

[0282] 46. ​​A circuit device comprising:

[0283] A first signal delay circuit, comprising a first element controlled by a process variable, wherein the first element affects a signal delay time of the first signal delay circuit;

[0284] a second signal delay circuit comprising a second element controlled by the same process variable, wherein the second element affects a signal delay time of the second signal delay circuit;

[0285] wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed;

[0286] wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit;

[0287] The degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit is smaller than the degree of influence of the process variable of the first element on the signal delay time of the first signal delay circuit.

[0288] 47. A circuit arrangement according to clause 46,

[0289] wherein the degree of influence of the process variable of the first element on the signal delay time of the first signal delay circuit is inversely proportional to the influence of the first element on the signal delay time of the first signal delay circuit; and

[0290] The degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit is inversely proportional to the influence of the second element on the signal delay time of the second signal delay circuit.

[0291] 48. A circuit arrangement according to clause 46 or 47, wherein:

[0292] The first element comprises a first resistor; and

[0293] The second element comprises a second resistor;

[0294] wherein the first resistor and the second resistor have different resistor widths;

[0295] The first resistor and the second resistor have the same nominal resistance value.

[0296] 49. A circuit arrangement as claimed in any one of clauses 46 to 48,

[0297] wherein the first signal delay circuit further comprises a first capacitor having a first capacitance;

[0298] wherein the second signal delay circuit further comprises a second capacitor having a second capacitance;

[0299] The second capacitor is different from the first capacitor.

[0300] 50. A circuit arrangement according to clause 49,

[0301] The second capacitance is higher than the first capacitance.

[0302] 51. The circuit arrangement of clauses 46 to 50, further comprising:

[0303] a third signal delay circuit comprising a third element controlled by the same process variable, wherein the third element affects the signal delay time of the third signal delay circuit;

[0304] The degree of influence of the process variable of the third element on the signal delay time of the third signal delay circuit is smaller than the degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit.

[0305] 52. A circuit arrangement as claimed in any one of clauses 46 to 51,

[0306] wherein the first signal delay circuit comprises a plurality of sub-delay circuits connected in series, each sub-delay circuit comprises a first element and a signal inverter; and

[0307] The second signal delay circuit includes a plurality of sub-delay circuits connected in series, and each sub-delay circuit includes a second element and a signal inverter.

[0308] 53. A pulse generating circuit device, comprising:

[0309] a pulse generating circuit configured to provide a pulse; and

[0310] A circuit device comprising:

[0311] A first signal delay circuit, comprising a first element controlled by a process variable, wherein the first element affects a signal delay time of the first signal delay circuit;

[0312] A second signal delay circuit, comprising a second element controlled by the same process variable, wherein the second element affects the signal delay time of the second signal delay circuit;

[0313] wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed;

[0314] wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit;

[0315] wherein the degree of influence of the process variable of the second element on the signal delay time of the second signal delay circuit is smaller than the degree of influence of the process variable of the first element on the signal delay time of the first signal delay circuit;

[0316] The pulse generating circuit is configured to provide the pulse so that the pulse is started by the signal provided by the first signal delay circuit and the pulse is terminated by the signal provided by the second signal delay circuit.

[0317] 54. A circuit arrangement according to clause 53,

[0318] The signal delay time is proportional to the lateral size of the resistor.

[0319] 55. A method for transmitting data in a clock signal transmission direction,

[0320] wherein the rising edge and the falling edge of the clock signal are transmitted via pulses with different polarities;

[0321] Wherein when no data is transmitted, the polarity of the pulses is not inverted; and wherein when data is transmitted, the polarity of at least one of the pulses is inverted.

[0322] 56. The method of clause 55, further comprising:

[0323] The presence of data transmission is detected by detecting whether the pulse has an unexpected polarity, which step includes detecting whether consecutive pulses have the same polarity.

[0324] 57. The method as described in clause 55,

[0325] When data is transmitted, only the polarity of every Nth pulse is reversed;

[0326] Where N is one of the following:

[0327] Greater than 2;

[0328] is equal to 5;

[0329] is equal to 8; and

[0330] Equals 16.

[0331] 58. A method as described in clauses 55 to 57,

[0332] The polarity is reversed only once after the rising edge of the data, and the polarity is reversed only once again after the falling edge of the data.

[0333] 59. A method as described in clauses 55 to 58,

[0334] The data is at least one of the following:

[0335] Configuration information of the converter;

[0336] A signal to the converter to start conversion; and

[0337] Calibration information.

Claims

1. A method for transmitting data in a clock signal transmission direction, When no data is transmitted, transmitting a pulse having a first polarity at a rising edge of the clock signal, and transmitting a pulse having a second polarity at a falling edge of the clock signal, wherein the first polarity is opposite to the second polarity; and When data is transmitted, the first polarity is inverted to the second polarity at the rising edge of the clock signal, or the second polarity is inverted to the first polarity at the falling edge of the clock signal.

2. The method of claim 1, further comprising: Detecting when data is being transmitted is done by detecting whether a pulse has an unexpected polarity, which includes detecting whether consecutive pulses have the same polarity.

3. The method according to claim 1, When data is transmitted, only the polarity of every Nth pulse is reversed; Where N is one of the following: Greater than 2; is equal to 5; is equal to 8; and Equals 16.

4. The method according to claim 1, The polarity is reversed only once after the rising edge of the data, and the polarity is reversed only once again after the falling edge of the data.

5. The method according to claim 1, The data is at least one of the following: Configuration information of the converter; A signal to the converter to start conversion; and Calibration information.

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