A split-gate MOSFET structure with reduced VF and a manufacturing method thereof

Abstract

The present invention provides a split-gate MOSFET structure with reduced VF, wherein a parasitic MOS diode structure is formed by using a polycrystalline gate electrode three, a gate oxide layer three, an N+ structure, an N-epitaxial layer, a P-well region and a source metal layer on the upper part, so that the reverse voltage drop VF of the parasitic MOS diode of the device is greatly reduced from a common 0.8V or more to 0.5-0.7V; at the same time, the cross-frequency characteristics of the split-gate MOSFET are greatly improved, especially in application occasions with relatively high reverse freewheeling requirements, the conversion efficiency is significantly improved, and the application field thereof is broadened.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of power semiconductor devices, and in particular to a separated gate MOSFET structure for reducing VF and a manufacturing method thereof. Background Art

[0002] As a type of power device, power MOSFET has been increasingly widely used in recent years. As an upgraded structure of the ordinary trench structure, the split-gate MOSFET has a lower on-resistance per unit area and a lower capacitance parameter per unit area. This further reduces the conduction and switching losses of the power MOSFET, greatly improves the current handling capacity per unit area, broadens the application range of MOSFET in the field of high current and high frequency, and further increases the demand for power MOSFET in recent years.

[0003] In many circuits, MOSFET is usually used in power conversion applications. Such applications require that the power MOSFET must have good cross-frequency characteristics, that is, the voltage drop VF of the parasitic body diode of the MOSFET must be low enough. Due to the work function characteristics of the PN junction, the VF value of the parasitic body diode will be above 0.7V, usually around 0.8V, while the VF values ​​of some low VF diodes or Schottky diodes are all below 0.7V.

[0004] In order to improve the cross-frequency characteristics of MOSFET, the early method of using a single power MOSFET device in parallel with a power Schottky diode device with a relatively lower VF was often used, such as Figure 1-2 As shown, Figure 1 The figure shows the structure of the existing common split gate product. Figure 2 The schematic diagram of parallel diodes is shown in Figure 1. Figure 2 The 104 mark is the Schottky diode, and the 102 mark is the MOS parasitic body diode. Some manufacturers also package the power MOS chip and the Schottky chip in parallel in an integrated block for use. These methods are effective, but have disadvantages such as low chip integration, complex manufacturing process, and high cost. Summary of the invention

[0005] Purpose of the Invention

[0006] The present invention provides a separated gate MOSFET structure capable of reducing VF and having high chip integration, simple manufacturing process and low cost, and a manufacturing method thereof.

[0007] Technical Solution

[0008] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a separated gate MOSFET structure with reduced VF, comprising an N+ substrate layer, an N-epitaxial layer is arranged on the N+ substrate layer, a groove is opened on the N-epitaxial layer, the groove is respectively provided with a gate oxide layer 1 and a gate oxide layer 2 along the vertical direction from the bottom to the top, the gate oxide layer 1 and the gate oxide layer 2 are respectively wrapped with a polycrystalline gate 1 and a polycrystalline gate 2, the top of the groove is provided with a gate oxide layer 3 on both sides, and a polycrystalline gate 3 is arranged on the gate oxide layer 3; wherein the sidewalls on both sides of the groove are provided with a P-well region, the P-well region is wrapped with an N+ structure, the N+ structure is directly connected to the source metal layer, and the source metal layer is arranged on the top of the polycrystalline gate 3. A drain metal layer is provided at the bottom of the N+ substrate layer.

[0009] Furthermore, a dielectric layer is provided on the top of the trench, and the dielectric layer separates the second polycrystalline gate and the source metal layer.

[0010] A method for manufacturing a split-gate MOSFET structure comprises the following steps:

[0011] manufacturing a substrate, and forming a groove on the substrate;

[0012] A gate oxide layer 1 and a polycrystalline gate 1 are formed in the trench, and the gate oxide layer 1 completely wraps the polycrystalline gate 1; a gate oxide layer 2 is formed by thermal oxidation in the trench, polycrystalline silicon is deposited in the trench and etched to form a polycrystalline gate 2; an oxide layer is deposited, and the trench is filled with the oxide layer, and the surface of the obtained product is smoothed by a CMP method; a gate oxide layer is formed by thermal oxidation, polycrystalline silicon is deposited on the gate oxide layer, and a gate oxide layer 3 and a polycrystalline gate 3 are formed by photolithography exposure; a P-well region and an N+ structure are formed on the side walls on both sides of the trench, so that the P-well region completely wraps the N+ structure to obtain a semi-finished product; a metal on the front side of the semi-finished product is deposited to form a source metal, and a metal on the back side of the semi-finished product is deposited to form a drain metal, and the source metal is in contact with the N+ structure to complete the production.

[0013] Furthermore, the steps of manufacturing a substrate and forming a groove 3 on the substrate are as follows:

[0014] An N-epitaxial layer is grown on the N+ substrate layer, and a trench etch barrier layer is formed by etching the N-epitaxial layer using a trench photolithography method; under the action of the trench etch barrier layer, the N-epitaxial layer is etched to form a deep trench.

[0015] Furthermore, a gate oxide layer 1 and a polycrystalline gate 1 are formed in the trench, and the gate oxide layer 1 completely wraps the polycrystalline gate 1. The specific steps are as follows: thermal oxidation or deposition forms a thick gate oxide layer in the trench; polycrystalline silicon is deposited in the trench; the polycrystalline silicon is etched, and the remaining polycrystalline silicon in the trench forms a polycrystalline gate 1; the thick gate oxide layer is etched away, so that the oxide layer is slightly lower than the top of the polycrystalline gate 1; the oxide layer is deposited by HDP method, and the trench is completely filled with the oxide layer; the oxide layer formed on the upper part of the trench by HDP deposition and a part of the oxide layer inside the trench are etched away to ensure that the oxide layer completely wraps the polycrystalline gate 1. This oxide layer is the gate oxide layer 1, which is isolated from the polycrystalline gate 2 above.

[0016] Furthermore, a gate oxide layer three and a polycrystalline gate three are formed by photolithography exposure, and the polysilicon and the oxide layer are etched using the photoresist as a barrier.

[0017] Furthermore, a P-well region and an N+ structure are formed on the side walls of both sides of the trench, so that the P-well region completely wraps the N+ structure. The specific steps are as follows: B ions are injected into the N-epitaxial layer, and then AS ions are injected, and the photoresist is removed; a high-temperature well is used to form a P-well region and an N+ structure. B ions are relatively light, and the P-well diffusion area is much larger than the N+, so that the P-well region completely wraps the N+ structure.

[0018] Beneficial Effects

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention provides a separated gate MOSFET structure with reduced VF. The principle of super barrier rectifier SBR is introduced on the basis of ordinary separated gate MOSFET. A parasitic MOS diode structure is formed by using the upper polycrystalline gate three, gate oxide layer three, N+ structure, N-epitaxial layer, P well region and source metal, so that the reverse voltage drop VF of the parasitic MOS diode of the device is greatly reduced from the ordinary 0.8V or more to 0.5-0.7V.

[0021] At the same time, the cross-frequency characteristics of the split-gate MOSFET are greatly improved, especially in applications where the reverse freewheeling requirements are relatively high, the conversion efficiency is significantly improved, and its application field is broadened.

[0022] It should be understood that the above general description and the following detailed description are merely exemplary and illustrative and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings are part of the specification of the present invention, and illustrate exemplary embodiments of the present invention. Together with the description of the specification, the accompanying drawings are used to explain the principles of the present invention.

[0024] Figure 1It is a schematic diagram of the structure of existing separation gate products;

[0025] Figure 2 It is a schematic diagram of the existing parallel diode diagram;

[0026] Figure 3 It is a schematic diagram of the structure of the present invention;

[0027] Figure 4 This is a schematic diagram of the current direction when the present invention is forward-conducting;

[0028] Figure 5 This is a schematic diagram of the current direction during reverse VF operation of the present invention;

[0029] Figure 6-20 The invention manufactures Figure 3 Schematic diagram of the various processes of the device shown.

[0030] Reference numerals

[0031] 1-N+ substrate layer; 2-N-epitaxial layer; 3-trench; 4-gate oxide layer one; 5-gate oxide layer two; 6-polycrystalline gate one; 7-polycrystalline gate two; 8-gate oxide layer three; 9-polycrystalline gate three; 10-P well region; 11-N+ structure; 12-source metal layer; 13-drain metal layer; 14-trench etching barrier layer; 15-photoresist; 16-dielectric. DETAILED DESCRIPTION

[0032] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0033] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to those skilled in the art. The present application description and examples are exemplary only.

[0034] Embodiment 1: Refer to the attached Figure 3A split-gate MOSFET structure for reducing VF, comprising an N+ substrate layer 1, an N-epitaxial layer 2 is arranged on the N+ substrate layer 1, a groove 3 is opened on the N-epitaxial layer 2, the groove 3 is respectively provided with a gate oxide layer 4 and a gate oxide layer 5 in a vertical direction from bottom to top, the gate oxide layer 4 and the gate oxide layer 5 are respectively wrapped with a polycrystalline gate 1 6 and a polycrystalline gate 2 7, gate oxide layers 3 8 are arranged on both sides of the top of the groove 3, and a polycrystalline gate 3 9 is arranged on the gate oxide layer 3 8; wherein the sidewalls on both sides of the groove 3 are provided with a P well region 10, the P well region 10 is wrapped with an N+ structure 11, the N+ structure 11 is directly connected to a source metal layer 12, the source metal layer 12 is arranged on the top of the polycrystalline gate 3 9, and a drain metal layer 13 is arranged at the bottom of the N+ substrate layer 1.

[0035] A dielectric layer 16 is disposed on the top of the trench 3 , and the dielectric layer 16 separates the polycrystalline gate 2 7 from the source metal layer 12 .

[0036] Specifically, in this embodiment, refer to the attached Figure 1 and attached Figure 3 In order to make MOSFET have better cross-frequency characteristics and solve the problem of too large reverse VF value, the present invention introduces a new structure. The main changes compared with the existing structure are as follows:

[0037] The polycrystalline gate in the trench of the common separation gate is divided into three, and a polycrystalline gate three 9 and a gate oxide layer three 8 in the horizontal direction are added;

[0038] The dielectric layer 16 is formed on the top of the trench 3, not higher than the silicon surface, and the source metal layer 12 is directly in contact with the N+ structure 11; the P well region 10 is separated on both sides of the side wall of the trench 3;

[0039] Thus, the functions of the polycrystalline gate 1 6 and the polycrystalline gate 2 7 are the same as those of ordinary split-gate MOSFETs, while the upper polycrystalline gate 3 9, the gate oxide layer 3 8, the P-well region 10, the N+ structure 11 and the source metal layer 12 together form a new MOS diode structure, in which the channel is in the horizontal direction, and the super-barrier rectifier principle is used to reduce the parasitic MOS diode VF value of the device.

[0040] The polysilicon gate 2 7 is the gate of the split-gate MOSFET device; the polysilicon gate 1 6 is connected to the source metal of the split-gate MOSFET device to form a complete split-gate MOSFET structure; the polysilicon gate 3 9 is the gate of the parasitic MOS diode to achieve low VF;

[0041] Specifically, the VF value of ordinary MOS depends on the PN junction. The potential barrier of silicon PN junction is about 0.7V. Add some contact voltage drop, and the VF value of general MOSFET is about 0.8V. After adopting this new structure, its VF value depends on the parasitic MOS diode turn-on voltage of the MOS diode. This turn-on voltage is about 0.4V when the gate oxide is relatively thin (10nm).

[0042] Working principle: When a positive bias voltage is applied between the drain and the source, the MOSFET is in a reverse cutoff state, and the P-well regions 10 on both sides and the two adjacent trenches 3 are completely depleted to form a depletion layer withstand voltage structure. At this time, the device is a normal split-gate MOSFET, and the on-off of the MOS is controlled by the voltage difference between the gate and the source. The channel is in the vertical direction, such as Figure 3 As shown;

[0043] When a reverse bias is applied between the drain and the source, for the MOS region formed by the super-barrier rectifier, its source and drain are opposite to the source and drain of the device. Since the source of the device is short-circuited with the gate metal, that is, the drain and gate of the parasitic MOS diode are short-circuited, the potential difference between the gate and the source is equal to the potential difference between the drain and the source. Since its gate oxide is thin, the turn-on voltage of the parasitic MOS diode is very low, assuming it is 0.4V, that is, when the reverse bias voltage is very low, the parasitic MOS diode begins to conduct;

[0044] Therefore, when a very low reverse bias voltage (usually less than 0.7V) is applied between the drain and source of the device, the device is turned on normally, which makes the MOSFET device have a very low body diode voltage drop VF.

[0045] Embodiment 2: Refer to the attached Figure 6-20 , a method for manufacturing a split-gate MOSFET structure, comprising the following steps:

[0046] like Figure 6 As shown, an N-epitaxial layer 2 is grown on an N+ substrate layer 1, and a trench etching stopper layer 14 is formed by etching the N-epitaxial layer 2 using a trench photolithography method;

[0047] like Figure 7 As shown, under the action of the trench etching barrier layer 14, the N-epitaxial layer 2 is etched to form a deep trench 3;

[0048] like Figure 8 As shown, a thick gate oxide layer is formed by thermal oxidation or deposition in the trench 3;

[0049] like Fig. 9 As shown, polysilicon is deposited into the trench 3;

[0050] like Fig.10 As shown, the polysilicon is etched, and the remaining polysilicon in the trench 3 forms a polycrystalline gate 6;

[0051] like Fig.11 As shown, the thick gate oxide layer is etched away so that the oxide layer is slightly lower than the top of the polycrystalline gate 6;

[0052] like Fig.12 As shown, an oxide layer is deposited by HDP method to completely fill the trench 3 with the oxide layer;

[0053] like Fig.13 As shown, the oxide layer formed by HDP deposition on the upper part of the trench 3 and a part of the oxide layer inside the trench 3 are etched away to ensure that the oxide layer completely wraps the polycrystalline gate 1 6. This oxide layer is the gate oxide layer 1 4, which is isolated from the polycrystalline gate 2 7 above.

[0054] like Fig.14 As shown, a gate oxide layer 5 is formed by thermal oxidation in the trench 3;

[0055] like Fig.15 As shown, polysilicon is deposited into the trench 3 and etched to form a polycrystalline gate 2 7;

[0056] like Fig.16 As shown, an oxide layer is deposited, at which time the oxide layer fills the groove, and the surface of the obtained product is polished by CMP, as shown in FIG. Fig.17 As shown;

[0057] like Fig.18 As shown, a gate oxide layer is formed by thermal oxidation, polysilicon is deposited on the gate oxide layer, and the polysilicon and the oxide layer are etched using photoresist as a barrier, and a gate oxide layer 3 8 and a polycrystalline gate 3 9 are formed by photolithography exposure;

[0058] like Fig.19 As shown, B ions are implanted into the N-epitaxial layer 2, and then AS ions are implanted, and the photoresist is removed;

[0059] like Fig. 20 As shown, the high temperature well push forms the P well region 10 and the N+ structure 11. The B ions are relatively light, and the P well diffusion area is much larger than the N+, so that the P well region 10 completely wraps the N+ structure 11, and a semi-finished product is obtained;

[0060] Deposit the semi-finished product front metal to form source metal, deposit the semi-finished product back metal to form drain metal, the source metal is in contact with the N+ structure 11, and the result is as follows Figure 3 The device shown is fabricated.

[0061] The above description is only an illustrative specific implementation manner of the present invention. Without departing from the concept and principle of the present invention, any equivalent changes and modifications made by those skilled in the art should fall within the scope of protection of the present invention.

Claims

1. A split-gate MOSFET structure for reducing VF, characterized in that: The invention comprises an N+ substrate layer (1), an N-epitaxial layer (2) is provided on the N+ substrate layer (1), a groove (3) is opened on the N-epitaxial layer (2), a gate oxide layer 1 (4) and a gate oxide layer 2 (5) are respectively provided in the vertical direction from the bottom to the top of the groove (3), a polycrystalline gate 1 (6) and a polycrystalline gate 2 (7) are respectively wrapped in the gate oxide layer 1 (4) and the gate oxide layer 2 (5), a gate oxide layer 3 (8) is provided on both sides of the top of the groove (3), and a polycrystalline gate 3 (9) is provided on the gate oxide layer 3 (8); Wherein, a P-well region (10) is provided on both side walls of the trench (3), an N+ structure (11) is enclosed in the P-well region (10), the N+ structure (11) is directly connected to a source metal layer (12), and the source metal layer (12) is provided on top of the polycrystalline gate three (9); A dielectric layer (16) is provided on the top of the trench (3), and the dielectric layer (16) separates the second polycrystalline gate (7) from the source metal layer (12); A drain metal layer (13) is provided at the bottom of the N+ substrate layer (1).

2. A method for manufacturing a split-gate MOSFET structure according to claim 1, characterized in that: The following steps are involved: Manufacturing a substrate and forming a groove on the substrate (3); A gate oxide layer (4) and a polycrystalline gate (6) are formed in the trench (3), wherein the gate oxide layer (4) completely wraps the polycrystalline gate (6); Thermally oxidizing the trench (3) to form a second gate oxide layer (5), depositing polysilicon in the trench (3) and etching to form a second polycrystalline gate (7); Deposit an oxide layer, which fills the grooves, and smoothes the surface of the product using CMP. Forming a gate oxide layer by thermal oxidation, depositing polysilicon on the gate oxide layer, and forming a gate oxide layer three (8) and a polycrystalline gate three (9) by photolithography exposure; Forming a P-well region (10) and an N+ structure (11) on the side walls of both sides of the trench (2), so that the P-well region (10) completely wraps around the N+ structure (11), thereby obtaining a semi-finished product; Deposit the semi-finished product front metal to form source metal, deposit the semi-finished product back metal to form drain metal, the source metal is in contact with the N+ structure (11), and the manufacturing is completed.

3. The method for manufacturing a split-gate MOSFET structure according to claim 2, wherein: The steps of manufacturing a substrate and forming a groove (3) on the substrate are as follows: Growing an N-epitaxial layer (2) on an N+ substrate layer (1), and etching the N-epitaxial layer (2) using a trench photolithography method to form a trench etching stop layer (14); Under the action of the trench etching barrier layer (14), the N-epitaxial layer (2) is etched to form a deep trench (3).

4. The method for manufacturing a split-gate MOSFET structure according to claim 2, wherein: A gate oxide layer (4) and a polycrystalline gate (6) are formed in the trench (3), wherein the gate oxide layer (4) completely wraps the polycrystalline gate (6). The specific steps are as follows: Thermally oxidizing or depositing a thick gate oxide layer in the trench (3); Depositing polysilicon into the trench (3); Etching the polysilicon, and the remaining polysilicon in the trench (3) forms a polycrystalline gate 1 (6); Etching and removing the thick gate oxide layer so that the oxide layer is slightly below the top of the polycrystalline gate 1 (6); Depositing an oxide layer using a HDP method to completely fill the trench (3) with the oxide layer; The oxide layer formed by HDP deposition on the upper part of the trench (3) and a part of the oxide layer inside the trench (3) are etched and removed to ensure that the oxide layer completely wraps the polycrystalline gate 1 (6). This oxide layer is the gate oxide layer 1 (4).

5. The method for manufacturing a split-gate MOSFET structure according to claim 2, wherein: A gate oxide layer three (8) and a polycrystalline gate three (9) are formed by photolithography exposure, and the polycrystalline silicon and the oxide layer are etched using the photoresist (15) as a barrier.

6. The method for manufacturing a split-gate MOSFET structure according to claim 2, wherein: A P-well region (10) and an N+ structure (11) are formed on the side walls of both sides of the trench (2), so that the P-well region (10) completely wraps around the N+ structure (11). The specific steps are as follows: Implanting B ions into the N-epitaxial layer (2), then implanting AS ions, and removing the photoresist; The high temperature well push-in forms a P-well region (10) and an N+ structure (11), so that the P-well region (10) completely wraps the N+ structure (11).

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