A voltage conversion circuit structure suitable for variable voltage domain

Abstract

The present invention discloses a voltage conversion circuit structure suitable for a variable voltage domain, including a first inverter, a second inverter is provided at the output end of the first inverter, a fourth transistor is also provided at the output end of the first inverter, a third transistor is provided at the output end of the second inverter, a first transistor is provided at the input end of the third transistor, a second transistor is also provided at the input end of the third transistor, and a fifth transistor is provided at the input end of the second transistor. The level conversion circuit of the present invention is composed of two groups of circuits, which respectively realize the functions of converting to the vicinity of the voltage value corresponding to the high level of the high voltage domain and converting to the vicinity of the voltage value corresponding to the low level of the high voltage domain. The voltage value of the low voltage domain and the voltage value of the high voltage domain in which the conversion circuit works can be selected relatively independently, and the difference between the high voltage and the low voltage of the high voltage domain after conversion can change with the selected current value and resistance value.

Description

Technical Field

[0001] The present invention relates to the technical field of level conversion, and more specifically, to a voltage conversion circuit structure suitable for a variable voltage domain. Background Art

[0002] The power domain of a typical mixed-analog circuit generally consists of at least two groups of voltages. The digital circuit realizes the output of "0" or "1". Considering the power consumption requirements, it is generally powered by a low voltage, such as VDD=1V. Considering the performance requirements of the analog circuit, the analog circuit is generally powered by a higher voltage, such as 1.8V and 5V. The interaction between the two groups of power domains requires the use of a level conversion circuit.

[0003] As attached Figure 5 It is a typical level conversion circuit structure, in which inverters INV1 and INV2 work in the low voltage domain, and transistors M1-M4 work in the high voltage domain. The low voltage logic controls the turn-off and turn-on of transistors M3 and M4, and the control logic in the high voltage domain is latched in the latch composed of transistors M1 and M2. The high and low voltages in the low voltage domain are VDD and GND, and the high and low voltages in the high voltage domain are VCC and VSS. When the GND voltage and the VSS voltage are equal, this structure can better complete the task of level conversion, but this structure has the following main disadvantages:

[0004] 1. When VSS is not equal to GND, the level conversion function of the structure fails;

[0005] 2. The high and low level outputs in the high voltage domain can only be VCC and VSS and cannot be changed. Summary of the invention

[0006] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a voltage conversion circuit structure suitable for a variable voltage domain, which can realize high-low level conversion when the power supply and ground voltage values ​​of the low voltage domain and the high voltage domain are completely unequal, and the voltage difference of the conversion level can be changed according to the value of the current or resistance, so as to solve the problems raised in the above-mentioned background technology.

[0007] To achieve the above-mentioned purpose, the present invention provides the following technical solution: comprising a first inverter, a second inverter is provided at the output end of the first inverter, a fourth transistor is further provided at the output end of the first inverter, a third transistor is provided at the output end of the second inverter, a first transistor is provided at the input end of the third transistor, a second transistor is further provided at the input end of the third transistor, a fifth transistor is provided at the input end of the second transistor, a current source is provided at the drain end of the fourth transistor, an output end of the current source is grounded, an input end of the first inverter is provided with an input low voltage domain voltage signal, and the first inverter is electrically connected to the input low voltage domain voltage signal, a resistor is provided at the drain end of the fourth transistor, an output end of the resistor is commonly grounded, and a circuit structure is converted to a voltage value near a voltage value corresponding to a low level in a high voltage domain, and a voltage value of a converted output voltage VOUT is VSS or VSS+IR. Among them, VIN is the input low voltage domain voltage signal, the voltage value is VDD or GND, the inverter INV1 output, the inverter INV2 input, the gate terminal of the transistor M4 is connected, the inverter INV2 output and the gate terminal of the transistor M3 are connected, the gate terminal and the drain terminal of the transistor M1, the gate terminal of the transistor M2, the drain terminal of the transistor M3, and the source terminal of the transistor M4 are connected, the source terminal of the transistor M5 and the drain terminal of the transistor M2 are connected, the source terminal of the transistor M1, the source terminal of the transistor M3, and the source terminal of the transistor M2 are connected to VDD, one end of the resistor R1 is connected to VSS, and the other end of the resistor R1 is connected to the drain terminal of the transistor M5, one end of the current source I1 is connected to GND, and the other end of the current source I1 is connected to the drain terminal of the transistor M4.

[0008] In a preferred embodiment, a buffer is further provided at the output end of the input low voltage domain voltage signal, and the buffer is electrically connected to the input low voltage domain voltage signal.

[0009] In a preferred embodiment, the output terminal of the buffer is electrically connected to the gate terminal of the third transistor, the source terminal of the third transistor is electrically connected to the current source, the input terminal of the current source is connected to a common voltage, the drain terminal of the third transistor is electrically connected to the source terminal of the fourth transistor, and the gate terminal of the fourth transistor is grounded.

[0010] In a preferred embodiment, the drain terminal of the fourth transistor, the gate terminal and the drain terminal of the first transistor, and the drain terminal of the second transistor are connected, and the source terminal of the first transistor and the source terminal of the second transistor are both commonly grounded.

[0011] In a preferred embodiment, the drain terminal of the second transistor is electrically connected to the input low voltage domain voltage signal, and the drain terminal of the second transistor is also electrically connected to the resistor. The input terminal of the resistor is connected to the common voltage, and the circuit structure is converted to a voltage value near the voltage value corresponding to the high level in the high voltage domain, and the voltage value of the converted output voltage VOUT is VCC or VCC-IR, wherein VIN is the input low voltage domain voltage signal, and the voltage value is VDD or GND, the output of the buffer BUF1 is connected to the gate terminal of the transistor M3, the drain terminal of the transistor M3 is connected to the source terminal of the transistor M4, the drain terminal of the transistor M4, the gate terminal and drain terminal of the transistor M1, and the gate terminal of the transistor M2 are connected, one end of the resistor R1 is connected to VCC, and the other end of the resistor R1 is connected to the drain terminal of the transistor M2 and VOUT, one end of the current source I1 is connected to VDD, and the other end is connected to the source terminal of the transistor M3, and the source terminal of the transistor M1 and the source terminal of the transistor M2 are connected to VSS.

[0012] In a preferred embodiment, the gate terminal of the fourth transistor is electrically connected to the first inverter, the gate terminal of the third transistor is electrically connected to the second inverter, the gate terminal and the drain terminal of the first transistor, the gate terminal of the second transistor, the drain terminal of the third transistor and the source terminal of the fourth transistor are connected, and the drain terminal of the fourth transistor is provided with a conversion output voltage, the source terminal of the first transistor, the source terminal of the third transistor and the source terminal of the second transistor are connected to a common voltage, when the input signal VIN voltage is GND, the transistor M4 is turned off, the transistor M3 is turned on, the gate voltage of the transistor M1 and the transistor M2 is VDD, the resistor R1 has no current, and the VOUT output voltage is VSS; when the input signal VIN is VDD, the transistor M3 is turned off, the transistor M4 is turned on, the resistor R1 has a current I1 flowing through, and the output voltage value is VSS+I1*R1. This circuit structure realizes the voltage of VIN The voltage conversion to VSS and VSS+I1*R1 can be adjusted by adjusting the value of I1*R1 to adjust the high and low voltage difference of VOUT. In this circuit structure, the VSS voltage is independent of the GND voltage value and can be 0V, -5V, or +1V. When the input signal VIN voltage is VDD, the transistor M3 is turned off, there is no current in the transistors M1 and M2, and there is no current in the resistor R1, and the output voltage of VOUT is VCC; when the input signal VIN is GND, the transistor M3 is turned on, and the current I1 flows through the transistors M1, M2 and the resistor R1, and the output voltage value is VCC-I1*R1. This circuit structure realizes the voltage conversion of VIN to VCC and VCC-I1*R1. The high and low voltage difference of VOUT can be realized by adjusting the value of I1*R1. In this circuit structure, the VSS voltage can be <0, and the VCC voltage can be 0V, -5V or 5V.

[0013] Technical effects and advantages of the present invention:

[0014] The level conversion circuit of the present invention is composed of two groups of circuits, which respectively realize the functions of converting to the vicinity of the voltage value corresponding to the high level of the high voltage domain and converting to the vicinity of the voltage value corresponding to the low level of the high voltage domain. The voltage value of the low voltage domain and the voltage value of the high voltage domain in which the conversion circuit works can be selected relatively independently. At the same time, the difference between the high voltage and the low voltage in the high voltage domain after conversion can change with the selected current value and resistance value. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit module diagram of low level in high voltage domain of the present invention.

[0016] Figure 2 It is a circuit module diagram of a high level in a high voltage domain of the present invention.

[0017] Figure 3 It is a circuit schematic diagram of low level in high voltage domain of the present invention.

[0018] Figure 4 It is a circuit schematic diagram of a high level in a high voltage domain of the present invention.

[0019] Figure 5 It is a schematic diagram of a level conversion circuit in the prior art.

[0020] The figure markings are: 1. conversion output voltage; 2. first transistor; 3. second transistor; 4. third transistor; 5. fourth transistor; 6. fifth transistor; 7. first inverter; 8. second inverter; 9. buffer; 10. current source; 11. input low voltage domain voltage signal; 12. resistor.

[0021] Schematic symbols:

[0022] VOUT: Converted output voltage

[0023] VSS: Common ground

[0024] VDD: common voltage

[0025] VIN: Input low voltage domain voltage signal

[0026] GND: Ground

[0027] M1: First transistor

[0028] M2: Second transistor

[0029] M3: The third transistor

[0030] M4: The fourth transistor

[0031] M5: The fifth transistor

[0032] INV1: First inverter

[0033] INV2: Second inverter

[0034] BUF1: Buffer

[0035] I1: Current source

[0036] R1: Resistor DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] Example 1

[0039] Refer to the instruction manual Figure 1 and attached Figure 3 , a voltage conversion circuit structure suitable for a variable voltage domain according to an embodiment of the present invention comprises a first inverter 7, a second inverter 8 is provided at the output end of the first inverter 7, a fourth transistor 5 is further provided at the output end of the first inverter 7, a third transistor 4 is provided at the output end of the second inverter 8, a first transistor 2 is provided at the input end of the third transistor 4, a second transistor 3 is further provided at the input end of the third transistor 4, a fifth transistor 6 is provided at the input end of the second transistor 3, a current source 10 is provided at the drain end of the fourth transistor 5, an output end of the current source 10 is grounded, an input end of the first inverter 7 is provided with an input low voltage domain voltage signal 11, and the first inverter 7 is electrically connected to the input low voltage domain voltage signal 11, a resistor 12 is provided at the drain end of the fourth transistor 5, an output end of the resistor 12 is commonly grounded, and a circuit structure is converted to a voltage value near a voltage value corresponding to a low level in a high voltage domain, and a voltage value of a converted output voltage VOUT is VSS or VSS+IR. Among them, VIN is the input low voltage domain voltage signal, the voltage value is VDD or GND, the inverter INV1 output, the inverter INV2 input, the gate terminal of the transistor M4 is connected, the inverter INV2 output and the gate terminal of the transistor M3 are connected, the gate terminal and the drain terminal of the transistor M1, the gate terminal of the transistor M2, the drain terminal of the transistor M3, and the source terminal of the transistor M4 are connected, the source terminal of the transistor M5 and the drain terminal of the transistor M2 are connected, the source terminal of the transistor M1, the source terminal of the transistor M3, and the source terminal of the transistor M2 are connected to VDD, one end of the resistor R1 is connected to VSS, and the other end of the resistor R1 is connected to the drain terminal of the transistor M5, one end of the current source I1 is connected to GND, and the other end of the current source I1 is connected to the drain terminal of the transistor M4.

[0040] Furthermore, the gate terminal of the fourth transistor 5 is electrically connected to the first inverter 7, the gate terminal of the third transistor 4 is electrically connected to the second inverter 8, the gate terminal and the drain terminal of the first transistor 2, the gate terminal of the second transistor 3, the drain terminal of the third transistor 4 and the source terminal of the fourth transistor 5 are connected, the drain terminal of the fourth transistor 5 is provided with a conversion output voltage 1, and the source terminal of the first transistor 2, the source terminal of the third transistor 4 and the source terminal of the second transistor 3 are connected to a common voltage.

[0041] Specific implementation method: when the voltage of the input low voltage domain voltage signal 11 is GND, the fourth transistor 5 is turned off, the third transistor 4 is turned on, the gate voltages of the first transistor 2 and the second transistor 3 are VDD, the resistor 12 has no current, and the converted output voltage is VSS. When the input low voltage domain voltage signal 11 is VDD, the third transistor 4 is turned off, the fourth transistor 5 is turned on, the current source 10 flows through the resistor 12, and the output voltage value is VSS+I1*R1. This circuit structure realizes the voltage conversion of the input low voltage domain voltage signal 11 to VSS and VSS+I1*R1. Adjusting the I1*R1 value can adjust the high and low voltage difference of the converted output voltage 1. In this circuit structure, the VSS voltage is independent of the GND voltage value and can be 0V, -5V or +1V.

[0042] Example 2

[0043] Refer to the instruction manual Figure 2 and attached Figure 4, a voltage conversion circuit structure suitable for a variable voltage domain according to an embodiment of the present invention comprises a first inverter 7, a second inverter 8 is provided at the output end of the first inverter 7, a fourth transistor 5 is further provided at the output end of the first inverter 7, a third transistor 4 is provided at the output end of the second inverter 8, a first transistor 2 is provided at the input end of the third transistor 4, a second transistor 3 is further provided at the input end of the third transistor 4, a fifth transistor 6 is provided at the input end of the second transistor 3, a current source 10 is provided at the drain end of the fourth transistor 5, an output end of the current source 10 is grounded, an input end of the first inverter 7 is provided with an input low voltage domain voltage signal 11, and the first inverter 7 is electrically connected to the input low voltage domain voltage signal 11, a resistor 12 is provided at the drain end of the fourth transistor 5, an output end of the resistor 12 is commonly grounded, and a circuit structure is converted to a voltage value near a voltage value corresponding to a low level in a high voltage domain, and a voltage value of a converted output voltage VOUT is VSS or VSS+IR. Among them, VIN is the input low voltage domain voltage signal, the voltage value is VDD or GND, the inverter INV1 output, the inverter INV2 input, the gate terminal of the transistor M4 is connected, the inverter INV2 output and the gate terminal of the transistor M3 are connected, the gate terminal and the drain terminal of the transistor M1, the gate terminal of the transistor M2, the drain terminal of the transistor M3, and the source terminal of the transistor M4 are connected, the source terminal of the transistor M5 and the drain terminal of the transistor M2 are connected, the source terminal of the transistor M1, the source terminal of the transistor M3, and the source terminal of the transistor M2 are connected to VDD, one end of the resistor R1 is connected to VSS, and the other end of the resistor R1 is connected to the drain terminal of the transistor M5, one end of the current source I1 is connected to GND, and the other end of the current source I1 is connected to the drain terminal of the transistor M4.

[0044] Furthermore, a buffer 9 is provided at the output end of the input low voltage domain voltage signal 11, and the buffer 9 is electrically connected to the input low voltage domain voltage signal 11, the output end of the buffer 9 is electrically connected to the gate end of the third transistor 4, the source end of the third transistor 4 is electrically connected to the current source 10, the input end of the current source 10 is connected to a common voltage, the drain end of the third transistor 4 is electrically connected to the source end of the fourth transistor 5, the gate end of the fourth transistor 5 is grounded, the drain end of the fourth transistor 5, the gate end and the drain end of the first transistor 2, and the drain end of the second transistor 3 are connected, the source end of the first transistor 2 and the source end of the second transistor 3 are both commonly grounded, the drain end of the second transistor 3 is electrically connected to the input low voltage domain voltage signal 11, and the drain end of the second transistor 3 is electrically connected to the input low voltage domain voltage signal 11. The end is also electrically connected to the resistor 12, the input end of the resistor 12 is connected to the common voltage, and the circuit structure is converted to a voltage value near the voltage value corresponding to the high level in the high voltage domain, and the voltage value of the converted output voltage VOUT is VCC or VCC-IR, wherein VIN is the input low voltage domain voltage signal, and the voltage value is VDD or GND, the output of the buffer BUF1 is connected to the gate end of the transistor M3, the drain end of the transistor M3 is connected to the source end of the transistor M4, the drain end of the transistor M4, the gate end and drain end of the transistor M1, and the gate end of the transistor M2 are connected, one end of the resistor R1 is connected to VCC, and the other end of the resistor R1 is connected to the drain end of the transistor M2 and VOUT, one end of the current source I1 is connected to VDD, and the other end is connected to the source end of the transistor M3, and the source end of the transistor M1 and the source end of the transistor M2 are connected to VSS.

[0045] Specific implementation method: When the voltage of the input low voltage domain voltage signal 11 is VDD, the third transistor 4 is turned off, there is no current in the first transistor 2 and the second transistor 3, and there is no current in the resistor 12. The output voltage of the converted output voltage 1 is VCC. When the input low voltage domain voltage signal 11 is GND, the third transistor 4 is turned on, and the current source 10 flows through the first transistor 2, the second transistor 3 and the resistor 12. The output voltage value is VCC-I1*R1. This circuit structure realizes the voltage conversion of the input low voltage domain voltage signal 11 to VCC and VCC-I1*R1. Adjusting the I1*R1 value can realize the high and low voltage difference of VOUT. In this circuit structure, the VSS voltage can be <0, and the VCC voltage can be 0V, -5V or 5V.

[0046] Finally, a few points should be explained: First, in the description of this application, it should be noted that, unless otherwise specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, which may refer to mechanical connection or electrical connection, or internal communication between two components, or direct connection. "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may change;

[0047] Secondly: In the drawings of the embodiments disclosed in the present invention, only the structures related to the embodiments disclosed in the present invention are involved, and other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

[0048] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage conversion circuit structure suitable for a variable voltage domain, characterized in that: The invention comprises a first inverter (7), wherein the output end of the first inverter (7) is provided with a second inverter (8), the output end of the first inverter (7) is also provided with a fourth transistor (5), and the output end of the first inverter (7) is connected to the gate end of the fourth transistor (5), the output end of the second inverter (8) is provided with a third transistor (4), and the output end of the second inverter (8) is connected to the gate end of the third transistor (4), the input end of the third transistor (4) is provided with a first transistor (2), the input end of the third transistor (4) is also provided with a second transistor (3), and the drain end of the third transistor (4) is connected to the gate end of the third transistor (4). The gate terminal of the second transistor (3) is connected, the input terminal of the second transistor (3) is provided with a fifth transistor (6), and the source terminal of the fifth transistor (6) is connected to the drain terminal of the second transistor (3), the drain terminal of the fourth transistor (5) is provided with a current source (10), the output terminal of the current source (10) is grounded, the input terminal of the first inverter (7) is provided with an input low voltage domain voltage signal (11), and the first inverter (7) is electrically connected to the input low voltage domain voltage signal (11), the drain terminal of the fifth transistor (6) is provided with a resistor (12), and the output terminal of the resistor (12) is commonly grounded.

2. The voltage conversion circuit structure applicable to a variable voltage domain according to claim 1, characterized in that: The drain terminal of the fifth transistor (6) is electrically connected to the converted output voltage (1).

3. The voltage conversion circuit structure applicable to a variable voltage domain according to claim 1, characterized in that: The source end of the first transistor (2), the source end of the third transistor (4) and the source end of the second transistor (3) are connected to a common voltage.

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