Circuit for transmitting signals between different voltage domains and corresponding method for transmitting signals

Abstract

Embodiments of the present disclosure relate to circuits for transmitting signals between different voltage domains and corresponding methods for transmitting signals. A circuit includes a current path and a negative bootstrap circuit arrangement coupled to the current path. The current path is coupled between a floating voltage and a reference ground and includes a current generator at a first node of the floating voltage coupled to a current generator through a resistor. The current generator is controlled by a pulse signal. The negative bootstrap circuit arrangement includes a pumping capacitor coupled to a second node of the current generator and the reference ground. The pumping capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Description

Technical Field

[0001] This specification relates to a circuit for transmitting signals in a circuit device including circuit stages supplied with voltage from different voltage domains. Background Art

[0002] High-voltage (HV) half-bridge switching circuits can be used in various applications, such as motor drives, fluorescent lamp electronic ballasts, and power supplies. The half-bridge switching circuits that can be used can include converters such as active-clamp flybacks and LLC resonant converters. Such a half-bridge circuit can employ a pair of totem-pole-connected switching elements (e.g., power MOSFETs, FETs, and GaN devices) placed on a high-voltage rail DC voltage supply.

[0003] Given the various possible applications, there is a pursuit of continuously improving drive circuits. Summary of the Invention

[0004] One or more embodiments can relate to a circuit used, for example, in a high-voltage half-bridge switching circuit, particularly including a switching device containing a floating well.

[0005] One or more embodiments can also relate to a method.

[0006] One or more embodiments can include a circuit including a circuit stage supplied with voltage from different voltage domains, the voltage domains including a first voltage domain of a first voltage level represented by a first voltage source and a first voltage reference, particularly a DC voltage source and a DC ground, and a second voltage domain of a second voltage level represented by a second voltage source and a second voltage reference, particularly a floating power supply and a floating ground, and a circuit for transmitting a command signal operating according to the first voltage domain to a stage operating according to the second voltage domain,

[0007] The circuit for transmitting the command signal includes: a logic component operating according to the second voltage domain for logically driving the stage, and a level-shifting circuit coupled to the second voltage source and a first ground reference,

[0008] The level-shifting circuit includes: two paths coupled between the second voltage source and the first ground reference, each path including a high-voltage transistor coupled to the second voltage source through a respective resistor and coupled to the first ground reference through a respective command current generator, each path being coupled to a respective input terminal of the logic component, the command current generator being commanded by a pulse signal, and the pulse signal being commanded by a pulse generator based on the command signal,

[0009] Wherein the level shift circuit includes: a negative bootstrap circuit, the negative bootstrap circuit at least includes a pumping capacitor arranged between a current generator and a first ground reference, and the pumping capacitor is configured to shift the first ground reference synchronously with the activation of a corresponding command current generator by a negative voltage.

[0010] The logic component that one or more embodiments may include is a set reset latch.

[0011] One or more embodiments may include a negative bootstrap circuit having a pumping capacitor coupled between a corresponding current generator and a first ground reference.

[0012] One or more embodiments may include that terminals of the pumping capacitor are selectively coupled to the first ground reference through corresponding selection circuits, and the corresponding selection circuits are commanded by corresponding pulse signals to couple the terminals of each capacitor in the capacitor to either the first ground reference or a first voltage source.

[0013] One or more embodiments may include: a negative bootstrap circuit including a single pumping capacitor coupled between a common node of a current generator and a first ground reference.

[0014] One or more embodiments may include: the terminals of the pumping capacitor are selectively coupled to the first ground reference through corresponding selection circuits, and the corresponding selection circuits are commanded by a combination of pulse signals (especially a logical OR) to couple the terminals of each capacitor in the capacitor to either the first ground reference or a first voltage source.

[0015] One or more embodiments may include: the selection circuit at least includes a selection buffer device, the selection buffer device includes an inverting buffer, the inverting buffer is supplied with an input of one of the digital pulses or the combination of digital pulses accordingly, an output of the inverting buffer is fed as an input of a switching transistor, especially an input of an n-channel MOS transistor, through a drain coupled to a lower node of a current generator and through a source coupled to the first ground reference, a capacitor is coupled to the lower node of the current generator at one terminal and to an output of another inverting buffer at another terminal, the output of the another inverting buffer is supplied with an input of the one of the digital pulses or the combination of digital pulses accordingly, a power supply terminal of the another inverting buffer is coupled to the first voltage domain for power supply, while a power supply terminal of the inverting buffer is coupled to a first power supply voltage and the lower node of the current generator.

[0016] One or more embodiments may include two selection buffer devices coupled to each of the paths.

[0017] One or more embodiments may include a floating well device.

[0018] One or more embodiments may include: the stage, which includes a half-bridge switching device, the half-bridge switching device includes a capacitor, the capacitor is used to drive a power switch through a capacitor arranged between a bootstrap terminal and an output terminal, and the output terminal is alternately switchable between a low voltage and a high voltage DC voltage.

[0019] The solutions described herein also refer to a method of operating a transmission command signal in a circuit according to a first voltage domain according to any one of the previous embodiments, the first voltage domain includes a first voltage level represented by a first voltage source and a first voltage reference, in particular a DC voltage source and a DC ground; the solution also refers to a stage operating according to a second voltage domain, the second voltage domain includes a second voltage level represented by a second voltage source and a second voltage reference, in particular a floating power supply and a floating ground; the solution includes performing negative bootstrap, the negative bootstrap at least includes a pumping capacitor arranged between a current generator and a first ground reference, the pumping capacitor offsets the first ground reference synchronously with the activation of a corresponding command current generator at a negative voltage.

[0020] In various embodiments, a pulse signal is generated by a pulse generator based on the command signal by alternately sending pulses on one of the pulse signals when a rising edge or a falling edge in the received command signal is detected, and the pulse is shorter than the interval between the rising edge and the falling edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0022] Figure 1 is a schematic representation of a half-bridge switching circuit having a floating well device;

[0023] Figure 2 is an exemplary circuit diagram of a level-shifting circuit;

[0024] Figure 3 is according to Figure 1 and Figure 2 is a timing diagram of the signals of the circuit according to the embodiments of;

[0025] Figure 4 is an exemplary circuit diagram of a level-shifting circuit according to one or more embodiments;

[0026] Figure 5 is an exemplary circuit diagram of a level-shifting circuit according to different embodiments; and

[0027] Figures 6 to 9 is a time function diagram of the signals of a level-shifting circuit according to one or more embodiments. Detailed implementation manners

[0028] In the following description, one or more implementations are illustrated, with the aim of providing an in-depth understanding of example embodiments. Embodiments can be obtained without using one or more implementations, or by using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments are not obscured.

[0029] In the framework of the present disclosure, the reference to "an embodiment" or "one embodiment" is intended to indicate that a specific configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to one or more identical embodiments. Additionally, a specific configuration, structure, or feature can be combined in any suitable manner in one or more embodiments.

[0030] The references used herein are for convenience only and thus do not define the scope or extent of protection of the embodiments.

[0031] High-voltage half-bridge switching circuits can be used in various applications, such as motor drives, fluorescent lamp electronic ballasts, and power supplies.

[0032] Literatures, such as US 5,572,156, US2017 / 0141775, US8,044,699, and the published "Noise Immunity Improvement Level-Shifting Structure for 600V HVIC" by Zhang et al., Journal of Semiconductors, Vol. 34, No. 6 (DOI: 10.1088 / 1674-4926 / 34 / 6 / 065008), are generally examples of the related art.

[0033] A half-bridge circuit can employ a pair of totem-pole-connected switching elements (e.g., power MOSFETs, IGBTs, FETs, and GaN devices) placed across a high-voltage (HV) rail DC voltage power supply.

[0034] For example, a conventional half-bridge switching circuit can include:

[0035] A first power transistor and a second power transistor, coupled to each other in a totem-pole configuration at a load node, for example, coupled to each other by interconnecting the source of the first transistor and the drain of the second transistor at the load node;

[0036] An HV rail DC voltage source, electrically connected to the drain of the first transistor and the source of the second transistor;

[0037] A gate drive buffer, electrically coupled to the gate of a transistor to provide control signals to turn the transistor on and off; and

[0038] A DC voltage source to supply power to a power device.

[0039] Under operating conditions, the transistors in the pair are "radially" controlled, e.g., turned on and off alternately so that they are not turned on simultaneously. In this way, the voltage at the load node, e.g., the voltage at the output node connected to the load, is not fixed but can be brought to the voltage level of the high-voltage (HV) rail DC voltage source or to zero volts, depending on which of the two transistors is turned on at a given moment.

[0040] Bootstrapping techniques can be used to derive a DC voltage source that floats with respect to the HV rail DC voltage source.

[0041] Figure 1 The block diagram of... is an example of this way.

[0042] In Figure 1 the illustration of..., the half-bridge device HB can include: a first power switch PW1 and a second power switch PW2, e.g., power transistors such as power MOSFETs, the first power switch PW1 and the second power switch PW2 are coupled in a totem-pole configuration, the source of the first transistor PW1 and the drain of the second transistor PW2 are interconnected at a load node, which is coupled to a floating ground node FG; and a high-voltage rail AC voltage source 11, electrically coupled to the drain of the first transistor PW1 and the source of the second transistor PW2. This floating ground node FG can be coupled to a MOSFET device configured with a floating well (e.g., the first transistor PW1). Gate drive buffers HS_DRV (high side) and LS_DRV (low side) driven by respective high-side control signal HIN and low-side control signal LIN are coupled (e.g., at nodes HVG and LVG) to the gates (control electrodes) of the transistors PW1, PW2 to provide control signals to turn on and off the transistors PW1 and PW2, respectively.

[0043] In one or more embodiments, a high-voltage diode DB can be coupled between the DC power supply VCC and the floating power supply FS pin, and a floating voltage V FS is formed on the floating power supply FS pin. The diode DB and a bootstrap capacitor CB coupled between the floating power supply FS and the floating ground reference can then be used to derive the power supply VFG of the high-side HS_DRV buffer that floats with respect to the high-voltage rail DC voltage source from the power supply VCC of the low-voltage side buffer LS_DRV.

[0044] The capacitor CB serves as a voltage source to power the driver HS_DRV. When the second transistor PW2 is turned on, the load node is effectively coupled to the low voltage, and the high-voltage diode DB allows current to flow from the DC power supply (VCC) to the bootstrap capacitor CB, charging the capacitor to approximately the voltage level of the DC power supply. When the second transistor PW2 is turned off and the first transistor PW1 is turned on, the voltage at the load node (i.e., the floating node FG) approximately assumes the voltage level of the HV rail DC voltage power supply 11, causing the diode DB to be reverse-biased without current flowing from the DC power supply to the bootstrap capacitor CB. While the diode DB remains reverse-biased, the charge stored in the bootstrap capacitor CB is supplied to the high-side buffer HS_DRV. However, the bootstrap capacitor CB is positioned to provide this voltage only for a limited time to turn off the first transistor PW1, and the second transistor PW2 is turned on to restore the charge on the bootstrap capacitor CB.

[0045] Therefore, in this case, the high-side driver and the low-side driver can be integrated on a single die. This is useful for processing signals by the same logic module 21.

[0046] To correctly drive the gate of the high-side transistor PW1 with a low-voltage input signal HIN belonging to the first voltage domain of the DC voltage source / domain defined by the levels on the DC nodes VCC, GND (the gate operates in the second voltage domain of the floating voltage domain with the voltage levels of the nodes FS, FG), a high-voltage level shifter 22 electrically coupled between the floating power node FS and the DC ground GND terminal is used. Due to the strict limitations in terms of power consumption and common-mode transient immunity for high-voltage gate driver products, a differential high-voltage level shifter operating in burst mode is used.

[0047] Such a high-voltage level shifter 22 thus receives a command signal as input, which is a first voltage domain signal issued by the logic module 21 based on the high-side control signal HIN. For example, the first voltage domain PWM (pulse width modulation signal) drives the first transistor PW1 radially along the low-side control signal LIN.

[0048] This high-voltage level shifter 22, as Figure 2 shown, includes two high-voltage (HV) MOS 221a, 221b and a control logic block 224. The drain electrodes of the two high-voltage (HV) MOS 221a, 221b are each floating at a voltage V through corresponding resistors 223a, 223b FSis coupled to a floating power supply node FS, while two command current sources 222a, 222b are coupled between the sources of two high-voltage MOSs 221a, 221b and DC ground GND, and are driven in an on state and an off state by corresponding digital pulse signals Tp1 and Tp2 (the pulses of which are narrow pulses), as Figure 3 shown. The gates are coupled to a fixed voltage, which is a DC voltage power supply VCC in the example.

[0049] The high-voltage level shifter circuit 22 receives a logic level control signal CS, which is also shown as a function of time t in the Figure 2 timing diagram, indicating whether the power switches PW1, PW2 at the input of the pulse generation circuit 225 must be turned on or off. The pulse generation circuit 225 generates a separate on pulse P and off pulse P1 carried on the digital pulse signals Tp2 and Tp1 respectively in response to the logic level control signal CS, as shown in the Figure 3 diagram.

[0050] In response to the on pulse on the second pulse signal Tp2 that commands the second current generator 222b, the corresponding high-voltage transistor 221b is turned on, and current is drawn from the floating power supply voltage V at the floating power supply node FS FS thereby creating a voltage drop across the resistor 223b, which is detected by the logic components of the control logic circuit 224 in the example of setting the set and reset inputs of a reset flip-flop, or more generally, in a set-reset latch logic circuit.

[0051] Therefore, the level shifter circuit 22 includes two circuit paths coupled between the floating power supply node FS at the floating voltage V FS and the DC ground reference GND. Each circuit path includes high-voltage transistors 221a, 221b coupled to the floating power supply node FS at the floating voltage V through corresponding resistors 223a, 223b FS and coupled to the DC ground reference GND through corresponding command current generators 222a, 222b. Each path is coupled to a corresponding input of the logic component 224, such as a set-reset input. The command current generators 222a, 222b are commanded by the pulse signals Tp1, Tp2, which are generated by the pulse generator 225 based on the command signal CS.

[0052] In one embodiment, such a control logic circuit 224 is coupled for floating power supply between the floating power supply node FS and DC ground GND so that the voltage difference between the floating power supply node FS and the floating ground FG remains less than the threshold admissible by its components.

[0053] One disadvantage of this approach may be that the current that has to be generated must be sufficient to ensure the correct setting or resetting of the final stage and good noise immunity. For this reason, the current must not be too low. However, since the current of the level shifter leaks from the floating power supply, most applications use a capacitor to provide the floating stage. Therefore, if the current is not well controlled and is too large, the floating power supply FS may be reduced too much and the system may not operate correctly.

[0054] For these reasons, in order to have a well-defined current, it is possible to implement a current generator to improve current consumption and noise immunity, as Figure 3 shown in the illustration.

[0055] The pulse generation circuit 225 can be configured to implement a pulse signal of a defined time length when there is a positive edge on the command signal CS. Additionally, when the command signal CS has a negative edge, the pulse generation circuit 225 generates a pulse signal of a defined duration. These two pulse signals, still referred to as the second pulse signal Tp2 and the first pulse signal Tp1, are used to drive the command current sources 222a, 222b, assert the set S and reset R of the control logic circuit 224, and transmit signals within the floating well. Therefore, in Figure 3 the output Q of the latch or the S-R flip-flop 224 is shown, which essentially corresponds to the command signal CS taking into account the propagation delay. The duration of these two narrow pulses in the second pulse signal Tp2 and the first pulse signal Tp1 must be sufficient to ensure the correct setting or resetting of the logic signal within the domain of the floating power supply FS, but at the same time need to be very short to ensure that the floating power supply voltage VFS provided by the bootstrap capacitor CB does not decrease too much.

[0056] This circuit arrangement facilitates the transmission of signals during the transition of the floating power supply from low voltage to high voltage and from high voltage to low voltage. The functionality of the structure is ensured by the control logic and the resistors 223a, 223b, which are implemented to ensure the correct setting of the output nodes. In fact, the following are selected: the values of the resistors 223a, 223b, the current values of the command current sources 222a, 222b, and the dimensions of the HV MOS transistors 221a and 22b, to ensure that the voltage across the resistors 223a, 223b can set the correct state of the output under any conditions.

[0057] With this circuit, it is possible to set the gate (e.g., the HVG node) of a MOSFET or an IGBT under any functional conditions. In fact, the floating ground FG voltage in all these applications can be from (V H+(0.7) is reduced to (GND - 0.7). These two values are the maximum and minimum voltages that the floating ground FG can reach when a device with MOS (or IGBT) drives a typical inductive load. Therefore, when current flows through the internal diode of the MOSFET, the voltage of the floating ground is clamped at (V H +(0.7) or (GND - 0.7).

[0058] In both cases, all set and reset signals can be transferred from low-voltage logic (i.e., the first voltage domain) to floating power supply logic (i.e., the second voltage domain).

[0059] However, when using GaN transistors, for example, there are some problems due to the physical differences in the structure of GaN transistors. In fact, compared with MOS or IGBT, GaN transistors have a very small gate voltage in the range of 4V - 6V, while the gate voltage of MOSFETs can be in the range of 5 - 25V. Therefore, the voltage between the floating power supply and the floating ground cannot be higher than 6V. In addition, GaN transistors do not include an intrinsic body diode between the drain and the body-source.

[0060] Therefore, the disadvantage of this method may lie in that the level shifter of the device according to Figure 2 shows limited functionality when used to drive GaN transistors. When the current in the GaN transistor recycles and makes the floating ground FG lower than the system (i.e., low signal) ground GND, there is no component to clamp the floating ground voltage. For this reason, the voltage between the floating power supply and the system ground (FS and GND) is not fixed and can also be reduced to a negative value.

[0061] The level shifter can transfer signals until the voltage across the floating power supply and the system ground is sufficient to ensure a sufficient voltage drop across resistors 223a, 223b. Therefore, when the voltage drop is too low, the signal cannot be transferred.

[0062] This is because the current sources or generators 222a, 222b absorb current from the floating power supply. Therefore, when the floating power supply moves below a defined value, the voltage drop across the current generator is not sufficient to generate current. In addition, the voltage drop across resistors 223a, 223b needs to be higher than a defined value, for example, depending on the technology and resistor values, to ensure the correct setting or reset of the logic in the floating well.

[0063] For this reason, for newer versions of bipolar CMOS - DMOS technology, such as BCD6S technology, between the floating power supply and the system ground V FS -V GNDThe voltage difference between them is about 3.5V. In this case, the signal cannot be transmitted to the floating logic. This value depends on the technology, but in any case, it must not be lower than 2VDS, that is, the voltage drop across the two drain-source voltages of the MOSFET and the resistors 223a and 223b.

[0064] It has been observed that when the floating power supply is below the defined voltage, the possibility of driving the floating well is very useful for all applications where the floating ground of the application is forced to be in a relevant condition below ground, such as those described above, when using GaN transistors or if the floating ground is not directly coupled to the drain of the low-voltage side switching transistor.

[0065] As Figure 4 shown, one or more example embodiments can solve the problem of the correct transmission of the control signal (such as a PWM command) of the switching transistor in the floating well when the floating power supply is equal to or lower than the system ground.

[0066] Figure 4 The high-voltage level shifter circuit device shown in [the figure] is configured to provide a negative voltage at the ground reference of the level shifter by using a negative bootstrap circuit implemented with capacitors, buffers, and logic, and the logic is configured to drive the negative bootstrap circuit to provide a negative voltage at the ground reference of the level shifter. Specifically, according to an embodiment, the negative bootstrap circuit may at least include a capacitor disposed between a current generator and a first ground reference (such as a DC or low-voltage ground reference), and the capacitor is configured to shift the voltage negatively at the first ground reference.

[0067] In one or more example embodiments as Figure 4 shown, the high-voltage level shifter circuit device, indicated as a whole by 32, basically includes Figure 2 circuit 22, so the corresponding components are denoted by the same reference numerals, but differently, the current generators 222a and 222b are now coupled to the DC ground GND node through the respective first capacitor C1 and second capacitor C2, rather than directly coupled to the ground GND. In other words, the lower nodes a and b of each of the current generators indicated as current generators 222a and 222b, that is, the nodes of the current generators not coupled to the sources of the transistors 221a and 221b, the terminals of the first capacitor C1 and the second capacitor C2 are coupled to the lower nodes a and b. The other terminals of the first capacitor C1 and the second capacitor C2 are coupled to the DC ground reference node GND, although the coupling is performed in an optional manner through a buffer to implement the negative bootstrap circuit, as will be better explained below.

[0068] Therefore, the high-voltage level shifter circuit device 32 is controlled by the digital pulse signals (i.e., Tp1 and Tp2) of the pulse generator 225 to synchronously command the capacitors C1 and C2 to temporarily generate a negative voltage. According to the state of the pulse Tp2 / Tp1, only for the time required to transmit the command on / off for the output Q of the command signal CS, for this negative voltage, the ground reference GND of the level shifter is pulled below ground (i.e., pulled to a sufficiently negative value), and the level shifter corresponds to each of the lower nodes a, b of the current generators 222a, 222b.

[0069] The current generators 222a, 222b can be implemented by resistor devices, for example, transistors configured as resistors or variable command resistors, or current mirrors. The digital pulses Tp1 and Tp2 are also provided to the corresponding inverting buffers INV1 and INV2, and their outputs are fed as inputs to the corresponding n-channel MOS transistors 226a, 226b, which are coupled by the drain to the lower nodes a, b of the current generators 222a, 222b and by the source to the DC ground GND. The capacitors C1 and C2 are coupled at one terminal to the lower nodes of the current generators 222a, 222b and at the other terminal to the outputs of the corresponding inverting buffers INV3 and INV4. The power supply terminals of the inverting buffers INV3 and INV4 are coupled to supply power to the DC voltage VCC and the ground GND. The power supply terminals of the inverting buffers INV1 and INV2 are coupled to the DC voltage VCC and the lower nodes a, b of the current generators 222a, 222b. The inverting buffers INV1 and INV2 and the inverting buffers INV3 and INV4 receive the digital pulses Tp1 and Tp2 as inputs, respectively.

[0070] The circuit includes capacitors C1, C2, inverting buffers INV1, INV2, and inverting buffers INV3, INV4. When receiving the digital pulses Tp1 and Tp2 - as Figure 2 shown, the digital pulses Tp1 and TP2 are generated at the positive and negative edges of the command signal CS to replicate such a command signal CS, which belongs to the first voltage domain, i.e., the DC or low-voltage domain, and in the output signal Q, which belongs to the second voltage domain, i.e., the floating voltage domain - performs a bootstrap for implementing a two-step cycle. In the first step, associated with the low-level pulse signals Tp2, Tp1, the capacitors C1, C2 are charged to the same voltage across the power supply Vcc. In the second step, associated with the high level of the pulse signals Tp2, Tp1, i.e., during the narrow pulse, the bootstrap circuit is reconfigured such that the capacitors C2, C1 are in series with the voltage across the floating power supply and the loads 221, 222, 223.

[0071] More specifically, when the pulse signals Tp1 and Tp2 are at a low level, the two capacitors C1 and C2 are charged with a fixed voltage (e.g., the DC power supply VCC) through the inverting buffer INV3 and the N-channel MOS 226a (for capacitor C1), and the buffer INV4 and the N-channel MOS 226b (for C2).

[0072] More specifically, the terminals of the capacitors C1 and C2, which are coupled to the lower nodes a, b of the current generators 222a, 222b and the drains of the N-channel MOS transistors 226a, 226b, are tied to the ground GND through the sources of the N-channel MOS transistors 226a, 226b, and the sources of the N-channel MOS transistors 226a, 226b are turned on because when the pulse signals Tp1 and Tp2 are at a low level, the outputs of the inverting buffers INV1 and INV2 are high. Since the outputs of the other inverting buffers INV3 and INV4 are high, the other nodes of the capacitors C1 and C2, which are coupled to the outputs of the other inverting buffers INV3 and INV4, are tied to the DC voltage VCC, that is, VCC, because the pulses Tp1 and tp2 are at a low level. Therefore, there is a voltage drop VCC across the capacitors C1 and C2.

[0073] When the pulse generator 225 generates a positive pulse on the pulse signal Tp1 or Tp2, the corresponding current generators 222a, 222b are enabled, and the corresponding capacitor C1 or C2 is pulled down under the DC ground reference GND of the low-voltage system, e.g., at zero voltage, and the negative voltage amount of the lower nodes a, b of the corresponding current generators 222a, 222b is equal to the charging voltage (e.g., VCC) on the capacitors C1 and C2.

[0074] After the positive pulse interval ends, the pulse signal Tp1 or Tp2 returns to the ground level, and the charge lost in the corresponding capacitors C1 and C2 during the negative transition is restored, charging the capacitors to a fixed voltage (e.g., VCC) again. This is generated periodically whenever an event in the pulse signals Tp1, Tp2 is triggered.

[0075] Therefore, compared to possible alternative solutions, such as a negative external power supply or a classical negative charge pump that require larger capacitors and higher current consumption, the proposed system is more advantageous in terms of circuit complexity, chip area occupancy, and consumption.

[0076] In Figure 5A variant embodiment is shown in which a single capacitor Cpump is used to simultaneously pull the two lower nodes a, b of the current generators 222a, 222b under the DC ground reference GND. In this case, it is necessary to combine the pulse signals Tp1 and Tp2 to ensure the correct setting of the voltage across the single capacitor Cpump and to ensure the correct signal transmission to the control logic 224.

[0077] Thus, in this case, the single capacitor Cpump is coupled to one end of the lower nodes a, b that are coupled together. A single inverting buffer SINV receives as input the output of an OR gate 228 having the pulse signals Tp1 and Tp2 as inputs. The output of the single inverting buffer SINV is fed as an input to an n-channel MOS transistor S226, which is coupled to the lower nodes a, b of the current generators 222a, 222b at the drain and to the ground GND at the source. In the same way, a single other inverting buffer FINV receives as input the output of an OR gate 229 having the pulse signals Tp1 and Tp2 as inputs. The output of the OR gate is low only when both pulse signals Tp1 and Tp2 are low. Therefore, the single capacitor Cpump is charged to +VCC only in this case, while during any one of the two pulses Tp1, Tp2, the current generators 222a, 222b are enabled and the single capacitor Cpump is pulled below the DC ground reference GND. For example, at zero voltage, in the example of VCC, the lower nodes a, b of the current generators 222a, 222b have a negative voltage amount equal to the voltage charged on the single capacitor Cpump.

[0078] Different from the dual-capacitor solution, the single-capacitor solution has a lower area impact and better noise immunity.

[0079] On the contrary, the dual-capacitor solution allows for higher-frequency signal transmission because the capacitor (C1 or C2) is only used for one signal transmission. In addition, the system has a simpler logic to control the capacitors C1 and C2.

[0080] In this way, it is possible to send a signal to the output nodes of the floating well and the control logic, and then when the difference between V FS -V GND is lower than a specified value (3.5V for BCS6SOffline), the high-side gate node HVG can also change direction.

[0081] In Figure 6 and Figure 7 are shown the command signal CS, the output Q of circuit 22, the output Q of circuit 32, and the voltage V at the floating power supply FS FS and the voltage V at the ground GNDGND A diagram showing the variation of the difference over time t.

[0082] The command signal CS should be transmitted to the output Q within the floating well, namely the driver HS_DRV and the switch PW1 operating in the floating voltage domain. As Figure 6 and Figure 7 shown, for simplicity, in the Figure 2 circuit 22, when the voltage (V FS -V GND ) between the floating power supply FS and the ground GND is at the defined value DV (3.5V in the figure), the command signal CS is not sent to the output Q, and the last transmitted state is latched by the control logic 224. In Figure 6 and Figure 7 , in the Figure 4 circuit 32, the output Q(32) instead copies the command signal CS.

[0083] In Figure 6 , the low state is locked, and in Figure 7 , the high state is locked.

[0084] In Figure 6 and Figure 7 , the voltage V FS -V GND between the node FS and GND is constant, so the output voltage has a fixed value V FS -V FG .

[0085] In Figure 8 and Figure 9 , the same quantities as in Figure 6 and Figure 7 are shown, but the voltage V FS -V GND is not constant and decreases. Therefore, the transmitted signal Q(32) decreases according to the difference of V FS- V GND . For example, when V FG = V GND , the transmitted signal Q(22) decreases, and when the threshold DV is reached, the command signal CS is not sent to the control logic. In Figure 8 and Figure 9 , in the Figure 4 circuit 32, the output Q(32) instead copies the command signal CS.

[0086] In Figure 8 , the low state is latched, and in Figure 9 , the high state is transmitted.

[0087] For the high-state latch, the latched output varies with V FS-V GND and decreases.

[0088] Without prejudice to the basic principles, the details and embodiments may vary, even significantly, only in respect of what is described by way of example, without departing from the scope of protection.

[0089] The scope of protection is defined by the appended claims.

[0090] The various embodiments described above may be combined to provide further embodiments. Where necessary, aspects of the embodiments may be modified to provide further embodiments.

[0091] Based on the above detailed description, these and other changes may be made to the embodiments. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A circuit, comprising: A first voltage domain of a first voltage level, including a first voltage source and a first voltage reference; A second voltage domain of a second voltage level, including a second voltage source and a second voltage reference; And A first circuit device configured to generate a second signal for operating in the second voltage domain based on a control signal, the first circuit including a logic component and a level shifter circuit, the level shifter circuit being coupled to the second voltage source and the first voltage reference, the level shifter circuit including: Two current paths coupled between the second voltage source and the first voltage reference; A negative bootstrap circuit coupled to each of the two current paths; and A pulse generator coupled to each of the two current paths, Wherein each of the two current paths includes a high-voltage transistor, the high-voltage transistor is coupled to the second voltage source through a corresponding resistor and coupled to the first voltage reference through a corresponding controlled current generator, each of the two current paths is coupled to a corresponding input of the logic component, the pulse generator is configured to generate a pulse signal based on the control signal, the corresponding controlled current generator is controlled by at least one of the pulse signals generated by the pulse generator, and the negative bootstrap circuit includes at least one pumping capacitor, the at least one pumping capacitor is coupled to provide a negative voltage at a first node of the corresponding controlled current generator.

2. The circuit according to claim 1, wherein the logic component is a set-reset latch.

3. The circuit according to claim 1, wherein the negative bootstrap circuit includes two pumping capacitors, each pumping capacitor being coupled to a corresponding current generator of the two current paths.

4. The circuit according to claim 3, wherein a first terminal of the pumping capacitor among the two pumping capacitors is selectively coupled to one of the first voltage reference or the first voltage source controlled by one of the pulse signals generated by the pulse generator.

5. The circuit according to claim 1, wherein the negative bootstrap circuit includes a single pumping capacitor coupled to a first node of the controlled current generator of the two current paths.

6. The circuit according to claim 5, wherein a terminal of the single pumping capacitor is selectively coupled to one of the first voltage reference or the first voltage source controlled by a combination of the pulse signals generated by the pulse generator.

7. The circuit according to claim 4, comprising: A selection circuit device configured to selectively couple the first terminal of the pumping capacitor to one of the first voltage reference or the first voltage source, the selection circuit device including at least one selection buffer device, the at least one selection buffer device including a first inverting buffer and a second inverting buffer coupled to one or more of the pulse signals. wherein, the output of the first inverting buffer is coupled to control a switch coupled between the first node of the corresponding current generator and the first voltage reference; and wherein, the output of the second inverting buffer is coupled to the first terminal of the pumping capacitor, and the second inverting buffer is controlled by the one or more pulse signals to selectively couple the first terminal of the pumping capacitor to one of the first voltage source or the first voltage reference.

8. The circuit according to claim 7, wherein the at least one selection buffer device includes two selection buffer devices, each selection buffer device being coupled to one of the two current paths.

9. The circuit according to claim 1, comprising: A floating well device arranged to operate in the second voltage domain.

10. The circuit according to claim 1, comprising: A half-bridge switching device arranged to operate in the second voltage domain and including a capacitor for driving a power switch, the capacitor being coupled between a bootstrap terminal and an output terminal, the output terminal being alternately switchable between a first DC voltage and a second DC voltage.

11. A circuit, comprising: A pulse generator; and A current path coupled between a first floating voltage and a first reference ground, the current path including a current generator coupled to the first floating voltage at a first node of the current generator through a resistor, and the current generator being coupled to be controlled by a pulse signal generated by the pulse generator; and A negative bootstrap circuit device coupled to the current path, the negative bootstrap circuit including a pumping capacitor coupled to a second node of the current generator and the first reference ground, the pumping capacitor being configured to provide a negative voltage at the second node of the current generator based on the pulse signal generated by the pulse generator, wherein the current generator is coupled to be controlled by the pulse signal independent of the negative bootstrap circuit device.

12. The circuit according to claim 11, wherein the first terminal of the pumping capacitor is selectively coupled to one of the first reference ground or the first voltage source based on the pulse signal generated by the pulse generator.

13. The circuit according to claim 11, wherein the second terminal of the pumping capacitor is coupled to the second node of the current generator.

14. The circuit according to claim 13, wherein the second node of the current generator is coupled to the first reference ground through a first transistor.

15. The circuit according to claim 14, wherein the second terminal of the pumping capacitor is coupled to the gate of the first transistor through a first inverting buffer.

16. The circuit according to claim 15, wherein a first voltage source is coupled to the gate of the first transistor through the first inverting buffer.

17. The circuit according to claim 16, wherein the first inverting buffer is coupled to be controlled by the pulse signal generated by the pulse generator.

18. A circuit, comprising: A current path is coupled between a first floating voltage and a first reference ground, and the current path includes a current generator and a resistor connected in series; and a negative bootstrap circuit device is coupled to a first node of the current generator. The negative bootstrap circuit includes a pumping capacitor having a first terminal and a second terminal. The first terminal is coupled to the first node of the current generator, and the second terminal is selectively coupled to either the first reference ground or a first voltage source through a first inverting buffer; wherein the current generator is coupled to be controlled by a pulse signal independent of the negative bootstrap circuit device.

19. The circuit according to claim 18, wherein in response to the second terminal of the pumping capacitor being coupled to the first voltage source, the pumping capacitor is charged with a potential difference between the second terminal and the first terminal.

20. The circuit according to claim 19, wherein in response to the second terminal of the pumping capacitor being coupled to the first reference ground, the first terminal of the pumping capacitor provides a negative voltage at the first node of the current generator based on the potential difference between the second terminal and the first terminal.

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