Bidirectional voltage level converter

Abstract

A voltage level converter switches signals between first and second voltage domains. The output buffer (100) for its channel includes a first plurality of PFETs (MP1-MPZ) and a first plurality of NFETs (MN1-MNZ) coupled to provide output signal (VOUT) interleaving. When the input voltage supply is greater than or equal to the VCCI trigger voltage of the output voltage supply (VCCO), the supply differential sensing circuit can disable interleaving by applying a disable signal (DISABL_STG) controlling the first set of switches (SP1-SPZ) coupled to the first plurality of PFETs (MP1-MPZ) and the second set of switches (SN1-SNZ) coupled to the first plurality of NFETs (MN1-MNZ).

Description

Technical Field

[0001] This invention generally relates to the field of voltage level converters. More specifically, and without limitation, this specification relates to bidirectional voltage level converters having output driver staggering controlled by a voltage supply difference. Summary of the Invention

[0002] Some embodiments provide a bidirectional voltage level converter capable of operating with an input voltage varying between 3.6 volts and 0.65 volts. The output buffer for the voltage level converter, combined with output signal edge control, also known as interleaving, is primarily used for low-to-high voltage switching when there is a large voltage supply difference. The voltage level converter senses the difference between the input and output supply voltages and activates the interleaving circuitry for a larger voltage difference when transitioning from a low voltage to a high voltage, and deactivates the interleaving circuitry for a smaller voltage difference when transitioning from a high voltage to a low voltage.

[0003] Some embodiments include a bidirectional voltage level converter chip comprising a first supply voltage pin for coupling to receive a first supply voltage for a first voltage domain; a second supply voltage pin for coupling to receive a second supply voltage for a second voltage domain; a third supply voltage pin for coupling to a ground plane to provide a lower rail; and a voltage level converter channel coupled to receive an input signal operating in the first voltage domain on a first data pin and to provide an output signal operating in the second voltage domain on a second data pin, the voltage level converter channel including an output buffer coupled to provide the output signal, the output buffer including: a first plurality of P-type field-effect transistors (PFETs) coupled in parallel between the second supply voltage and the output signal, the first plurality of PFETs having a standard threshold voltage Vt, the gate of each of the first plurality of PFETs being coupled to a corresponding resistor in a plurality of first resistors, the plurality of first resistors being... A first set of resistors is coupled in series and connected to receive a first gate control signal; a first plurality of switches, each of which is coupled in parallel to a corresponding resistor in a plurality of first resistors; a first plurality of N-type field-effect transistors (NFETs) coupled in parallel between the output signal and the lower rail, the first plurality of NFETs having a standard Vt, the gate of each of the first plurality of NFETs being coupled to a corresponding resistor in a plurality of second resistors, the corresponding resistors in the plurality of second resistors being coupled in series and connected to receive a second gate control signal; and a second plurality of switches, each of which is coupled in parallel to a corresponding resistor in a plurality of second resistors, wherein the first plurality of switches and the second plurality of switches are coupled to close when the first supply voltage is greater than or equal to a corresponding VCCI trigger voltage for the second supply voltage, and to open when the first supply voltage is less than the corresponding VCCI trigger voltage.

[0004] Some embodiments include an output buffer for a voltage level converter that is coupled to convert an input signal operating in a first voltage domain having a first supply voltage into an output signal operating in a second voltage domain having a second supply voltage. The output buffer includes a first plurality of P-type field-effect transistors (PFETs) coupled in parallel between a second supply voltage and an output signal, the first plurality of PFETs having a standard threshold voltage (Vt), the gate of each of the first plurality of PFETs being coupled to a corresponding resistor in a plurality of first resistors, the corresponding resistors in the plurality of first resistors being coupled in series and coupled to receive a first gate control signal; a first plurality of switches, each of the first plurality of switches being coupled in parallel to a corresponding resistor in the plurality of first resistors; a first plurality of N-type field-effect transistors (NFETs) coupled in parallel between the output signal and a lower rail, the first plurality of NFETs having a standard Vt, the gate of each of the first plurality of NFETs being coupled to a corresponding resistor in a plurality of second resistors, the corresponding resistors in the plurality of second resistors being coupled in series and coupled to receive a second gate control signal; and a second plurality of switches, each of the second plurality of switches being coupled in parallel to a corresponding resistor in the plurality of second resistors, wherein the first plurality of switches and the second plurality of switches are coupled to close when the first supply voltage is greater than or equal to a corresponding VCCI trigger voltage for the second supply voltage and to open when the first supply voltage is less than the corresponding VCCI trigger voltage.

[0005] Some embodiments include a method of operating a voltage level converter, the method comprising providing a voltage level converter embodied on an integrated circuit (IC) chip, each output buffer of the voltage level converter including a plurality of field-effect transistors and a plurality of resistors coupled to provide output signal interleaving; coupling a first supply voltage for a first voltage domain to a first supply voltage pin; coupling a second supply voltage for a second voltage domain to a second supply voltage pin; coupling a first data pin for a first channel to receive a first signal operating in the first voltage domain; coupling a second data pin for the first channel to provide a converted first signal operating in the second voltage domain, wherein the voltage level converter is coupled to determine whether the first supply voltage is greater than or equal to a first VCCI trigger voltage for the second supply voltage and is further coupled to disable interleaving in the first output buffer of the first channel in response to determining that the first supply voltage is greater than or equal to the first VCCI trigger voltage. Attached Figure Description

[0006] The described embodiments are illustrated by way of example and not limitation in the accompanying drawings, wherein like reference numerals indicate like elements. References to “a” or “an” embodiment do not necessarily refer to the same embodiment, and such references may mean “at least one.” Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic may be implemented in conjunction with other embodiments, whether or not explicitly described. As used herein, the term “coupled” refers to an indirect or direct electrical connection, unless defined in “communicable coupling” which may include a wireless connection. Thus, if a first device is coupled to a second device, the connection may be via a direct electrical connection or via an indirect electrical connection via other devices and connections.

[0007] The accompanying drawings illustrate examples of this description. Various advantages and features will emerge from the following detailed description and the appended claims, with reference to the accompanying drawings, wherein:

[0008] Figure 1 An example of an output buffer according to an embodiment is depicted;

[0009] Figure 1A An example of a supply difference sensing circuit for disabling unnecessary interleaving is depicted according to an embodiment;

[0010] Figure 1B A graph depicting the relationship between the output supply voltage and the trigger voltage of the input supply voltage according to an embodiment;

[0011] Figure 2A Plot a graph that depicts the data rate simulation of circuits with and without a supply differential sensing circuit and associated switches;

[0012] Figure 2B and Figure 2C Depicting the embodiment of the situation in the Figure 1 The output buffer processes the maximum difference between the rising and falling edges of the signal from the first voltage domain to the second voltage domain and from the second voltage domain to the first voltage domain.

[0013] Figure 2D Depicts an example output waveform provided by the output buffer according to an embodiment;

[0014] Figure 3 A method for operating a voltage converter according to an embodiment is described;

[0015] Figure 4 The system shown is one in which the embodiments described can be utilized;

[0016] Figure 5A and Figure 5B Describe the rising and falling edges of the waveform that cause non-monotonic behavior in the output signal due to noise, respectively; and

[0017] Figure 6 An example of circuitry in one channel of a bidirectional voltage level converter in which embodiments can be incorporated is depicted. Detailed Implementation

[0018] Specific embodiments will now be described in detail with reference to the accompanying drawings. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

[0019] Figure 4 System 400 is depicted, in which a bidirectional voltage level converter chip 404 is coupled to convert the voltage level of a signal transmitted between a controller 402 and a system 406. A first supply voltage pin VCC1 is used to couple to a first voltage domain, which uses a first supply voltage VCCA used by the controller 402; a second supply voltage pin VCC2 is used to couple to a second voltage domain, which uses a second supply voltage VCCB used by the system 406; and a third supply voltage pin GND is used to couple to a third supply voltage (which may be a ground plane) to provide a lower rail. In the illustrated embodiment, the bidirectional voltage level converter chip 404 also has four channels for conversion, but the bidirectional voltage level converter chip 404 may also have eight, sixteen, or any number of channels. Data pins A1 and B1 are coupled to the first channel; data pins A2 and B2 are coupled to the second channel; data pins A3 and B3 are coupled to the third channel; and data pins A4 and B4 are coupled to the fourth channel.

[0020] In this embodiment, the first direction pin DIR1, the second direction pin DIR2, the third direction pin DIR3, and the fourth direction pin DIR4 are all coupled to indicate the direction of information flow on the respective channels. In other embodiments, the direction pins may be associated with a group of two or more channels. Coupling any one of the direction pins to a first supply voltage VCCA indicates that the information flow on the respective channel or channel group is from the first voltage domain to the second voltage domain, while coupling any one of the direction pins to a third supply voltage (e.g., the lower rail) indicates that the information flow on the respective channel or channel group is from the second voltage domain to the first voltage domain. In the illustrated embodiment, a first channel with data pins A1 and B1, a second channel with data pins A2 and B2, and a third channel with data pins A3 and B3 are coupled to process data flowing from the first voltage domain to the second voltage domain, while a fourth channel with data pins A4 and B4 processes information flowing from the second voltage domain to the first voltage domain.

[0021] As semiconductor devices have steadily shrunk in size, the operating voltages have become much lower, so the operating voltages of controller 402 and system 406 can depend on the chip's creation time. Given the current state of the art, the first supply voltage VCCA and the second supply voltage VCCB can vary by orders of magnitude. For example, one of controller 402 and system 406 could use a voltage of 3.6V while the other uses a voltage of 0.65V. Providing the ability to switch signals between these two extremes presents many challenges for circuit design.

[0022] One such challenge is Figure 5A and Figure 5B As shown, they represent the rising edge of the output signal 500A and the falling edge of the output signal 500B from the voltage converter, respectively. Figure 5A , Figure 5B In each of these diagrams, the monotonicity of output signals 500A and 500B is disrupted by glitches 505A and 505B, respectively, circled in the figure. For example, the glitches seen in output signals 500A and 500B are typically caused by voltage level converters that convert signals between a low voltage domain (e.g., 0.65V) and a high voltage domain (e.g., 3.6V) in both directions. As multiple signals pass through a voltage level converter chip (such as bidirectional voltage level converter chip 404), parasitic interactions between signal lines close to each other cause noise generated by low-to-high conversion to couple to the signal from the voltage converter performing the high-to-low conversion. When glitches occur during the rise or fall phase of a signal, the receiver may misinterpret the signal and cause errors.

[0023] In one example illustrating the worst-case scenario Figure 4 The controller 402 has a first supply voltage VCCA of 0.65V and the system 406 has a second supply voltage VCCB of 3.6V. The first, second, and third channels are used to convert the signal from A to B, i.e., from 0.65V to 3.6V, and the fourth channel is used to convert the signal from B to A, i.e., from 3.6V to 0.65V. The first, second, and third channels draw a large current from the second supply voltage VCCB. This large current will produce both supply bounce and ground bounce. If all channels share the same ground and supply voltage, the output of the fourth channel, which provides the conversion from 3.6V to 0.65V, will be affected by noise coupling from the other channels. The presence of this noise during the rise or fall phase of the signal then leads to… Figure 5A and Figure 5B The types of spikes seen in the signal can, in turn, lead to misinterpretation of the signal.

[0024] Figure 6Half of an example voltage level converter channel 600 for converting signals between voltage domain A and voltage domain B is depicted and is taken from U.S. Patent No. 10,027,325, issued July 17, 2018, in the name of Christopher Michael Graves, which is incorporated herein by reference in its entirety. Figure 6 The circuit shown converts a signal from voltage domain A to voltage domain B, while the same circuit (not specifically shown) is coupled to convert a signal from voltage domain B to voltage domain A. Only one of these two circuits constituting voltage level converter channel 600 is active at a time, while the output buffer of the inactive circuit is in a high-impedance mode; the directionality of the conversion is determined by reference... Figure 4 The voltage coupling of the corresponding pins is determined as described.

[0025] The following description provides Figure 6 A quick overview of the circuitry is provided; further details can be found in the aforementioned patent. The voltage level converter channel 600 includes an input buffer circuit 605, a voltage converter circuit 610, a gate control circuit 615, an output buffer circuit 620, and an enable / disable control circuit 625. The input buffer circuit 605 receives the input signal VIN, generates a first control signal S1 and a second control signal S2, and is the only circuit powered by a first supply voltage VCCA in the "A" voltage domain. The first control signal S1 and the second control signal S2 are used to drive the transistors in the voltage converter circuit 610 to provide the output control signal S3T, which currently operates in the "B" voltage domain. In the gate control circuit 615, the first control signal S1, the second control signal S2, and the output control signal S3T are all used to drive the transistors in this circuit to generate gate control signals VP and VN, which are passed to the output buffer circuit 620. The gate control signals VP and VN control the gate of the output transistor used to provide the output signal VOUT. The enable / disable circuit 625 provides enable signals EN1 and EN2, which ensure that the gate control signals VP and VN can place the output buffer circuit in a high-impedance state when needed.

[0026] Due to the inherent difficulties in providing voltage conversion over a wide voltage range, the voltage level converter channel 600 is designed to provide a parallel threshold voltage (Vt) architecture, in which a low-Vt transistor is coupled in parallel with a standard Vt transistor. Although not specifically labeled, examples of low-Vt transistors coupled in parallel with standard Vt transistors can be seen in each of the input buffer circuit 605, the voltage converter circuit 610, and the gate control circuit 615, where both parallel-coupled transistors are controlled by any one of the input signal VIN, the first control signal S1, the second control signal S2, or the output control signal S3T. In the output buffer circuit 620, two P-type transistors, namely a low-Vt P-type field-effect transistor (PFET) MPL and a standard Vt transistor MPS, are coupled in parallel between the second supply voltage VCCB and the output signal VOUT, and each receives a gate control signal VP. Similarly, two N-type transistors, namely a low-Vt N-type field-effect transistor (NFET) MNL and a standard Vt NFET MNS, are coupled in parallel between the output signal VOUT and the lower rail, and each receives a gate control signal VN.

[0027] The voltage coupled to the specific circuit used for conversion determines whether the standard Vt transistor or the low Vt transistor contributes most to the conversion. For example, when a voltage of 0.65V is used as the supply voltage for the circuit, the standard Vt transistor generally does not conduct, while the low Vt transistor dominates. When a voltage of 3.6V is used as the supply voltage for the circuit, the low Vt transistor cannot provide sufficient current to supply the necessary output voltage, so in this case, the standard Vt transistor dominates.

[0028] Co-pending U.S. Patent Application No. 16 / 213,230 (hereinafter referred to as '230 Application), filed December 7, 2018, in the names of Amar Kanteti and Ankur Kumar Singh, entitled "Bidirectional Level Translator Having Noise Reduction and Improved Data Rate," is incorporated herein by reference in its entirety. '230 Application describes a modified output buffer as an output buffer circuit 620 of a voltage level converter channel 600. The modified output buffer comprises an interleaved combination of standard Vt NFETs and P-type field-effect transistors (PFETs), which improves noise on high-voltage outputs by boosting, thus improving monotonic behavior and potentially improving data rates on low-voltage outputs.

[0029] The circuit provided in application '230 is effective in providing a monotonic output when there is a large difference between a first supply voltage from a first voltage domain and a second supply voltage from a second voltage domain (e.g., the first supply voltage VCCA is 3.6V and the second supply voltage VCCB is 0.65V). One problem identified by the applicant in application '230' is that interleaving exists for each input / output voltage combination, even when interleaving is not needed at lower supply voltage differences, for example, when one supply voltage is 1.8V and the second supply voltage is 3.6V. When the voltage difference is low, ground noise generated by the higher voltage output channel can be tolerated by the lower voltage output channel. However, regardless of the supply voltage difference, the use of interleaving reduces the data rate across all supply voltage ranges.

[0030] Figure 1 The circuit diagram of output buffer 100 is shown, which provides a further modification to the output buffer of the '230 application, which disables interleaving when it is not required. For the channel of output buffer 100 as part of it, the output supply voltage VCCO represents the upper supply voltage of the output signal VOUT, while VCCI mentioned below is... Figure 6 The input signal VIN shown is supplied with an upper voltage. For example, given... Figure 4 The coupling of the center pins is such that the first supply voltage VCCA provides the input supply voltage VCCI, and the second supply voltage VCCB provides the output supply voltage VCCO for the first, second, and third channels. Similarly, the second supply voltage VCCB provides the input supply voltage VCCI, and the first supply voltage VCCA provides the output supply voltage VCCO for the fourth channel.

[0031] Output buffer 100 includes a low-Vt PFET MPL and a first plurality of PFETs MP1-MPZ having a standard Vt. Each of the low-Vt PFET MPL and the first plurality of PFETs MP1-MPZ is coupled in parallel between the output supply voltage VCCO and the output signal VOUT. The gates of the first plurality of PFETs MP1-MPZ are each coupled to a corresponding resistor in a plurality of first resistors RP1-RPZ, and the plurality of first resistors RP1-RPZ are coupled in series between node 103 and the gate of the PFET MPZ. A first plurality of switches SP1-SPZ are provided, wherein each of the first plurality of switches SP1-SPZ is coupled in parallel with a corresponding resistor in the plurality of first resistors RP1-RPZ, such that when each of the first plurality of switches SP1-SPZ is closed, the corresponding resistor in the plurality of first resistors RP1-RPZ is bypassed. The first plurality of switches SP1-SPZ are controlled by a disable-interleaving signal DISABL_STG.

[0032] During operation of output buffer 100, driver control 102 provides a first gate control signal VP and a second gate control signal VN to output buffer 100. A first boost control signal BOOSTR-CNTRL1 and a second boost control signal BOOSTR-CNTRL2 are also shown to be provided by driver control 102; in one embodiment, these boost control signals are a first control signal S1 and a second control signal S2 from input buffer circuit 605. The first gate control signal VP is provided to the gate of the low Vt PFET MPL and the first node 103. In one embodiment, when the disable-interleaving signal DISABL_STG is low, the first plurality of switches SP1-SPZ are turned off and the first gate control signal VP is sequentially passed from the first node 103 through each of the plurality of first resistors RP1-RPZ and to the corresponding transistor in the first plurality of PFETs MP1-MPZ. As the first gate control signal VP is passed through each of the plurality of first resistors RP1-RPZ, each resistor introduces a small delay, such that the gates of the first plurality of PFETs MP1-MPZ are turned on at interleaved intervals. This interleaving reduces noise caused by switching of the output buffer 100. In the same embodiment, when the disable-interleaving signal DISABL_STG is high, the first plurality of switches SP1-SPZ are closed and the first gate control signal VP is passed from the first node 103 through each of the first plurality of switches SP1-SPZ to the corresponding transistor in the first plurality of PFETs MP1-MPZ. Because there is no delay caused by the transmission through the sequence resistors, each of the first plurality of PFETs MP1-MPZ is turned on simultaneously, thus providing a faster signal.

[0033] The second plurality of PFETs MP1P-MPZP are each coupled between the output supply voltage VCCO and the gate of a corresponding one of the first plurality of PFETs MP1-MPZ, to act as pull-up transistors that can quickly turn off the first plurality of PFETs MP1-MPZ. Inverter 104 provides the inversion of the first gate control signal / VP to provide a signal for controlling the gates of the second plurality of PFETs MP1P-MPZP.

[0034] The output buffer 100 also includes a low-Vt NFET MNL and a first plurality of NFETs MN1-MNZ with a standard Vt. Each of the low-Vt NFET MNL and the first plurality of NFETs MN1-MNZ is coupled in parallel between the output signal VOUT and the lower rail. The gates of the first plurality of NFETs MN1-MNZ are each coupled to a corresponding resistor in a plurality of second resistors RN1-RNZ, and the plurality of second resistors RN1-RNZ are coupled in series. A second plurality of switches SN1-SNZ are provided, wherein each of the second plurality of switches SN1-SNZ is coupled in parallel with a corresponding resistor in the plurality of second resistors RN1-RNZ, such that when each of the second plurality of switches SN1-SNZ is closed, the corresponding resistor in the plurality of second resistors RN1-RNZ is bypassed. The second plurality of switches SN1-SNZ are also controlled by a disable-interleaving signal DISABL_STG.

[0035] During operation of the output buffer 100, driver control 102 provides a second gate control signal VN to the gate of the low VtNFET MNL and the second node 105. In one embodiment, when the disable-interleaving signal DISABL_STG is low, the second plurality of switches SN1-SNZ are open and the second gate control signal VN is sequentially passed from the second node 105 through each of the plurality of second resistors RN1-RNZ and to the corresponding gate of the first plurality of NFETs MN1-MNZ. As the second gate control signal VN is passed through each of the plurality of second resistors RN1-RNZ, each resistor again introduces a small delay, causing the gates of the first plurality of NFETs MN1-MNZ to be turned on at an interleaved interval. In the same embodiment, when the disable-interleaving signal DISABL_STG is high, the second plurality of switches SN1-SNZ are closed and the second gate control signal VN is sequentially passed from the second node 105 through each of the second plurality of switches SN1-SNZ to the gate of the first plurality of NFETs. Because there is no delay introduced by the transmission through the sequential resistors, each of the first plurality of NFETs MN1-MNZ conducts simultaneously, thus providing a stronger signal.

[0036] The first plurality of switches SP1-SPZ and the second plurality of switches SN1-SNZ together form an interleaved enable-disable circuit 110, which, in conjunction with circuitry providing an enable-interleaved signal DISABL_STG, provides the ability to utilize the output signal VOUT for interleaving when necessary, but bypass interleaving at other times. Control of the interleaved enable-disable circuit 110 is related to... Figure 1A The description depicts an embodiment of a circuit that provides the disable-interleaved signal DISABL_STG.

[0037] continue Figure 1Each of the second plurality of NFETs MN1P-MNZP is coupled between the gate and lower rail of a corresponding one of the first plurality of NFETs MN1-MNZ to act as a pull-down transistor that can quickly turn off the first plurality of NFETs MN1-MNZ. Inverter 106 provides the inversion of the second gate control signal / VN to provide a signal controlling the gates of NFETs MN1P to MNZP.

[0038] A third resistor RA is coupled in series with the first boost NFET MNA and the second boost NFET MNB between the output supply voltage VCCO and the lower rail. Point 108 is coupled between the source of the NFET MNA and the drain of the NFET MNB to help provide the output signal VOUT. Both the first boost NFET MNA and the second boost NFET MNB are standard Vt transistors. The driver control circuit 102 provides both a first gate control signal VP and a second gate control signal VN, and also provides two additional boost control signals BOOSTR-CNTRL1 and BOOSTR-CNTRL2, which are provided to the gates of the first boost NFET MNA and the second boost NFET MNB, respectively.

[0039] Unlike the first gate control signal VP and the second gate control signal VN generated in the voltage domain of the output supply voltage VCCO, the first boost control signal BOOSTR-CNTRL1 and the second boost control signal BOOSTR-CNTRL2 are generated in the input supply voltage VCCI (e.g., ...). Figure 6 The boost control signals BOOSTR-CNTRL1 and BOOSTR-CNTRL2 are generated in the voltage domain of the first supply voltage (VCCA). In one embodiment, the boost control signals BOOSTR-CNTRL1 and BOOSTR-CNTRL2 are the first control signal S1 and the second control signal S2 from the input buffer circuit 605. If the output buffer 100 is disabled, i.e., placed in high impedance mode, the boost signals BOOSTR-CNTRL1 and BOOSTR-CNTRL2 have binary low values.

[0040] When the output buffer 100 is receiving a high output supply voltage VCCO, e.g., 3.6V, while the input supply voltage VCCI is low (e.g., 0.65V), interleaving is enabled and the first plurality of PFETs MP1-MPZ and the first plurality of NFETs MN1-MNZ operate to reduce noise on the upper and lower rails of the supply voltage. The low-Vt PFET MPL and low-Vt NFET MNL are fully turned on, but do not deliver sufficient current to significantly contribute to the output signal VOUT. Simultaneously, since the first boost NFET MNA and the second boost NFET MNB are controlled by the first boost control signal BOOSTR-CNTRL1 and the second boost control signal BOOSTR-CNTRL2, which are generated using the input supply voltage VCCI, the boost NFETs MNA and MNB will not be turned on because the corresponding control signals do not exceed the threshold voltages of the first boost NFET MNA and the second boost NFET MNB. In a similar example where the difference between the input supply voltage VCCI and the output supply voltage VCCO is not significant, such as when the input supply voltage VCCI is 1.2V and the output supply voltage VCCO is 3.6V, the boost NFETs MNA and MNB, which are standard Vt transistors, can be turned on, but the current from the boost NFETs MNA and MNB will not be sufficient to change the output state.

[0041] Conversely, when the input supply voltage VCCI is high (3.6V) and the output supply voltage VCCO is low (0.65V), the first plurality of PFETs MP1-MPZ and the first plurality of NFETs MN1-MNZ will not conduct; the low Vt PFET MPL and the low Vt NFET MNL will conduct, and the first boost NFET MNA and the second boost NFET MNB will conduct very quickly because they have strong boost control signals BOOSTR-CNTRL1 and BOOSTR-CNTRL2. By rapidly switching the first boost NFET MNA and the second boost NFET MNB, the received noise does not appear on the rising or falling edge of the signal.

[0042] While interleaving higher voltage signals, as described in the preceding paragraphs, can avoid many noise problems, it also reduces data rates and increases propagation delay. For high voltage differences that can be coupled to a voltage converter coupled to the output buffer 100, a trade-off between noise and data rate is necessary; however, when the voltage difference is small, unnecessarily reducing the data rate is undesirable. Therefore, it is determined that interleaving should be disabled when unnecessary. To this end, the ground bounce amplitude (which provides accompanying noise) and peak ground current for various voltages are determined according to Table 1 below:

[0043] Table 1

[0044] VCCO Ground bounce Grounding peak current 3.6 0.66 120mA 3.3 0.6 107mA 3 0.55 91mA 2.7 0.5 77.4mA 2.4 0.43 64mA

[0045] As the output voltage decreases, both the shoot-through current and ground bounce decrease, thus reducing the need for interleaving. As shown in Table 1, reducing the supply voltage by 10% also reduces the ground bounce by 10%. The VCCI trigger voltage can be determined for each output voltage; that is, for each output voltage, the minimum input voltage at which interleaving is not required can be determined. If the input voltage to a converter channel is at or above the VCCI trigger voltage, interleaving for that channel will be disabled using multiple first switches SP1-SPZ and multiple second switches SN1-SNZ.

[0046] Figure 1A An example of a supply difference sensing circuit 100A is depicted, which can provide a disable-interleaving signal DISABL_STG to disable interleaving if the input supply voltage VCCI of a particular channel is greater than or equal to the VCCI trigger voltage of the corresponding output supply voltage VCCO. In this embodiment, the supply difference sensing circuit 100A is an inverter circuit consisting of a P-type silicon-oxide-semiconductor (PMOS) transistor with a standard voltage threshold, a PMOS transistor with a low voltage threshold, and an N-type silicon-oxide-semiconductor (NMOS) transistor with a low voltage threshold. A first plurality of stacked PMOS transistors 122 with a standard voltage threshold are coupled in series with a first plurality of stacked NMOS transistors 124 with a low voltage threshold between the output supply voltage VCCO and the lower rail VSS. The gates of the first plurality of stacked PMOS transistors 122 and the first plurality of stacked NMOS transistors 124 both receive the input supply voltage VCCI. The point between the first plurality of stacked PMOS transistors 122 and the first plurality of stacked NMOS transistors 124 is coupled to provide a disable-interleaving-bar signal DISABL-STG-BAR. A second plurality of stacked PMOS transistors 126 with a low voltage threshold is also coupled in series with a second plurality of stacked NMOS transistors 128 with a low voltage threshold between the output supply voltage and the lower rail (shown here as VSS). A disable-interleaved-bar signal DISABL-STG-BAR is provided to the gates of the second plurality of stacked PMOS transistors 126 and the second plurality of stacked NMOS transistors 128, while the point between the second plurality of stacked PMOS transistors 126 and the second plurality of stacked NMOS transistors 128 is coupled to provide the disable-interleaved signal DISABL_STG.

[0047] A typical inverter circuit (i.e., all transistors have the same nominal threshold voltage) will switch between a low and a high state at the midpoint of the voltage difference between the two rails. Figure 1AIn this process, by using a standard Vt PMOS transistor and a low Vt NMOS transistor, the transition between low and high states is shifted to reflect the VCCI trigger voltage Vtrigger. This voltage can be used to provide a disable-interleaved signal DISABL_STG to close the first plurality of switches SP1-SPZ and the second plurality of switches SN1-SNZ, bypassing the interleaving of the output signal Vout. The VCCI trigger voltage Vtrigger is based on the following equation:

[0048]

[0049] Where Vdd is the output supply voltage VCCO used in the output buffer 100.

[0050] Vtrigger is the input supply voltage VCCI, at which interleaving can be turned off.

[0051] Vtn and Vtp are the threshold voltages of a low-Vt NMOS transistor and a standard Vt PMOS transistor, respectively, and

[0052] The β(βp) of a P-type transistor and the β(βn) of an N-type transistor are defined by the following equations:

[0053] and Equation 2

[0054]

[0055] Where μn and μp are the mobilities of the NMOS and PMOS dopants, respectively.

[0056] Cox is the capacitance of the gate oxide.

[0057] Wn and Wp are the widths of the N-type and P-type transistors, respectively, and

[0058] Ln and Lp are the lengths of the N-type and P-type transistors, respectively.

[0059] Figure 1B Plotting curve 100B shows the relationship between the output supply voltage VCCO and the corresponding VCCI trigger voltage Vtrigger, while Table 2 below provides the specific values ​​of the output supply voltage VCCO and the corresponding VCCI trigger voltage Vtrigger for the output buffer 100. If the corresponding input supply voltage VCCI is at or above the VCCI trigger voltage Vtrigger, the interleaving can be safely turned off or bypassed without affecting the overall noise.

[0060] Table 2

[0061] VCCO(V) VCCI trigger voltage (V) 3.6 1.417 3.3 1.3 3 1.18 2.7 1.004 2.4 0.886 2.1 0.768 1.8 0.624

[0062] Figure 2A This demonstrates the situation where interleaving is unnecessary and shows the resulting data rate loss. Both output signals are recorded for an input voltage of 1.8V and an output signal of 3.3V, with an input data rate of 500Mbps. Output signal 202 is generated by an output buffer that always applies interleaving; output signal 202 has an output data rate of 350Mbps. In contrast, output signal 204 is generated by an output buffer that disables interleaving when not needed. From Table 2, it can be determined that for an output voltage of 3.3V Vout, an input voltage of 1.8V Vin is higher than the 1.3V value of the VCCI trigger voltage Vtrigger, therefore interleaving is disabled in this case, and the maximum output data rate of 500Mbps is achieved.

[0063] Although the output buffer 100 can provide the maximum output data rate when the input and output voltages are relatively close together, the output buffer 100 can also provide clean signals for signals in both directions when the voltage difference is maximum. Figure 2B and Figure 2C It is generated by a voltage converter with a first supply voltage VCCA equal to 3.6V and a second supply voltage VCCB equal to 0.65V. Output signal 212 comes from a single channel operating in the A-to-B direction, causing the output voltage to operate in the 0.65V range. Output signal 214 represents three output signals from the remaining three channels, all operating in the B-to-A direction, causing output signal 214 to operate in the 3.6V range. Figure 2B Show the rising edge of these signals and Figure 2C The falling edge of the same signal is shown. Even with a large voltage difference, monotonic behavior of output signals 212 and 214 is observed. Figure 2D A compressed version of the output signal 212 depicting operation in the 0.65V domain. (e.g.) Figure 2D As can be seen, although some noise 216 is observed in this waveform, the use of a boost converter has ensured that the output signal 212 rises fast enough to ensure that there are no glitches below the output high voltage (VOH) and no glitches above the output low voltage (VOL).

[0064] Figure 3A method 300 is described for operating a voltage level converter (i.e., a voltage level converter in conjunction with an output buffer 100) according to an embodiment. The method begins by providing a voltage level converter 305 embodied on an IC chip. The output buffer of the voltage level converter includes a plurality of field-effect transistors and a plurality of resistors coupled to provide interleaved output signals. In one embodiment, the plurality of field-effect transistors include a first plurality of PMOS transistors MP1-MPZ and a first plurality of NMOS transistors MN1-MNZ, and the plurality of resistors include a plurality of first resistors RP1-RPZ and a plurality of second resistors RN1-RNZ. The method continues as follows: a first supply voltage of a first voltage domain is coupled 310 to a first supply voltage pin, and a second supply voltage of a second voltage domain is coupled 315 to a second supply voltage pin. A first data pin of a first channel is coupled 320 to receive a first signal operating in the first voltage domain, and a second data pin of the first channel is coupled 325 to provide a converted first signal operating in the second voltage domain. The voltage level converter is coupled to determine whether a first supply voltage is greater than or equal to a first VCCI trigger voltage for a second supply voltage, and is also coupled to disable interleaving in the first output buffer of the first channel in response to determining that the first supply voltage is greater than or equal to the first VCCI trigger voltage.

[0065] A third data pin for the second channel is coupled at 330 to receive a second signal operating in the second voltage domain, and a fourth data pin for the second channel is coupled at 335 to provide a converted second signal operating in the first voltage domain. A voltage level converter is coupled to determine whether the second supply voltage is greater than or equal to the second VCCI trigger voltage for the first supply voltage, and is also coupled to disable interleaving in the second output buffer of the second channel in response to determining that the second supply voltage is greater than or equal to the second VCCI trigger voltage.

[0066] It can be noted that regarding the comparison of the VCCI trigger voltage between the current input supply voltage VCCI and the current output supply voltage VCCO, when the input supply voltage VCCI is greater than the output supply voltage VCCO, the input supply voltage VCCI will always be greater than the corresponding VCCI trigger voltage. Therefore, interleaving is always disabled in channels transitioning from a higher voltage domain to a lower voltage domain. When there is a voltage difference between the input supply voltage VCCI and the output supply voltage VCCO, interleaving can be disabled in both transition directions.

[0067] Some examples provide output buffers for voltage converters capable of handling conversions across a wide range of voltages. To maximize the data rate across all voltage conversion combinations, interleaving is applied when the voltage conversion is from a lower voltage domain to a higher voltage domain and the difference between the two voltage domains is large. Interleaving is disabled at lower differences and when converting from a higher voltage domain to a lower voltage domain. This arrangement reduces the impact of supply noise when the supply domains are far apart and does not reduce the data rate. Disabling interleaving when converting between two voltage domains that are closer to each other improves the data rate due to the propagation delay of these smaller voltage differences. Methods for operating voltage converters are also described.

[0068] Unless otherwise stated, reference to an element in the singular means "one or more". Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A bidirectional voltage level shifter circuit comprising: an input voltage input adapted to receive a first voltage of a first voltage domain, an output voltage input adapted to receive a second voltage of a second voltage domain, the second voltage different from the first voltage, a ground rail, a signal input, and a signal output; an input buffer having an input coupled to the signal input, having an input buffer output, and coupled to the input voltage input and the ground rail; an output buffer having a first gate control input coupled to the input buffer output and a second gate control input, having a buffer output coupled to the signal output, and coupled to the output voltage input and the ground rail, the output buffer including: a first resistor coupled in series with the first gate control input; a first switch across the first resistor; a first transistor having a standard threshold voltage (Vt) having a gate coupled to the first gate control input through the first resistor, having a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; a second resistor coupled in series with the second gate control input; a second switch across the second resistor; a second transistor having a standard threshold voltage having a gate coupled to the second gate control input through the second resistor, having a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail, wherein the first switch and the second switch turn on or off based on a voltage difference between the first voltage of the first voltage domain and the second voltage of the second voltage domain.

2. The bidirectional voltage level shifter circuit of claim 1 comprising: a first inverter having an input coupled to the first gate control input and having a first inverted output; a third transistor having a gate coupled to the first inverted output, a first terminal coupled to the output voltage input, and having a second terminal coupled to the gate of the first transistor; a second inverter having an input coupled to the second gate control input and having a second inverted output; a fourth transistor having a gate coupled to the second inverted output, a first terminal coupled to the gate of the second transistor, and having a second terminal coupled to the ground rail.

3. The bidirectional voltage level shifter circuit of claim 2 comprising: a first low threshold voltage (Vt) transistor having a gate coupled to the first inverted output, a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; and a second low Vt transistor having a gate coupled to the second inverted output, a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail. ​ 4. The bidirectional voltage level shifter circuit of claim 3, wherein, The output buffer includes a first boost input and a second boost input, and the bidirectional voltage level translator circuit includes: a first boost transistor having a gate coupled to the first boost input, having a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; a second boost transistor having a gate coupled to the second boost input, having a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail.

5. The bidirectional voltage level translator circuit of claim 1, including a supply differential sense circuit, the supply differential sense circuit including: a first set of stacked P-type metal oxide silicon transistors (PMOS transistors) coupled in series between the second voltage input and an inverting interleaved output coupled to the second switch, each PMOS transistor of the first set of stacked PMOS transistors having a standard threshold voltage; a first set of stacked N-type metal oxide silicon transistors (NMOS transistors) coupled in series between the inverting interleaved output and the ground rail, each NMOS transistor of the first set of stacked NMOS transistors having a low threshold voltage, respective gates of the first set of stacked PMOS transistors and the first set of stacked NMOS transistors being coupled to the first voltage input; a second set of stacked PMOS transistors coupled in series between the second voltage input and an interleaved output coupled to the first switch, each PMOS transistor of the second set of stacked PMOS transistors having a standard threshold voltage; and a second set of stacked NMOS transistors coupled in series between the interleaved output and the ground rail, each NMOS transistor of the second set of stacked NMOS transistors having a low threshold voltage, respective gates of the second set of stacked PMOS transistors and the second set of stacked NMOS transistors being coupled to the inverting interleaved output.

6. The bidirectional voltage level translator circuit of claim 5, including: a voltage translator circuit having an input coupled to the input buffer output, and having a translator output; and a gate control circuit having an input coupled to the translator output, and having a first gate control output coupled to the first gate control input, and having a second gate control output coupled to the second gate control input.

7. The bidirectional voltage level shifter circuit of claim 1, wherein, The bidirectional voltage level translator circuit is included in an integrated circuit.

8. The bidirectional voltage level shifter circuit of claim 1, wherein, The first voltage and the second voltage are each in a range between 0.65 volts and 3.6 volts.

9. An output buffer for a translator circuit, including: a first gate control input, a second gate control input, an output voltage input, a ground rail, and a buffer output; a first resistor coupled in series with the first gate control input; a first switch across the first resistor; a second resistor coupled in series with the second gate control input; a first transistor having a standard threshold voltage, having a gate coupled to the first gate control input through the first resistor, having a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; a second resistor coupled in series with the second gate control input; a second switch across the second resistor; a second transistor having a standard threshold voltage, having a gate coupled to the second gate control input through the second resistor, having a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail, wherein the first switch and the second switch are turned on or off based on a voltage difference between a first voltage of a first voltage domain and a second voltage of a second voltage domain.

10. The output buffer of claim 9, comprising: a first inverter having an input coupled to the first gate control input, and having a first inverted output; a third transistor having a gate coupled to the first inverted output, a first terminal coupled to the output voltage input, and having a second terminal coupled to the gate of the first transistor; a second inverter having an input coupled to the second gate control input, and having a second inverted output; a fourth transistor having a gate coupled to the second inverted output, a first terminal coupled to the gate of the second transistor, and having a second terminal coupled to the ground rail.

11. The output buffer of claim 10, comprising: a first low threshold voltage transistor having a gate coupled to the first inverted output, a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; and a second low threshold voltage transistor having a gate coupled to the second inverted output, a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail. The output buffer comprises a first boost input and a second boost input, and the output buffer comprises:

12. The output buffer of claim 11, wherein, a first boost transistor having a gate coupled to the first boost input, a first terminal coupled to the output voltage input, and having a second terminal coupled to the buffer output; and a second boost transistor having a gate coupled to the second boost input, a first terminal coupled to the buffer output, and having a second terminal coupled to the ground rail.

13. A method of operating a voltage level shifter circuit, comprising: (a) receiving a first voltage of a first voltage domain on a first voltage input; (b) receiving a second voltage of a second voltage domain on a second voltage input, the second voltage being different than the first voltage; (c) receiving a first signal from the first voltage domain on a first signal input; (d) in response to receiving the first signal, providing a second signal to the second voltage domain on a second signal output; ​ (e) based on a voltage difference between the first voltage of the first voltage domain and the second voltage of the second voltage domain, causing the provision of the second signal to be interleaved or not interleaved.

14. The method of claim 13, wherein, The causing the provision of the second signal to be interleaved includes opening a switch in an interleaving circuit in an output buffer.

15. The method of claim 13, wherein, The causing the provision of the second signal to be not interleaved includes closing a switch in an interleaving circuit in an output buffer.

16. The method of claim 13, wherein, The first voltage and the second voltage are each in a range between 0.65 volts and 3.6 volts.

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